Branch prediction method, device and system, computer device, medium and product

Abstract

The embodiment of the invention discloses a branch prediction method, device and system, a computer device, a medium and a product. The branch prediction method comprises the following steps: at least dividing a jump threshold value of a first direction predictor into a first jump threshold value and a second jump threshold value which respectively correspond to an unconditional branch and a conditional branch of a zero-delay branch target buffer; according to the hit result, determining a jump threshold corresponding to the first direction predictor and jump thresholds of other direction predictors; if the determined jump threshold value corresponding to the first direction predictor is a first jump threshold value, determining a jump prediction result according to a symbol of the first jump threshold value; and if the determined jump threshold value corresponding to the first direction predictor is a second jump threshold value, performing addition operation on the second jump threshold value and jump threshold values of other direction predictors, and determining a jump prediction result according to a symbol of an addition operation result. According to the method, the logic depth of the ZBTB can be reduced, the capacity of the ZBTB can be improved, and the BP prediction speed can be improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of branch prediction, and in particular to a branch prediction method, device, system, computer device, medium and product. BACKGROUND

[0002] The development of high-performance processors requires the BP to improve the prediction accuracy while the prediction speed is as fast as possible. Currently, the BP microarchitecture including a multi-level BTB is commonly used for branch prediction. A typical BP microarchitecture includes a ZBTB, an L1 BTB and an L2 BTB. The ZBTB has a small capacity and the smallest prediction delay, generally 0 cycle; the L1 BTB has a larger capacity and a prediction delay of generally 1-2 cycles; and the L2 BTB has a very large capacity and a prediction delay of generally 3-4 cycles.

[0003] In the prediction process of the ZBTB, the branch type of the hit branch of the ZBTB needs to be combined with the direction prediction result of the direction predictor after obtaining the hit result of the ZBTB, so as to give a jump prediction result. The inventors find that the above-mentioned combination logic is indispensable for the microarchitecture of the ZBTB, which makes the logic depth of the ZBTB in the prior art large, the capacity of the ZBTB difficult to improve, and the prediction speed of the BP not conducive to improvement. SUMMARY

[0004] Therefore, the embodiments of the present disclosure provide a branch prediction method, device, system, computer device, medium and product, which can help to reduce the logic depth of the ZBTB, improve the capacity of the ZBTB, and further improve the prediction speed of the BP.

[0005] In a first aspect, the embodiments of the present disclosure provide a branch prediction method, which adopts the following technical scheme: The branch prediction method comprises: dividing a jump threshold of a first direction predictor into at least a first jump threshold and a second jump threshold, the first jump threshold corresponding to a non-conditional branch of a zero-delay branch target buffer, and the second jump threshold corresponding to a conditional branch of the zero-delay branch target buffer; determining the jump threshold corresponding to the first direction predictor and the jump thresholds of other direction predictors according to a hit result of the zero-delay branch target buffer; if the determined jump threshold corresponding to the first direction predictor is the first jump threshold, determining a jump prediction result according to a sign of the first jump threshold; if the determined jump threshold corresponding to the first direction predictor is the second jump threshold, performing addition operation on the second jump threshold and the jump thresholds of the other direction predictors, and determining a jump prediction result according to a sign of the addition operation result.

[0006] Optionally, the first jump threshold has a first bit number, the second jump threshold has a second bit number, and the first bit number and the second bit number satisfy: the first bit number is greater than a bit number of a jump threshold of another direction predictor, and the second bit number is consistent with the bit number of the jump threshold of the another direction predictor.

[0007] Optionally, the first jump threshold includes a fixed sign bit, an interval bit, and a value bit, and a bit number of the value bit of the first jump threshold is the same as the second bit number.

[0008] Optionally, the jump threshold of the first direction predictor is divided into a first jump threshold, a second jump threshold, and a third jump threshold, the third jump threshold corresponds to a branch not contained in a zero-delay branch target buffer, and the branch prediction method further includes: if the determined jump threshold corresponding to the first direction predictor is the third jump threshold, determining a jump prediction result according to a sign of the third jump threshold.

[0009] Optionally, the third jump threshold has a third bit number, and the third bit number satisfies: the third bit number is greater than a bit number of a jump threshold of another direction predictor.

[0010] Optionally, the third jump threshold includes a fixed sign bit, an interval bit, and a value bit, and a bit number of the value bit of the third jump threshold is the same as the second bit number.

[0011] Optionally, the fixed sign bit occupies at least one bit, and the interval bit occupies at least one bit.

[0012] Optionally, the fixed sign bit occupies 1 bit, and the interval bit occupies 1 bit.

[0013] Optionally, the first direction predictor is a PC index direction predictor, and the another direction predictor is an HP index direction predictor.

[0014] Optionally, the first direction predictor is a PC index direction predictor, and the branch prediction method further includes: after the zero-delay branch target buffer is updated, using a current PC to update the first jump threshold and the second jump threshold in the PC index direction predictor.

[0015] In a second aspect, the embodiments of the present disclosure further provide a branch prediction device, which adopts the following technical scheme: The branch prediction device includes: The threshold dividing module is configured to divide a jump threshold of the first direction predictor into at least a first jump threshold corresponding to a non-conditional branch of the zero-latency branch target buffer and a second jump threshold corresponding to a conditional branch of the zero-latency branch target buffer. The threshold determining module is configured to determine the jump threshold corresponding to the first direction predictor and the jump thresholds of other direction predictors according to a hit result of the zero-latency branch target buffer. The jump prediction module is configured to determine a jump prediction result according to a sign of the first jump threshold when the determined jump threshold corresponding to the first direction predictor is the first jump threshold, and to perform addition operation on the second jump threshold and the jump thresholds of other direction predictors when the determined jump threshold corresponding to the first direction predictor is the second jump threshold, and determine a jump prediction result according to a sign of a result of the addition operation.

[0016] In a third aspect, the embodiments of the present disclosure further provide a branch prediction system, which adopts the following technical scheme. The branch prediction system comprises a zero-latency branch target buffer, a first-level branch target buffer, a second-level branch target buffer, and the branch prediction device corresponding to the zero-latency branch target buffer.

[0017] Optionally, only the Tag field, the Val field and the Target field of each entry are saved in the zero-latency branch target buffer.

[0018] In a fourth aspect, the embodiments of the present disclosure further provide a branch prediction system, which adopts the following technical scheme. The computer device comprises: at least one processor; and a memory connected to the at least one processor in communication; wherein The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the branch prediction method described in any one of the above.

[0019] In a fifth aspect, the embodiments of the present disclosure further provide a branch prediction system, which adopts the following technical scheme. The computer readable storage medium stores computer instructions for causing a computer to perform the branch prediction method described in any one of the above.

[0020] In a sixth aspect, the embodiments of the present disclosure further provide a computer program product, which adopts the following technical scheme. The computer program product comprises computer instructions which, when executed by a processor, implement the steps of the branch prediction method according to any one of the preceding embodiments.

[0021] In the branch prediction method provided by the embodiments of the present disclosure, the jump threshold of the first direction predictor is divided into at least a first jump threshold and a second jump threshold, and the first jump threshold and the second jump threshold correspond to the unconditional branch and the conditional branch of the ZBTB respectively, so that the first jump threshold and the second jump threshold themselves embody the branch type (unconditional branch or conditional branch) of the ZBTB. When the jump threshold corresponding to the first direction predictor is determined to be the first jump threshold, the jump prediction result can be determined according to the sign of the first jump threshold. When the jump threshold corresponding to the first direction predictor is determined to be the second jump threshold, the second jump threshold is added to the jump threshold of the other direction predictor, and the jump prediction result can be determined according to the sign of the addition result. Compared with the prior art, the above two cases both reduce the logic of combining the branch type of the branch hitting the ZBTB to determine the jump, and thus can help to reduce the logic depth of the ZBTB, improve the capacity of the ZBTB, and further improve the prediction speed of the BP.

[0022] The above description is only a summary of the technical solutions of the present disclosure. In order to more clearly understand the technical means of the present disclosure, the contents of the specification can be implemented, and in order to make the above and other purposes, characteristics and advantages of the present disclosure more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0024] Figure 1 The schematic diagram of the BP micro-architecture provided by the embodiments of the present disclosure; Figure 2 The prediction process of the ZBTB provided by the embodiments of the present disclosure Figure 1 ; Figure 3 The flowchart of the branch prediction method provided by the embodiments of the present disclosure; Figure 4 The prediction process of the ZBTB provided by the embodiments of the present disclosure Figure 2 ; Figure 5 The schematic diagram of the branch prediction device provided by the embodiments of the present disclosure; Figure 6 A structural schematic diagram of a computer device provided by an embodiment of the present disclosure is shown in FIG. 1. DETAILED DESCRIPTION

[0025] The embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0026] It should be apparent that the following describes embodiments of this disclosure by way of specific examples, and that one skilled in the art could readily derive other advantages and effects from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and are not all the embodiments. This disclosure can also be implemented or applied by other different specific embodiments, and the details in this specification can be modified or changed in various ways without departing from the spirit of this disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in this disclosure, all other embodiments obtained by one of ordinary skill in the art without creative labor are within the scope of protection of this disclosure.

[0027] It should be noted that the various aspects of the embodiments described below are within the scope of the appended claims. It should be apparent that the aspects described herein can be embodied in a wide variety of forms and that any specific structure and / or function described herein is merely illustrative. Based on the teachings provided herein one skilled in the art will appreciate that one aspect described herein can be implemented independently of any other aspects and that the various aspects described herein can be combined in various ways. For example, an apparatus can be implemented or a method can be practiced using any number of the aspects set forth herein. In addition, such an apparatus can be implemented or such a method can be practiced using other structure and / or functionality in addition to or other than one or more of the aspects set forth herein.

[0028] It should also be noted that the drawings provided in the following embodiments are only to illustrate the basic concept of the present disclosure in a schematic manner, and only show the components related to the present disclosure in the drawings, not drawn according to the number, shape and size of the components in actual implementation, the shape, number and proportion of each component in actual implementation can be a random change, and the layout pattern of its components can be more complex.

[0029] In addition, in the following description, specific details are provided in order to facilitate a thorough understanding of the examples. However, one skilled in the art will understand that the aspects described can be practiced without these specific details.

[0030] Abbreviation explanation: BP: branch prediction ZBTB: Zero-bubble branch target buffer L1BTB: level 1 branch target buffer L2BTB: level 2 branch target buffer SRAM: Static Random Access Memory PC-indexed direction predictor Hashed Perceptron Predictor

[0031] Ideally, BP should be a ZBTB with as large a capacity as possible, but the number of entries and the supported branch types of the ZBTB are limited by the frequency and cannot be effectively improved. In order to meet the requirements of speed and accuracy, as shown in Figure 1 The embodiments of the present disclosure provide a BP microarchitecture including a ZBTB, an L1BTB and an L2BTB multi-level BTB, wherein the ZBTB has a small capacity but a high speed, the L1BTB / L2BTB has a large capacity but a low speed. The ZBTB has the smallest capacity and the smallest prediction delay, generally 0 cycle, that is, the linear address can be updated when the cycle is clicked; the L1BTB has a larger capacity, and the prediction delay is generally 1-2 cycles; the L2BTB has a very large capacity, and the prediction delay is generally 3-4 cycles.

[0032] The branch prediction process of the BP microarchitecture with the above structure includes: sequentially sending a Next Instruction PC (the address of the next instruction to be taken by the processor at the end of the current instruction fetch period, referred to as NIP) into the ZBTB, the L1BTB and the L2BTB for multi-level BTB access, querying whether there is a hit, and if there is a hit, combining the result of the direction predictor to give a target address for updating the NIP. The updated NIP continues to be accessed in the BP microarchitecture for multi-level BTB access until all the BTBs have no hit, and then the NIP is updated to a sequential address.

[0033] In the above branch prediction process, the ZBTB needs to use the branch type of the entry of the hit ZBTB in combination with the result of the direction predictor to give the final jump prediction result. Taking the direction predictor as an example, which is composed of an HP-indexed direction predictor and a PC-indexed direction predictor, as shown in Figure 2As shown, the prediction process of the ZBTB includes: (1) after linear address input to the ZBTB, entry1 in the ZBTB is matched from N ZBTB entries; (2) a direction predictor is accessed to obtain PC BIAS and HP BIAS respectively, and conditional branch jump information is obtained by addition; (3) according to the conditional branch jump information, combined with JCC1 of the entry1 hit in the ZBTB, jump judgment is performed, (4) the jump judgment result and the signal of the ZBTB hit are logically ANDed to give the final ZBTB prediction result.

[0034] As shown in the above process, the Tag field, the Val field, the Target field and the JCC field need to be stored in the ZBTB, wherein the Tag field is used as the identification of the entry, the Val field is used to indicate whether the entry is valid, such as 1 indicating valid and 0 indicating invalid, the Target field is used to indicate the target address of the entry, and the JCC field is used to indicate the branch type of the entry, such as 11 representing conditional branch, 10 representing unconditional branch, and 00 representing no ZBTB branch. Figure 2

[0035] From the above, in the prediction process of the ZBTB, the prediction result cannot be given until the direction predictor obtains the conditional branch jump information and combines the branch type of the ZBTB. This part of the timing logic cannot be omitted, so that the logic depth of the ZBTB in the prior art is large, the capacity of the ZBTB is difficult to improve, and it is not conducive to improving the prediction speed of the BP.

[0036] To solve the above problems, as shown in the above process, the disclosure embodiment provides a branch prediction method, which comprises: Figure 3 Step S1, the jump threshold of the first direction predictor is divided into at least a first jump threshold and a second jump threshold.

[0037] The first jump threshold corresponds to the unconditional branch of the zero-delay branch target buffer, and the second jump threshold corresponds to the conditional branch of the zero-delay branch target buffer. The above first jump threshold and second jump threshold respectively represent a type of jump threshold, rather than a specific value of a jump threshold, and the specific value of the jump threshold also needs to be configured according to various different situations of the first direction predictor.

[0038] In this step, the first jump threshold and the second jump threshold of the first direction predictor correspond to the unconditional branch and the conditional branch of the ZBTB respectively, so that the first jump threshold and the second jump threshold themselves embody the branch type (unconditional branch or conditional branch) of the ZBTB, providing a basis for simplifying the subsequent branch prediction logic. ​​

[0039] Optionally, in the embodiments of the present disclosure, the second jump threshold value and the conditional branch of the ZBTB can have a one-to-one relationship or a many-to-one relationship. If they have a many-to-one relationship, the multiple second jump threshold values obtained in the prediction process all need to participate in the subsequent calculation process to determine the final jump prediction result.

[0040] In the embodiments of the present disclosure, dividing the jump threshold value of the first direction predictor into at least a first jump threshold value and a second jump threshold value includes multiple cases. For example, the jump threshold value of the first direction predictor is divided into only the first jump threshold value and the second jump threshold value. For another example, the jump threshold value of the first direction predictor is divided into the first jump threshold value, the second jump threshold value, and other jump threshold values. For example, the jump threshold value of the first direction predictor is divided into the first jump threshold value, the second jump threshold value, and a third jump threshold value. The third jump threshold value corresponds to a branch not contained in the zero-delay branch target buffer. When the jump threshold value of the first direction predictor is divided into the first jump threshold value, the second jump threshold value, and the third jump threshold value, the branch prediction method further includes: if the determined jump threshold value corresponding to the first direction predictor is the third jump threshold value, determining the jump prediction result according to the sign of the third jump threshold value.

[0041] Optionally, in the embodiments of the present disclosure, the first direction predictor is a PC index direction predictor. The jump threshold value of the PC index direction predictor is actually a counter with a sign bit. The jump threshold value is trained according to the result of the executed instruction. If the jump occurs, the corresponding jump threshold value is increased by 1. If the jump does not occur, the corresponding jump threshold value is decreased by 1.

[0042] Optionally, in the embodiments of the present disclosure, the first jump threshold value has a first bit number, and the second jump threshold value has a second bit number. The first bit number and the second bit number satisfy: the first bit number is greater than the bit number of the jump threshold value of the other direction predictor, and the second bit number is consistent with the bit number of the jump threshold value of the other direction predictor.

[0043] For example, the first jump threshold value includes a fixed sign bit, an interval bit, and a value bit. The bit number of the value bit of the first jump threshold value is the same as the second bit number. Since the second bit number is consistent with the bit number of the jump threshold value of the other direction predictor, even if the first jump threshold value is added to the jump threshold value of the other direction predictor, the sign of the addition result will always be the same as the sign of the first jump threshold value, and the final jump prediction result will not be affected.

[0044] The second jump threshold value does not have the fixed sign bit and the interval bit compared with the first jump threshold value, and has the same representation form as the prior art, representing the positive or negative value corresponding to the entry of the specific hit by a specific form. The value bit in the first jump threshold value can be consistent with the form of the second jump threshold value to reduce the complexity of the design, but the sign bit contained in the representation form of the value bit of the first jump threshold value does not have any actual effect, and the sign bit contained in the representation form of the second jump threshold value has an effect on the sign of the final addition calculation result.

[0045] Optionally, in the case that the jump threshold value of the first direction predictor is divided into the first jump threshold value, the second jump threshold value and the third jump threshold value, the third jump threshold value has a third bit number corresponding to the case that the branch is not contained in the zero-delay branch target buffer, and the third bit number satisfies: the third bit number is greater than the bit number of the jump threshold value of the other direction predictor.

[0046] Exemplarily, the third jump threshold value includes the fixed sign bit, the interval bit and the value bit, and the bit number of the value bit of the third jump threshold value is the same as the second bit number. Since the second bit number is consistent with the bit number of the jump threshold value of the other direction predictor, such setting can make the sign of the addition operation result always the same as the sign of the third jump threshold value even if the third jump threshold value is added with the jump threshold value of the other direction predictor, and does not affect the final jump prediction result. Similarly, the value bit in the third jump threshold value can be consistent with the form of the second jump threshold value to reduce the complexity of the design, but the sign bit contained in the representation form of the value bit of the third jump threshold value does not have any actual effect.

[0047] Further, the fixed sign bit included in the first jump threshold value and / or the fixed sign bit included in the third jump threshold value occupies at least one bit, and the interval bit included in the first jump threshold value and / or the interval bit included in the third jump threshold value occupies at least one bit. The specific selection of the bit number of the fixed sign bit and the interval bit can be determined by comprehensively considering the timing logic and the performance result. If more attention is paid to the timing logic, a smaller bit number can be set, and if more attention is paid to the performance result, a larger bit number can be set. Optionally, in the embodiment of the present disclosure, the fixed sign bit occupies 1 bit and the interval bit occupies 1 bit to have both the timing logic and the performance result.

[0048] In this embodiment of the disclosure, the other direction predictors can be one or more direction predictors other than the first direction predictor. If there are multiple direction predictors, the number of the first bit must be greater than the number of bits of the jump threshold of all other direction predictors, so that the sign of the first jump threshold remains unchanged after being added to the jump thresholds of any or all other direction predictors. A similar setting applies to the third bit. Optionally, in this embodiment of the disclosure, the other direction predictor is an HP index direction predictor.

[0049] Taking the first direction predictor as the PC index direction predictor and the other direction predictors as the HP index direction predictors as an example, the bias of each entry in the HP BIAS is 3 bits, with the highest bit being the sign bit. In the prior art, the bias of each entry in the PC BIAS is also 3 bits, with the highest bit being the sign bit. Therefore, in this embodiment, the PC BIAS can be configured as 5 bits. The PC Bias corresponding to the unconditional branch of ZBTB is 01000 (0 is the fixed sign bit, 1 is the interval bit, and 000 is the value bit, corresponding to the specific case of the entry). The PC Bias corresponding to the conditional branch of ZBTB is still 3 bits without special processing, and its representation is consistent with the above value bit. When it is not a branch type visible to ZBTB or ZBTB does not have this branch, the corresponding PC Bias is 11000 (1 is the fixed sign bit, 1 is the interval bit, and 000 is the value bit, corresponding to the specific case of the entry). That is to say, the PC BIAS will have three cases: 11000, 01000, and normal BIAS.

[0050] Step S2: Based on the hit result of the zero-delay branch target buffer, determine the jump threshold corresponding to the first direction predictor and the jump thresholds of other direction predictors.

[0051] For example, such as Figure 4 As shown, NIP is sent to ZBTB to check if there is a hit. If entry1 is hit, the first direction predictor determines the corresponding jump threshold based on the hit entry1, and the other direction predictors also determine the corresponding jump threshold based on the hit entry1.

[0052] Step S3: Determine whether the jump threshold corresponding to the determined first direction predictor is the first jump threshold or the second jump threshold; For example, if the hit entry1 is a non-conditional branch, the corresponding jump threshold is the first jump threshold; if the hit entry1 is a conditional branch, the corresponding jump threshold is the second jump threshold.

[0053] When dividing the jump threshold of the first direction predictor into a first jump threshold, a second jump threshold, and a third jump threshold, a similar method can be used to determine whether the corresponding jump threshold is the third jump threshold.

[0054] Step S4: When the jump threshold corresponding to the determined first direction predictor is the first jump threshold, determine the jump prediction result according to the sign of the first jump threshold; Different signs of the first jump threshold indicate different jump results. For example, if the sign bit of the first jump threshold is 0, a jump result is given; if the sign bit of the first jump threshold is 1, a non-jump result is given.

[0055] When a first jump threshold has a first number of bits and a second jump threshold has a second number of bits, and the first and second numbers satisfy the following: the first number of bits is greater than the number of bits of the jump thresholds of other direction predictors, and the second number of bits is the same as the number of bits of the jump thresholds of other direction predictors, determining the jump prediction result based on the sign of the first jump threshold can include two cases: First, without performing an addition calculation, the sign of the first jump threshold is directly used as the final sign to determine the jump prediction result; Second, such as... Figure 4 As shown, the first jump threshold is added to the jump thresholds of other direction predictors. Since the number of bits in the first jump threshold is greater than the number of bits in the jump thresholds of other direction predictors, the sign of the addition result remains consistent with the sign of the first jump threshold. The jump prediction result is determined based on the sign of the addition result, which is essentially determining the jump prediction result based on the sign of the first jump threshold. Using the first method reduces the number of addition operations. While the second method requires additional addition operations, it does not require adjustments to the logic and architecture of the existing direction predictor. Those skilled in the art can choose according to their actual needs.

[0056] The specific method for the above addition operation can be: the first jump threshold corresponding to the first direction predictor and the jump threshold corresponding to the other direction predictors are directly added together, which is equivalent to them having the same weight; or, the weight of the jump threshold corresponding to each direction predictor is determined according to the test set, and the addition is performed according to the weight.

[0057] Similarly, when the jump threshold corresponding to the determined first direction predictor is the third jump threshold, the jump prediction result is determined according to the sign of the third jump threshold.

[0058] Step S5: If the jump threshold corresponding to the determined first direction predictor is the second jump threshold, then the second jump threshold is added to the jump thresholds of other direction predictors. The jump prediction result is determined according to the sign of the addition result.

[0059] The specific method for the above addition operation can be: the second jump threshold corresponding to the first direction predictor is directly added to the jump threshold corresponding to other direction predictors, which is equivalent to them having the same weight; or, the weight of the jump threshold corresponding to each direction predictor is determined according to the test set, and the addition is performed according to the weight.

[0060] Taking the first direction predictor as the PC index direction predictor and the other direction predictors as the HP index direction predictors as an example, the steps S3 to S5 will be illustrated. During branch prediction, there are three possible scenarios: Scenario 1: PCBIAS is 01000, indicating that the entry hit in ZBTB is an unconditional branch. Regardless of whether HP BIAS is any one of 100 (-4) to 011 (+3) or whether additive calculation is performed, the jump is determined based on the highest sign bit of PC BIAS being 0. Scenario 2: PC BIAS is 11000, indicating that there is no such branch in ZBTB or ZBTB does not support this type of branch. Regardless of whether HP BIAS is any one of 100 (-4) to 011 (+3) or whether additive calculation is performed, the jump is determined based on the highest sign bit of PC BIAS being 1. Scenario 3: PC BIAS is neither 11000 nor 01000, indicating that it is a conditional branch, and additive calculation can be performed in the usual way.

[0061] Optionally, when the first direction predictor is a PC index direction predictor, the branch prediction method in this embodiment further includes: after the zero-latency branch target buffer is updated, the first jump threshold and the second jump threshold in the PC index direction predictor are updated using the current PC. The above steps can, on the one hand, configure the corresponding number of bits for the first jump threshold and the second jump threshold in the PC index direction predictor according to the previously described rules, and on the other hand, after the number of bits has been configured, make the first jump threshold and the second jump threshold more accurately correspond to the jump result after execution.

[0062] like Figure 4 As shown, after determining the jump prediction result, it can be directly ANDed with the ZBTB hit signal. Figure 2 Compared to the previous approach, this reduces the logic of jumping between the result of the addition operation and the JCC stored in ZBTB. This reduction in logic allows for a two-level logical cell in ZBTB's microarchitecture. Figure 2 Optimization of jmp | jcc & JccTaken.

[0063] In the branch prediction method provided by the embodiments of the present disclosure, the jump threshold of the first direction predictor is divided into at least a first jump threshold and a second jump threshold, the first jump threshold and the second jump threshold correspond to the unconditional branch and the conditional branch of the ZBTB respectively, so that the first jump threshold and the second jump threshold themselves embody the branch type (unconditional branch or conditional branch) of the ZBTB. When the jump threshold corresponding to the first direction predictor is determined to be the first jump threshold, the sign of the first jump threshold is used to determine the jump prediction result. When the jump threshold corresponding to the first direction predictor is determined to be the second jump threshold, the second jump threshold is added to the jump threshold of the other direction predictor, and the sign of the addition result is used to determine the jump prediction result. Compared with the prior art, the above two cases both reduce the logic of combining the branch type of the hit branch of the ZBTB for jump judgment, thereby helping to reduce the logic depth of the ZBTB, improve the capacity of the ZBTB, and further improve the prediction speed of the BP.

[0064] In addition, the embodiments of the present disclosure also provide a branch prediction device, as shown in Figure 5 The branch prediction device comprises: The threshold dividing module 10 is configured to divide the jump threshold of the first direction predictor into at least a first jump threshold and a second jump threshold, the first jump threshold corresponding to the unconditional branch of the ZBTB, and the second jump threshold corresponding to the conditional branch of the ZBTB. The threshold determining module 20 is configured to determine the jump threshold corresponding to the first direction predictor and the jump threshold of the other direction predictor according to the hit result of the ZBTB. The jump prediction module 30 is configured to, when the jump threshold corresponding to the first direction predictor is determined to be the first jump threshold, determine the jump prediction result according to the sign of the first jump threshold, and when the jump threshold corresponding to the first direction predictor is determined to be the second jump threshold, add the second jump threshold to the jump threshold of the other direction predictor, and determine the jump prediction result according to the sign of the addition result.

[0065] The specific details of each step of the above branch prediction method are applicable to the corresponding modules of the branch prediction device, and will not be described here.

[0066] In addition, the embodiments of the present disclosure also provide a branch prediction system, which comprises: a ZBTB, a first-level BTB, a second-level BTB, and the above-mentioned branch prediction device corresponding to the ZBTB. The cascade mode of the ZBTB, the first-level BTB and the second-level BTB is as shown in Figure 1The capacity and form of the ZBTB in the embodiments of the present disclosure are not limited, as long as it is a zero-delay BTB.

[0067] Optionally, only the Tag field, the Val field and the Target field of each entry are saved in the zero-delay branch target buffer. The Tag field is used as the identification of the entry, the Val field is used to indicate whether the entry is valid, 1 indicating valid and 0 indicating invalid, and the Target field is used to indicate the target address of the entry. Compared with the saved content in the prior art, 2 bits of JCC information are reduced, and the structure of the ZBTB is optimized.

[0068] The computer device according to the embodiments of the present disclosure includes a memory and a processor. The memory is configured to store non-transitory computer readable instructions. Specifically, the memory can include one or more computer program products, which can include various forms of computer readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may, for example, include random access memory (RAM), cache memory, and / or the like. The non-volatile memory may, for example, include read-only memory (ROM), hard disk, flash memory, and / or the like.

[0069] The processor can be a central processing unit (CPU) or other forms of processing units having data processing and / or instruction execution capabilities, and can control other components in the computer device to perform desired functions. In one embodiment of the present disclosure, the processor is configured to execute the computer readable instructions stored in the memory, so that the computer device performs all or part of the steps of the branch prediction method according to the embodiments of the present disclosure.

[0070] Those skilled in the art should understand that, in order to solve the technical problem of how to obtain a good user experience effect, the embodiments of the present disclosure can also include well-known structures such as communication buses, interfaces, and the like, which should also be included in the protection scope of the present disclosure.

[0071] Figure 6 A structural schematic diagram of a computer device according to an embodiment of the present disclosure is provided. The structural schematic diagram shows the structure of a computer device suitable for implementing the computer device according to the embodiments of the present disclosure. Figure 6 The computer device shown is only an example, and should not limit the functions and use range of the embodiments of the present disclosure.

[0072] As Figure 6As shown, the computer device can include a processor (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to programs stored in a read-only memory (ROM) or loaded into a random access memory (RAM) from a storage device. In the RAM, various programs and data required for the operation of the computer device are also stored. The processor, the ROM, and the RAM are connected to each other through a bus. An input / output (I / O) interface is also connected to the bus.

[0073] Generally, the following devices can be connected to the I / O interface: input devices including, for example, a sensor or a visual information collection device; output devices including, for example, a display screen; storage devices including, for example, a magnetic tape, a hard disk, etc.; and communication devices. The communication devices can allow the computer device to communicate wirelessly or wired with other devices (such as edge computing devices) to exchange data. Although Figure 6 The computer device is shown with various devices, but it should be understood that all of the shown devices are not required to be implemented or present. More or fewer devices can alternatively be implemented or present.

[0074] In particular, according to embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network through the communication device, or installed from the storage device, or installed from the ROM. When the computer program is executed by the processor, all or part of the steps of the branch prediction method of the embodiments of the present disclosure are performed.

[0075] Detailed descriptions of the embodiments can refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0076] A computer-readable storage medium according to embodiments of the present disclosure has non-transitory computer-readable instructions stored thereon. When the non-transitory computer-readable instructions are run by a processor, all or part of the steps of the branch prediction method of the embodiments of the present disclosure described above are performed.

[0077] The computer-readable storage medium described above includes, but is not limited to, an optical storage medium (e.g., CD-ROM and DVD), a magneto-optical storage medium (e.g., MO), a magnetic storage medium (e.g., magnetic tape or a mobile hard disk), a medium with a built-in rewritable non-volatile memory (e.g., a memory card), and a medium with a built-in ROM (e.g., a ROM cartridge).

[0078] Detailed descriptions of the embodiments can refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0079] The above describes the basic principles of the present disclosure in conjunction with specific embodiments, but it should be noted that the advantages, benefits, effects and the like mentioned in the present disclosure are only examples and are not limiting, and these advantages, benefits, effects and the like cannot be considered as necessary for each embodiment of the present disclosure. In addition, the specific details of the above disclosure are only for the purpose of example and for the purpose of understanding, and are not limiting, and the above details do not limit the present disclosure to be necessarily implemented with the above specific details.

[0080] In the present disclosure, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. The block diagrams of the devices, apparatuses, equipment, systems involved in the present disclosure are only illustrative examples and are not intended to require or imply the connection, arrangement, configuration as shown in the block diagram. As those skilled in the art will recognize, these devices, apparatuses, equipment, systems can be connected, arranged, configured in any manner. The words such as "include", "contain", "have" and the like are open-ended words, which mean "including but not limited to", and can be used interchangeably. The words "or" and "and" used herein mean the word "and / or", and can be used interchangeably unless the context clearly indicates otherwise. The word "such as" used herein means the phrase "such as but not limited to", and can be used interchangeably.

[0081] In addition, as used herein, "or" used in the listing of items "at least one of the items" indicates a disjunctive list, such that, for example, a list of "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). In addition, the word "example" does not mean that the described example is preferred or better than other examples.

[0082] It should also be noted that in the systems and methods of the present disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalents of the present disclosure.

[0083] Various changes, substitutions and alterations can be made to the technology described herein without departing from the teachings of the technology defined by the appended claims. In addition, the scope of the claims of the present disclosure is not limited to the specific aspects of the process, machine, manufacture, composition of matter, means, methods and acts described above. Processes, machines, manufacture, compositions of matter, means, methods or acts currently existing or later developed that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Accordingly, the appended claims include within their scope such processes, machines, manufacture, compositions of matter, means, methods or acts.

[0084] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0085] The above description has been presented to enable any person skilled in the art to make or use the disclosure. Furthermore, the purpose of the above description is not intended to limit the embodiments of the present disclosure to the form disclosed herein. Although various example aspects and embodiments have been discussed above, those of ordinary skill in the art will appreciate a variety of modifications, alternatives, permutations, additions, and sub-combinations, which fall within the scope of the disclosed aspects.

Claims

1. A branch prediction method, characterized in that, include: The jump threshold of the first direction predictor is divided into at least a first jump threshold and a second jump threshold, wherein the first jump threshold corresponds to the unconditional branch of the zero-delay branch target buffer, and the second jump threshold corresponds to the conditional branch of the zero-delay branch target buffer; Based on the hit result of the zero-delay branch target buffer, determine the jump threshold corresponding to the first direction predictor and the jump thresholds of other direction predictors; If the jump threshold corresponding to the determined first direction predictor is the first jump threshold, then the jump prediction result is determined according to the sign of the first jump threshold. If the jump threshold corresponding to the determined first direction predictor is the second jump threshold, then the second jump threshold is added to the jump thresholds of other direction predictors, and the jump prediction result is determined according to the sign of the addition result.

2. The branch prediction method according to claim 1, characterized in that, The first jump threshold has a first number of bits, and the second jump threshold has a second number of bits. The first number of bits and the second number of bits satisfy the following conditions: the first number of bits is greater than the number of bits of the jump threshold of other direction predictors, and the second number of bits is the same as the number of bits of the jump threshold of other direction predictors.

3. The branch prediction method according to claim 2, characterized in that, The first jump threshold includes a fixed sign bit, an interval bit, and a value bit, and the number of bits in the value bit of the first jump threshold is the same as the number of bits in the second jump threshold.

4. The branch prediction method according to claim 1, characterized in that, The jump threshold of the first direction predictor is divided into a first jump threshold, a second jump threshold, and a third jump threshold; The third jump threshold corresponds to a branch that is not included in the zero-latency branch target buffer; The branch prediction method further includes: if the jump threshold corresponding to the determined first direction predictor is a third jump threshold, then the jump prediction result is determined according to the sign of the third jump threshold.

5. The branch prediction method according to claim 4, characterized in that, The third jump threshold has a third number of bits, which satisfies the following condition: the third number of bits is greater than the number of bits of the jump threshold of other direction predictors.

6. The branch prediction method according to claim 5, characterized in that, The third jump threshold includes a fixed sign bit, an interval bit, and a value bit, and the number of bits in the value bit of the third jump threshold is the same as the number of bits in the second jump threshold.

7. The branch prediction method according to claim 3 or 6, characterized in that, The fixed sign bit occupies at least one bit, and the interval bit occupies at least one bit.

8. The branch prediction method according to claim 1, characterized in that, The first direction predictor is a PC index direction predictor, and the branch prediction method further includes: after the zero-latency branch target buffer is updated, updating the first jump threshold and the second jump threshold in the PC index direction predictor using the current PC.

9. A branch prediction device, characterized in that, include: The threshold division module is used to divide the jump threshold of the first direction predictor into at least a first jump threshold and a second jump threshold, wherein the first jump threshold corresponds to the unconditional branch of the zero-delay branch target buffer, and the second jump threshold corresponds to the conditional branch of the zero-delay branch target buffer; The threshold determination module is used to determine the jump threshold corresponding to the first direction predictor and the jump threshold of other direction predictors based on the hit result of the zero-delay branch target buffer. The jump prediction module is used to determine the jump prediction result based on the sign of the first jump threshold when the jump threshold corresponding to the first direction predictor is the first jump threshold, and to perform an addition operation on the second jump threshold and the jump thresholds of other direction predictors when the jump threshold corresponding to the first direction predictor is the second jump threshold, and to determine the jump prediction result based on the sign of the addition operation result.

10. A branch prediction system, comprising: A zero-latency branch target buffer, a first-level branch target buffer, a second-level branch target buffer, and a branch prediction device as described in claim 9 corresponding to the zero-latency branch target buffer.

11. The branch prediction system according to claim 10, characterized in that, The zero-latency branch target buffer only stores the Tag field, Val field, and Target field for each entry.

12. A computer device, characterized in that, The computer device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the branch prediction method according to any one of claims 1 to 8.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the branch prediction method according to any one of claims 1 to 8.

14. A computer program product comprising computer instructions, characterized in that, When executed by a processor, the computer instructions implement the steps of the branch prediction method according to any one of claims 1 to 8.

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