Branch prediction method, apparatus, system, computer device, medium and product
By dividing the jump threshold of the first direction predictor into unconditional and conditional branches, the branch prediction logic is simplified, the capacity and branch prediction speed of ZBTB are improved, and the problem of large logic depth and difficult capacity improvement in ZBTB in the prior art is solved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HYGON INFORMATION TECH CO LTD
- Filing Date
- 2025-08-15
- Publication Date
- 2026-05-12
AI Technical Summary
In existing technologies, ZBTB has a large logic depth, making it difficult to increase capacity and affecting the branch prediction speed of high-performance processors.
The jump threshold of the first direction predictor is divided into a first jump threshold and a second jump threshold, which correspond to the unconditional branch and conditional branch of the zero-delay branch target buffer, respectively. The jump prediction result is determined by determining the sign or addition operation of the jump threshold, thereby reducing the jump judgment logic of branch types.
The logic depth of ZBTB was reduced, and the capacity of ZBTB was increased, thereby improving the speed of branch prediction.
Smart Images
Figure CN121029243B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of branch prediction technology, and in particular to a branch prediction method, apparatus, system, computer device, medium and product. Background Technology
[0002] The development of high-performance processors demands that branch prediction (BP) be as fast as possible while improving prediction accuracy. Currently, BP microarchitectures with multi-level branch buckets (BTBs) are commonly used for branch prediction. Typical BP microarchitectures include ZBTB, L1BTB, and L2BTB. ZBTB has a small capacity and the lowest prediction latency, typically 0 cycles; L1BTB has a slightly larger capacity and a prediction latency of 1-2 cycles; L2BTB has a very large capacity and a prediction latency of 3-4 cycles.
[0003] In the prediction process, after obtaining the ZBTB hit result, it is necessary to further combine the branch type of the hit branch of ZBTB with the direction prediction result of the direction predictor in order to give the jump prediction result. The inventors found that the above-mentioned combination logic is essential to the microarchitecture of ZBTB, which makes the logic depth of ZBTB in the prior art relatively large, making it difficult to increase the capacity of ZBTB and hindering the improvement of BP prediction speed. Summary of the Invention
[0004] In view of this, embodiments of the present disclosure provide a branch prediction method, apparatus, system, computer device, medium, and product that can help reduce the logic depth of ZBTB, increase the capacity of ZBTB, and thus improve the prediction speed of BP.
[0005] In a first aspect, embodiments of this disclosure provide a branch prediction method, employing the following technical solution:
[0006] The branch prediction method includes:
[0007] The jump threshold of the first direction predictor is divided into at least a first jump threshold and a second jump threshold, wherein the first jump threshold corresponds to the unconditional branch of the zero-delay branch target buffer, and the second jump threshold corresponds to the conditional branch of the zero-delay branch target buffer;
[0008] Based on the hit result of the zero-delay branch target buffer, determine the jump threshold corresponding to the first direction predictor and the jump thresholds of other direction predictors;
[0009] If the jump threshold corresponding to the determined first direction predictor is the first jump threshold, then the jump prediction result is determined according to the sign of the first jump threshold.
[0010] If the jump threshold corresponding to the determined first direction predictor is the second jump threshold, then the second jump threshold is added to the jump thresholds of other direction predictors, and the jump prediction result is determined according to the sign of the addition result.
[0011] Optionally, the first jump threshold has a first number of bits, and the second jump threshold has a second number of bits, wherein the first number of bits and the second number of bits satisfy the following: the first number of bits is greater than the number of bits of the jump threshold of other direction predictors, and the second number of bits is consistent with the number of bits of the jump threshold of other direction predictors.
[0012] Optionally, the first jump threshold includes a fixed sign bit, an interval bit, and a value bit, wherein the number of bits in the value bit of the first jump threshold is the same as the number of bits in the second jump threshold.
[0013] Optionally, the jump threshold of the first direction predictor is divided into a first jump threshold, a second jump threshold, and a third jump threshold; the third jump threshold corresponds to a branch not included in the zero-latency branch target buffer; the branch prediction method further includes: if the determined jump threshold corresponding to the first direction predictor is the third jump threshold, then the jump prediction result is determined according to the sign of the third jump threshold.
[0014] Optionally, the third jump threshold has a third number of bits, which satisfies the following condition: the third number of bits is greater than the number of bits of the jump threshold of other direction predictors.
[0015] Optionally, the third jump threshold includes a fixed sign bit, an interval bit, and a value bit, wherein the number of bits in the value bit of the third jump threshold is the same as the number of bits in the second jump threshold.
[0016] Optionally, the fixed sign bit occupies at least one bit, and the interval bit occupies at least one bit.
[0017] Optionally, the fixed sign bit occupies 1 bit, and the interval bit occupies 1 bit.
[0018] Optionally, the first direction predictor is a PC index direction predictor; the other direction predictors are HP index direction predictors.
[0019] Optionally, the first direction predictor is a PC index direction predictor; the branch prediction method further includes: after the zero-latency branch target buffer is updated, updating the first jump threshold and the second jump threshold in the PC index direction predictor using the current PC.
[0020] Secondly, this disclosure also provides a branch prediction device, which adopts the following technical solution:
[0021] The branch prediction device includes:
[0022] The threshold division module is used to divide the jump threshold of the first direction predictor into at least a first jump threshold and a second jump threshold, wherein the first jump threshold corresponds to the unconditional branch of the zero-delay branch target buffer, and the second jump threshold corresponds to the conditional branch of the zero-delay branch target buffer;
[0023] The threshold determination module is used to determine the jump threshold corresponding to the first direction predictor and the jump threshold of other direction predictors based on the hit result of the zero-delay branch target buffer.
[0024] The jump prediction module is used to determine the jump prediction result based on the sign of the first jump threshold when the jump threshold corresponding to the first direction predictor is the first jump threshold, and to perform an addition operation on the second jump threshold and the jump thresholds of other direction predictors when the jump threshold corresponding to the first direction predictor is the second jump threshold, and to determine the jump prediction result based on the sign of the addition operation result.
[0025] Thirdly, this disclosure also provides a branch prediction system, which adopts the following technical solution:
[0026] The branch prediction system includes: a zero-latency branch target buffer, a first-level branch target buffer, a second-level branch target buffer, and the branch prediction device described above corresponding to the zero-latency branch target buffer.
[0027] Optionally, the zero-latency branch target buffer stores only the Tag field, Val field, and Target field for each entry.
[0028] Fourthly, this disclosure also provides a branch prediction system, which adopts the following technical solution:
[0029] The computer device includes:
[0030] At least one processor; and,
[0031] A memory communicatively connected to the at least one processor; wherein,
[0032] The memory stores instructions that can be executed by the at least one processor, which, when executed, enable the at least one processor to perform any of the branch prediction methods described above.
[0033] Fifthly, this disclosure also provides a branch prediction system, which adopts the following technical solution:
[0034] The computer-readable storage medium stores computer instructions for causing the computer to perform any of the branch prediction methods described above.
[0035] Sixthly, this disclosure also provides a computer program product, which adopts the following technical solution:
[0036] The computer program product includes computer instructions that, when executed by a processor, implement the steps of any of the branch prediction methods described above.
[0037] In the branch prediction method provided in this embodiment, since the jump threshold of the first direction predictor is divided into at least a first jump threshold and a second jump threshold, and the first jump threshold and the second jump threshold correspond to the unconditional branch and conditional branch of ZBTB respectively, the first jump threshold and the second jump threshold themselves already reflect the branch type (unconditional branch or conditional branch) of ZBTB. When the jump threshold corresponding to the determined first direction predictor is the first jump threshold, the jump prediction result can be determined according to the sign of the first jump threshold. When the jump threshold corresponding to the determined first direction predictor is the second jump threshold, the second jump threshold is added to the jump thresholds of other direction predictors, and the jump prediction result can be determined according to the sign of the addition result. Compared with the prior art, both of the above cases reduce the logic of combining the branch type of the hit ZBTB for jump judgment, which can help reduce the logic depth of ZBTB, increase the capacity of ZBTB, and thus improve the prediction speed of BP.
[0038] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0039] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0040] Figure 1 A schematic diagram of the BP microarchitecture provided in an embodiment of this disclosure;
[0041] Figure 2 A schematic diagram of the ZBTB prediction process provided in this embodiment of the disclosure. Figure 1 ;
[0042] Figure 3 A flowchart of the branch prediction method provided in the embodiments of this disclosure;
[0043] Figure 4 A schematic diagram of the ZBTB prediction process provided in this embodiment of the disclosure. Figure 2 ;
[0044] Figure 5 A schematic diagram of a branch prediction device provided in an embodiment of this disclosure;
[0045] Figure 6 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present disclosure. Detailed Implementation
[0046] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.
[0047] It should be understood that the following specific examples illustrate the implementation of this disclosure, and those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.
[0048] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.
[0049] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0050] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.
[0051] Explanation of abbreviations:
[0052] BP: branch prediction;
[0053] ZBTB: Zero-bubble branch target buffer;
[0054] L1BTB: Level 1 branch target buffer;
[0055] L2BTB: Level 2 branch target buffer.
[0056] SRAM: Static Random Access Memory;
[0057] PC-indexed direction predictor;
[0058] HP Index Direction Predictor: Hashed Perceptron Predictor.
[0059] Ideally, a BP should be a ZBTB with the largest possible capacity. However, the number of entries and supported branch types in a ZBTB are limited by the clock speed, preventing effective improvements. To meet the requirements of speed and accuracy, such as... Figure 1 As shown, this disclosure provides a BP microarchitecture including ZBTB, L1BTB, and L2BTB multi-level BTBs. ZBTB has a small capacity but high speed, while L1BTB / L2BTB have large capacity but slow speed. ZBTB has the smallest capacity and the smallest prediction latency, typically 0 cycles, meaning the linear address can be updated within one cycle. L1BTB has a slightly larger capacity and a prediction latency typically of 1-2 cycles. L2BTB has a very large capacity and a prediction latency typically of 3-4 cycles.
[0060] In a BP microarchitecture with the above structure, the branch prediction process includes: The Next Instruction PC (the address of the next instruction to be fetched by the processor at the end of the current fetch cycle, abbreviated as NIP) is sequentially loaded into the ZBTB, L1BTB, and L2BTB for multi-level BTB access. A hit is checked; if a hit occurs, the target address is determined based on the direction prediction result to update the NIP. The updated NIP continues to undergo multi-level BTB access in the BP microarchitecture until all BTBs fail to find a hit, at which point the NIP is updated to a sequential address.
[0061] In the above branch prediction process, ZBTB needs to combine the branch type of the entry that hits ZBTB with the result of the direction predictor to give the final jump prediction result. Taking a direction predictor composed of both an HP index direction predictor and a PC index direction predictor as an example, ... Figure 2 As shown, the prediction process of ZBTB includes: (1) After the linear address is input into ZBTB, the entry1 of ZBTB is matched from the N ZBTB entries; (2) The direction predictor is accessed to obtain PC BIAS and HP BIAS respectively, and the conditional branch jump information is obtained by addition; (3) According to this conditional branch jump information, the jump judgment is made in combination with the JCC1 of the entry1 hit by ZBTB; (4) The jump judgment result and the signal hit by ZBTB are logically ANDed to give the final ZBTB prediction result.
[0062] like Figure 2 As shown, in the above process, ZBTB needs to store the Tag field, Val field, Target field, and JCC field. The Tag field is used as the identifier of the entry, the Val field is used to indicate whether the entry is valid (e.g., 1 indicates valid, 0 indicates invalid), the Target field is used to indicate the target address of the entry, and the JCC field is used to indicate the branch type of the entry (e.g., 11 represents a conditional branch, 10 represents an unconditional branch, and 00 represents no ZBTB branch).
[0063] As can be seen from the above, in the ZBTB prediction process, the prediction result can only be given after the direction predictor receives the conditional branch jump information and the ZBTB branch type. This part of the timing logic cannot be omitted, which makes the logic depth of ZBTB in the existing technology relatively large, making it difficult to increase the capacity of ZBTB and hindering the improvement of BP prediction speed.
[0064] To solve the above problems, such as Figure 3 As shown in the embodiments of this disclosure, a branch prediction method is provided, which includes:
[0065] Step S1: Divide the jump threshold of the first direction predictor into at least a first jump threshold and a second jump threshold.
[0066] The first jump threshold corresponds to the unconditional branch of the zero-latency branch target buffer, and the second jump threshold corresponds to the conditional branch of the zero-latency branch target buffer. The first and second jump thresholds represent different types of jump thresholds, rather than specific values. The specific values of the jump thresholds need to be configured according to various conditions of the first direction predictor.
[0067] In this step, the first jump threshold and the second jump threshold of the first direction predictor are respectively assigned to the unconditional branch and the conditional branch of ZBTB, so that the first jump threshold and the second jump threshold themselves already reflect the branch type of ZBTB (unconditional branch or conditional branch), providing a basis for simplifying the subsequent branch prediction logic.
[0068] Optionally, in this embodiment of the disclosure, the relationship between the second jump threshold and the conditional branch of ZBTB can be one-to-one or many-to-one. If the relationship is many-to-one, during the prediction process, all the second jump thresholds queried need to participate in the subsequent calculation process to determine the final jump prediction result.
[0069] In this embodiment of the disclosure, dividing the jump threshold of the first direction predictor into at least a first jump threshold and a second jump threshold includes several cases. Example 1: dividing the jump threshold of the first direction predictor into only a first jump threshold and a second jump threshold. Example 2: dividing the jump threshold of the first direction predictor into a first jump threshold, a second jump threshold, and other jump thresholds. For example, dividing the jump threshold of the first direction predictor into a first jump threshold, a second jump threshold, and a third jump threshold; the third jump threshold corresponds to a branch not included in the zero-latency branch target buffer. When the jump threshold of the first direction predictor is divided into a first jump threshold, a second jump threshold, and a third jump threshold, the branch prediction method further includes: if the determined jump threshold corresponding to the first direction predictor is the third jump threshold, then determining the jump prediction result based on the sign of the third jump threshold.
[0070] Optionally, the first direction predictor in this embodiment is a PC-indexed direction predictor. The jump threshold of the PC-indexed direction predictor is actually a signed counter. This jump threshold is trained based on the result of the executed instruction. If a jump occurs, the corresponding jump threshold is incremented by 1; if no jump occurs, the corresponding jump threshold is decremented by 1.
[0071] Optionally, in this embodiment of the disclosure, the first jump threshold has a first number of bits, and the second jump threshold has a second number of bits. The first number of bits and the second number of bits satisfy the following: the first number of bits is greater than the number of bits of the jump threshold of other direction predictors, and the second number of bits is consistent with the number of bits of the jump threshold of other direction predictors.
[0072] For example, the first jump threshold includes a fixed sign bit, an interval bit, and a value bit. The number of bits in the value bit of the first jump threshold is the same as the number of bits in the second bit. Since the number of bits in the second bit is the same as the number of bits in the jump threshold of other direction predictors, this setting ensures that even if the first jump threshold is added to the jump threshold of other direction predictors, the sign of the addition result will always be the same as the sign of the first jump threshold, and it will not affect the final jump prediction result.
[0073] Compared to the first jump threshold, the second jump threshold does not have a fixed sign bit and interval bit. Its representation is the same as that of the prior art. It represents the positive or negative value corresponding to the specific hit entry in a specific form. The numerical bits in the first jump threshold can be consistent with the form of the second jump threshold to reduce the complexity of the design. However, for the first jump threshold, the sign bit contained in the representation of the numerical bits will not have any practical effect. For the second jump threshold, the sign bit contained in its representation will affect the sign of the final addition calculation result.
[0074] Optionally, when the jump threshold of the first direction predictor is divided into a first jump threshold, a second jump threshold, and a third jump threshold, and the third jump threshold corresponds to a branch not included in the zero-delay branch target buffer, the third jump threshold has a third number of bits, and the third number of bits satisfies the following condition: the third number of bits is greater than the number of bits of the jump thresholds of other direction predictors.
[0075] For example, the third jump threshold includes a fixed sign bit, an interval bit, and a value bit. The number of bits in the value bit of the third jump threshold is the same as the number of bits in the second jump threshold. Since the number of bits in the second jump threshold is the same as the number of bits in the jump thresholds of other direction predictors, this setting ensures that even if the third jump threshold is added to the jump thresholds of other direction predictors, the sign of the addition result will always be the same as the sign of the third jump threshold, and it will not affect the final jump prediction result. Similarly, the value bit in the third jump threshold can be consistent with the form of the second jump threshold to reduce design complexity, but for the third jump threshold, the sign bit included in the representation of the value bit has no practical effect.
[0076] Furthermore, the fixed sign bit included in the first jump threshold, and / or the fixed sign bit included in the third jump threshold, occupies at least one bit, and the interval bit included in the first jump threshold, and / or the interval bit included in the third jump threshold, occupies at least one bit. The specific selection of the number of bits for the fixed sign bit and the interval bit can be determined by comprehensively considering the timing logic and performance results. If more attention is paid to the timing logic, a smaller number of bits can be set; if more attention is paid to the performance results, a larger number of bits can be set. Optionally, in this embodiment of the disclosure, the fixed sign bit occupies 1 bit and the interval bit occupies 1 bit to balance timing logic and performance results.
[0077] In this embodiment of the disclosure, the other direction predictors can be one or more direction predictors other than the first direction predictor. If there are multiple direction predictors, the number of the first bit must be greater than the number of bits of the jump threshold of all other direction predictors, so that the sign of the first jump threshold remains unchanged after being added to the jump thresholds of any or all other direction predictors. A similar setting applies to the third bit. Optionally, in this embodiment of the disclosure, the other direction predictor is an HP index direction predictor.
[0078] Taking the first direction predictor as the PC index direction predictor and the other direction predictors as the HP index direction predictors as an example, the bias of each entry in the HP BIAS is 3 bits, with the highest bit being the sign bit. In the prior art, the bias of each entry in the PC BIAS is also 3 bits, with the highest bit being the sign bit. Therefore, in this embodiment, the PC BIAS can be configured as 5 bits. The PC Bias corresponding to the unconditional branch of ZBTB is 01000 (0 is the fixed sign bit, 1 is the interval bit, and 000 is the value bit, corresponding to the specific case of the entry). The PC Bias corresponding to the conditional branch of ZBTB is still 3 bits without special processing, and its representation is consistent with the above value bit. When it is not a branch type visible to ZBTB or ZBTB does not have this branch, the corresponding PC Bias is 11000 (1 is the fixed sign bit, 1 is the interval bit, and 000 is the value bit, corresponding to the specific case of the entry). That is to say, the PC BIAS will have three cases: 11000, 01000, and normal BIAS.
[0079] Step S2: Based on the hit result of the zero-delay branch target buffer, determine the jump threshold corresponding to the first direction predictor and the jump thresholds of other direction predictors.
[0080] For example, such as Figure 4As shown, NIP is sent to ZBTB to check if there is a hit. If entry1 is hit, the first direction predictor determines the corresponding jump threshold based on the hit entry1, and the other direction predictors also determine the corresponding jump threshold based on the hit entry1.
[0081] Step S3: Determine whether the jump threshold corresponding to the determined first direction predictor is the first jump threshold or the second jump threshold;
[0082] For example, if the hit entry1 is a non-conditional branch, the corresponding jump threshold is the first jump threshold; if the hit entry1 is a conditional branch, the corresponding jump threshold is the second jump threshold.
[0083] When dividing the jump threshold of the first direction predictor into a first jump threshold, a second jump threshold, and a third jump threshold, a similar method can be used to determine whether the corresponding jump threshold is the third jump threshold.
[0084] Step S4: When the jump threshold corresponding to the determined first direction predictor is the first jump threshold, determine the jump prediction result according to the sign of the first jump threshold;
[0085] Different signs of the first jump threshold indicate different jump results. For example, if the sign bit of the first jump threshold is 0, a jump result is given; if the sign bit of the first jump threshold is 1, a non-jump result is given.
[0086] When a first jump threshold has a first number of bits and a second jump threshold has a second number of bits, and the first and second numbers satisfy the following: the first number of bits is greater than the number of bits of the jump thresholds of other direction predictors, and the second number of bits is the same as the number of bits of the jump thresholds of other direction predictors, determining the jump prediction result based on the sign of the first jump threshold can include two cases: First, without performing an addition calculation, the sign of the first jump threshold is directly used as the final sign to determine the jump prediction result; Second, such as... Figure 4 As shown, the first jump threshold is added to the jump thresholds of other direction predictors. Since the number of bits in the first jump threshold is greater than the number of bits in the jump thresholds of other direction predictors, the sign of the addition result remains consistent with the sign of the first jump threshold. The jump prediction result is determined based on the sign of the addition result, which is essentially determining the jump prediction result based on the sign of the first jump threshold. Using the first method reduces the number of addition operations. While the second method requires additional addition operations, it does not require adjustments to the logic and architecture of the existing direction predictor. Those skilled in the art can choose according to their actual needs.
[0087] The specific method for the above addition operation can be: the first jump threshold corresponding to the first direction predictor and the jump threshold corresponding to the other direction predictors are directly added together, which is equivalent to them having the same weight; or, the weight of the jump threshold corresponding to each direction predictor is determined according to the test set, and the addition is performed according to the weight.
[0088] Similarly, when the jump threshold corresponding to the determined first direction predictor is the third jump threshold, the jump prediction result is determined according to the sign of the third jump threshold.
[0089] Step S5: If the jump threshold corresponding to the determined first direction predictor is the second jump threshold, then the second jump threshold is added to the jump thresholds of other direction predictors. The jump prediction result is determined according to the sign of the addition result.
[0090] The specific method for the above addition operation can be: the second jump threshold corresponding to the first direction predictor is directly added to the jump threshold corresponding to other direction predictors, which is equivalent to them having the same weight; or, the weight of the jump threshold corresponding to each direction predictor is determined according to the test set, and the addition is performed according to the weight.
[0091] Taking the first direction predictor as the PC index direction predictor and the other direction predictors as the HP index direction predictors as an example, the steps S3 to S5 will be illustrated. During branch prediction, there are three possible scenarios: Scenario 1: PCBIAS is 01000, indicating that the entry hit in ZBTB is an unconditional branch. Regardless of whether HP BIAS is any one of 100 (-4) to 011 (+3) or whether additive calculation is performed, the jump is determined based on the highest sign bit of PC BIAS being 0. Scenario 2: PC BIAS is 11000, indicating that there is no such branch in ZBTB or ZBTB does not support this type of branch. Regardless of whether HP BIAS is any one of 100 (-4) to 011 (+3) or whether additive calculation is performed, the jump is determined based on the highest sign bit of PC BIAS being 1. Scenario 3: PC BIAS is neither 11000 nor 01000, indicating that it is a conditional branch, and additive calculation can be performed in the usual way.
[0092] Optionally, when the first direction predictor is a PC index direction predictor, the branch prediction method in this embodiment further includes: after the zero-latency branch target buffer is updated, the first jump threshold and the second jump threshold in the PC index direction predictor are updated using the current PC. The above steps can, on the one hand, configure the corresponding number of bits for the first jump threshold and the second jump threshold in the PC index direction predictor according to the previously described rules, and on the other hand, after the number of bits has been configured, make the first jump threshold and the second jump threshold more accurately correspond to the jump result after execution.
[0093] like Figure 4 As shown, after determining the jump prediction result, it can be directly ANDed with the ZBTB hit signal. Figure 2 Compared to the previous approach, this reduces the logic of jumping between the result of the addition operation and the JCC stored in ZBTB. This reduction in logic allows for a two-level logical cell in ZBTB's microarchitecture. Figure 2 Optimization of jmp | jcc & JccTaken.
[0094] In the branch prediction method provided in this embodiment, since the jump threshold of the first direction predictor is divided into at least a first jump threshold and a second jump threshold, and the first jump threshold and the second jump threshold correspond to the unconditional branch and conditional branch of ZBTB respectively, the first jump threshold and the second jump threshold themselves already reflect the branch type (unconditional branch or conditional branch) of ZBTB. When the jump threshold corresponding to the determined first direction predictor is the first jump threshold, the jump prediction result can be determined according to the sign of the first jump threshold. When the jump threshold corresponding to the determined first direction predictor is the second jump threshold, the second jump threshold is added to the jump thresholds of other direction predictors, and the jump prediction result can be determined according to the sign of the addition result. Compared with the prior art, both of the above cases reduce the logic of combining the branch type of the hit ZBTB for jump judgment, which can help reduce the logic depth of ZBTB, increase the capacity of ZBTB, and thus improve the prediction speed of BP.
[0095] Furthermore, embodiments of this disclosure also provide a branch prediction device, such as... Figure 5 As shown, the branch prediction device includes:
[0096] The threshold division module 10 is used to divide the jump threshold of the first direction predictor into at least a first jump threshold and a second jump threshold, wherein the first jump threshold corresponds to the unconditional branch of the zero-delay branch target buffer and the second jump threshold corresponds to the conditional branch of the zero-delay branch target buffer.
[0097] The threshold determination module 20 is used to determine the jump threshold corresponding to the first direction predictor and the jump threshold of other direction predictors based on the hit result of the zero-delay branch target buffer.
[0098] The jump prediction module 30 is used to determine the jump prediction result based on the sign of the first jump threshold when the jump threshold corresponding to the determined first direction predictor is the first jump threshold, and to perform an addition operation on the second jump threshold and the jump thresholds of other direction predictors when the jump threshold corresponding to the determined first direction predictor is the second jump threshold, and to determine the jump prediction result based on the sign of the addition operation result.
[0099] The specific details of each step in the above branch prediction method are applicable to the corresponding module of the branch prediction device, and will not be elaborated here.
[0100] Furthermore, this disclosure also provides a branch prediction system, comprising: a zero-latency branch target buffer, a first-level branch target buffer, a second-level branch target buffer, and the aforementioned branch prediction device corresponding to the zero-latency branch target buffer. The cascading method of the zero-latency branch target buffer, the first-level branch target buffer, and the second-level branch target buffer is as follows: Figure 1 As shown. The capacity and form of the ZBTB in this embodiment are not limited; any zero-latency BTB is acceptable.
[0101] Optionally, the zero-latency branch target buffer only stores the Tag, Val, and Target fields for each entry. The Tag field serves as the entry identifier, the Val field indicates whether the entry is valid (1 for valid, 0 for invalid), and the Target field indicates the target address of the entry. Compared to the content stored in existing technologies, this reduces the amount of JCC information by 2 bits, thus optimizing the ZBTB structure.
[0102] A computer device according to embodiments of the present disclosure includes a memory and a processor. The memory is used to store non-transitory computer-readable instructions. Specifically, the memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may, for example, include random access memory (RAM) and / or cache memory. The non-volatile memory may, for example, include read-only memory (ROM), hard disk, flash memory, etc.
[0103] The processor may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the computer device to perform desired functions. In one embodiment of this disclosure, the processor is used to execute computer-readable instructions stored in the memory, causing the computer device to perform all or part of the steps of the branch prediction methods of the foregoing embodiments of this disclosure.
[0104] Those skilled in the art will understand that, in order to solve the technical problem of how to achieve a good user experience, this embodiment may also include well-known structures such as communication buses and interfaces, and these well-known structures should also be included within the protection scope of this disclosure.
[0105] Figure 6 This is a schematic diagram of a computer device provided for an embodiment of the present disclosure. It illustrates a structural schematic diagram suitable for implementing the computer device in the embodiments of the present disclosure. Figure 6 The computer device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.
[0106] like Figure 6 As shown, a computer device may include a processor (such as a central processing unit, graphics processing unit, etc.), which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) or programs loaded from storage devices into random access memory (RAM). The RAM also stores various programs and data required for the operation of the computer device. The processor, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.
[0107] Typically, the following devices can be connected to the I / O interface: input devices, such as sensors or visual information acquisition devices; output devices, such as displays; storage devices, such as magnetic tapes or hard drives; and communication devices. Communication devices allow the computer device to communicate wirelessly or wiredly with other devices (such as edge computing devices) to exchange data. Although Figure 6 A computer apparatus with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown. More or fewer devices may be implemented or included alternatively.
[0108] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device, or installed from a ROM. When the computer program is executed by a processor, all or part of the steps of the branch prediction method of embodiments of this disclosure are performed.
[0109] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.
[0110] A computer-readable storage medium according to embodiments of the present disclosure stores non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are executed by a processor, all or part of the steps of the branch prediction methods of the foregoing embodiments of the present disclosure are performed.
[0111] The aforementioned computer-readable storage media include, but are not limited to: optical storage media (e.g., CD-ROM and DVD), magneto-optical storage media (e.g., MO), magnetic storage media (e.g., magnetic tape or portable hard drive), media with built-in rewritable non-volatile memory (e.g., memory card), and media with built-in ROM (e.g., ROM cartridge).
[0112] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.
[0113] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.
[0114] In this disclosure, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The block diagrams of devices, apparatuses, devices, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as "comprising," "including," "having," etc., are open-ended terms meaning "including but not limited to," and are used interchangeably with them. The terms "or" and "and" as used herein refer to the terms "and / or," and are used interchangeably with them unless the context clearly indicates otherwise. The term "such as" as used herein refers to the phrase "such as but not limited to," and is used interchangeably with it.
[0115] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.
[0116] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.
[0117] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.
[0118] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.
[0119] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.
Claims
1. A branch prediction method, characterized in that, include: The jump threshold of the first direction predictor is divided into at least a first jump threshold and a second jump threshold, wherein the first jump threshold corresponds to the unconditional branch of the zero-delay branch target buffer, and the second jump threshold corresponds to the conditional branch of the zero-delay branch target buffer; Based on the hit result of the zero-delay branch target buffer, determine the jump threshold corresponding to the first direction predictor and the jump thresholds of other direction predictors; If the jump threshold corresponding to the determined first direction predictor is the first jump threshold, then the jump prediction result is determined according to the sign of the first jump threshold. If the jump threshold corresponding to the determined first direction predictor is the second jump threshold, then the second jump threshold is added to the jump thresholds of other direction predictors, and the jump prediction result is determined according to the sign of the addition result. Wherein, the first jump threshold and the second jump threshold are jump counts with signed bits. The first jump threshold has a first number of bits, and the second jump threshold has a second number of bits. The first number of bits and the second number of bits satisfy the following: the first number of bits is greater than the number of bits of the jump threshold of other direction predictors, and the second number of bits is consistent with the number of bits of the jump threshold of other direction predictors.
2. The branch prediction method according to claim 1, characterized in that, The first jump threshold includes a fixed sign bit, an interval bit, and a value bit, and the number of bits in the value bit of the first jump threshold is the same as the number of bits in the second jump threshold.
3. The branch prediction method according to claim 1, characterized in that, The jump threshold of the first direction predictor is divided into a first jump threshold, a second jump threshold, and a third jump threshold; The third jump threshold corresponds to a branch that is not included in the zero-latency branch target buffer; The branch prediction method further includes: if the jump threshold corresponding to the determined first direction predictor is a third jump threshold, then the jump prediction result is determined according to the sign of the third jump threshold.
4. The branch prediction method according to claim 3, characterized in that, The third jump threshold has a third number of bits, which satisfies the following condition: the third number of bits is greater than the number of bits of the jump threshold of other direction predictors.
5. The branch prediction method according to claim 4, characterized in that, The third jump threshold includes a fixed sign bit, an interval bit, and a value bit, and the number of bits in the value bit of the third jump threshold is the same as the number of bits in the second jump threshold.
6. The branch prediction method according to claim 2 or 5, characterized in that, The fixed sign bit occupies at least one bit, and the interval bit occupies at least one bit.
7. The branch prediction method according to claim 1, characterized in that, The first direction predictor is a PC index direction predictor, and the branch prediction method further includes: after the zero-latency branch target buffer is updated, updating the first jump threshold and the second jump threshold in the PC index direction predictor using the current PC.
8. A branch prediction device, characterized in that, include: The threshold division module is used to divide the jump threshold of the first direction predictor into at least a first jump threshold and a second jump threshold, wherein the first jump threshold corresponds to the unconditional branch of the zero-delay branch target buffer, and the second jump threshold corresponds to the conditional branch of the zero-delay branch target buffer; The threshold determination module is used to determine the jump threshold corresponding to the first direction predictor and the jump threshold of other direction predictors based on the hit result of the zero-delay branch target buffer. The jump prediction module is used to determine the jump prediction result based on the sign of the first jump threshold when the jump threshold corresponding to the first direction predictor is the first jump threshold, and to add the second jump threshold to the jump threshold of other direction predictors when the jump threshold corresponding to the first direction predictor is the second jump threshold, and to determine the jump prediction result based on the sign of the addition result. Wherein, the first jump threshold and the second jump threshold are jump counts with signed bits. The first jump threshold has a first number of bits, and the second jump threshold has a second number of bits. The first number of bits and the second number of bits satisfy the following: the first number of bits is greater than the number of bits of the jump threshold of other direction predictors, and the second number of bits is consistent with the number of bits of the jump threshold of other direction predictors.
9. A branch prediction system, comprising: A zero-latency branch target buffer, a first-level branch target buffer, a second-level branch target buffer, and a branch prediction device as described in claim 8 corresponding to the zero-latency branch target buffer.
10. The branch prediction system according to claim 9, characterized in that, The zero-latency branch target buffer only stores the Tag field, Val field, and Target field for each entry.
11. A computer device, characterized in that, The computer device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the branch prediction method according to any one of claims 1 to 7.
12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the branch prediction method according to any one of claims 1 to 7.
13. A computer program product comprising computer instructions, characterized in that, When executed by a processor, the computer instructions implement the steps of the branch prediction method according to any one of claims 1 to 7.