A memory failure processing method and system

Abstract

The application discloses a memory fault processing method and system, and relates to the technical field of servers.The method comprises the following steps: acquiring first serial bus communication information between a processor and a plurality of memory banks; determining a memory overheating fault type according to the first serial bus communication information between the processor and the plurality of memory banks, and generating a log file of the controller according to the memory overheating fault type data; in response to the fact that no memory bank heat dissipation problem or processor fault problem data is recorded in the log file of the controller, acquiring error data of the first serial bus communication information; and determining a fault type of the error of the first serial bus communication information according to the error data of the first serial bus communication information. According to the application, the memory fault problem caused by the overheating of the memory and the processor can be investigated without the need of opening a machine box, and the time cost and the research and development manpower of detection are reduced.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to a memory fault handling method and system. Background Technology

[0002] In the relevant solution design, after the memory overheating problem occurs, apart from memory temperature being too high and can be read by command, memory overheating caused by the processor itself and memory overheating caused by I3C link failure requires opening the case for measurement. Not all measurement points are on the front, and it is even necessary to disconnect the power and resolder the wires for reproduction and verification, which increases the difficulty of detection. In some cases, it may take several months to reproduce and analyze the situation.

[0003] Related design schemes such as Figure 1 As shown, after a memory overheating event occurs, the controller (BMC, Baseboard Management Controller) can record the event. However, further verification and analysis are needed to determine the cause of the overheating. Typically, the temperature of all memory modules is first checked to see if overheating is present. If overheating is indeed present, the cooling strategy is analyzed. If no overheating is found, it's necessary to determine whether the overheating is caused by the processor itself or by an unresponsive I3C link. This requires opening the chassis for measurement. The first step is to measure the connection from the CPU to the FPGA (Field-Programmable Gate Array). If the memory overheating signal of the array is pulled low, further measurement is needed to determine how many I3C links are abnormal. Here, two difficulties arise: First, if there are many cables and structural heat dissipation layouts inside the chassis, it may be difficult to locate the measurement point; second, even if the measurement point can be located, it is possible to measure which I3C link is abnormal, but because the level is low after an I3C link is abnormal, and because three memory modules are connected on one I3C bus, it is usually necessary to solder wires to determine which one is faulty. This method increases the time cost and R&D manpower cost for production line shipment. Summary of the Invention

[0004] The application provides a memory fault processing method and system. The method comprises the following steps: obtaining first serial bus communication information between a processor and a plurality of memory banks; determining a memory overheating fault type according to the first serial bus communication information between the processor and the plurality of memory banks, generating a log file of a controller according to the memory overheating fault type data, and storing error data of the first serial bus communication information, wherein the memory overheating fault type comprises a memory bank heat dissipation problem and a processor fault problem; in response to the fact that the memory bank heat dissipation problem or the processor fault problem data is not recorded in the log file of the controller, the error data of the first serial bus communication information is obtained; and the fault type of the error of the first serial bus communication information is determined according to the error data of the first serial bus communication information. According to the application, the memory fault problem caused by the overheating of the memory and the processor can be investigated without the need of opening a machine box, and the time cost and the research and development manpower of detection are reduced.

[0005] The application provides a memory fault processing system. The memory fault processing system comprises a controller, a processor, a switching integrated circuit, a logic device, a plurality of switches and a plurality of memory banks. The first output end of the controller is connected with the switching integrated circuit. The switching integrated circuit is connected with the plurality of switches in a one-to-one correspondence. Each switch is connected with the plurality of memory banks in a one-to-one correspondence. The second output end of the controller is connected with the logic device. The logic device is connected with the plurality of switches in a one-to-one correspondence. The logic device is connected with the processor. The processor is connected with the plurality of switches in a one-to-one correspondence. The system further comprises a storage card, and the storage card is connected with the logic device.

[0006] The processor and the plurality of switches are connected through a first serial bus link.

[0007] Each switch and the plurality of memory banks are connected through a first serial bus link in a one-to-one correspondence.

[0008] The controller and the logic device are connected through a second serial bus link.

[0009] The application further provides a memory fault processing method. The method is applied to a controller in a memory fault processing system. The method comprises the following steps:

[0010] Obtaining first serial bus communication information between a processor and a plurality of memory banks.

[0011] Determining a memory overheating fault type according to the first serial bus communication information between the processor and the plurality of memory banks, generating a log file of a controller according to the memory overheating fault type data, and storing error data of the first serial bus communication information, wherein the memory overheating fault type comprises a memory bank heat dissipation problem and a processor fault problem.

[0012] In response to the fact that the memory bar heat dissipation problem or the processor failure problem data is not recorded in the log file of the controller, the error data of the first serial bus communication information is acquired;

[0013] The fault type of the error of the first serial bus communication information is determined according to the error data of the first serial bus communication information.

[0014] The application further provides a memory failure processing system, which comprises a controller, a processor, a switching integrated circuit, a logic device, a plurality of switches and a plurality of memory bars, the first output end of the controller is connected with the switching integrated circuit, the switching integrated circuit is connected with the plurality of switches in a corresponding manner respectively, each switch is connected with the plurality of memory bars in a corresponding manner, the second output end of the controller is connected with the logic device, the logic device is connected with the plurality of switches in a corresponding manner respectively, the logic device is connected with the processor, the processor is connected with the plurality of switches in a corresponding manner respectively, and the controller is used for:

[0015] acquiring the first serial bus communication information between the processor and the plurality of memory bars;

[0016] determining a memory overheating fault type according to the first serial bus communication information between the processor and the plurality of memory bars, generating a log file of the controller according to the memory overheating fault type data, and storing the error data of the first serial bus communication information, wherein the memory overheating fault type comprises a memory bar heat dissipation problem and a processor failure problem;

[0017] In response to the fact that the memory bar heat dissipation problem or the processor failure problem data is not recorded in the log file of the controller, the error data of the first serial bus communication information is acquired;

[0018] The fault type of the error of the first serial bus communication information is determined according to the error data of the first serial bus communication information.

[0019] The application further provides a computer readable storage medium, and the computer readable storage medium stores a computer program, wherein the computer program is executed by a processor to realize the steps of the memory failure processing method, and the method comprises:

[0020] acquiring the first serial bus communication information between the processor and the plurality of memory bars;

[0021] determining a memory overheating fault type according to the first serial bus communication information between the processor and the plurality of memory bars, generating a log file of the controller according to the memory overheating fault type data, and storing the error data of the first serial bus communication information, wherein the memory overheating fault type comprises a memory bar heat dissipation problem and a processor failure problem;

[0022] In response to the fact that the memory bank heat dissipation problem or the processor failure problem data is not recorded in the log file of the controller, the error data of the first serial bus communication information is acquired;

[0023] The fault type of the error of the first serial bus communication information is determined according to the error data of the first serial bus communication information.

[0024] According to the application, since the method comprises acquiring first serial bus communication information between a processor and a plurality of memory banks; determining a memory overheating fault type according to the first serial bus communication information between the processor and the plurality of memory banks, generating a log file of a controller according to the memory overheating fault type data, and storing error data of the first serial bus communication information, wherein the memory overheating fault type comprises a memory bank heat dissipation problem and a processor failure problem; in response to the fact that the memory bank heat dissipation problem or the processor failure problem data is not recorded in the log file of the controller, the error data of the first serial bus communication information is acquired; and the fault type of the error of the first serial bus communication information is determined according to the error data of the first serial bus communication information. The application can troubleshoot the memory failure problem caused by the memory overheating and the processor without the need of opening the case, thereby reducing the time cost and research and development manpower of detection.

[0025] The technical scheme of the application can troubleshoot the problem caused by the memory overheating and the processor itself without the need of opening the case. If the problem is caused by the processor, the processor can be directly replaced without the need of measuring, cross-verification and reproduction by opening the case. If the problem is caused by the I3C link, the problem data can be reserved, and the problem of which memory channel occurs can be recorded, and the analysis direction of whether the problem is caused by the memory or the system can be roughly determined, thereby providing data support for further reproduction and cross-verification analysis, and avoiding the problem of cross-verification of which memory bank on the same I3C path has a problem during reproduction.

[0026] The technical scheme of the application can record the problem data, and the cross-verification and reproduction problem in the early stage can be reproduced without the need of a logic analyzer and an oscilloscope, thereby facilitating the reproduction operation of the production line personnel without the need of too much intervention of the research and development personnel. For the problem of the processor, the production line personnel can determine the replacement of the processor by reading the log of the controller. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0028] Figure 1A structure diagram of a related memory fault processing system provided for an embodiment of the present application is provided.

[0029] Figure 2 A structure diagram of a memory fault processing system provided for an embodiment of the present application is provided.

[0030] Figure 3 A first flow chart of a memory fault processing method provided for an embodiment of the present application is provided.

[0031] Figure 4 A second flow chart of a memory fault processing method provided for an embodiment of the present application is provided.

[0032] Figure 5 A specific flow chart of a memory fault processing method provided for an embodiment of the present application is provided.

[0033] Figure 6 An exemplary system that can be used to implement various embodiments of the present application is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0035] It should be noted that, in the description of the present application, the terms “include”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0036] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0037] Modern society enters the period of high-speed development of informationization and intelligentization, and servers, as the core equipment of informationization system, play a crucial role in modern information technology architecture.

[0038] Servers are an integral part of modern computing and communication architectures, and their efficient operation supports various online services and enterprise operations, enabling information and resources to be quickly and securely shared and processed on a global scale. With the development of technology, the functions and performance of servers are constantly improving to meet the growing demand for data processing.

[0039] Among servers, memory is a key component for temporarily storing data. Memory plays an important role in communication between CPU and other components, especially when processing large amounts of data or running large programs, the capacity and speed of memory are particularly important. Memory also plays an indispensable role in the operation of servers.

[0040] Memory problems have always been the most important problem in servers. Once the memory problem occurs, the entire system operation will be affected, and every problem of memory needs attention. During the operation of the server, the processor CPU may alarm the memhot problem, but there are many reasons for the triggering of the memory overheating memhot problem: the first is that the processor CPU itself has a problem, which needs to be replaced; the second problem is that the memory temperature is too high, which needs to check whether the cooling strategy is correct and whether there is a blocked air duct in the server case; the third problem is that the I3C bus of the processor CPU accessing the memory bank cannot respond, which needs to check whether there are hidden dangers in the current design. If the operation of the production line personnel is not proper, it may cause the phenomenon to disappear, and the research and development personnel need to invest a lot of manpower and material resources to reproduce and analyze.

[0041] In related scheme design, the following disadvantages exist:

[0042] 1. In addition to the memhot problem caused by memory overheating, the memory overheating problem caused by the abnormality of the processor CPU and the I3C link needs to be measured in the open case to achieve it;

[0043] 2. The open case needs to find the measurement point, if it is on the back of the board card, it needs to be powered off and reproduced to capture, so as to make a rough judgment;

[0044] 3. After the problem occurs, a soldering line needs to be added to the oscilloscope or logic analyzer to reproduce and capture the problem waveform to determine the cause of the problem and replace the problem component.

[0045] Embodiments of the present application provide a memory fault processing method, such as Figure 2 , Figure 3As shown, the method is applied to a controller in a memory fault processing system, the system further includes a processor, a switching integrated circuit, a logic device, a plurality of switches, and a plurality of memory bars, a first output end of the controller is connected with the switching integrated circuit, the switching integrated circuit is connected with the plurality of switches in correspondence respectively, each switch is connected with the plurality of memory bars in correspondence, a second output end of the controller is connected with the logic device, the logic device is connected with the plurality of switches in correspondence respectively, the logic device is connected with the processor, and the processor is connected with the plurality of switches in correspondence respectively, and the method includes:

[0046] obtaining first serial bus communication information between the processor and the plurality of memory bars;

[0047] determining a memory overheating fault type according to the first serial bus communication information between the processor and the plurality of memory bars, generating a log file of the controller according to memory overheating fault type data, and storing error data of the first serial bus communication information, wherein the memory overheating fault type includes a memory bar heat dissipation problem and a processor fault problem;

[0048] in response to the memory bar heat dissipation problem or the processor fault problem data not being recorded in the log file of the controller, obtaining error data of the first serial bus communication information;

[0049] determining a fault type of the first serial bus communication information error according to the error data of the first serial bus communication information.

[0050] It can be understood that the application connects each group of I3C link to the memory bar to the logic device FPGA in design, and data monitoring and grabbing are performed through the logic device, meanwhile, the logic device FPGA adds a storage card (SD card) to store problem data, so that the data of the problem that the I3C link cannot respond can be read, and the reason why the I3C link cannot respond is analyzed.

[0051] The first serial bus is an improved I2C serial bus, that is, an I3C serial bus.

[0052] Embodiments of the application provide a memory fault processing method, as shown in Figure 4 As shown, the method is applied to a controller in a memory fault processing system, the system further includes a processor, a switching integrated circuit, a logic device, a plurality of switches, and a plurality of memory bars, a first output end of the controller is connected with the switching integrated circuit, the switching integrated circuit is connected with the plurality of switches in correspondence respectively, each switch is connected with the plurality of memory bars in correspondence, a second output end of the controller is connected with the logic device, the logic device is connected with the plurality of switches in correspondence respectively, the logic device is connected with the processor, and the processor is connected with the plurality of switches in correspondence respectively, and the method includes:

[0053] Step S01, obtaining first serial bus communication information between the processor and the plurality of memory bars.

[0054] Step S02, determining a memory overheating fault type according to the first serial bus communication information between the processor and the plurality of memory bars, generating a log file of the controller according to the memory overheating fault type data, and storing error data of the first serial bus communication information, wherein the memory overheating fault type includes a memory bar heat dissipation problem and a processor fault problem.

[0055] Step S021, the system further includes a storage card connected with the logic device.

[0056] The logic device monitors the memory overheating event.

[0057] Determining whether the logic device receives a memory overheating interrupt event.

[0058] If yes, determining whether the first serial bus communication information between the processor and the plurality of memory bars includes a start bit and an end bit; if no, stopping storing the first serial bus communication information data.

[0059] Determining whether the first serial bus communication information between the processor and the plurality of memory bars includes a start bit and an end bit, includes:

[0060] In response to the first serial bus communication information between the processor and the plurality of memory bars including a start bit and an end bit, determining whether the first serial bus communication information between the processor and the plurality of memory bars includes a new start bit and an end bit after the last end bit ends transmission.

[0061] In response to the first serial bus communication information between the processor and the plurality of memory bars including a start bit or an end bit, determining whether the clock line and the data line of the first serial bus communication link between the switch and the plurality of memory bars are both high level.

[0062] Determining whether the first serial bus communication information between the processor and the plurality of memory bars includes a new start bit and an end bit after the last end bit ends transmission, includes:

[0063] In response to the first serial bus communication information between the processor and the plurality of memory bars including a new start bit and an end bit after the last end bit ends transmission, stopping storing the first serial bus communication information data.

[0064] In response to the first serial bus communication information between the processor and the plurality of memory banks including a start bit or an end bit after the transmission ends at a last end bit, error data of the first serial bus communication information is stored in the memory card, wherein the error data of the first serial bus communication information includes a waveform of a clock line or a data line, a transmission timestamp, and a memory bank physical identifier.

[0065] A determination is made as to whether the clock line and the data line of the first serial bus communication between the switch and the plurality of memory banks are both high.

[0066] In response to the clock line and the data line of the first serial bus communication between the switch and the plurality of memory banks being both high, error data of the first serial bus communication information is stored in the memory card.

[0067] In response to the clock line or the data line of the first serial bus communication between the switch and the plurality of memory banks being low, a determination is made as to whether the low duration of the clock line or the data line of the first serial bus communication between the switch and the plurality of memory banks is greater than a first threshold (50 ms).

[0068] Specifically, the logic device FPGA simultaneously performs data capture and monitoring on the memory overheating event and the I3C data;

[0069] After detecting the memory overheating event, a determination is made as to whether to store the I3C data;

[0070] If, after the memory overheating signal is triggered, there are two complete start bits and stop bits in the I3C link, the first piece of data is not saved, and only the second piece of data is saved into the I3C error register in the storage SD card for temporary storage. If there are no complete start bits and stop bits from the first piece of I3C link data, it is proved that the I3C link has a problem, and both pieces of data are stored into the I3C error register in the SD card;

[0071] After the memory overheating event occurs, a determination is made as to whether the I3C bus (the first serial bus between the switch and the plurality of memory banks) is idle (bus idle: the clock line SCL is high and the data line SDA is high). If the I3C bus is idle, the current I3C data is saved into the I3C error register in the SD card.

[0072] If the I3C bus is not idle, it is necessary to determine whether the SCL (clock line) and the SDA (data line) are always low.

[0073] Step S022, in response to the low level duration of the clock line or the data line of the first serial bus communication between the switch and the plurality of memory sticks being greater than a first threshold value, error data of the first serial bus communication information is stored in the memory card.

[0074] In response to the low level duration of the clock line or the data line of the first serial bus communication between the switch and the plurality of memory sticks being less than or equal to the first threshold value and the clock line and the data line of the first serial bus communication between the plurality of memory sticks continuously having high-low frequency change data, the temperature of all the memory sticks is acquired, and whether the temperature of each memory stick is greater than a second threshold value (80℃) is judged.

[0075] Judging whether the temperature of each memory stick is greater than the second threshold value comprises:

[0076] In response to the temperature of any one memory stick being greater than the second threshold value, it is determined that the memory overheating fault type is a memory stick heat dissipation problem.

[0077] In response to the temperature of all the memory sticks being less than or equal to the second threshold value, it is determined that the memory overheating fault type is a processor fault problem.

[0078] Specifically, if the data level of one clock line or data line is always low (the signal line is continuously low: the duration exceeds the normal communication clock period or the Clock Stretching time allowed by the protocol (for example, >1ms)), the FPGA records a piece of data on the I3C link into the error register;

[0079] If the I3C bus is not idle and the clock line SCL and the data line SDA continuously have high-low frequency change data, the controller BMC needs to read the temperature of each memory stick, and if there is an overheated memory stick, the controller BMC records the overheated memory stick into the log log of the controller.

[0080] If the memory temperatures are all normal, it is proved that the I3C link communication is normal, and the cause of the memory overheating event is the processor CPU itself, and the controller BMC records the processor CPU itself problem into the log log of the controller.

[0081] Step S03, in response to the log file of the controller not recording the memory stick heat dissipation problem or the processor fault problem data, error data of the first serial bus communication information is acquired.

[0082] Step S04, determining the fault type of the error of the first serial bus communication information according to the error data of the first serial bus communication information.

[0083] Step S041, in response to the clock line of the first serial bus communication link being interrupted, determining that the fault type of the first serial bus communication information error is a system problem, wherein the system problem includes a processor problem and a first serial bus communication abnormal interference problem;

[0084] In response to the memory bank of the first serial bus (I3C) communication link not responding to transmission, it is determined that the fault type of the first serial bus communication information error is a memory bank fault problem;

[0085] In response to the switch reading data from any memory bank abnormally, it is determined that the fault type of the first serial bus communication information error is a system problem.

[0086] Specifically, the researchers can first exclude whether it is a processor CPU problem or a memory bank over-temperature problem by collecting the one-key log of the BMC;

[0087] If the one-key log of the controller BMC does not record the processor CPU problem and the over-temperature problem of the memory bank, the content in the SD card of the logic device FPGA needs to be exported. By reading the error I3C record data in the SD card, it can be recorded in detail when accessing which memory bank error occurs, and it can be judged whether it is a memory bank problem or a system problem.

[0088] According to the error I3C record data, the error can be classified. If the clock line of the first serial bus is not sent, it can be judged that it is a system problem; if the memory bank response is abnormal, it can be judged that it is a memory problem; if the memory bank data is read abnormally, it can be judged that it is a system problem, and further investigation is needed to find out what causes the data communication error.

[0089] Step S05, when the memory over-temperature fault type is a processor fault problem, the processor fault problem is processed;

[0090] The processor fault problem is processed, including:

[0091] When the processor appears over-temperature error, the corresponding fan speed of the processor is increased and / or the working frequency of the processor is reduced through the controller;

[0092] When the processor sends an unmaskable interrupt or alarm signal to the controller, the error code of the processor is obtained, and the processor is restarted according to the error code of the processor;

[0093] When the processor sends a machine check exception signal to the controller, the working mode of the processor is set to a safe mode through the controller, and the error log of the processor is recorded.

[0094] Step S06, when the memory overheating fault type is a memory bank heat dissipation problem, then the memory bank heat dissipation problem is processed;

[0095] The memory bank heat dissipation problem is processed, including:

[0096] The temperature of each memory bank is obtained through the controller;

[0097] In response to the temperature of any one memory bank being greater than a third threshold value (70°C ~ 75°C), it is determined that the memory bank has a heat dissipation problem, the memory bank is set as a target memory bank, and the target memory bank is subjected to heat dissipation processing;

[0098] The target memory bank is subjected to heat dissipation processing, including:

[0099] The memory bandwidth of the target memory bank is reduced through the controller and / or the access load of the target memory bank is reduced by reducing the working frequency of the processor;

[0100] In response to the target memory bank being a non-critical memory bank, the target memory bank is set to a disabled mode;

[0101] The temperature of the target memory bank is re-obtained at a first interval threshold value (2-5 seconds), and in response to the temperature of the target memory bank being less than or equal to the third threshold value, the memory bandwidth and the access load of the target memory bank are restored.

[0102] Step S07, when the memory overheating fault type is a first serial bus link communication problem, then the first serial bus link communication problem is processed;

[0103] The first serial bus link communication problem is processed, including:

[0104] In response to the low level duration of the clock line and the data line of the first serial bus link being greater than a first threshold value (1ms), the universal input and output interface of the first serial bus link and the reset pin of the first serial bus buffer integrated circuit are controlled through the controller to reset the first serial bus link communication;

[0105] In response to the dynamic address allocation of the first serial bus link failing, a dynamic address allocation process is sent to the first serial bus link through the controller to re-perform dynamic address allocation;

[0106] In response to the first serial bus master controller of the processor being abnormal, the system is reset and / or the first serial bus master controller and the first serial bus link of the processor are re-initialized through the controller.

[0107] Step S08, in response to the input / output interface voltage of the power supply being abnormal or the voltage regulator efficiency being less than a fourth threshold value (85%), the fault type of the memory overheating is determined as a power supply problem, and the input / output interface voltage of the power supply is dynamically adjusted to a fifth threshold value (set according to the memory type, for example, 1.144V);

[0108] In response to the controller error identifying the first serial bus link communication data or the error identifying the memory overheating event, the fault type of the memory overheating is determined as a controller firmware failure problem, the firmware of the controller is upgraded and / or the firmware of the controller is reset, and an alarm prompt is given;

[0109] In response to the system error rate being greater than a sixth threshold value (10 times / hour / memory channel), the fault type of the memory overheating is determined as a system behavior problem, and the system memory frequency is dynamically adjusted by the controller and / or the load scheduling of each memory bank is optimized;

[0110] In response to the thermal response characteristics of each memory bank being inconsistent, the fault type of the memory overheating is determined as a memory bank compatibility problem, and the incompatible memory bank is isolated by the controller, and an alarm prompt is given.

[0111] Here, as shown in Figure 5 The present application can locate and record the root cause of the memory overheating memhot, and the problem root cause can be classified and recorded by the controller BMC and the logic device FPGA in cooperation with reading data;

[0112] For the processor CPU problem and the memory temperature problem, the BMC can record in detail;

[0113] For the abnormal problem caused by the I3C link, the logic device FPGA can record the problem data and perform simple analysis.

[0114] In addition, the memory fault processing method further comprises:

[0115] In response to the temperature reported by the digital temperature sensor on any one memory bank being greater than or equal to a seventh threshold value (85℃), the system receives real-time temperature information and related states, adjusts the duty cycle PWM curve of the memory bank fan, and sends a network shared channel protocol (NCSI) or modern platform management protocol (PLDM) command to notify the server;

[0116] In response to the sensor of the memory bank being damaged or having a calibration error, reporting a false high temperature, whether the memory bank is a real overheating event is determined through cross-validation of multiple sources of data, and a "sensor failure" event is reported;

[0117] In response to the absence of the memory bank heat-conducting pad, air duct blockage, and insufficient fan rotation speed, all server fans are boosted to 100% duty cycle PWM, the percentage of heat dissipation efficiency is calculated, and the "high temperature exhaust / outlet air temperature" alarm is reported;

[0118] In response to the failure of the server room air conditioner, the temperature of each device in the server is increased, and a hierarchical response is started according to the temperature preset threshold;

[0119] The hierarchical response is started according to the temperature preset threshold, including:

[0120] When the air temperature at the server inlet is greater than or equal to a first preset value (35°C), a warning is given through the controller;

[0121] When the air temperature at the server inlet is greater than or equal to a second preset value (40°C), the heat dissipation is actively enhanced through the controller;

[0122] When the air temperature at the server inlet is greater than or equal to a third preset value (45°C), the memory is subjected to frequency reduction processing, the processor is subjected to dynamic frequency reduction, and the dynamic overclocking function of the processor is actively reduced or disabled;

[0123] When the processor temperature is greater than or equal to a fourth preset value (90°C), the controller triggers the stop of assigning new Pod services to the node and stops the non-critical services of the server;

[0124] When the air temperature at the server inlet is greater than or equal to a fifth preset value (50°C), the controller reports a "soon to be overheated" prompt, and the data center management system starts the memory load migration;

[0125] When the air temperature at the server inlet is greater than or equal to a sixth preset value (55°C), the controller executes the case power supply shutdown instruction to forcibly shut down the server;

[0126] In response to the heat generated by the processor or the voltage regulation module being conducted to the memory area through the circuit board, the fan rotation speed is increased to prevent heat accumulation, and the high-bandwidth memory bank is preferentially scheduled to a channel away from the heat source.

[0127] Here, the complete server intelligent thermal management and memory fault response strategy covers a closed-loop system from memory temperature monitoring, sensor reliability verification, heat dissipation control, multi-level overheating response to resource scheduling linkage, and is suitable for modern data centers, AI high-density servers, or intelligent server platforms supporting Redfish + OpenBMC architecture.

[0128] The memory fault processing method provided by the embodiments of the present application can also be improved and optimized without departing from the technical solutions of the present application, and these improvements and optimizations should also be considered as the protection scope of the present application.

[0129] The application can also use the logic device FPGA to perform waveform monitoring analysis on other signal buses, such as data transmitted by the universal asynchronous receiver-transmitter UART, the second serial bus I2C, and the serial peripheral interface SPI.

[0130] The technical scheme provided by the embodiment of the application has the following beneficial effects:

[0131] The application can troubleshoot memory failure problems caused by memory overheating and processor reasons without opening the machine box, thereby reducing the time cost and research and development manpower of detection.

[0132] The technical scheme of the application can troubleshoot problems caused by memory overheating and the processor itself without opening the machine box. If the problem is caused by the processor, the processor can be directly replaced without opening the machine box for measurement, cross-validation, and reproduction. If the problem is caused by the I3C link, the problem data can be preserved, and the problem occurring in which memory channel can be recorded. In addition, the application can roughly analyze whether the problem is caused by the memory or the system. For further reproduction and cross-validation analysis, the application has data support, and the problem occurring in which memory on the same I3C path can be cross-validated without problems.

[0133] The technical scheme of the application can record problem data. The cross-validation and reproduction of the problem in the early stage can be performed without a logic analyzer and an oscilloscope, which is convenient for production line personnel to perform reproduction operations without the intervention of research and development personnel. For problems occurring in the processor, production line personnel can determine whether to replace the processor by reading the controller log.

[0134] Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software and a necessary general hardware platform, and of course, the method can also be implemented by hardware. However, in many cases, the former is a better implementation.

[0135] The embodiment of the application also provides a memory failure processing system. The system includes a controller, a processor, a switching integrated circuit, a logic device, a plurality of switches, and a plurality of memory sticks. The first output end of the controller is connected with the switching integrated circuit. The switching integrated circuit is connected with the plurality of switches in a corresponding manner. Each switch is connected with the plurality of memory sticks in a corresponding manner. The second output end of the controller is connected with the logic device. The logic device is connected with the plurality of switches in a corresponding manner. The logic device is connected with the processor. The processor is connected with the plurality of switches in a corresponding manner. The controller is used to:

[0136] acquire first serial bus communication information between the processor and the plurality of memory sticks;

[0137] Determine a memory overheating fault type according to first serial bus communication information between the processor and the plurality of memory banks, generate a log file of the controller according to the memory overheating fault type data, and store error data of the first serial bus communication information, wherein the memory overheating fault type includes a memory bank heat dissipation problem and a processor fault problem;

[0138] In response to no memory bank heat dissipation problem or processor fault problem data being recorded in the log file of the controller, acquire error data of the first serial bus communication information;

[0139] Determine a fault type of the first serial bus communication information error according to the error data of the first serial bus communication information.

[0140] The controller is configured to monitor a memory overheating event by the logic device;

[0141] Determine whether the logic device receives a memory overheating interrupt event;

[0142] If yes, determine whether the first serial bus communication information between the processor and the plurality of memory banks includes a start bit and an end bit; if no, stop storing the first serial bus communication information data;

[0143] The determination of whether the first serial bus communication information between the processor and the plurality of memory banks includes a start bit and an end bit comprises:

[0144] In response to the first serial bus communication information between the processor and the plurality of memory banks including a start bit and an end bit, determine whether the first serial bus communication information between the processor and the plurality of memory banks includes a new start bit and an end bit after transmission of a previous end bit ends;

[0145] In response to the first serial bus communication information between the processor and the plurality of memory banks including a start bit or an end bit, determine whether clock lines and data lines of the first serial bus communication link between the switch and the plurality of memory banks are both at a high level;

[0146] The determination of whether the first serial bus communication information between the processor and the plurality of memory banks includes a new start bit and an end bit after transmission of a previous end bit ends comprises:

[0147] In response to the first serial bus communication information between the processor and the plurality of memory banks including a new start bit and an end bit after transmission of a previous end bit ends, stop storing the first serial bus communication information data;

[0148] in response to the first serial bus communication information between the processor and the plurality of memory banks including a start bit or an end bit after an end bit ends transmission, storing error data of the first serial bus communication information in the memory card, wherein the error data of the first serial bus communication information includes a waveform of a clock line or a data line, a transmission timestamp, and a memory bank physical identifier;

[0149] the determining whether the clock line and the data line of the first serial bus communication between the switch and the plurality of memory banks are both high levels includes:

[0150] in response to the clock line and the data line of the first serial bus communication between the switch and the plurality of memory banks being both high levels, storing error data of the first serial bus communication information in the memory card;

[0151] in response to the clock line or the data line of the first serial bus communication between the switch and the plurality of memory banks being a low level, determining whether a low level duration of the clock line or the data line of the first serial bus communication between the switch and the plurality of memory banks is greater than a first threshold.

[0152] the controller is configured to: in response to the low level duration of the clock line or the data line of the first serial bus communication between the switch and the plurality of memory banks being greater than the first threshold, store error data of the first serial bus communication information in the memory card;

[0153] in response to the low level duration of the clock line or the data line of the first serial bus communication between the switch and the plurality of memory banks being less than or equal to the first threshold and the clock line and the data line of the first serial bus communication between the plurality of memory banks continuously having high-low frequency change data, obtaining temperatures of all the memory banks, and determining whether a temperature of each memory bank is greater than a second threshold;

[0154] the determining whether the temperature of each memory bank is greater than the second threshold includes:

[0155] in response to the temperature of any one memory bank being greater than the second threshold, determining that the memory overheating fault type is a memory bank heat dissipation problem;

[0156] in response to the temperatures of all the memory banks being less than or equal to the second threshold, determining that the memory overheating fault type is a processor fault problem.

[0157] The controller is configured to determine that the fault type of the first serial bus communication information error is a system problem in response to a clock line of the first serial bus communication link being interrupted, wherein the system problem includes a processor problem and a first serial bus communication abnormal interference problem.

[0158] The controller is configured to determine that the fault type of the first serial bus communication information error is a memory bank failure problem in response to a memory bank of the first serial bus communication link not responding to transmission.

[0159] The controller is configured to determine that the fault type of the first serial bus communication information error is a system problem in response to the switch abnormally reading data of any memory bank.

[0160] The technical scheme provided by the embodiment of the application has the following beneficial effects:

[0161] The application can troubleshoot the memory failure problem caused by the over-temperature of the memory and the processor without the need of opening the machine box, thereby reducing the time cost and research and development manpower of detection.

[0162] The technical scheme of the application can troubleshoot the problem caused by the over-temperature of the memory and the processor itself without the need of opening the machine box. If the problem is caused by the processor, the processor can be directly replaced without the need of opening the machine box for measurement, cross verification and reproduction. If the problem is caused by the I3C link, the problem data can be preserved, and the problem of which memory channel occurs can be recorded, and whether the problem is caused by the memory or the system can be roughly analyzed. For further reproduction and cross verification analysis, data support is provided, and the problem of which memory of the same I3C path occurs can be avoided when cross verification is performed.

[0163] The technical scheme of the application can record problem data, and the cross verification and reproduction problem in the early stage can be performed without the need of a logic analyzer and an oscilloscope, thereby facilitating reproduction operation of production line personnel and reducing the intervention of research and development personnel. For the problem of the processor, the production line personnel can determine the replacement of the processor by reading the controller log.

[0164] The embodiment of the application further provides a memory failure processing system, as shown in Figure 2As shown, the memory fault processing system comprises a controller, a processor, a switching integrated circuit, a logic device, a plurality of switches and a plurality of memory banks, a first output end of the controller is connected with the switching integrated circuit, the switching integrated circuit is connected with the plurality of switches respectively, each switch is connected with the plurality of memory banks respectively, a second output end of the controller is connected with the logic device, the logic device is connected with the plurality of switches respectively, the logic device is connected with the processor, the processor is connected with the plurality of switches respectively, the system further comprises a storage card, and the storage card is connected with the logic device;

[0165] The processor is connected with the plurality of switches through a first serial bus link;

[0166] Each switch is connected with the plurality of memory banks through a first serial bus link;

[0167] The controller is connected with the logic device through a second serial bus link.

[0168] The second serial bus is an I2C serial bus.

[0169] The technical scheme provided by the embodiment of the application has the beneficial effects that:

[0170] The application can troubleshoot the memory fault problem caused by the memory over-temperature and the processor without opening the machine box, thereby reducing the time cost and research and development manpower of detection.

[0171] The technical scheme of the application can troubleshoot the problem caused by the memory over-temperature and the processor itself without opening the machine box, if the problem is caused by the processor, the processor can be directly replaced without opening the machine box for measurement and cross verification and reproduction; if the problem is caused by the I3C link, the problem data can be preserved, and the problem of which memory channel occurs can be recorded, and whether the problem is caused by the memory or the system can be roughly analyzed, which can provide data support for further reproduction and cross verification analysis, and the problem of which memory bank on the same I3C path has a problem in cross verification can be avoided.

[0172] The technical scheme of the application can record problem data, and the cross verification and reproduction problem in the early stage can be reproduced without a logic analyzer and an oscilloscope, which is convenient for production line personnel to reproduce the operation without the intervention of too many research and development personnel, and for the problem of the processor, the production line personnel only need to read the controller log to determine whether to replace the processor.

[0173] The features of the embodiments of the memory fault processing system can be referred to the related descriptions of the embodiments of the memory fault processing method, which will not be repeated here.

[0174] Embodiments of the present application also provide an electronic device, which comprises a memory fault processing system, the memory fault processing system comprising a controller, a processor, a switching integrated circuit, a logic device, a plurality of switches and a plurality of memory banks, the first output end of the controller being connected with the switching integrated circuit, the switching integrated circuit being connected with the plurality of switches respectively, each switch being connected with the plurality of memory banks respectively, the second output end of the controller being connected with the logic device, the logic device being connected with the plurality of switches respectively, the logic device being connected with the processor, the processor being connected with the plurality of switches respectively, the system further comprising a storage card, the storage card being connected with the logic device;

[0175] The processor and the plurality of switches are connected through a first serial bus link I3C (Improved Inter-Integrated Circuit);

[0176] Each switch and the plurality of memory banks are connected through a first serial bus link respectively;

[0177] The controller and the logic device are connected through a second serial bus link I2C.

[0178] Embodiments of the present application also provide an electronic device, which comprises a memory and a processor, the memory storing a computer program, and the processor being configured to run the computer program to implement the steps in the embodiments of the memory fault processing method, the method comprising:

[0179] Obtaining first serial bus communication information between the processor and the plurality of memory banks;

[0180] Determining a memory overheating fault type according to the first serial bus communication information between the processor and the plurality of memory banks, generating a log file of the controller according to the memory overheating fault type data, and storing error data of the first serial bus communication information, wherein the memory overheating fault type comprises a memory bank heat dissipation problem and a processor fault problem;

[0181] In response to no memory bank heat dissipation problem or processor fault problem data being recorded in the log file of the controller, error data of the first serial bus communication information is obtained;

[0182] Determining a fault type of the first serial bus communication information error according to the error data of the first serial bus communication information.

[0183] As Figure 6 shown, the embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps in the memory fault processing method embodiments when running, and the method comprises:

[0184] obtaining first serial bus communication information between the processor and the plurality of memory banks;

[0185] determining a memory overheating fault type according to the first serial bus communication information between the processor and the plurality of memory banks, generating a log file of the controller according to the memory overheating fault type data, and storing error data of the first serial bus communication information, wherein the memory overheating fault type includes a memory bank heat dissipation problem and a processor fault problem;

[0186] in response to no memory bank heat dissipation problem or processor fault problem data being recorded in the log file of the controller, obtaining error data of the first serial bus communication information;

[0187] determining a fault type of the error of the first serial bus communication information according to the error data of the first serial bus communication information.

[0188] In an exemplary embodiment, the above computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0189] The embodiments of the present application also provide a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps in the memory fault processing method embodiments, and the method comprises:

[0190] obtaining first serial bus communication information between the processor and the plurality of memory banks;

[0191] determining a memory overheating fault type according to the first serial bus communication information between the processor and the plurality of memory banks, generating a log file of the controller according to the memory overheating fault type data, and storing error data of the first serial bus communication information, wherein the memory overheating fault type includes a memory bank heat dissipation problem and a processor fault problem;

[0192] In response to the fact that the memory bar heat dissipation problem or the processor failure problem data is not recorded in the log file of the controller, the error data of the first serial bus communication information is acquired;

[0193] The fault type of the error of the first serial bus communication information is determined according to the error data of the first serial bus communication information.

[0194] Embodiments of the present application also provide another computer program product, comprising a nonvolatile computer readable storage medium, the nonvolatile computer readable storage medium storing a computer program, the computer program being executed by a processor to implement the steps in the memory failure processing method embodiment, the method comprising:

[0195] The first serial bus communication information between the processor and the plurality of memory bars is acquired;

[0196] The memory overheating failure type is determined according to the first serial bus communication information between the processor and the plurality of memory bars, the log file of the controller is generated according to the memory overheating failure type data, and the error data of the first serial bus communication information is stored, wherein the memory overheating failure type comprises a memory bar heat dissipation problem and a processor failure problem;

[0197] In response to the fact that the memory bar heat dissipation problem or the processor failure problem data is not recorded in the log file of the controller, the error data of the first serial bus communication information is acquired;

[0198] The fault type of the error of the first serial bus communication information is determined according to the error data of the first serial bus communication information.

[0199] The present application does not need to reproduce the open box to troubleshoot the memory failure problem caused by the memory overheating and the processor, thereby reducing the time cost and research and development manpower of detection.

[0200] The present application technical solution does not need to reproduce the open box to troubleshoot the problem caused by the memory overheating and the processor itself, if it is a processor problem, the processor can be directly replaced, without the need of open box measurement and cross verification and reproduction; if it is an I3C link problem, the problem data can be reserved, and which memory channel has the problem is recorded, and whether it is a memory problem or a system problem can be roughly analyzed, for further reproduction and cross verification analysis, there is data support, and the problem of cross verification of which memory bar on the same I3C path has a problem does not occur.

[0201] The technical scheme of the application can record problem data, cross-verify and reproduce problems in the early stage, can not pass through a logic analyzer and an oscilloscope, is convenient for production line personnel to reproduce operation, does not need too much intervention of R&D personnel, and only needs production line personnel to read controller logs to determine replacement of a processor for problems of the processor.

[0202] Those skilled in the art will further realize that the units and algorithms described with reference to the embodiments disclosed herein can be implemented with electronic hardware, computer software, or any combination thereof. To clearly illustrate the interchangeability of hardware and software, various aspects of examples have been described herein in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

[0203] The above provides a detailed introduction to the memory fault processing method and system. The principle and implementation of the application are described by applying specific examples. The above description of the examples is only applicable to help understand the method and its core idea. It should be pointed out that, for those skilled in the art, without departing from the principle of the application, the application can be improved and modified in several ways, and these improvements and modifications also fall within the protection scope of the application.

Claims

1. A memory fault handling method, characterized in that, The method is applied to a controller in a memory fault handling system. The system further includes a processor, a switching integrated circuit, a logic unit, several switches, and several memory modules. A first output terminal of the controller is connected to the switching integrated circuit. The switching integrated circuit is connected to each of the several switches, and each switch is connected to one of the several memory modules. A second output terminal of the controller is connected to the logic unit, which is connected to each of the several switches. The logic unit is connected to the processor, and the processor is connected to each of the several switches. The method includes: Obtain the first serial bus communication information between the processor and the plurality of memory modules; The memory overheating fault type is determined based on the first serial bus communication information between the processor and the plurality of memory modules. The controller's log file is generated based on the memory overheating fault type data, and the error data of the first serial bus communication information is stored. The memory overheating fault type includes memory module heat dissipation problems and processor failure problems. If no data on memory module overheating or processor malfunction is recorded in the controller's log file, then error data of the first serial bus communication information is obtained. The fault type of the first serial bus communication information error is determined based on the error data of the first serial bus communication information. The system also includes a memory card connected to the logic unit. The step of determining the memory overheating fault type based on the first serial bus communication information between the processor and the plurality of memory modules includes: The logic unit monitors memory overheating events. Determine whether the logic unit has received a memory overheat interrupt event; If yes, then determine whether the first serial bus communication information between the processor and the plurality of memory modules includes a start bit and an end bit; if no, then stop storing the first serial bus communication information data. The determination of whether the first serial bus communication information between the processor and the plurality of memory modules includes a start bit and an end bit includes: In response to the fact that the first serial bus communication information between the processor and the plurality of memory modules includes a start bit and an end bit, a determination is made as to whether the first serial bus communication information between the processor and the plurality of memory modules includes a new start bit and an end bit after the transmission ends at the previous end bit. In response to the fact that the first serial bus communication information between the processor and the plurality of memory modules includes a start bit or an end bit, it is determined whether the clock line and data line levels of the first serial bus communication link between the switch and the plurality of memory modules are both high. The determination of whether the first serial bus communication information between the processor and the plurality of memory modules includes new start and end bits after the previous end bit ends the transmission includes: In response to the fact that the first serial bus communication information between the processor and the plurality of memory modules includes a new start bit and an end bit after the previous end bit ends the transmission, the storage of the first serial bus communication information data is stopped. In response to the fact that the first serial bus communication information between the processor and the plurality of memory modules includes a start bit or an end bit after the previous end bit ends the transmission, the error data of the first serial bus communication information is stored in the memory card, wherein the error data of the first serial bus communication information includes the waveform of the clock line or data line, the transmission timestamp, and the physical identifier of the memory module. The determination of whether the clock line and data line levels of the first serial bus communication link between the switch and the plurality of memory modules are both high includes: In response to the clock line and data line levels of the first serial bus communication between the switch and the plurality of memory modules being both high, the erroneous data of the first serial bus communication information is stored in the memory card. In response to a low level on the clock line or data line of the first serial bus communication between the switch and the plurality of memory modules, a determination is made as to whether the duration of the low level on the clock line or data line of the first serial bus communication between the switch and the plurality of memory modules is greater than a first threshold. The determination of whether the low-level duration of the clock line or data line for communication between the switch and the plurality of memory modules is greater than a first threshold includes: If the low-level duration of the clock line or data line of the first serial bus communication between the switch and the plurality of memory modules is greater than a first threshold, then the erroneous data of the first serial bus communication information is stored in the memory card. In response to the low-level duration of the clock line or data line of the first serial bus communication between the switch and the plurality of memory modules being less than or equal to a first threshold and the clock line and data line of the first serial bus communication between the plurality of memory modules continuously having high and low frequency change data, the temperature of all memory modules is acquired, and it is determined whether the temperature of each memory module is greater than a second threshold. The determination of whether the temperature of each memory module is greater than the second threshold includes: If the temperature of any memory module exceeds the second threshold, the memory overheating fault type is determined to be a memory module heat dissipation problem. If the temperature of all memory modules is less than or equal to the second threshold, then the memory overheating fault type is determined to be a processor fault problem.

2. The memory fault handling method according to claim 1, characterized in that, The step of determining the fault type of the first serial bus communication information error based on the error data of the first serial bus communication information includes: In response to an interruption in the clock line of the first serial bus communication link, the fault type of the first serial bus communication information error is determined to be a system problem, wherein the system problem includes processor problems and abnormal interference problems in the first serial bus communication; If the memory module in the first serial bus communication link does not respond with a transmission response, then the fault type of the first serial bus communication information error is determined to be a memory module failure problem. In response to an abnormal data read from any memory module by the switch, the fault type of the first serial bus communication information error is determined to be a system problem.

3. The memory fault handling method according to claim 1, characterized in that, After determining the memory overheating fault type based on the first serial bus communication information between the processor and the plurality of memory modules, the process includes: When the memory overheating fault type is a processor fault, then the processor fault is handled. The handling of processor malfunctions includes: When the processor experiences an over-temperature error, the controller increases the fan speed corresponding to the processor and / or decreases the processor's operating frequency. When the processor sends a non-maskable interrupt or alarm signal to the controller, the error code of the processor is obtained, and the processor is restarted according to the error code. When the processor sends a machine check anomaly signal to the controller, the controller sets the processor's operating mode to safe mode and records the processor's error log.

4. The memory fault handling method according to claim 1, characterized in that, After determining the memory overheating fault type based on the first serial bus communication information between the processor and the plurality of memory modules, the method further includes: When the memory overheating fault type is a memory module heat dissipation problem, then the memory module heat dissipation problem should be addressed. The measures taken to address the memory module overheating issue include: The temperature of each memory module is obtained through the controller; If the temperature of any memory module exceeds the third threshold, it is determined that the memory module has a heat dissipation problem, the memory module is set as the target memory module, and heat dissipation treatment is performed on the target memory module; The heat dissipation treatment of the target memory module includes: The memory bandwidth of the target memory module is reduced by the controller and / or the access load of the target memory module is reduced by reducing the operating frequency of the processor; If the target memory module is a non-critical memory module, then the target memory module is set to a disabled mode; The temperature of the target memory module is reacquired according to the first interval threshold. If the temperature of the target memory module is less than or equal to the third threshold, the memory bandwidth and access load of the target memory module are restored.

5. The memory fault handling method according to claim 1, characterized in that, After determining the fault type of the first serial bus communication information error based on the error data of the first serial bus communication information, the process includes: When the memory overheating fault type is a first serial bus link communication problem, then the first serial bus link communication problem is handled. The handling of the first serial bus link communication problem includes: If the low-level duration of both the clock line and data line of the first serial bus link is greater than the first threshold, the controller controls the general-purpose input / output interface of the first serial bus link and the reset pin of the first serial bus buffer integrated circuit to reset the communication of the first serial bus link. If the dynamic address allocation of the first serial bus link fails, the controller sends a dynamic address allocation process to the first serial bus link to re-allocate the dynamic address. In response to an anomaly in the processor's first serial bus master controller, the system is reset and / or the processor's first serial bus master controller and first serial bus link are reinitialized via the controller.

6. The memory fault handling method according to claim 1, characterized in that, The method further includes: If the input / output interface voltage of the power supply is abnormal or the efficiency of the voltage regulator is less than the fourth threshold, the fault type of the memory overheating is determined to be a power supply problem, and the input / output interface voltage of the power supply is dynamically adjusted to the fifth threshold. In response to the controller incorrectly identifying the first serial bus link communication data or incorrectly identifying the memory overheating event, the fault type of the memory overheating is determined to be a firmware fault problem of the controller. The firmware of the controller is upgraded and / or the firmware of the controller is reset, and an alarm is issued. If the system error rate exceeds the sixth threshold, the fault type of the memory overheating is determined to be a system behavior problem, and the system memory frequency is dynamically adjusted and / or the load scheduling of each memory module is optimized by the controller. If the thermal response characteristics of the various memory modules are inconsistent, the fault type of the memory overheating is determined to be a memory module compatibility issue. The controller then isolates the incompatible memory modules and issues an alarm.

7. The memory fault handling method according to claim 1, characterized in that, The processor is connected to the plurality of switches via a first serial bus link; Each switch is connected to the plurality of memory modules via a first serial bus link; The controller and the logic unit are connected via a second serial bus link.

8. A memory fault handling system, characterized in that, The system includes a controller, a processor, a switching integrated circuit, a logic unit, several switches, and several memory modules. The first output of the controller is connected to the switching integrated circuit. Each switching integrated circuit is connected to one of the several switches, and each switch is connected to one of the several memory modules. The second output of the controller is connected to the logic unit. The logic unit is connected to the processor, and the processor is connected to one of the several switches. The controller is used for: Obtain the first serial bus communication information between the processor and the plurality of memory modules; The memory overheating fault type is determined based on the first serial bus communication information between the processor and the plurality of memory modules. The controller's log file is generated based on the memory overheating fault type data, and the error data of the first serial bus communication information is stored. The memory overheating fault type includes memory module heat dissipation problems and processor failure problems. If no data on memory module overheating or processor malfunction is recorded in the controller's log file, then error data of the first serial bus communication information is obtained. The fault type of the first serial bus communication information error is determined based on the error data of the first serial bus communication information. The system also includes a memory card connected to the logic unit. The step of determining the memory overheating fault type based on the first serial bus communication information between the processor and the plurality of memory modules includes: The logic unit monitors memory overheating events. Determine whether the logic unit has received a memory overheat interrupt event; If yes, then determine whether the first serial bus communication information between the processor and the plurality of memory modules includes a start bit and an end bit; if no, then stop storing the first serial bus communication information data. The determination of whether the first serial bus communication information between the processor and the plurality of memory modules includes a start bit and an end bit includes: In response to the fact that the first serial bus communication information between the processor and the plurality of memory modules includes a start bit and an end bit, a determination is made as to whether the first serial bus communication information between the processor and the plurality of memory modules includes a new start bit and an end bit after the transmission ends at the previous end bit. In response to the fact that the first serial bus communication information between the processor and the plurality of memory modules includes a start bit or an end bit, it is determined whether the clock line and data line levels of the first serial bus communication link between the switch and the plurality of memory modules are both high. The determination of whether the first serial bus communication information between the processor and the plurality of memory modules includes new start and end bits after the previous end bit ends the transmission includes: In response to the fact that the first serial bus communication information between the processor and the plurality of memory modules includes a new start bit and an end bit after the previous end bit ends the transmission, the storage of the first serial bus communication information data is stopped. In response to the fact that the first serial bus communication information between the processor and the plurality of memory modules includes a start bit or an end bit after the previous end bit ends the transmission, the error data of the first serial bus communication information is stored in the memory card, wherein the error data of the first serial bus communication information includes the waveform of the clock line or data line, the transmission timestamp, and the physical identifier of the memory module. The determination of whether the clock line and data line levels of the first serial bus communication link between the switch and the plurality of memory modules are both high includes: In response to the clock line and data line levels of the first serial bus communication between the switch and the plurality of memory modules being both high, the erroneous data of the first serial bus communication information is stored in the memory card. In response to a low level on the clock line or data line of the first serial bus communication between the switch and the plurality of memory modules, a determination is made as to whether the duration of the low level on the clock line or data line of the first serial bus communication between the switch and the plurality of memory modules is greater than a first threshold. The determination of whether the low-level duration of the clock line or data line for communication between the switch and the plurality of memory modules is greater than a first threshold includes: If the low-level duration of the clock line or data line of the first serial bus communication between the switch and the plurality of memory modules is greater than a first threshold, then the erroneous data of the first serial bus communication information is stored in the memory card. In response to the low-level duration of the clock line or data line of the first serial bus communication between the switch and the plurality of memory modules being less than or equal to a first threshold and the clock line and data line of the first serial bus communication between the plurality of memory modules continuously having high and low frequency change data, the temperature of all memory modules is acquired, and it is determined whether the temperature of each memory module is greater than a second threshold. The determination of whether the temperature of each memory module is greater than the second threshold includes: If the temperature of any memory module exceeds the second threshold, the memory overheating fault type is determined to be a memory module heat dissipation problem. If the temperature of all memory modules is less than or equal to the second threshold, then the memory overheating fault type is determined to be a processor fault problem.

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