CPU pipeline running monitoring system, method and electronic device

Abstract

The application provides a CPU pipeline operation monitoring system, method and electronic equipment. The system comprises a pipeline monitoring circuit and an event printing device. The pipeline monitoring circuit is in communication connection with the event printing device. The pipeline monitoring circuit is used for monitoring the operation state of a CPU core circuit, and capturing instruction information generated by the CPU core circuit at different stages of an instruction pipeline. The instruction pipeline comprises an acquisition stage, a decoding stage, a transmission stage, an execution stage and a retirement stage. The event printing device is used for triggering an event printing module corresponding to the instruction event category to print and output the instruction information when the pipeline monitoring circuit captures the instruction information, according to the instruction event category of the generated instruction information. The instruction event category comprises an acquisition event, a distribution event, an execution event and a retirement event. The system is a monitoring mechanism independent of the CPU core circuit, records the instruction information of each stage of the CPU pipeline, and improves the monitoring granularity.

Description

Technical Field

[0001] This application relates to the field of CPU monitoring technology, and in particular to a CPU pipeline operation monitoring system, method and electronic device. Background Technology

[0002] CPU pipelines are a technique that achieves parallel processing by breaking down instructions into multiple steps and overlapping the execution of these steps. To improve CPU execution efficiency and accelerate program execution, instruction processing is divided into multiple stages, such as fetch, decode, execute, memory access, and write-back. Each stage is operated in parallel by independent hardware circuits, thereby improving overall throughput through instruction-level parallelism. Existing CPU monitoring technologies include hardware performance counter monitoring and instruction-level tracing. Hardware performance counter monitoring collects CPU register states through the BMC controller, but it can only obtain macroscopic indicators such as temperature and load, and cannot obtain intermediate value information of each stage of the instruction pipeline. Instruction tracing technology compresses tracing data based on the program counter (PC) range, only recording the instruction address stream, and lacks the ability to reconstruct the intermediate states of the instruction execution process. Moreover, full instruction tracing leads to a significant increase in storage overhead, and existing compression methods such as PC value range filtering are prone to losing critical context, affecting the accuracy of fault diagnosis. The verification stage requires an additional conversion layer to map hardware signals into transaction-level data, resulting in poor real-time performance and increased verification complexity. Summary of the Invention

[0003] In view of this, embodiments of this application provide a CPU pipeline operation monitoring system, method, and electronic device, which can record instruction information at each stage of the CPU pipeline, improve monitoring granularity, enhance monitoring real-time performance, and reduce monitoring complexity.

[0004] A first aspect of this application provides a CPU pipeline operation monitoring system, including a pipeline monitoring circuit and an event printing device. The pipeline monitoring circuit is communicatively connected to the event printing device. The pipeline monitoring circuit monitors the operating state of the CPU core circuit and captures instruction information generated by the CPU core circuit at different stages of the instruction pipeline. The instruction pipeline includes an acquisition stage, a decoding stage, a dispatch stage, an execution stage, and a retirement stage. The event printing device, when the pipeline monitoring circuit captures instruction information, triggers an event printing module corresponding to the instruction event category that generated the instruction information to print and output the instruction information. The instruction event categories include acquisition events, dispatch events, execution events, and retirement events.

[0005] In one possible implementation, the pipeline monitoring circuit includes a buffer, an update logic module, a retirement monitor, a rearrangement buffer virtual queue, and an output queue. The buffer, the update logic module, the retirement monitor, and the output queue are respectively connected to the rearrangement buffer virtual queue. Specifically: the buffer is connected to the decoding module in the CPU core circuitry and is used to monitor the decoding module, capturing first instruction information generated by the target instruction during the acquisition, decoding, and distribution stages; the buffer is also connected to the rearrangement buffer virtual queue and is used to write the target instruction and its first instruction information into the rearrangement buffer virtual queue; the update logic module is connected to the execution module in the CPU core circuitry, used for... The system monitors the execution module to capture the second instruction information generated by the target instruction during the execution phase. The update logic module is connected to the rearrangement buffer virtual queue and is used to update the first instruction information of the target instruction in the rearrangement buffer virtual queue according to the second instruction information. The retirement monitor is connected to the general control module or retirement buffer module in the CPU core circuit and is used to monitor the general control module or retirement buffer module to capture the third instruction information generated by the target instruction during the retirement phase. The retirement monitor is connected to the rearrangement buffer virtual queue and is used to remove the target instruction and its first instruction information from the rearrangement buffer virtual queue to the output queue according to the third instruction information.

[0006] In one possible implementation, the buffer includes a pre-decoding buffer, a pre-renaming buffer, a post-renaming buffer, and a sending buffer, wherein: the pre-decoding buffer is used to capture instruction information generated by the decoding module during the acquisition phase before decoding the target instruction; the pre-renaming buffer is used to capture instruction information generated by the decoding module during the decoding phase before renaming the target instruction after decoding; the post-renaming buffer is used to capture instruction information generated by the decoding module during the decoding phase after renaming the target instruction; and the sending buffer is used to capture instruction information generated by the decoding module during the distribution phase for distributing the target instruction to the execution module.

[0007] In one possible implementation, the event printing device includes an event acquisition printing module, an event distribution printing module, an execution event printing module, and a retirement event printing module, wherein: the event acquisition printing module is communicatively connected to the pre-decoding buffer, and when the pre-decoding buffer captures the instruction information before the target instruction is decoded, it triggers the event acquisition printing module to print and output the instruction information before the target instruction is decoded; the event distribution printing module is communicatively connected to the sending buffer, and when the sending buffer captures the instruction information of the target instruction distributed to the execution module, it triggers the event distribution printing module to print and output the instruction information of the target instruction distributed to the execution module; the execution event printing module is communicatively connected to the update logic module, and when the update logic module captures the second instruction information generated by the target instruction during the execution phase, it triggers the execution event printing module to print and output the second instruction information; the retirement event printing module is communicatively connected to the output queue, and when the target instruction and its first instruction information are moved from the rearrangement buffer virtual queue to the output queue, it triggers the retirement event printing module to print and output the target instruction and its first instruction information moved to the output queue.

[0008] In one possible implementation, the buffer is connected non-intrusively to the decoding module in the CPU core circuitry, the update logic module is connected to the execution module in the CPU core circuitry, and the retirement monitor is connected to the general control module or retirement buffer module in the CPU core circuitry.

[0009] In one possible implementation, the instruction information includes one or more of the following: the PC address information corresponding to the instruction, the binary code information of the instruction, the instruction number information in the rearranged buffer virtual queue, the target logical register information before the instruction is renamed, the target physical register information after the instruction is renamed, information related to integer registers, information related to floating-point registers, and information related to vector registers.

[0010] A second aspect of this application provides a method for monitoring CPU pipeline operation, comprising: monitoring the operating state of a CPU core circuit through a pipeline monitoring circuit, capturing instruction information generated by the CPU core circuit at different stages of the instruction pipeline, wherein the instruction pipeline includes an acquisition stage, a decoding stage, a dispatch stage, an execution stage, and a retirement stage; when the pipeline monitoring circuit captures instruction information, triggering an event printing module corresponding to the instruction event category that generated the instruction information to print and output the instruction information, wherein the instruction event category includes an acquisition event, a dispatch event, an execution event, and a retirement event.

[0011] In one possible implementation, the step of monitoring the operating state of the CPU core circuit and capturing instruction information generated by the CPU core circuit at different stages of the instruction pipeline includes: monitoring the decoding module in the CPU core circuit; when the decoding module receives a target instruction, capturing the PC address information and binary code information corresponding to the target instruction; and / or monitoring the decoding module in the CPU core circuit; when the decoding module decodes the target instruction, capturing the target logic register information before the target instruction is renamed; and / or monitoring the decoding module in the CPU core circuit; when the decoding module renames the target instruction... The system retrieves the target physical register information after the target instruction is renamed; and / or monitors the decoding module in the CPU core circuit, retrieving the distribution order information and the number information in the rearranged buffer virtual queue when the decoding module distributes the target instruction; and / or monitors the execution module in the CPU core circuit, retrieving the register-related information of the target instruction when the execution module finishes executing the target instruction; and / or monitors the retirement cache module in the CPU core circuit, reading the number of retirement instructions and the number information of each retirement instruction in the rearranged buffer virtual queue when the retirement cache module receives a retirement instruction.

[0012] In one possible implementation, the step of monitoring the execution module in the CPU core circuit and retrieving the register-related information of the target instruction when the execution module finishes executing the target instruction includes: monitoring whether the execution module in the CPU core circuit has a run-end signal; if so, triggering the condition signal of the update logic and recording the number information of the target instruction corresponding to the run-end signal in the rearranged buffer virtual queue; and retrieving the value and register number information of the register in the execution module according to the condition signal.

[0013] A third aspect of this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the electronic device. When the processor executes the computer program, it implements the functions of the CPU pipeline operation monitoring system provided in the first aspect or the steps of the CPU pipeline operation monitoring method provided in the second aspect.

[0014] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the functions of the CPU pipeline operation monitoring system provided in the first aspect or the steps of the CPU pipeline operation monitoring method provided in the second aspect.

[0015] The fifth aspect of this application provides a computer program product that, when run on an electronic device, enables the electronic device to perform the functions of the CPU pipeline operation monitoring system provided in the first aspect or the steps of the CPU pipeline operation monitoring method provided in the second aspect.

[0016] The CPU pipeline operation monitoring system, method, and electronic device provided in this application have the following beneficial effects:

[0017] Based on the pipeline monitoring circuit and event printing device in the CPU pipeline operation monitoring system, the pipeline monitoring circuit monitors the operating status of the CPU core circuit and captures the instruction information generated by the CPU core circuit at different stages of the instruction pipeline. When the pipeline monitoring circuit captures instruction information, the event printing device triggers the event printing module corresponding to the instruction event category to print and output the instruction information. This realizes a monitoring mechanism independent of the CPU core circuit, records the instruction information of each stage of the CPU pipeline, improves the granularity of monitoring, enhances the real-time performance of monitoring, and reduces the complexity of monitoring. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a CPU pipeline operation monitoring system provided in an embodiment of this application.

[0020] Figure 2 This is a first logic diagram of the pipeline monitoring circuit monitoring the CPU core circuit in the CPU pipeline operation monitoring system provided in the embodiments of this application.

[0021] Figure 3 This is another schematic diagram of the CPU pipeline operation monitoring system provided in the embodiments of this application.

[0022] Figure 4 This is a flowchart illustrating the implementation of a CPU pipeline operation monitoring method provided in an embodiment of this application.

[0023] Figure 5 This is a second logic diagram of the pipeline monitoring circuit monitoring the CPU core circuit in the CPU pipeline operation monitoring system provided in the embodiments of this application.

[0024] Figure 6This is a third logic diagram of the pipeline monitoring circuit monitoring the CPU core circuit in the CPU pipeline operation monitoring system provided in the embodiments of this application.

[0025] Figure 7 This is a basic structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0026] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of this application with unnecessary detail.

[0027] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0028] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0029] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0030] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0031] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. "A plurality" means "two or more."

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0033] CPU (Central Processing Unit) pipeline is a technology that achieves parallel processing by breaking down instructions into multiple steps and overlapping the execution of different steps. To improve CPU execution efficiency, the CPU breaks down and combines the various stages of the CPU pipeline during program execution. In practice, the main logic in the pipeline generally only stores necessary information. For example, after decoding, the original instruction is redundant information for subsequent circuits and will not participate in subsequent pipeline transmission. However, for the designers of the CPU core circuit, the information of the original instruction is essential to determine whether the subsequent execution logic is correct; that is, it is not redundant information. When designing the CPU core circuit, in order to achieve the best balance of PPA (performance-power-area), it is difficult to store all the information of the CPU core circuit because implementing the relevant logic requires a large area. Therefore, this application aims to design a monitoring mechanism independent of the CPU core circuit logic, which stores all execution-related information inside the CPU during the development process and isolates it from the fabricated circuit during the tape-out stage, ensuring that auxiliary circuits during the development process do not interfere with the final product.

[0034] In some embodiments of this application, please refer to Figure 1 , Figure 1 This is a schematic diagram of a CPU pipeline operation monitoring system provided in an embodiment of this application. Figure 1As shown, the CPU pipeline operation monitoring system is independent of the CPU core circuit logic and mainly includes a pipeline monitoring circuit 10 and an event printing device 20. In this embodiment, the pipeline monitoring circuit 10 is used to monitor the operating status of the CPU core circuit and capture instruction information generated by the CPU core circuit at different stages of the instruction pipeline. The instruction pipeline includes the fetch stage, decode stage, issue stage, execution stage, and retirement stage. The event printing device 20 is used to trigger the event printing module corresponding to the instruction event category to print and output the instruction information when the pipeline monitoring circuit captures instruction information, based on the instruction event category that generated the instruction information. The instruction event categories include fetch events, issue events, execution events, and retirement events.

[0035] In the CPU core circuitry, the instruction fetching stage of the pipeline includes generating virtual address or virtual address sequence of instructions through the prediction unit (PRU / BPU) and sending it to the instruction fetching unit (IFU). The instruction fetching unit translates the virtual address into a physical address and reads the instruction or instruction sequence from its cache and sends it to the decoding unit (DEC). In another specific implementation, some instructions are stored in the physical address space. The instruction fetching unit in the CPU core circuitry can be configured with a mechanism to translate virtual addresses into physical addresses. In this case, if the instruction fetching unit does not store the relevant virtual address and physical address mapping, it can obtain the mapping by requesting an update from the page table traversal engine (TWE). It is understood that the page table traversal engine is a dedicated hardware component within the memory management unit (MMU). When a valid virtual address to physical address mapping cannot be found in the translation back buffer (TLB), it automatically traverses the multi-level page table structure in memory to find the required address translation information. The decoding stage of the instruction pipeline includes parsing the instruction operation type and addressing mode. The instruction decoder breaks down and interprets the obtained instruction according to a predetermined instruction format, identifying different instruction categories and various methods for obtaining operands. The issue stage of the instruction pipeline is responsible for selecting instructions that have been renamed in registers from the issue queue and sending them to the execution module for computation. The execution stage of the instruction pipeline is responsible for executing the specific operations of the instructions, performing arithmetic / logical operations, and storing the results in the destination location. The retirement stage of the instruction pipeline ensures the consistency between out-of-order execution results and program order; after completing a calculation or memory access operation, the instruction writes the result to the reordering buffer virtual queue. At different stages of the instruction pipeline, the CPU core circuitry generates intermediate state instruction information corresponding to each stage based on the processing tasks performed on the instructions at each stage.

[0036] In some embodiments of this application, the instruction information includes, but is not limited to, one or more of the following: the PC address information corresponding to the instruction, the binary code information of the instruction, the instruction number information in the rearranged buffer virtual queue, the target logical register information before the instruction is renamed, the target physical register information after the instruction is renamed, information related to integer registers, information related to floating-point registers, and information related to vector registers.

[0037] In some embodiments of this application, please refer to Figure 2 , Figure 2 This is a first logic diagram illustrating the process of a pipeline monitoring circuit monitoring the CPU core circuit in a CPU pipeline operation monitoring system provided in this application embodiment. (See diagram below.) Figure 2 As shown, the pipeline monitoring circuit includes a buffer 101, an update logic module 102, a retirement monitor 103, a rearrangement buffer virtual queue 104, and an output queue 105. The buffer 101, update logic module 102, retirement monitor 103, and output queue 105 are all connected to the rearrangement buffer virtual queue 104. In this embodiment, the pipeline monitoring circuit is separated from the CPU core circuit, realizing a monitoring mechanism independent of the CPU core main circuit. By monitoring the core modules involved in the instruction pipeline operation in the CPU core circuit, instruction information generated by the CPU core circuit at different stages of the instruction pipeline is captured. The core modules involved in the instruction pipeline operation in the CPU core circuit include, but are not limited to, the decoding module, the execution module, and the retirement buffer module.

[0038] In this embodiment, the buffer 101 in the pipeline monitoring circuit is connected to the decoding module in the CPU core circuit, enabling monitoring of the decoding module and capturing the first instruction information generated during the acquisition, decoding, and distribution phases of the target instruction. In the pipeline monitoring circuit, the buffer 101 is connected to the rearrangement buffer virtual queue 104, allowing the target instruction and its first instruction information to be written into the rearrangement buffer virtual queue 104. In this embodiment, the first instruction information may include, but is not limited to, the original information of the target instruction and related PC address information, logical register number and related instruction type information, physical register number information, and the number information when the target instruction is written into the rearrangement buffer virtual queue. It can be understood that the PC address is the memory address of the next instruction to be executed in the CPU pipeline, stored in the program counter (PC). The PC address is the address of the instruction in the program counter (PC).

[0039] The update logic module 102 in the pipeline monitoring circuit is connected to the execution module in the CPU core circuit, enabling monitoring of the execution module and capturing the second instruction information generated by the target instruction during its execution phase. In the pipeline monitoring circuit, the update logic module 102 is connected to the rearrangement buffer virtual queue 104, and can update the first instruction information of the target instruction in the rearrangement buffer virtual queue 104 according to the second instruction information. In this embodiment, the second instruction information may include, but is not limited to, instruction information generated after the target instruction is executed, such as integer register-related information, floating-point register-related information, vector register-related information, etc.

[0040] The retirement monitor 103 in the pipeline monitoring circuit is connected to the retirement buffer module in the CPU core circuit, enabling monitoring of the retirement buffer module and capturing the third instruction information generated by the target instruction during the retirement stage. In the pipeline monitoring circuit, the retirement monitor 103 is connected to the rearrangement buffer virtual queue 104, and can move the target instruction and its first instruction information from the rearrangement buffer virtual queue 104 to the output queue 105 based on the third instruction information. In this embodiment, the third instruction information may include, but is not limited to, the number of retirement instructions and the corresponding number information of each retirement instruction in the rearrangement buffer virtual queue. The rearrangement buffer virtual queue 104 stores the relevant instruction information of all instructions entering the instruction pipeline in the CPU core circuit. Each instruction written to the rearrangement buffer virtual queue 104 has a corresponding number information, which flows continuously with the instruction in the instruction pipeline. This ensures that regardless of the stage of the instruction pipeline, the relevant instruction information of the instruction can be found in the rearrangement buffer virtual queue 104 based on the number information. Therefore, based on the third instruction information, the corresponding instruction and its instruction information can be found in the rearranged buffer virtual queue 104 and moved to the output queue 105. It is understandable that the retirement buffer module in the CPU core circuit can use a general-purpose control module to implement its specific functions. In this case, the pipeline monitoring circuit can connect to the general-purpose control module through a retirement monitor to monitor the retirement stage of the CPU core circuit.

[0041] In some embodiments of this application, non-intrusive connections can be established between the buffer and the decoding module in the CPU core circuit, between the update logic module and the execution module in the CPU core circuit, and between the retirement monitor and the retirement buffer module in the CPU core circuit. This facilitates the separation of the pipeline monitoring circuit and the CPU core circuit. Specifically, this non-intrusive connection can be a non-intrusive connection based on the UVM Interface. It is understood that UVM (Universal Verification Methodology) refers to a verification methodology in the field of integrated circuit design, built on SystemVerilog to create a verification environment, primarily used to improve the level of verification automation and shorten chip development cycles. In UVM verification, a non-intrusive connection interface typically refers to communication between components through a standard interface protocol without modifying the original design.

[0042] In some embodiments of this application, please refer to Figure 3 , Figure 3 This is another schematic diagram of the CPU pipeline operation monitoring system provided in an embodiment of this application. (See diagram below.) Figure 3 As shown, the buffers in the pipeline monitoring circuit specifically include a pre-decoding buffer 1011, a pre-renaming buffer 1012, a post-renaming buffer 1013, and a transmission buffer 1014. In this embodiment, when the pipeline monitoring circuit 10 captures the first instruction information generated by the target instruction during the acquisition, decoding, and distribution stages through the buffer 101, it specifically does so as follows: It captures the instruction information generated by the decoding module during the acquisition stage before decoding through the pre-decoding buffer 1011, wherein the instruction information before decoding includes the original information of the target instruction and related PC address information; it captures the instruction information generated by the decoding module during the decoding stage after decoding and before renaming through the pre-renaming buffer 1012, wherein the instruction information before renaming includes logical register numbers and related instruction type information; it captures the instruction information generated by the decoding module during the decoding stage after renaming through the post-renaming buffer 1013, wherein the instruction information after renaming includes physical register number information; and it captures the instruction information generated by the decoding module during the distribution stage and distributed to the execution module through the send buffer 1014, wherein the instruction information distributed to the execution module includes the distribution order of the target instruction and its number in the rearrangement buffer virtual queue when written into the rearrangement buffer virtual queue.

[0043] In some embodiments of this application, such as Figure 3As shown, the event printing device 20 includes an event acquisition printing module 201, an event distribution printing module 202, an execution event printing module 203, and a retirement event printing module 204. In this embodiment, the event printing device 20 can classify events according to the timing when the pipeline monitoring circuit 10 captures instruction information. The event printing device 20 is equipped with multiple event printing modules according to instruction event categories, with one event printing module corresponding to each instruction event category. This allows the target instruction to be displayed at an intermediate stage in the instruction pipeline and can also prompt the CPU core circuit developers about the current execution status of the target instruction in the instruction pipeline stage.

[0044] In this device, the event printing module 201 in the event printing device 20 is communicatively connected to the pre-decoding buffer 1011 in the pipeline monitoring circuit 10. Whenever a new instruction enters the decoding module in the CPU core circuit, the pre-decoding buffer 1011 can promptly detect and capture the relevant information. This new instruction is the target instruction. When the pre-decoding buffer 1011 captures the instruction information before decoding the target instruction, it promptly communicates with the event printing device 20, triggering the event printing module 201 in the event printing device 20 to print and output the instruction information before decoding the target instruction. The instruction information printed and output by the event printing module 201 includes the original instruction code of the target instruction and its corresponding PC address.

[0045] In this device, the event printing module 202 in the event printing device 20 is communicatively connected to the send buffer 1014 in the pipeline monitoring circuit 10. Whenever a target instruction is distributed from the decoding module to the execution module in the CPU core circuit, the target instruction will be assigned a number. The send buffer 1014 can detect this in time and capture the relevant information. When the send buffer 1014 captures the instruction information of the target instruction distributed to the execution module, it will communicate with the event printing device 20 in time to trigger the event printing module 202 in the event printing device 20 to print and output the instruction information of the target instruction distributed to the execution module. The instruction information printed and output by the event printing module 202 includes the number assigned when the target instruction is distributed, as well as the physical register number and logical register number assigned to the target instruction.

[0046] In this device, the execution event printing module 203 in the event printing device 20 is communicatively connected to the update logic module 102 in the pipeline monitoring circuit 10. Whenever a target instruction in the CPU core circuit is executed and the corresponding register is changed, the update logic module 102 can detect it in time and capture the relevant information. When the update logic module 102 captures the second instruction information generated by the target instruction during the execution phase, it will communicate with the event printing device 20 in time to trigger the execution event printing module 203 in the event printing device 20 to print and output the second instruction information. The second instruction information printed and output by the execution event printing module 203 includes the modified register information corresponding to the target instruction.

[0047] The retirement event printing module 204 in the event printing device 20 is communicatively connected to the output queue 105 in the pipeline monitoring circuit 10. Whenever a target instruction in the CPU core circuit completes execution and enters the retirement buffer module, the retirement monitor 103 in the pipeline monitoring circuit 10 can promptly detect and capture relevant information. The pipeline monitoring circuit 10 will traverse the information stored in the rearranged buffer virtual queue 104 based on the information captured by the retirement monitor 103, and move the first instruction information related to the target instruction entering the retirement buffer module from the rearranged buffer virtual queue 104 to the output queue 105. When the target instruction and its first instruction information are moved from the rearranged buffer virtual queue 104 to the output queue 105, it will promptly communicate with the event printing device 20, triggering the retirement event printing module 204 in the event printing device 20 to print and output the target instruction and its first instruction information moved to the output queue 105. This target instruction and its first instruction information are the specific information of the retired instruction.

[0048] In some embodiments of this application, please refer to Figure 4 , Figure 4 This is a flowchart illustrating the implementation of a CPU pipeline operation monitoring method provided in an embodiment of this application. Figure 4 As shown, it may specifically include steps S41 to S42.

[0049] S41: Monitor the operating status of the CPU core circuit through the pipeline monitoring circuit, and capture the instruction information generated by the CPU core circuit at different stages of the instruction pipeline, the instruction pipeline including the fetch stage, decode stage, issue stage, execution stage and retirement stage;

[0050] S42: When the pipeline monitoring circuit captures instruction information, it triggers the event printing module corresponding to the instruction event category to print and output the instruction information according to the instruction event category that generated the instruction information. The instruction event category includes acquisition event category, distribution event category, execution event category and retirement event category.

[0051] In this embodiment, based on the CPU pipeline operation monitoring system provided in the above embodiments, the CPU core circuit is connected to the pipeline monitoring circuit in the CPU pipeline operation monitoring system. The pipeline monitoring circuit monitors the operating status of the CPU core circuit and captures the instruction information generated by the CPU core circuit at different stages of the instruction pipeline. The CPU pipeline operation monitoring system also includes an event printing device, which is communicatively connected to the pipeline monitoring circuit. When the pipeline monitoring circuit captures instruction information, the event printing device triggers the event printing module corresponding to the instruction event category that generated the instruction information to print and output the generated instruction information. In this embodiment, the instruction pipeline includes an acquisition stage, a decoding stage, a dispatch stage, an execution stage, and a retirement stage. Instruction event categories include acquisition events, dispatch events, execution events, and retirement events. In the instruction pipeline, instruction information generated during the retrieval phase is categorized into retrieval event classes, which are printed and output by the retrieval event printing module in the event printing device. Similarly, instruction information generated during the distribution phase is categorized into distribution event classes, which are printed and output by the distribution event printing module in the event printing device. It can be understood that instruction information generated during the decoding phase can be merged with that generated during the distribution phase and printed and output by the distribution event printing module. Instruction information generated during the execution phase is categorized into execution event classes, which are printed and output by the execution event printing module in the event printing device. Finally, instruction information generated during the retirement phase is categorized into retirement event classes, which are printed and output by the retirement event printing module in the event printing device.

[0052] In some embodiments of this application, please refer to Figure 5 , Figure 5 This is a second logic diagram illustrating the monitoring of the CPU core circuit by the pipeline monitoring circuit in the CPU pipeline operation monitoring system provided in this application embodiment. For example... Figure 5As shown, when monitoring the operating status of the CPU core circuit through the CPU pipeline monitoring system provided in this embodiment, it can specifically include one or more of the following monitoring logics: Monitoring the decoding module in the CPU core circuit through a pre-decoding buffer in the pipeline monitoring circuit; when the decoding module receives a target instruction, the pre-decoding buffer captures the PC address information and binary code information corresponding to the target instruction. Monitoring the decoding module in the CPU core circuit through a pre-renaming buffer in the pipeline monitoring circuit; after the decoding module decodes the target instruction, the pre-renaming buffer captures the target logical register information before the target instruction is renamed. Monitoring the decoding module in the CPU core circuit through a post-renaming buffer in the pipeline monitoring circuit; after the decoding module renames the target instruction, the post-renaming buffer captures the target physical register information after the target instruction is renamed. Monitoring the decoding module in the CPU core circuit through a send buffer in the pipeline monitoring circuit; when the decoding module distributes the target instruction, the send buffer captures the distribution order information of the target instruction and its number information in the rearrangement buffer virtual queue. The pipeline monitoring circuit monitors the execution modules in the CPU core circuit through an update logic module. When an execution module finishes executing a target instruction, the update logic module retrieves the register-related information of the target instruction, including but not limited to integer register information, floating-point register information, and vector register information. In this embodiment, there can be multiple execution modules in the CPU core circuit, such as a floating-point execution module, an integer execution module, and a vector execution module. In a specific implementation, the pipeline monitoring circuit can also monitor the load-memory module in the CPU core circuit through an update logic module, thereby enabling timely feedback to the update logic module when cached data in the CPU core circuit is updated. The pipeline monitoring circuit also monitors the retirement cache module in the CPU core circuit through a retirement monitor. When a retirement instruction is received by the retirement cache module, the retirement monitor reads the number of retirement instructions and the number of each retirement instruction in the rearranged buffer virtual queue.

[0053] In some embodiments of this application, different execution modules may have different numbers of pipeline stages in the CPU core circuitry. Please refer to... Figure 6 , Figure 6 This is a third logic diagram illustrating the monitoring of the CPU core circuit by the pipeline monitoring circuit in the CPU pipeline operation monitoring system provided in this application embodiment. (See diagram below.) Figure 6As shown, the integer execution module in the CPU core circuit can be configured as a three-stage pipeline, specifically including integer operator fetching, level-one integer instruction execution, and level-two integer instruction execution. The floating-point execution module in the CPU core circuit can be configured as a four-stage pipeline, specifically including floating-point operator fetching, level-one floating-point instruction execution, level-two floating-point instruction execution, and level-three floating-point instruction execution. During the execution phase, the various execution modules in the CPU core circuit are in an out-of-order execution state. When the pipeline monitoring circuit monitors, it captures instruction information from the end-of-run signal based on the signal characteristics of each execution module, and then updates the corresponding information in the rearranged virtual queue based on the captured instruction information. The instruction information capture and update process during the execution phase mainly consists of three steps, such as... Figure 6 The steps are A1, A2, and A3. Step A1 specifically monitors whether each execution module has a completion signal. If so, it triggers the update logic's condition signal and records the target instruction's ID in the rearrangement buffer virtual queue. Step A2 specifically retrieves the corresponding register value and register ID in the execution module based on the condition signal triggered in step A1. Step A3 specifically updates the register information and value in the rearrangement buffer virtual queue corresponding to the instruction's ID based on the target instruction's ID recorded in step A1 and the register value and register ID retrieved in step A2. During retirement, the pipeline monitoring circuit can monitor retired instructions in the CPU core circuitry through a retirement monitor and delete the corresponding instruction information. The monitoring and deletion process for instruction information during retirement mainly consists of four steps, such as... Figure 6 The steps are B1, B2, B3, and B4. Specifically, step B1 involves monitoring the number of retired instructions in the retirement cache module and retrieving the instruction numbers in the rearrangement buffer virtual queue. Step B2 involves monitoring changes in registers in each execution module to adapt to different instruction update cycles. Step B3 involves finding the corresponding instruction and its information in the rearrangement buffer virtual queue based on the number of retired instructions obtained in step B1 and the retrieving instruction numbers in the rearrangement buffer virtual queue. Step B4 involves removing the instruction and its information found in step B3 from the rearrangement buffer virtual queue and placing the removed instruction and its information into the output queue. When the pipeline monitoring circuit in the CPU pipeline operation monitoring system retrieves instruction information, the description and data format of the instruction information are shown in Table 1 below:

[0054] Table 1

[0055]

[0056] The instruction information stored in the rearranged virtual queue and the output queue includes the following: Rob_id, representing the instruction's ID in the rearranged virtual queue; Pc_addr, representing the PC address corresponding to the instruction; Pc_data, representing the instruction's binary code; Pre_reg, representing the target logical register information before renaming; Post_reg, representing the target physical register information after renaming; Xreg, representing integer register information; Freg, representing floating-point register information; and Vreg, representing vector register information.

[0057] It is understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0058] In some embodiments of this application, please refer to Figure 7 , Figure 7 This is a basic structural block diagram of an electronic device provided in an embodiment of this application. Figure 7 As shown, the electronic device 7 of this embodiment includes: a processor 71, a memory 72, and a computer program 73 stored in the memory 72 and executable on the processor 71, such as a program for a CPU pipeline operation monitoring method. When the processor 71 executes the computer program 73, it implements the steps in the various embodiments of the CPU pipeline operation monitoring methods described above. Alternatively, when the processor 71 executes the computer program 73, it implements the functions of each module in the embodiments corresponding to the CPU pipeline operation monitoring system described above. Please refer to the relevant descriptions in the embodiments for details, which will not be repeated here.

[0059] For example, the computer program 73 can be divided into one or more modules (units) for performing the various steps in the above method embodiments. The one or more modules are stored in the memory 72 and executed by the processor 71 to complete this application. The one or more modules can be a series of computer program instruction segments capable of performing specific functions, which describe the execution process of the computer program 73 in the electronic device 7.

[0060] The electronic device may include, but is not limited to, a processor 71 and a memory 72. Those skilled in the art will understand that... Figure 7 This is merely an example of electronic device 7 and does not constitute a limitation on electronic device 7. It may include more or fewer components than shown, or combine certain components, or different components. For example, the electronic device may also include input / output devices, network access devices, buses, etc.

[0061] The processor 71 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0062] The memory 72 can be an internal storage unit of the electronic device 7, such as a hard disk or memory. The memory 72 can also be an external storage device of the electronic device 7, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory 72 can include both internal and external storage units of the electronic device 7. The memory 72 is used to store the computer program and other programs and data required by the electronic device. The memory 72 can also be used to temporarily store data that has been output or will be output.

[0063] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0064] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can implement the steps in the various method embodiments described above. In this embodiment, the computer-readable storage medium can be either non-volatile or volatile.

[0065] This application provides a computer program product that, when run on a mobile terminal, enables the mobile terminal to implement the steps described in the various method embodiments.

[0066] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above device can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0067] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0068] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0069] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A CPU pipeline operation monitoring system independent of CPU core circuit logic, characterized in that, It includes a pipeline monitoring circuit and an event printing device, wherein the pipeline monitoring circuit is communicatively connected to the event printing device, wherein: The pipeline monitoring circuit is used to monitor the operating status of the CPU core circuit and capture the instruction information generated by the CPU core circuit at different stages of the instruction pipeline. The instruction pipeline includes the fetch stage, decode stage, issue stage, execution stage, and retirement stage. The event printing device is used to trigger the event printing module corresponding to the instruction event category to print and output the instruction information when the pipeline monitoring circuit captures instruction information, according to the instruction event category that generated the instruction information. The instruction event categories include acquisition event category, distribution event category, execution event category, and retirement event category. The pipeline monitoring circuit includes a buffer, an update logic module, a retirement monitor, a rearrangement buffer virtual queue, and an output queue. The buffer, the update logic module, the retirement monitor, and the output queue are respectively connected to the rearrangement buffer virtual queue, wherein: The buffer is connected to the decoding module in the CPU core circuit and is used to monitor the decoding module and capture the first instruction information generated by the target instruction during the acquisition, decoding and distribution stages. The buffer is connected to the rearranged buffer virtual queue and is used to write the target instruction and its first instruction information into the rearranged buffer virtual queue. The update logic module is connected to the execution module in the CPU core circuit and is used to monitor the execution module and capture the second instruction information generated by the target instruction during the execution phase. The update logic module is connected to the rearrangement buffer virtual queue and is used to update the first instruction information of the target instruction in the rearrangement buffer virtual queue according to the second instruction information. The retirement monitor is connected to the general control module or retirement buffer module in the CPU core circuit, and is used to monitor the general control module or retirement buffer module, capture the third instruction information generated by the target instruction during the retirement stage, and the retirement monitor is connected to the rearrangement buffer virtual queue, and is used to move the target instruction and its first instruction information from the rearrangement buffer virtual queue to the output queue according to the third instruction information.

2. The CPU pipeline operation monitoring system according to claim 1, characterized in that, The buffer includes a pre-decoding buffer, a pre-renaming buffer, a post-renaming buffer, and a sending buffer, wherein: The pre-decoding buffer is used to capture instruction information generated by the decoding module during the acquisition phase before the target instruction is decoded. The pre-renaming buffer is used to capture instruction information generated by the decoding module during the decoding stage before the target instruction is renamed after decoding. The renamed buffer is used to capture the renamed instruction information of the target instruction generated by the decoding module during the decoding stage. The sending buffer is used to capture the instruction information generated by the decoding module during the distribution phase and distributed to the execution module.

3. The CPU pipeline operation monitoring system according to claim 2, characterized in that, The event printing device includes an event printing acquisition module, an event printing distribution module, an event printing execution module, and a retirement event printing module, wherein: The event acquisition and printing module is communicatively connected to the pre-decoding buffer. When the pre-decoding buffer captures the instruction information before the target instruction is decoded, it triggers the event acquisition and printing module to print and output the instruction information before the target instruction is decoded. The dispatch event printing module is communicatively connected to the sending buffer. When the sending buffer captures the instruction information of the target instruction dispatched to the execution module, it triggers the dispatch event printing module to print and output the instruction information of the target instruction dispatched to the execution module. The execution event printing module is communicatively connected to the update logic module. When the update logic module captures the second instruction information generated by the target instruction during the execution phase, it triggers the execution event printing module to print and output the second instruction information. The retirement event printing module is communicatively connected to the output queue. When the target instruction and its first instruction information are moved from the rearranged buffer virtual queue to the output queue, the retirement event printing module is triggered to print and output the target instruction and its first instruction information that have been moved to the output queue.

4. The CPU pipeline operation monitoring system according to claim 1, characterized in that, The buffer is connected non-intrusively to the decoding module in the CPU core circuit, the update logic module is connected to the execution module in the CPU core circuit, and the retirement monitor is connected to the general control module or retirement buffer module in the CPU core circuit.

5. The CPU pipeline operation monitoring system according to any one of claims 1-4, characterized in that, The instruction information includes one or more of the following: the PC address information corresponding to the instruction, the binary code information of the instruction, the instruction number information in the rearranged buffer virtual queue, the target logical register information before the instruction is renamed, the target physical register information after the instruction is renamed, information related to integer registers, information related to floating-point registers, and information related to vector registers.

6. A method for monitoring CPU pipeline operation independent of CPU core circuit logic, characterized in that, include: The CPU core circuit's operating status is monitored by a pipeline monitoring circuit, which captures instruction information generated by the CPU core circuit at different stages of the instruction pipeline, including the fetch stage, decode stage, issue stage, execution stage, and retirement stage. When the pipeline monitoring circuit captures instruction information, it triggers the event printing module corresponding to the instruction event category to print and output the instruction information according to the instruction event category that generated the instruction information. The instruction event category includes acquisition event, distribution event, execution event and retirement event. The pipeline monitoring circuit includes a buffer, an update logic module, a retirement monitor, a rearrangement buffer virtual queue, and an output queue. The buffer, update logic module, retirement monitor, and output queue are each connected to the rearrangement buffer virtual queue. The buffer is connected to the decoding module in the CPU core circuit and is used to monitor the decoding module, capturing the first instruction information generated by the target instruction during the acquisition, decoding, and distribution stages. The buffer is also connected to the rearrangement buffer virtual queue and is used to write the target instruction and its first instruction information into the rearrangement buffer virtual queue. The update logic module is connected to the execution module in the CPU core circuit and is used to monitor the execution... The execution module captures the second instruction information generated by the target instruction during the execution phase. The update logic module is connected to the rearrangement buffer virtual queue and is used to update the first instruction information of the target instruction in the rearrangement buffer virtual queue according to the second instruction information. The retirement monitor is connected to the general control module or retirement buffer module in the CPU core circuit and is used to monitor the general control module or retirement buffer module, capture the third instruction information generated by the target instruction during the retirement phase, and is connected to the rearrangement buffer virtual queue. It is used to remove the target instruction and its first instruction information from the rearrangement buffer virtual queue to the output queue according to the third instruction information.

7. The CPU pipeline operation monitoring method according to claim 6, characterized in that, The steps of monitoring the operating status of the CPU core circuit and capturing instruction information generated by the CPU core circuit at different stages of the instruction pipeline include: Monitor the decoding module in the CPU core circuitry; when the decoding module receives a target instruction, capture the PC address information and binary code information corresponding to the target instruction; and / or The CPU core circuitry is monitored, and after the decoding module decodes the target instruction, the target logic register information before the target instruction is renamed is captured; and / or Monitor the decoding module in the CPU core circuitry; when the decoding module renames the target instruction, capture the target physical register information after the target instruction is renamed; and / or Monitor the decoding module in the CPU core circuitry; when the decoding module distributes the target instruction, capture the distribution order information of the target instruction and its number information in the rearranged buffer virtual queue; and / or Monitor the execution module in the CPU core circuitry, and when the execution module finishes executing the target instruction, capture the register-related information of the target instruction; and / or The CPU core circuitry is monitored for retirement cache modules. When a retirement instruction is received by the retirement cache module, the number of retirement instructions and the number of each retirement instruction in the rearranged buffer virtual queue are read.

8. The CPU pipeline operation monitoring method according to claim 7, characterized in that, The step of monitoring the execution module in the CPU core circuit and capturing the register-related information of the target instruction when the execution module finishes executing the target instruction includes: Monitor whether there is a run-end signal in the execution module of the CPU core circuit. If there is, trigger the condition signal of the update logic and record the number information of the target instruction corresponding to the run-end signal in the rearranged buffer virtual queue. The value and register number information corresponding to the register in the execution module are retrieved based on the condition signal.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the functions of the system according to any one of claims 1-5 or the steps of the method according to any one of claims 6-8.

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