Server power-on display method and device, electronic equipment and storage medium

Abstract

The application discloses a power-on display method and device of a server, electronic equipment and a storage medium, relates to the technical field of computers, and comprises the following steps: in response to a power-on instruction of the server, at least one key hardware device except memory is initialized, a first initialization completion event is triggered when the initialization is completed, corresponding bus numbers are written for at least one node of a hardware link where a target display module is located in a baseboard management controller, memory resource addresses, input / output resource addresses, memory base address registers and input / output base address registers are allocated, a second initialization completion event is generated, and finally, power-on self-test data is generated and displayed on a display device, so that the problems of a too long black screen time in an early server starting stage and difficult fault diagnosis are solved, the initialization of the display device is brought forward to an early PEI stage, the initialization of the display device is brought forward by using an event triggering mechanism, early display functions are realized, and the hardware operation and maintenance efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and particularly relates to a server power-on display method and device, electronic equipment and a storage medium. BACKGROUND

[0002] In a startup process, a server will execute UEFI (Unified Extensible Firmware Interface) BIOS (Basic Input Output System) firmware code, but as more and more devices are integrated together, the time between the start of the BIOS and the completion of the initialization of the display device will be longer and longer.

[0003] In the related art, the initialization of the display device is usually performed in the DXE (Driver Execution Environment) phase, which will cause the display device to be in a black screen state in the PEI (Pre-EFI Initialization) phase before the DXE phase, some key hardware initialization, so that the user may not be able to discover abnormal conditions of the hardware in time during this period, thereby causing difficulty in diagnosing hardware faults, which needs to be solved urgently. SUMMARY

[0004] The present application provides a server power-on display method and device, electronic equipment and a storage medium to at least solve the problem of long black screen time and difficult fault diagnosis in the early stage of server startup in the related art.

[0005] The present application provides a server power-on display method, the server comprising a baseboard management controller and a display device, the baseboard management controller being connected to the display device, wherein the method comprises the following steps: in response to a power-on instruction of the server, initializing at least one key hardware device except for a memory, and triggering a first initialization completion event when the at least one key hardware device completes the initialization; in response to the first initialization completion event, writing a corresponding bus number for at least one node of a hardware link where a target display module is located in the baseboard management controller, and allocating a memory resource address and an input / output resource address for the target display module in the baseboard management controller, and configuring a memory base address register and an input / output base address register of the target display module in the baseboard management controller to generate a second initialization completion event; in response to the second initialization completion event, generating power-on self-test data based on the second initialization completion event, and outputting the power-on self-test data to the display device for display.

[0006] The application further provides a server power-on display device, the server comprising a baseboard management controller and a display device, the baseboard management controller being connected with the display device, wherein the baseboard management controller comprises:

[0007] an initialization module, configured to initialize at least one key hardware device except memory in response to a power-on instruction of the server, and trigger a first initialization completion event when the at least one key hardware device completes initialization;

[0008] a generation module, configured to write a corresponding bus number for at least one node of a hardware link where a target display module is located in the baseboard management controller in response to the first initialization completion event, and allocate a memory resource address and an input / output resource address for the target display module in the baseboard management controller, and configure a memory base address register and an input / output base address register of the target display module in the baseboard management controller to generate a second initialization completion event;

[0009] a data output module, configured to generate power-on self-test data based on the second initialization completion event in response to the second initialization completion event, and output the power-on self-test data to the display device for display.

[0010] The application further provides an electronic device, comprising a memory for storing a computer program, and a processor for executing the computer program to implement the steps of any one of the server power-on display methods.

[0011] The application further provides a computer readable storage medium, the computer readable storage medium storing a computer program, wherein the computer program is executed by a processor to implement the steps of any one of the server power-on display methods.

[0012] The application further provides a computer program product, comprising a computer program, the computer program being executed by a processor to implement the steps of any one of the server power-on display methods.

[0013] Through the application, at least one key hardware device except memory is initialized in response to a power-on instruction of a server, and a first initialization completion event is triggered when the initialization is completed, a corresponding bus number is written for at least one node of a hardware link where a target display module is located in a baseboard management controller, and a memory resource address, an input / output resource address, a memory base address register and an input / output base address register are allocated, so as to generate a second initialization completion event, and finally, power-on self-test data is generated and displayed on a display device, thereby solving the problems of long black screen time in the early server startup and difficult fault diagnosis, and through early initialization of the display device to the early PEI stage and early completion of the initialization of the display device by using an event triggering mechanism, early display function is realized, and hardware operation and maintenance efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0015] Figure 1 A flowchart of a server power-on display method according to an embodiment of the present application is provided.

[0016] Figure 2 A system architecture diagram of an Intel Birch Stream and later CPU (Central Processing Unit) platform \ Amd CPU platform according to an embodiment of the present application is provided.

[0017] Figure 3 A system architecture diagram of an Intel Eagle Stream and earlier CPU platform according to an embodiment of the present application is provided.

[0018] Figure 4 A module design and data flow diagram according to an embodiment of the present application is provided.

[0019] Figure 5 A BIOS code module initialization process diagram according to an embodiment of the present application is provided.

[0020] Figure 6 A trigger module flowchart according to an embodiment of the present application is provided.

[0021] Figure 7 A display calculation unit initialization flowchart according to an embodiment of the present application is provided.

[0022] Figure 8Fig. 1 is a flowchart illustrating a display function module initialization process according to an embodiment of the present application;

[0023] Figure 9 Fig. 2 is a block diagram of a server power-on display device according to an embodiment of the present application;

[0024] Figure 10 Fig. 3 is a structural diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, any other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0026] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0027] In order for those skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0028] Specifically, before introducing the embodiments of the present application, first introduce the related background of the present application and the problems existing in the prior art.

[0029] In the startup process of a computer system, especially a server, a POST (Power-On Self Test) process is experienced to check whether the hardware is working properly. In a UEFI system, the startup process can be divided into seven stages, including SEC (Security Phase), PEI, DXE, BDS (Boot Device Selection), TSL (Transient System Load), RT (Run Time) and AL (After Life) stages.

[0030] In a traditional startup process, the scanning of a PCIe (peripheral component interconnect express) bus, enumeration of devices, and loading and initialization of drivers of display devices (such as graphics cards) usually occur in the DXE stage. This means that, during the process from power-on of the system to completion of the DXE stage, the server screen is in a "black screen" state, and as the server integration level increases and the hardware complexity increases, this black screen time can be as long as tens of seconds. As a result, the long black screen greatly disturbs the user: the user cannot determine whether the server is normally starting, starting slowly, or has failed, resulting in a very poor user experience. More importantly, if a hardware failure (such as a CPU or memory initialization failure) occurs in an early stage such as PEI, since the display device is not ready at this time, any error information cannot be output to the screen, making fault diagnosis extremely difficult. Only limited means such as diagnostic lights or buzzers on the motherboard can be relied on, which seriously reduces the operation and maintenance efficiency.

[0031] Therefore, in order to solve the problem of no output of the display in the power-on self-test stage of the above-mentioned system, and output error indication to the display screen in this stage, some solutions are proposed in the related art, for example, by adding a set of independent display unit on the server motherboard, specifically including (1) a server display device, at least including a PCH (Platform Controller Hub), a BMC (Baseboard Management Controller), and a newly added display unit connected with the PCH and the BMC, the newly added display unit at least including an EPLD (Erasable Programmable Logic Device) and a switching device; (2) the newly added display unit, when the BMC has not started, if the start state signal sent by the PCH is detected, the pre-stored information is output to the display screen, and when it is detected that the display module of the BMC has been initialized, the VGA (Video Graphics Array) signal output by the display module of the BMC is switched to the display screen; (3) the EPLD is connected with the PCH, the BMC and the switching device, when the BMC has not started, if the start state signal sent by the PCH is detected, the input selection signal of the switching device is controlled to be the VGA signal output by the EPLD, and when it is detected that the display module of the BMC has been initialized, the input selection signal of the switching device is controlled to be the VGA signal output by the display module of the BMC; (4) the switching device is connected with the BMC and the EPLD, when the input selection signal is controlled by the EPLD or the BMC to be the VGA signal output by the EPLD, the pre-stored information in the EPLD is output to the display screen, and when the input selection signal is controlled by the EPLD to be the VGA signal output by the display module of the BMC, the VGA signal output by the display module of the BMC is switched to the display screen.

[0032] However, the above-mentioned solution needs to add extra hardware, which increases the cost, and the output static information cannot truly reflect the real-time state and specific error code of the system, there may be a situation that the output pre-stored information does not match the real state of the system, which cannot accurately reflect the system state and has limited diagnostic value.

[0033] Therefore, there is an urgent need for a solution that can display quickly after the server is powered on without increasing hardware costs, to monitor the start state in real time and output error information, which will be described in detail below in conjunction with specific embodiments.

[0034] The embodiments of the present application provide a server power-on display method, which is described in detail in combination with the execution process of the server power-on display method.

[0035] Specifically,Figure 1 This is a flowchart illustrating a server power-on display method provided in an embodiment of the present invention.

[0036] like Figure 1 As shown, in the power-on display method for the server, the server includes a baseboard management controller and a display device, the baseboard management controller is connected to the display device, and the method includes the following steps:

[0037] In step S101, in response to the power-on command of the server, at least one critical hardware device other than memory is initialized, and a first initialization completion event is triggered when at least one critical hardware device completes initialization.

[0038] Specifically, firstly, let me introduce the service life display system architecture involved in the embodiments of this application. The CPU platform architectures of different manufacturers, or even different eras of CPU systems from the same manufacturer, differ. Figure 2 As shown, a server display device includes at least a CPU, BMC, and BIOS chip, but for Intel Eagle Stream and earlier CPU platforms, such as Figure 3 As shown, in addition to the server display device mentioned above, a PCH is also required. This is a component that is included in all server system architectures and does not require additional hardware. The BIOS chip is used to store BIOS code and connects to the PCH or CPU via the SPI (Serial Peripheral Interface) protocol. The display module in the BMC is a display computing unit that connects to the CPU or PCH via the PCIe bus. The display data it generates is output to the monitor via a VGA cable, and then the monitor completes the display function.

[0039] Specifically, based on the problems existing in related technologies, namely the "long early black screen period" caused by the late initialization of the display device during server startup, and the difficulty in diagnosing hardware faults and resulting in low maintenance efficiency if hardware abnormalities occur during this period, the embodiments of this application advance the initialization of the display device to the early stage of PEI, that is, the screen is lit up before the initialization of hardware devices such as CPU and memory. In this way, all POST process information can be displayed on the screen, and even if problems are encountered in the POST stage, the user can promptly display the error information.

[0040] Therefore, the embodiment of the present application initiates the hardware device in advance to the PEI stage, and in the PEI stage, a pure software method is used, i.e. by modifying and optimizing the BIOS firmware code, the event mechanism (PreMemoryInitDone+ EarlyVideoInitDone) of the PEI stage is used to complete the initialization of the display device (integrated in the BMC) in advance before the initialization of the CPU and the memory and other hardware devices, so as to realize the early display function. The initialization process in the PEI stage will be described in detail below.

[0041] After the system is powered on, the CPU reads the BIOS code in the BIOS chip through the SPI protocol, executes the BIOS code to enter the PEI stage, and then performs the display device initialization before the CPU initialization in the PEI stage, and installs the early display device display interface PPI (PEIM-to-PEIM Interfaces, PEIM (Pre-EFI Initialization Module) to PEIM interface) after the display device initialization is completed, so as to provide an interface program for outputting information in the power-on self-test stage. The error information found in the power-on self-test process and the self-test process of the CPU, the memory, the PCIe and other hardware devices can be displayed on the display device (such as a VGA screen) by calling the display interface.

[0042] Further, as shown in Figure 4 , the initialization process in the PEI stage of the present application is mainly realized by three modules, which are a triggering module, a display computing unit initialization module and a display function module. The main purpose of the triggering module is to trigger the display initialization process at a sufficiently early time of the BIOS initialization after the system is powered on. The display computing unit initialization module is a target display module built in the BMC, which is used to monitor the display device initialization after the PreMemoryInitDone event. The display function module is a display device used for display. After the system is powered on, as shown in Figure 5 , the triggering module, the display computing unit initialization module and the display function module are initialized and executed synchronously in the PEI stage of the BIOS power-on self-test.

[0043] Specifically, as shown in Figure 6As shown, first, at least one key hardware device except memory is initialized in response to a power-on instruction of the server, and a first initialization completion event (e.g., a PreMemoryInitDone event, i.e., an initialization end event of other devices before memory initialization) is triggered when the at least one key hardware device completes the initialization, that is, after the BIOS code runs to the pre-PEI stage CPU initialization stage in response to the power-on instruction of the server, the PreMemoryInitDone event is triggered, and in the case of an Intel EMR CPU, the initialization end event of other devices before memory initialization is triggered when the PCH initialization is completed, then, in response to the first initialization completion event, an initialization process of the display computing unit initialization module is started, and the initialization operation of the display computing unit initialization module is started.

[0044] In step S102, in response to the first initialization completion event, a corresponding bus number is written in the at least one node of the hardware link where the target display module is located in the baseboard management controller, and the memory resource address and the input / output resource address of the target display module are allocated in the baseboard management controller, and the memory base address register and the input / output base address register of the target display module in the baseboard management controller are configured, to generate a second initialization completion event.

[0045] According to an embodiment of the present application, writing the corresponding bus number in the at least one node of the hardware link where the target display module is located in the baseboard management controller comprises: determining the device path of the at least one node of the hardware link where the target display module is located; determining a target node to which the bus number is to be written from the at least one node, and determining the bus number range of the target node according to the device path of the nodes between the target node and the target display module; and writing the bus number range to the target node.

[0046] Specifically, after the first initialization completion event is triggered, the first initialization completion event is monitored and responded to, and if it is monitored that the first initialization completion event before memory initialization is triggered, the display computing unit initialization module is initialized, that is, the target display module in the BMC is initialized.

[0047] Specifically, as shown in FIG. 1, the display computing unit initialization module comprises a display computing unit initialization module 1 and a display computing unit initialization module 2. Figure 7As shown, first, according to the actual situation of hardware design, the corresponding bus number (for example, the PCIe bus number) is written in the BMC for at least one node of the hardware link where the target display module is located, in the embodiment of the present application, the PCIe bus number needs to be written for all nodes on the path of the target display module, and the main process includes determining the device path of at least one node of the hardware link where the target display module is located, that is, the device path of all nodes on the PCIe path, which mainly includes the bus number, the device number and the function number; then, the target node to which the bus number needs to be written is determined from all nodes, and the target node can be the root port, the bridge and the target display module; finally, the bus number range of the target node is determined according to the device path of the nodes between the target node and the target display module, and the bus number range is written into the target node.

[0048] For example, if the nodes of the hardware link where the target display module is located are represented as the root port, the bridge and the target display module in the BMC from top to bottom, then according to the actual situation, the bus number, the device number and the function number of the device path of the root port are set to 0x0, 0xF and 0x0 respectively, the bus number, the device number and the function number of the device path of the bridge are set to 0x2, 0x0 and 0x0 respectively, and the bus number, the device number and the function number of the device path of the target display module are set to 0x3, 0x0 and 0x0 respectively.

[0049] It should be noted that the types of the above-mentioned root port and bridge are both bridges, so the bus number of the device path where the target display module is located needs to be set through the registers of the root port and the bridge, and the type of the target display module is the end device, and the register does not need to be set.

[0050] Further, after the bus numbers of the device paths of all nodes of the hardware link where the target display module is located are set respectively, the bus number range of the target node is further determined according to the device path of the nodes between the target node and the target display module, and the bus number range is written into the target node.

[0051] Therefore, by writing the PCIe bus number for all nodes on the path of the target display module, the CPU can directly address and access the target display module on the BMC before the system automatic enumeration process is started, realize the initialization in advance, and can bypass the firmware enumeration, significantly shorten the black screen time, and realize the real-time diagnosis of early hardware failure.

[0052] According to one embodiment of the present application, the bus number range of the target node is determined according to the device path of the nodes between the target node and the target display module, comprising: determining the start bus number of the bus number range according to the device path of the target node; determining the intermediate bus number according to the device path of the nodes between the target node and the target display module; determining the final bus number of the bus number range according to the device path of the target display module; and obtaining the bus number range according to the start bus number, the intermediate bus number and the final bus number.

[0053] According to one embodiment of the present application, the bus number range is written into the target node, comprising: writing the start bus number into the primary bus number of the target node; writing the bus number which is downstream of the target node and closest to the target node among the intermediate bus number into the secondary bus number of the target node; and writing the final bus number into the subordinate bus number of the target node.

[0054] Specifically, the process of determining the bus number range of the target node according to the device path of the nodes between the target node and the target display module mainly comprises: firstly, determining the start bus number of the bus number range according to the device path of the target node, when the target node is a root port, i.e. firstly determining the start bus number according to the device path of the root port, for example, setting the start bus number of the root port by writing the start bus number PrimaryBusNumber (offset 0x18) register in the PCIe configuration space of the root port as the preset bus number of the root port (0x0 in the embodiment of the present application); then, determining the intermediate bus number according to the device path of the nodes between the target node and the target display module, for example, setting the bus number of the next device of the root port by writing the intermediate bus number Secondary BusNumber (offset 0x19) register in the PCIe configuration space of the root port as the preset bus number of the bridge (0x2 in the embodiment of the present application); finally, determining the final bus number of the bus number range according to the device path of the target display module, for example, setting the final bus number of the last device of the root port by writing the final bus number SuboridinateBusNumber (offset 0x20) register in the PCIe configuration space of the root port as the preset bus number of the target display module (0x3 in the embodiment of the present application), thus obtaining the bus number range according to the above-mentioned start bus number, intermediate bus number and final bus number, and then writing the bus number range into the root port, i.e. writing the start bus number of the root port into the primary bus number of the root port, writing the bus number which is downstream of the root port and closest to the root port among the intermediate bus number of the root port into the secondary bus number of the root port, and writing the final bus number of the root port into the subordinate bus number of the root port.

[0055] Further, when the target node is a bridge, the starting bus number is first determined according to the device path of the bridge, for example, by writing the starting bus number PrimaryBusNumber (offset 0x18) register in the PCIe configuration space of the bridge to the bus number preset for the bridge (0x2 in the embodiment of the present application) to set the starting bus number of the bridge; then, the intermediate bus number is determined according to the device path between the target node and the target display module, for example, by writing the intermediate bus number Secondary BusNumber (offset 0x19) register in the PCIe configuration space of the bridge to the bus number preset for the target display module (0x3 in the embodiment of the present application) to set the bus number of the next device of the bridge; finally, the final bus number of the bus number range is determined according to the device path of the target display module, for example, by writing the final bus number SuboridinateBusNumber (offset 0x20) register in the PCIe configuration space of the bridge to the bus number preset for the target display module (0x3 in the embodiment of the present application) to set the final bus number of the last device of the bridge, then writing the starting bus number of the bridge to the primary bus number of the bridge, writing the intermediate bus number of the bridge to the secondary bus number of the bridge, writing the final bus number of the bridge to the subordinate bus number of the bridge, based on the determination of the above bus numbers, the bus addressing path from the CPU to the target display module is established.

[0056] Thus, by correctly setting the primary, secondary and subordinate bus numbers in the complex PCIe topology, the configuration cycle or data packet issued by the CPU can be correctly forwarded by the bridge device and finally reach the end display device, thereby completing the key transition from "software discovery" to "physical connection establishment" of the PCIe device, so that the system software can identify and control the display device through the standard PCIe configuration space read-write operation, and by allocating appropriate and non-overlapping bus number ranges for different PCIe links, the logical isolation of hardware resources is effectively realized, preventing the system conflict, crash or device identification failure caused by the allocation of multiple devices to the same bus number, at the same time, the PCIe switch can also quickly and accurately determine the forwarding path of the data packet according to these bus numbers, reducing unnecessary broadcast and search overhead, ensuring efficient and low-delay transmission of display data flow.

[0057] According to one embodiment of the present application, allocating memory resource addresses and input / output resource addresses for a target display module in a baseboard management controller comprises: identifying at least one memory base address register and at least one input / output base address register in the target display module; calculating a memory base address value of the at least one memory base address register and an input / output base address value of the at least one input / output base address register; and allocating the memory resource addresses and the input / output resource addresses for the target display module based on the memory base address value of the at least one memory base address register and the input / output base address value of the at least one input / output base address register.

[0058] According to one embodiment of the present application, identifying at least one memory base address register and at least one input / output base address register in a target display module comprises: writing a full mask value to at least one base address register of the target display module, and reading back the value of the at least one base address register to obtain a read-back value of the at least one base address register; and identifying the at least one memory base address register and the at least one input / output base address register based on the read-back value of the at least one base address register.

[0059] According to one embodiment of the present application, identifying the at least one memory base address register and the at least one input / output base address register based on the read-back value of the at least one base address register comprises: identifying, based on the read-back value of the at least one base address register, a base address register whose read-back value is valid and whose least significant bit is a memory bit, to obtain the at least one memory base address register; and identifying, based on the read-back value of the at least one base address register, a base address register whose read-back value is valid and whose next least significant bit is an input / output bit, to obtain the at least one input / output base address register.

[0060] Specifically, after writing the corresponding bus numbers for at least one node of a hardware link in which the target display module is located in the baseboard management controller, the baseboard management controller further allocates memory resource addresses and input / output resource addresses for the target display module, and configures the memory base address register and the input / output base address register of the target display module in the baseboard management controller, to generate a second initialization completion event (EarlyVideoInitDone event).

[0061] Specifically, as shown in FIG. 2, the baseboard management controller 200 writes the corresponding bus numbers for the at least one node of the hardware link in which the target display module is located, and then writes the memory resource addresses and the input / output resource addresses for the target display module, and configures the memory base address register and the input / output base address register of the target display module in the baseboard management controller 200, to generate the second initialization completion event (EarlyVideoInitDone event). Figure 7As shown, first, BIT0 and BIT1 of Command (offset 0x4) register in PCIe configuration space of the root port, the bridge and the target display module are written as 1 respectively to start the memory address resolution function and the IO (input output) address resolution function of the root port, the bridge and the target display module; then, at least one memory base address register and at least one input output base address register in the target display module are identified, for example, 6 BAR (Base Address Register, base address register) registers (offset from 0x10 to 0x24) are set for the target display module, mainly including: writing a full mask value into at least one base address register of the target display module, reading back the value of at least one base address register, obtaining the read-back value of at least one base address register, and identifying at least one memory base address register and at least one input output base address register according to the read-back value of at least one base address register, so that based on the read-back value, the BAR is a memory space or an IO space and the size of the required address space can be determined by analyzing the bit width of the read-back value.

[0062] For example, by writing a full mask value 0xFFFFFFFF into the 6 BAR registers respectively, and then reading back the value of the BAR register, the read-back value of the base address register is obtained, if the read-back value is a valid value and the least significant bit is a memory bit, then at least one memory base address register is obtained, for example, if the read-back value is 0, the BAR does not need to allocate resources, at this time, if BIT0 of the read-back value is 1, it can be judged that the BAR is a memory base address register; similarly, based on the read-back value of at least one base address register, the base address register whose read-back value is a valid value and the next least significant bit is an input output bit is identified, and at least one input output base address register is obtained, for example, if the read-back value is 0, the BAR does not need to allocate resources, at this time, if BIT0 of the read-back value is 0, it can be judged that the BAR is an IO base address register.

[0063] Thus, by allocating memory resource addresses, the control register of the target display module is mapped to the memory address space of the system, completing the "software driver" of the device, enabling device register access and data transfer, achieving efficient data transmission, at the same time, the resource addresses allocated by the system for each device are in a unified global address space and are managed by the operating system or firmware, ensuring that resource requests between different devices do not conflict, achieving orderly and standardized management of hardware resources.

[0064] According to one embodiment of the present application, the method for calculating the memory base address value of at least one memory base address register and the input / output base address value of at least one input / output base address register comprises: calculating the required memory address value of at least one memory base address register and the required input / output address value of at least one input / output base address register; determining the memory base address value of a first memory base address register in at least one memory base address register, and calculating the memory base address value of at least one memory base address register according to the memory base address value of the first memory base address register and the required memory address value of at least one memory base address register; determining the base address value of a first input / output base address register in at least one input / output base address register, and calculating the input / output base address value of at least one input / output base address register according to the base address value of the first input / output base address register and the required input / output address value of at least one input / output base address register.

[0065] According to one embodiment of the present application, the method for calculating the memory base address value of at least one memory base address register comprises: performing a bitwise AND operation between the read-back value of at least one memory base address register and a preset address mask to obtain a first initial result of at least one memory base address register; and performing a bitwise NOT operation on the first initial result to obtain the memory base address value of at least one memory base address register.

[0066] According to one embodiment of the present application, the method for determining the memory base address value of a first memory base address register in at least one memory base address register comprises: obtaining the address range of a memory mapping region in the address space of a central processing unit; and taking any address value in the address range of the memory mapping region as the memory base address value of the first memory base address register.

[0067] According to one embodiment of the present application, the memory base address value of any memory base address register except the memory base address value of the first memory base address register is the sum of the memory base address value of the previous memory base address register of any memory base address register and the required memory address value of the previous memory base address register of any memory base address register.

[0068] Specifically, the memory base address value of each memory base address register in the target display module and the input / output base address value of the input / output base address register are calculated. First, the required memory address value of at least one memory base address register and the required input / output address value of at least one input / output base address register are calculated, and the memory base address value of the first memory base address register in the at least one memory base address register is determined, wherein the memory base address value of the first memory base address register can be set as the address range of the memory mapping region in the address space of the currently matched CPU, and any address value in the address range of the memory mapping region can be taken as the memory base address value of the first memory base address register, for example, the memory address of the first memory base address register can be set as a value in the MMIO (Memory-Mapped I / O (Input / Output), memory-mapped input / output) address range in the address space of the currently matched CPU. Then, the memory base address value of any memory base address register except the memory base address value of the first memory base address register is the sum of the memory base address value of the previous memory base address register of any memory base address register and the required memory address value of the previous memory base address register of any memory base address register, that is, the value of the subsequent other memory base address is the sum of the previous memory base address value and the memory address length.

[0069] Secondly, the read-back value of at least one memory base address register is ANDed with a preset address mask bit by bit to obtain a first initial result of at least one memory base address register, and the first initial result is inverted bit by bit to obtain the memory base address value of at least one memory base address register, for example, the read-back value of the memory base address register is ANDed with 0xFFFFFFF0 bit by bit to obtain the first initial result of at least one memory base address register, and the first initial result is inverted bit by bit again, and the result is the required memory resource address and the input / output resource address length of the BAR.

[0070] Therefore, by calculating the values of the memory base address registers in the target display module, the unique and correct starting address of the multiple memory resources (such as the control register area, the display memory frame buffer area, etc.) required by the target display module in the global memory address space of the system is calculated, so that the device can work normally and does not conflict with other devices in the system or the system memory itself.

[0071] According to one embodiment of the present application, the input / output base address value of at least one input / output base address register is calculated, comprising: ANDing the read-back value of at least one memory base address register with a preset address mask bit by bit to obtain a second initial result of at least one input / output base address register; and inverting the second initial result of at least one input / output base address register bit by bit to obtain the input / output base address value of at least one input / output base address register.

[0072] According to one embodiment of the present application, the base address value of the first input / output base address register among the at least one input / output base address register is determined by: obtaining an input / output address range in an address space of the central processing unit; and taking any address value in the input / output address range as the base address value of the first input / output base address register.

[0073] According to one embodiment of the present application, the address value of any input / output base address register except the first input / output base address register is the sum of the input / output base address value of the previous input / output base address register of the any input / output base address register and the required input / output address value of the previous input / output base address register of the any input / output base address register.

[0074] Specifically, the base address values of the IO base address registers of the target display module are calculated, an input / output address range in an address space of the CPU is obtained, and any address value in the input / output address range is taken as the base address value of the first input / output base address register, that is, the memory address of the first IO base address register can be set as one value in the current CPU address space divided into the IO address range, and then the address value of any input / output base address register except the first input / output base address register is the sum of the input / output base address value of the previous input / output base address register of the any input / output base address register and the required input / output address value of the previous input / output base address register of the any input / output base address register, that is, the value of the subsequent other IO base address is the sum of the value of the previous IO base address and the IO address length.

[0075] Finally, the calculated values of all memory base addresses and IO base addresses are written into the respective base address registers of the target display module, and the work of allocating memory resource addresses and input / output resource addresses for the display module is completed, a second initialization completion event is generated, and then the target display module is initialized and font libraries are loaded according to the register specification of the target display module, so that the target display module starts to work normally and sends the second initialization completion event.

[0076] Thus, by calculating the values of the IO base address registers of the target display module, a unique and correct access entry is allocated in the IO address space of the system for the components in the target display module that need to be accessed through the IO address space, so that the CPU can reliably communicate with the components through IO instructions, and the most basic and reliable text information output is ensured to be implemented on a wide range of hardware.

[0077] In step S103, in response to the second initialization completion event, power-on self-test data is generated based on the second initialization completion event, and the power-on self-test data is output to the display device for display.

[0078] According to one embodiment of the present application, after responding to the second initialization completion event, further comprising: registering a display output interface of the display device; judging whether there is a text color adjustment instruction; if there is a text color adjustment instruction, adjusting the foreground color and the background color of the output text in the power-on self-test data based on the text color adjustment instruction, and calling the display output interface to output the adjusted output text.

[0079] According to one embodiment of the present application, after registering the display output interface of the external display device, further comprising: judging whether there is a screen clearing instruction; if there is a screen clearing instruction, calling the display output interface to clear the power-on self-test data in the display device.

[0080] Specifically, as shown in Figure 8 the second initialization completion event, i.e., an EarlyVideoInitDone event, if it is monitored that the EarlyVideoInitDone event is triggered, a display output interface of the display device, i.e., a PPI interface, is installed, and the power-on self-test data is output to the display device for display by calling the PPI interface; secondly, it is judged whether there is a text color adjustment instruction, if there is a text color adjustment instruction, the foreground color and the background color of the output text in the power-on self-test data are adjusted based on the text color adjustment instruction, and the display output interface is called to output the adjusted output text, which is used to display text on the display device, mainly calling the PPI interface to realize the function of displaying text on the display device.

[0081] Further, it is judged whether there is a screen clearing instruction, if there is a screen clearing instruction, the PPI interface is called to clear the power-on self-test data in the display device.

[0082] Thus, through the "display function module", all functions related to display output (such as drawing text and clearing screen) are centrally managed, which is separated from the hardware initialization logic, making the system architecture clear, at the same time, the PPI interface installed by the module provides the functions of clearing screen and displaying text, greatly simplifying the difficulty of outputting information in other parts of BIOS, and in the PEI stage of UEFI, PPI is the standard mechanism for service discovery and invocation between modules, other modules can "find" and "use" the display service in a standard and safe way, avoiding chaotic function pointer passing or direct dependence, thereby ensuring the standardization of service invocation and the stability of the whole system.

[0083] In summary, based on the specific description of the above embodiments, the application realizes the initialization of the display device in the early stage of power-on self-test without adding new hardware, and provides a method for outputting information on the display device, so that the real state of the system can be displayed on the display device. The scheme initializes the display device in advance to the early stage of PEI, that is, the screen is lit up before the initialization of CPU, memory and other devices, all POST process information can be displayed on the screen, even if there is a problem in the POST stage, the error information can be displayed in time, which can make the user understand the system state faster, improve the user experience, and make the identification and solution of hardware problems more efficient and accurate, which is also a great help to technical support personnel in the field.

[0084] According to the server power-on display method provided by the embodiment of the application, at least one key hardware device except memory is initialized in response to a power-on instruction of the server, and a first initialization completion event is triggered when the initialization is completed, the corresponding bus number is written for at least one node of a hardware link where a target display module is located in a baseboard management controller, and a memory resource address, an input / output resource address, a memory base address register and an input / output base address register are allocated, so as to generate a second initialization completion event, and finally, power-on self-test data is generated and displayed on a display device, solving the problem of long black screen time in the early stage of server startup and difficult fault diagnosis, and through the early initialization of the display device to the early stage of PEI and the early completion of the initialization of the display device by using an event triggering mechanism, the early display function is realized, so that the hardware operation and maintenance efficiency is improved.

[0085] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment.

[0086] The embodiment of the application also provides a server power-on display device.

[0087] Figure 9 is a block diagram of the server power-on display device of the embodiment of the application, the server includes a baseboard management controller and a display device, and the baseboard management controller is connected with the display device.

[0088] As shown in Figure 9 , the server power-on display device 10 includes an initialization module 100, a generation module 200 and a data output module 300.

[0089] The initialization module 100 is configured to initialize at least one key hardware device except memory in response to a power-on instruction of the server, and trigger a first initialization completion event when the at least one key hardware device is initialized.

[0090] The generation module 200 is configured to write a corresponding bus number for at least one node of a hardware link where the target display module is located in the baseboard management controller in response to the first initialization completion event, and allocate a memory resource address and an input / output resource address for the target display module in the baseboard management controller, and configure a memory base address register and an input / output base address register of the target display module in the baseboard management controller to generate a second initialization completion event.

[0091] The data output module 300 is configured to generate power-on self-test data based on the second initialization completion event in response to the second initialization completion event, and output the power-on self-test data to the display device for display.

[0092] In summary, the features of the embodiments of the server power-on display device can be referred to the related descriptions of the embodiments of the server power-on display method, which will not be repeated here.

[0093] The embodiments of the present application further provide an electronic device, which can include:

[0094] The memory 1001, the processor 1002, and a computer program stored in the memory 1001 and executable on the processor 1002.

[0095] The processor 1002 executes the program to implement the server power-on display method provided in the above embodiments.

[0096] Further, the electronic device further includes:

[0097] The communication interface 1003 is configured to communicate between the memory 1001 and the processor 1002.

[0098] The memory 1001 is configured to store the computer program executable on the processor 1002.

[0099] The memory 1001 can include a high-speed RAM memory, and can also include a non-volatile memory, such as at least one disk memory.

[0100] If the memory 1001, the processor 1002 and the communication interface 1003 are implemented independently, the communication interface 1003, the memory 1001 and the processor 1002 can be connected with each other through a bus and complete communication between each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For convenience of representation, Figure 10 Only one thick line is used to represent the bus in the figure, but it does not mean that there is only one bus or only one type of bus.

[0101] Optionally, in a specific implementation, if the memory 1001, the processor 1002 and the communication interface 1003 are integrated on a chip, the memory 1001, the processor 1002 and the communication interface 1003 can complete communication between each other through an internal interface.

[0102] The processor 1002 can be a Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present application.

[0103] Embodiments of the present application also provide a computer readable storage medium, which stores a computer program, and the computer program is configured to execute steps in any of the above-mentioned power-on display method embodiments when running.

[0104] In an example embodiment, the above-mentioned computer readable storage medium can include, but is not limited to, a U disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0105] Embodiments of the present application also provide a computer program product, which includes a computer program, and the computer program is executed by a processor to implement steps in any of the above-mentioned power-on display method embodiments.

[0106] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0107] The power-on display method for a server provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A method for power-on display on a server, the method comprising: The server comprises a baseboard management controller and a display device, the baseboard management controller is connected with the display device, and the method comprises the following steps: in response to a power-on instruction of the server, at least one key hardware device except memory is initialized, and a first initialization completion event is triggered when the at least one key hardware device completes initialization; in response to the first initialization completion event, a corresponding bus number is written in at least one node of a hardware link where a target display module is located in the baseboard management controller, memory resource addresses and input / output resource addresses are allocated for the target display module in the baseboard management controller, and a memory base address register and an input / output base address register of the target display module in the baseboard management controller are configured to generate a second initialization completion event; in response to the second initialization completion event, power-on self-test data is generated based on the second initialization completion event, and the power-on self-test data is output to the display device for display; the step of writing the corresponding bus number in at least one node of a hardware link where a target display module is located in the baseboard management controller comprises the following steps:

2. The method of claim 1, wherein, determining a device path of at least one node of a hardware link where the target display module is located; determining a target node to which the bus number is to be written from the at least one node, and determining a bus number range of the target node according to the device path of nodes between the target node and the target display module; writing the bus number range into the target node. the step of determining the bus number range of the target node according to the device path of nodes between the target node and the target display module comprises the following steps: determining a starting bus number of the bus number range according to the device path of the target node; 3. The method of claim 2, wherein, determining an intermediate bus number according to the device path of nodes between the target node and the target display module; determining a final bus number of the bus number range according to the device path of the target display module; obtaining the bus number range according to the starting bus number, the intermediate bus number and the final bus number. the step of writing the bus number range into the target node comprises the following steps:

4. The method of claim 1, wherein, writing the starting bus number into a primary bus number of the target node; writing a bus number which is downstream of the target node and closest to the target node in the intermediate bus number into a secondary bus number of the target node; writing the final bus number into a slave bus number of the target node. the step of allocating memory resource addresses and input / output resource addresses for the target display module in the baseboard management controller comprises the following steps: identifying at least one memory base address register and at least one input / output base address register in the target display module; calculating a memory base address value of the at least one memory base address register and an input / output base address value of the at least one input / output base address register; allocating memory resource addresses and input / output resource addresses for the target display module based on the memory base address value of the at least one memory base address register and the input / output base address value of the at least one input / output base address register.

5. The method of claim 4, wherein, The identifying the at least one memory base address register and the at least one input / output base address register in the target display module comprises: writing a full mask value to at least one base address register of the target display module, and reading back a value of the at least one base address register to obtain a read-back value of the at least one base address register; identifying the at least one memory base address register and the at least one input / output base address register according to the read-back value of the at least one base address register.

6. The method of claim 5, wherein, The identifying the at least one memory base address register and the at least one input / output base address register according to the read-back value of the at least one base address register comprises: identifying, based on the read-back value of the at least one base address register, a base address register whose read-back value is a valid value and whose least significant bit is a memory bit, to obtain the at least one memory base address register; identifying, based on the read-back value of the at least one base address register, a base address register whose read-back value is a valid value and whose next least significant bit is an input / output bit, to obtain the at least one input / output base address register.

7. The method of claim 5, wherein, The calculating the memory base address value of the at least one memory base address register and the input / output base address value of the at least one input / output base address register comprises: calculating a required memory address value of the at least one memory base address register and a required input / output address value of the at least one input / output base address register; determining a memory base address value of a first memory base address register in the at least one memory base address register, and calculating the memory base address value of the at least one memory base address register according to the memory base address value of the first memory base address register and the required memory address value of the at least one memory base address register; determining a base address value of a first input / output base address register in the at least one input / output base address register, and calculating the input / output base address value of the at least one input / output base address register according to the base address value of the first input / output base address register and the required input / output address value of the at least one input / output base address register.

8. The method of claim 7, wherein, The calculating the memory base address value of the at least one memory base address register comprises: performing a bitwise AND operation on the read-back value of the at least one memory base address register and a preset address mask to obtain a first initial result of the at least one memory base address register; performing a bitwise NOT operation on the first initial result to obtain the memory base address value of the at least one memory base address register.

9. The method according to claim 7 or 8, characterized in that, The determining the memory base address value of the first memory base address register in the at least one memory base address register comprises: obtaining an address range of a memory mapping region in an address space of a central processing unit; taking any address value in the address range of the memory mapping region as the memory base address value of the first memory base address register.

10. The method of claim 9, wherein, The memory base address value of any memory base address register except the first memory base address register is the sum of the memory base address value of the previous memory base address register of the any memory base address register and the required memory address value of the previous memory base address register of the any memory base address register.

11. The method of claim 7, wherein, The input / output base address value of the at least one input / output base address register is calculated, including: bitwise ANDing the readback value of the at least one memory base address register and a preset address mask to obtain a second initial result of the at least one input / output base address register; bitwise NOTing the second initial result of the at least one input / output base address register to obtain the input / output base address value of the at least one input / output base address register.

12. The method of claim 7 or 11, wherein, The base address value of the first input / output base address register in the at least one input / output base address register is determined, including: obtaining an input / output address range in an address space of a central processing unit; taking any address value in the input / output address range as the base address value of the first input / output base address register.

13. The method of claim 12, wherein, The address value of any input / output base address register except the first input / output base address register is the sum of the input / output base address value of the previous input / output base address register of the any input / output base address register and the required input / output address value of the previous input / output base address register of the any input / output base address register.

14. The method of claim 1, wherein, After responding to the second initialization completion event, further comprising: registering a display output interface of the display device; determining whether there is a text color adjustment instruction; if there is the text color adjustment instruction, adjusting the foreground color and the background color of the output text in the power-on self-test data based on the text color adjustment instruction, and calling the display output interface to output the adjusted output text.

15. The method of claim 14, wherein, After registering the display output interface of the display device, further comprising: determining whether there is a screen clearing instruction; if there is the screen clearing instruction, calling the display output interface to clear the power-on self-test data in the display device.

16. A server power-on display device, comprising: The server comprises a baseboard management controller and a display device, the baseboard management controller being connected with the display device, and comprising: an initialization module, configured to respond to a power-on instruction of a server, initialize at least one key hardware device except memory, and trigger a first initialization completion event when the at least one key hardware device completes initialization; a generation module, configured to respond to the first initialization completion event, write a corresponding bus number for at least one node of a hardware link where a target display module is located in the baseboard management controller, allocate a memory resource address and an input / output resource address for the target display module in the baseboard management controller, and configure a memory base address register and an input / output base address register of the target display module in the baseboard management controller, to generate a second initialization completion event; the server further comprises a display module, configured to respond to the second initialization completion event, and register a display output interface of the display device. a data output module, configured to output power-on self-test data to the display device for display in response to the second initialization completion event and based on the second initialization completion event; The generating module is further configured to: determine a device path of at least one node of a hardware link where the target display module is located; determine a target node to be written with a bus number from the at least one node, and determine a bus number range of the target node according to the device path of nodes between the target node and the target display module; and write the bus number range to the target node.

17. An electronic device, comprising: comprising: a memory, configured to store a computer program; a processor, configured to implement the steps of the power-on display method of the server according to any one of claims 1 to 15 when executing the computer program.

18. A non-transitory computer readable storage medium, comprising: The computer program is stored in the computer readable storage medium and is executed by the processor to implement the steps of the power-on display method of the server according to any one of claims 1 to 15.

19. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the power-on display method of the server according to any one of claims 1 to 15.

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