Chip layout size recommendation method and device, equipment and storage medium

Abstract

The application provides a chip layout size recommendation method and device, equipment and a storage medium. The method comprises the following steps: analyzing the size setting information of a target region in a chip to obtain the change constraint condition of the layout height and the layout width of the target region; determining the candidate height of the layout height and the candidate width of the layout width based on the change constraint condition; combining the candidate height and the candidate width to obtain a candidate size and form a corresponding candidate size set; determining the index value corresponding to a preset index for the candidate size in the candidate size set; sorting the candidate sizes meeting a preset condition according to the index value and outputting a recommended target layout size. The suitable chip target region layout size can be efficiently determined, which helps to improve the chip design efficiency.

Description

Technical Field

[0001] This application relates to the field of chip layout, and more particularly to a recommended method, apparatus, device, and storage medium for chip layout dimensions. Background Technology

[0002] In the chip physical design flow, the floorplan is the starting point for placement and routing, and its core area's dimensions affect many aspects of the chip's characteristics. A core area that is too small will lead to placement failure, while one that is too large will waste silicon area and increase costs. Determining the appropriate floorplan size requires manual adjustment, manual operation, and judgment based on experience, which is time-consuming and labor-intensive. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a recommended method, system, device and storage medium for chip layout size.

[0004] In a first aspect, this application provides a method for recommending chip layout dimensions, comprising:

[0005] Based on the size setting information of the target area in the chip, the variation constraints of the layout height and layout width of the target area are obtained by parsing.

[0006] Based on the changing constraints, candidate heights for the layout height and candidate widths for the layout width are determined.

[0007] Based on the candidate height and the candidate width, candidate sizes are obtained, forming a corresponding set of candidate sizes;

[0008] For each candidate size in the candidate size set, determine the index value corresponding to the preset index;

[0009] The candidate sizes that meet the preset conditions are sorted according to the index values, and the recommended target layout size is output.

[0010] A second aspect of this application provides an improved recommended apparatus for chip layout size, comprising:

[0011] The condition parsing module is used to parse the size setting information of the target area in the chip to obtain the constraint conditions for the change of the layout height and layout width of the target area;

[0012] The candidate size module is used to determine the candidate height of the layout height and the candidate width of the layout width based on the changing constraints; and to combine the candidate height and the candidate width to obtain candidate sizes, forming a corresponding set of candidate sizes.

[0013] The indicator calculation module is used to determine the indicator value corresponding to the preset indicator for the candidate size in the candidate size set;

[0014] The size recommendation module is used to sort the candidate sizes that meet the preset conditions according to the index values ​​and output the recommended target layout size.

[0015] In a third aspect, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the method described in the first aspect.

[0016] In a fourth aspect, this application provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the method described in the first aspect.

[0017] As described above, this application provides a method, system, device, and storage medium for recommending chip layout dimensions. It parses the size settings information of the target region in the chip to obtain the constraints on the variation of layout height and width, thereby determining candidate heights and widths and combining them into a candidate size set. Then, it determines preset index values ​​for each candidate size in the set, and finally outputs the recommended target layout dimensions by sorting the candidate sizes that meet the preset conditions according to the index values. This method can efficiently determine suitable chip target region layout dimensions, helping to improve chip design efficiency, reduce the time and effort costs of manual selection, and provide a more scientific and reasonable size reference for chip layout. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of the structure of an exemplary electronic device according to an embodiment of this application is shown.

[0020] Figure 2 A schematic flowchart illustrating a recommended method for chip layout dimensions according to an embodiment of this application is shown.

[0021] Figure 3 A schematic diagram of a recommended device for chip layout dimensions according to an embodiment of this application is shown. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0023] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0024] In the chip physical design flow, the floorplan is the starting point for placement and routing. The dimensions of its core region directly impact chip feasibility, performance, power consumption, and cost. If the core region is too small, subsequent placement and routing may not be able to accommodate all cells, leading to placement failure; if it is too large, it wastes silicon area and increases manufacturing costs. In related technologies, determining the appropriate floorplan size typically relies on manual adjustments to the core region size based on the initial design, and macrocell packing, congestion, and density analysis are performed for each size. This leads to the following shortcomings in the evaluation process: low efficiency in both adjustment and analysis, difficulty in timely coverage of multiple candidate sizes, lack of automation, and the requirement of significant time and effort for evaluation. Therefore, improving the efficiency and decision-making quality of placement size evaluation has become an urgent technical problem to be solved.

[0025] Figure 1 A schematic diagram of an electronic device 100 according to an embodiment of this application is shown. The electronic device 100 may be an electronic device running a simulation system. For example... Figure 1 As shown, the electronic device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. The processor 102, memory 104, network interface 106, and peripheral interface 108 are interconnected within the electronic device via the bus 110.

[0026] Processor 102 may be a Central Processing Unit (CPU), a graphics processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 can be used to perform functions related to the techniques described in this application. In some embodiments, processor 102 may also include multiple processors integrated into a single logic component. Figure 1 As shown, processor 102 may include a first processor 102a, a second processor 102b, and a third processor 102c.

[0027] Memory 104 can be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, a simulation test system for simulation test design can be a computer program stored in memory 104. Figure 1 As shown, the data stored in the memory may include program instructions (e.g., program instructions for implementing the verification system of this application) and data to be processed (e.g., the memory may store temporary code generated during the compilation process). The processor 102 may also access the program instructions and data stored in the memory and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include random access memory (RAM), read-only memory (ROM), optical disk, magnetic disk, hard disk, solid-state drive (SSD), flash memory, memory stick, etc.

[0028] Network interface 106 can be configured to provide communication with other external devices to electronic device 100 via a network. This network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, Near Field Communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0029] The peripheral interface 108 can be configured to connect the electronic device 100 to one or more peripheral devices to enable information input and output. For example, peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, and various sensors, as well as output devices such as displays, speakers, vibrators, and indicator lights.

[0030] Bus 110 can be configured to transfer information between various components of electronic device 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), such as internal buses (e.g., processor-memory bus), external buses (USB port, PCI-E bus), etc.

[0031] It should be noted that although the above electronic device architecture only shows the processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110, in specific implementations, this electronic device architecture may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above electronic device architecture may only include the components necessary for implementing the embodiments of this application, and does not necessarily include all the components shown in the figures.

[0032] See Figure 2 , Figure 2 A schematic flowchart illustrating a method for recommending chip layout dimensions according to an embodiment of this application is shown. The method for recommending chip layout dimensions according to an embodiment of this application can be deployed on a terminal or server. Figure 2 In the recommended method 200 for chip layout dimensions, the following steps may be further included.

[0033] In step S210, the size setting information of the target area in the chip is parsed to obtain the variation constraints of the layout height and layout width of the target area.

[0034] In this context, "chip" refers to a miniaturized electronic component that integrates circuitry (mainly semiconductor devices and passive components) onto a semiconductor wafer. "Target area" refers to the region in chip design that requires specific layout planning. This area may contain specific functional modules, such as logic units and memory units, and its size and layout significantly impact the chip's overall performance, power consumption, and area. Size setting information refers to the pre-defined size settings of the target area during layout, potentially including initial width and height values, aspect ratio, width and height range, and relative size relationships with other areas. Layout height refers to the vertical dimension of the target area, and layout width refers to the horizontal dimension. Layout height and width determine the physical size and shape of the target area within the chip, directly affecting the chip's area and the arrangement of internal components. Variation constraints are the rules governing adjustments to the layout height and width. These constraints may be based on chip manufacturing process requirements, electrical performance needs, and heat dissipation considerations, ensuring that the size variations of the target area remain within a reasonable range to guarantee the chip's normal operation and reliability.

[0035] By analyzing the size settings of target regions within a chip, the constraints on variations in the target region's layout height and width can be precisely extracted, providing clear boundaries and directions for subsequently determining reasonable layout dimensions. This improves the rationality and accuracy of the layout, helps optimize chip performance (such as increasing processing speed and reducing power consumption), and effectively controls chip area, reducing manufacturing costs. Simultaneously, it provides a systematic and efficient method for determining layout dimensions, reducing the cost and time of manual trial and error, and improving the efficiency and quality of chip design.

[0036] Specifically, the size settings can specify at least one of height or width; step size > 0; if a region [start, end] is given, the starting value of the region start must be less than or equal to the ending value of the region end; the current core region size must fall within the given region, otherwise an error will be reported and the process will terminate. The size settings can allow multiple modes, such as changing only the height, changing only the width, or changing both height and width simultaneously; when the aspect ratio or the aspect ratio fixed_aspect_ratio is true and both height and width are specified, only candidates with an aspect ratio |h / w−H0 / W0|<1e-3 from the original core region aspect ratio are retained. For example, the aspect ratio can be used to constrain the deviation range between the aspect ratio (h / w) of the candidate size and the target aspect ratio (H0 / W0) in the chip layout. For example, the tolerance threshold can be 0.001 to ensure that the layout size maintains the accuracy of the geometric proportions while meeting functional requirements.

[0037] In step S220, candidate heights for the layout height and candidate widths for the layout width are determined based on the change constraints.

[0038] Candidate height can refer to one or more optional discrete values ​​generated for the layout height (vertical dimension) under the condition of satisfying the chip target area layout constraints. These values ​​are determined based on the height variation range and step size rules. For example, in fixed width mode, the candidate height may cover multiple incremental values ​​from the minimum height to the maximum height. Candidate width can refer to one or more optional discrete values ​​generated for the layout width (horizontal dimension), generated according to the width variation range and step size rules. For example, in fixed height mode, the candidate width may contain multiple step size increments from the minimum width to the maximum width. Candidate dimensions are systematically generated through varying constraints (including variation mode, height / width variation range, and step size type).

[0039] In some embodiments, the variation constraints include a variation mode, a height variation range of the layout height, and a width variation range of the layout width;

[0040] Determining candidate heights for the layout height and candidate widths for the layout width based on the aforementioned variation constraints includes:

[0041] In response to the change pattern being a fixed height and a changing width, the candidate height is determined to be a fixed height, and the candidate width is determined based on a preset width step within the width change range;

[0042] In response to the change pattern being a fixed width and a changing height, the candidate width is determined to be a fixed width, and the candidate height is determined based on a preset height step size within the height change range;

[0043] In response to the change pattern being a change in both height and width, and based on a preset aspect ratio change, a candidate width and a candidate height that conform to the preset aspect ratio are determined based on a preset width step and a preset width step within the width change range and the height change range;

[0044] In response to the change pattern being that both height and width change and there is no aspect ratio constraint, the candidate width is determined based on a preset width step size within the width change range, and the candidate height is determined based on a preset height step size within the height change range;

[0045] The type of the preset height step or the preset width step includes absolute change type or relative change type.

[0046] The variation mode refers to how the layout height and width change. A variation mode with fixed height and varying width means the candidate height has a single fixed value, while the candidate width varies discretely within a range of increments. A variation mode with fixed width and varying height means the candidate width has a single fixed value, while the candidate height varies discretely within a range of increments. A variation mode where both candidate width and height change according to a preset aspect ratio means that both candidate width and height must simultaneously satisfy a proportional relationship. A free adjustment mode means that candidate width and height can be independently adjusted with increments, generating a grid-like candidate set. For absolute variation types, the increment can be directly defined (e.g., m micrometers, where m is a positive number), while for relative variation types, the increment can be adjusted proportionally (e.g., percentage). Through constraints and increment rules, candidate width and height are automatically generated, avoiding the time-consuming and incomplete manual enumeration. For example, in a mode without aspect ratio constraints, multiple candidate combinations can be quickly generated, comprehensively covering the design space.

[0047] In step S230, the candidate height and the candidate width are combined to obtain the candidate size, forming a corresponding set of candidate sizes.

[0048] Among them, based on the determined candidate height and candidate width, a set of candidate sizes is generated through systematic combination, providing a complete set of optional size schemes for the layout of the target area of ​​the chip.

[0049] In some embodiments, candidate sizes are obtained by combining the candidate height and the candidate width, forming a corresponding set of candidate sizes, including:

[0050] The candidate size is obtained by performing a Cartesian combination based on the candidate height and the candidate width;

[0051] The candidate size set is formed based on the candidate size.

[0052] Specifically, a Cartesian product combination strategy is used to perform full permutation pairing of candidate heights and candidate widths, generating all possible candidate size combinations (i.e., each height is matched with each width one-to-one), ultimately forming a candidate size set containing all potential size solutions. This ensures the comprehensiveness of size exploration, avoiding the omission of possible optimization solutions, and is particularly suitable for scenarios that require systematic traversal of geometric parameters (such as balancing area, latency, and aspect ratio constraints in chip layout). At the same time, the generated set can be used as input for subsequent screening (such as based on aspect ratio tolerance, area threshold, etc.), supporting multi-objective optimization decisions and improving the robustness and efficiency of layout design.

[0053] Specifically, when the variation pattern is a fixed height and a variable width, the candidate height is a single value, and the candidate width is generated into multiple values ​​according to the step size, combined as (H_fixed, W1), (H_fixed, W2), ..., (H_fixed, W... n ), where n is a positive integer. When the variation pattern is a fixed width and a variable height, the candidate width is a single value, and the candidate height generates multiple values ​​according to the step size, combined as (H1, W_fixed), (H2, W_fixed), ..., (H n’ The model is defined as follows: (W_fixed), where n' is a positive integer. When the change pattern involves changes in both height and width, and is based on a preset aspect ratio, candidate pairs satisfying W = k × H (where k is the scaling factor, H is the candidate height, and W is the candidate width) are retained. When the change pattern involves changes in both height and width, and there are no aspect ratio constraints, all candidate heights and widths can be combined using a Cartesian product to generate a complete mesh. For example, if the candidate height is [H1, H2, H3] and the candidate width is [W1, W2], the combination is (H1, W1), (H1, W2), (H2, W1), (H2, W2), (H3, W1), (H3, W2). Verification can be performed based on the height and width change ranges to ensure that the combined size is within the height range [H_min, H_max] and width range [W_min, W_max], eliminating out-of-bounds values. If a relative step size is used, the step size value needs to be dynamically adjusted to avoid exceeding the range (e.g., if the height step size is 10%H_min, the increment stops when it approaches H_max).

[0054] For example, using the current core area size (coreW = width, coreH = height) as a baseline, the height (H sequence) and width (W sequence) are generated within a specified adjustment interval [start, end] in micrometer or percentage steps. A candidate size set (candidates) is generated using Cartesian combinations under various modes such as "fixed width / fixed height / two-way adjustment". When adjusting the core area size, the relative offset between the core and the unpackaged chip die must be maintained to avoid altering the chip's peripheral alignment. The coordinates of the top-left corner or center point of the core area can be kept fixed, adjusting only its width and height. If the original core area coordinates are (x, y), the adjusted coordinates remain (x, y), only the size changes to (new_w, new_h). The layout tool automatically checks whether the alignment between the adjusted core area and the die edge, I / O units, power networks, etc., is consistent. This achieves a complete process from parameter parsing to combinatorial optimization, ensuring both the flexibility of adjustment and the physical feasibility of the layout through constraints.

[0055] In step S240, for the candidate size in the candidate size set, the index value corresponding to the preset index is determined.

[0056] Specifically, for candidate dimensions in the candidate size set, a pre-defined index calculation model (such as an area model) is used. A = h × w The delay model is based on parasitic parameter estimation, and the power consumption model is combined with circuit activity analysis, etc., to quantify the corresponding index values ​​(such as area, delay time, power consumption, etc.), forming a "size-index value" mapping relationship. In this way, geometric parameters (height, width) can be transformed into measurable performance indicators, providing data support for subsequent multi-objective optimization and selection (such as minimum area, shortest delay, lowest power consumption or aspect ratio constraints). At the same time, the unified index framework enables horizontal comparison of different size schemes, improving the scientific nature and efficiency of layout decisions.

[0057] Specifically, an automated evaluation process can be performed on candidate sizes (resetting / adjusting layout, macrocell packaging, deducing blocking regions, layout analysis, and saving results). Parallel or serial execution can be selected based on the availability of the distributed environment, and task-level fault tolerance is achieved.

[0058] In some embodiments, determining the index value corresponding to a preset index for the candidate dimensions in the candidate size set includes:

[0059] Based on the candidate sizes, macrocells are packaged to obtain candidate layouts;

[0060] Identify congested regions in the candidate layouts;

[0061] The index values ​​of the preset indicators in the candidate layout are determined based on the congested region; the preset indicators include at least one of congestion peak, cell distribution density, or critical channel utilization.

[0062] For candidate sizes, the process begins by generating corresponding candidate layouts through macrocell packaging, simulating the cell arrangement in an actual chip. Then, congested regions in the layout (such as areas with dense wiring or excessive cell concentration) are identified, and pre-defined metrics are quantified based on these regions (e.g., congestion peak reflects the degree of local congestion, cell distribution density measures cell space utilization, and critical channel utilization assesses critical path resource occupancy). This layout-level simulation exposes potential design bottlenecks in advance, transforming abstract geometric dimensions into quantifiable performance indicators. This provides data support for subsequently selecting optimized sizes with low congestion and high uniformity, thereby improving the feasibility of chip layout and manufacturing yield.

[0063] Specifically, firstly, macrocells (such as RAM, IP cores, and simulation modules) can be automatically packaged into the core area to avoid overlap and conform to Design Rules (DRC). For example, macrocell positions can be optimized based on simulated annealing, genetic algorithms, or machine learning (such as DREAM-GAN). If there is no overlap after packaging and the minimum spacing requirement is met, True is returned; otherwise, False is returned and the reason for failure is recorded (such as insufficient space or rule conflict). Multiple macrocells can be packaged in parallel, accelerated by distributed dynamic programming (such as multi-GPU collaborative computing).

[0064] Next, identify areas in the layout where cells cannot be placed (such as power networks, clock trees, and reserved areas). For example, occupancy regions are derived from layout data (such as power loops and metal layer occupancy). The occupancy regions are recalculated after resizing to ensure subsequent analysis considers the latest layout state. A occupancy region mask is generated for density analysis and macrocell packing.

[0065] Next, the layout quality is quantified, outputting metrics such as peak congestion and density uniformity. The congestion level of routing channels (e.g., line length density, via density) is calculated, outputting the peak congestion (maximum congestion value) and a congestion heatmap (PNG). Cell distribution uniformity is evaluated (e.g., standard deviation, ratio of local density to global density), outputting density uniformity (higher values ​​indicate greater uniformity) and a density heatmap (PNG). The utilization rate of major routing channels (e.g., metal layer occupancy) is calculated to ensure it does not exceed process thresholds (e.g., 80%).

[0066] The optimized layout is saved as a DEF file (Design Exchange Format), containing physical information such as cell location, size, and hierarchy. The packaged DEF file contains macro cell location and layout information. Numerical metrics such as congestion peak, density uniformity, and macro packaging success flags are exported in CSV / JSON format for subsequent aggregation and optimization. For example, the DEF file can include a physical description of the layout for subsequent routing, verification, and other processes. Congestion PNGs can use color gradient maps to display congestion levels (e.g., red for high congestion, blue for low congestion). Density PNGs can use heatmaps to show cell distribution uniformity (e.g., warm colors for high density, cool colors for low density).

[0067] In some embodiments, method 200 further includes:

[0068] In response to the detection that a distributed data parallel environment is available, the calculation of the indicator value is processed in parallel.

[0069] In response to the detection that the distributed data parallel environment is unavailable, the calculation of the indicator value is processed serially.

[0070] Robustness of task execution can be ensured through dynamic resource scheduling and fault tolerance mechanisms. First, the system detects the availability of the distributed DP (Data Parallelism) environment: if the environment supports parallel computing, candidate tasks are split and dispatched in parallel to multiple computing nodes, fully utilizing cluster resources to improve processing efficiency; if the environment is unavailable, it automatically degrades to a serial execution mode, ensuring that tasks can still run completely in a single-machine environment. Specifically, if multi-GPU / multi-machine resources are detected, task-level parallelism can be implemented to accelerate the evaluation process. If resources are limited, it automatically degrades to a serial mode, processing candidate sizes one by one.

[0071] In some embodiments, method 200 further includes:

[0072] In response to the detection of an anomaly in the calculation of the index value of the candidate size, the anomaly information is recorded; and the calculation of the index values ​​of the other candidate sizes continues.

[0073] This system incorporates a task-level fault tolerance strategy. When a single candidate task fails, the system only records the reason for the failure (such as insufficient resources or data anomalies) without interrupting the execution of other candidate tasks, thus preventing the overall process from stalling due to localized failures. This balances high performance and reliability: parallel mode maximizes resource utilization, serial mode ensures basic compatibility, and task-level fault tolerance enhances system fault tolerance by isolating faults, ultimately achieving dual optimization of task execution efficiency and stability. Specifically, the failure of a single candidate evaluation (such as macro packaging failure) does not affect the overall process; an error log is recorded, and other candidates continue. The system can aggregate the success / failure status and metric data of all candidates, providing a complete dataset for subsequent optimization.

[0074] In step S250, the candidate sizes that meet the preset conditions are sorted according to the index values, and the recommended target layout size is output.

[0075] The process involves filtering candidate sizes based on preset conditions (such as aspect ratio tolerance and area thresholds) to eliminate invalid sizes that do not meet geometric or performance constraints. Then, for the remaining candidate sizes, a comprehensive score or priority ranking value is calculated based on preset indicators (such as congestion peak, cell distribution density, and critical channel utilization). Finally, the candidate sizes are ranked from best to worst according to their indicator values, and the top-ranked sizes are output as recommended target layout sizes. This hierarchical filtering and quantitative ranking process simplifies a massive number of candidate sizes into an optimal solution set, ensuring that the recommended results simultaneously meet geometric constraints and performance optimization goals. This significantly improves the efficiency and reliability of chip layout design and provides highly manufacturable size solutions for subsequent process implementation.

[0076] In some embodiments, the candidate sizes that meet preset conditions are sorted according to the index values, and a recommended target layout size is output, including:

[0077] Candidate sizes that meet the preset conditions are sorted from smallest to largest according to the congestion peak or the cell distribution density; the preset conditions include successful macrocell packaging;

[0078] The candidate sizes for the target number before sorting are output as the recommended target layout sizes.

[0079] The process involves several steps. First, prioritizing successful packaging, the system filters feasible macrocell packaging sizes from the candidate size set to ensure the recommended results are practically manufacturable. Second, the selected sizes are ranked based on two key indicators: peak congestion (reflecting local wiring congestion) and cell distribution density (measuring the uniformity of cell space utilization). Sizes with lower congestion and more uniform distribution are prioritized to optimize layout quality. Finally, the top K optimal sizes are selected based on the ranking results to generate a recommended list. This three-step process of "feasibility assurance - performance quantification - optimal truncation" simplifies the candidate sizes into a high-quality solution set that balances manufacturability and layout efficiency, effectively reducing subsequent design verification costs. It also provides low-risk, high-reliability size solutions for chip physical implementation, significantly improving the efficiency and success rate of the overall design process.

[0080] As can be seen, the chip layout size recommendation method proposed in this application can reproduce the end-to-end automation of the evaluation process. For the same parameter input, it guarantees a unique candidate set and result output. Parameter scanning and parallel execution significantly shorten the overall evaluation time, covering a larger size design space. Unified structured metrics and image output facilitate automated ranking and subsequent script / report integration; it maintains equivalent functionality in non-parallel environments (serial degradation), supporting failure isolation and continued execution. It avoids the inefficiency, non-reproducibility, and missed boundary combinations caused by multiple manual size trials in traditional techniques, solves the problems of scattered result files and non-machine-readable metrics in traditional evaluations, supports one-click aggregation and comparison, overcomes the time bottleneck of serial evaluation under large-scale parameter scanning in traditional methods, and provides controllable, top-ranked preferred outputs.

[0081] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0082] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement a method for a recommended chip layout size as described in any of the above embodiments.

[0083] Based on the same inventive concept, corresponding to any of the methods in the above embodiments, this application also provides a chip layout size recommendation device, such as... Figure 3As shown, the recommended device for chip layout size includes:

[0084] The condition parsing module is used to parse the size setting information of the target area in the chip to obtain the constraint conditions for the change of the layout height and layout width of the target area;

[0085] The candidate size module is used to determine the candidate height of the layout height and the candidate width of the layout width based on the changing constraints; and to combine the candidate height and the candidate width to obtain candidate sizes, forming a corresponding set of candidate sizes.

[0086] The indicator calculation module is used to determine the indicator value corresponding to the preset indicator for the candidate size in the candidate size set;

[0087] The size recommendation module is used to sort the candidate sizes that meet the preset conditions according to the index values ​​and output the recommended target layout size.

[0088] For ease of description, the above devices are described in terms of function, divided into various modules. Of course, in implementing this application, the functions of each module can be implemented in one or more software and / or hardware.

[0089] The apparatus described above is used to implement the corresponding motor parameter detection method based on frequency domain analysis in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0090] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform the recommended method for chip layout size as described in any of the above embodiments.

[0091] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0092] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to execute the recommended chip layout size method as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0093] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0094] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0095] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0096] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A method of recommending a chip layout size, characterized by, The method comprises: based on the size setting information of the target region in the chip, the layout height and the layout width of the target region are obtained, and the change constraint condition of the layout height and the layout width is obtained; the change constraint condition comprises a change mode, a height change interval of the layout height, and a width change interval of the layout width, and the change mode is used to indicate the change mode of the layout height and the layout width; based on the change constraint condition, the candidate height of the layout height and the candidate width of the layout width are determined; based on the candidate height and the candidate width, the candidate size is obtained by combination, and a corresponding candidate size set is formed; for the candidate size in the candidate size set, the macro unit is packaged to obtain the candidate layout, and the index value corresponding to the preset index about the congestion region in the candidate layout is determined; the candidate size meeting the preset condition is sorted according to the index value, and the recommended target layout size is output.

2. The method of claim 1, wherein, based on the change constraint condition, the candidate height of the layout height and the candidate width of the layout width are determined, comprising: in response to the change mode being fixed height and variable width, the candidate height is determined as fixed height, and the candidate width is determined based on a preset width step in the width change interval; in response to the change mode being fixed width and variable height, the candidate width is determined as fixed width, and the candidate height is determined based on a preset height step in the height change interval; in response to the change mode being variable height and variable width, and based on a preset aspect ratio change, the candidate width and the candidate height meeting the preset aspect ratio are determined based on a preset width step and a preset height step in the width change interval and the height change interval; in response to the change mode being variable height and variable width without aspect ratio constraint, the candidate width is determined based on a preset width step in the width change interval, and the candidate height is determined based on a preset height step in the height change interval; wherein the type of the preset height step or the preset width step comprises an absolute change type or a relative change type.

3. The method of claim 1, wherein, based on the candidate height and the candidate width, the candidate size is obtained by combination to form a corresponding candidate size set, comprising: the candidate size is obtained by Cartesian combination based on the candidate height and the candidate width; the candidate size set is formed based on the candidate size.

4. The method of claim 1, wherein, determining the index value corresponding to the preset index about the congestion region in the candidate layout, comprising: identifying the congestion region in the candidate layout; based on the congestion region, the index value of the preset index in the candidate layout is determined; the preset index comprises at least one of congestion peak value, cell distribution density or key channel utilization rate.

5. The method of claim 1, wherein, the candidate size meeting the preset condition is sorted according to the index value, and the recommended target layout size is output, comprising: the candidate size meeting the preset condition is sorted according to the index value from small to large according to the congestion peak value or the cell distribution density; the preset condition comprises successful macro unit packaging; Output the target quantity of candidate sizes before sorting as the recommended target layout size.

6. The method of claim 1, wherein, Further comprising: In response to detecting that a distributed data parallel environment is available, processing the calculation of the indicator value in parallel; In response to detecting that a distributed data parallel environment is not available, processing the calculation of the indicator value in series.

7. The method of claim 6, wherein, Further comprising: In response to detecting that the calculation of the indicator value of the candidate size is abnormal, recording abnormal information of the abnormality; And continue to calculate the indicator values of other candidate sizes.

8. A device for recommending a chip layout size, characterized by Comprise: A condition analysis module is configured to analyze size setting information of a target region in a chip to obtain change constraint conditions of layout height and layout width of the target region; the change constraint conditions include a change mode, a height change interval of the layout height, and a width change interval of the layout width, and the change mode is used to indicate a change manner of the layout height and the layout width; A candidate size module is configured to determine a candidate height of the layout height and a candidate width of the layout width based on the change constraint conditions, and combine the candidate height and the candidate width to obtain a candidate size and form a corresponding candidate size set; An indicator calculation module is configured to perform macro cell packaging on the candidate size in the candidate size set to obtain a candidate layout, and determine an indicator value corresponding to a preset indicator about a congestion region in the candidate layout; A size recommendation module is configured to sort the candidate sizes that meet a preset condition according to the indicator value, and output a recommended target layout size.

9. An electronic device, comprising: The computer program stored in the memory and executable on the processor, when the processor executes the program, implements the method of any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium, comprising: The non-transitory computer readable storage medium stores computer instructions for causing a computer to execute the method of any one of claims 1 to 7.

Images