Constant data loading methods and graphics processors, media

Abstract

A constant data loading method, a graphics processor, and a medium are disclosed. The constant data loading method includes: storing at least a portion of data units in a constant cache into a target storage space; the target storage space includes at least one vector register; obtaining a data access instruction for accessing target data in the constant cache; detecting that the target data is stored in the target storage space, and compiling the data access instruction into an arithmetic logic unit (ALU) instruction; the ALU instruction indicates the location of the target data in the target storage space. This approach can improve the operating efficiency of the shader.

Description

Technical Field

[0001] This invention relates to the field of graphics processing technology, and in particular to a constant data loading method, a graphics processor, and a media. Background Technology

[0002] As 3D game scenes become increasingly realistic and visually stunning, shader design has become more complex. Improving shader efficiency can reduce real-time latency and provide a better user experience.

[0003] Currently, in some scenarios, such as game scenarios, a constant buffer is typically used to store constant data. During runtime, the shader reads the corresponding data from the constant buffer through data loading instructions to complete the specific functional calculations of the shader.

[0004] In the existing technology, the operating efficiency of shaders is relatively low. Summary of the Invention

[0005] This invention addresses the technical problem of low shader operating efficiency.

[0006] To address the aforementioned technical problems, this invention provides a constant data loading method, comprising: storing at least a portion of data units in a constant cache into a target storage space; the target storage space including at least one vector register; obtaining a data access instruction, the data access instruction being used to access target data in the constant cache; detecting that the target data is stored in the target storage space, then compiling the data access instruction into an arithmetic logic unit instruction; and reading the target data from the target storage space based on the arithmetic logic unit instruction.

[0007] Optionally, storing at least a portion of the data units in the constant cache into the target storage space includes: establishing a mapping relationship between the at least a portion of the data units and the free channels in the target storage space; and storing the at least a portion of the data units into the corresponding free channels in the target storage space based on the mapping relationship.

[0008] Optionally, establishing the mapping relationship between the at least part of the data and the free channels in the target storage space includes: if the remaining unoccupied storage space in the target storage space is not less than the total data volume of the constant cache, then establishing a mapping relationship between each data unit in the constant cache and the free channels in the target storage space; if the remaining unoccupied storage space in the target storage space is less than the total data volume of the constant cache, then establishing a mapping relationship between M data units in the constant cache and the free channels in the target storage space; M is a positive integer, and the total data volume of the M data units is not greater than the storage space corresponding to the free channels in the target storage space.

[0009] Optionally, the M data units are the M data units with the smallest constant cache address identifiers.

[0010] Optionally, establishing the mapping relationship between the at least part of the data and the free channel in the target storage space includes: obtaining the address identifier of each data unit in the at least part of the data; determining the starting vector register for storing the at least part of the data from the target storage space; and determining the channel and vector register corresponding to each data unit based on the address identifier of each data unit and the starting vector register.

[0011] Optionally, determining the channel and vector register corresponding to each data unit based on the address identifier of each data unit and the start vector register includes: the identifier lane of the channel corresponding to the data unit with address identifier c. index The index in is c- ×N; the identifier of the vector register corresponding to the data unit with address identifier c is: R index = R （start + ） ;in, To Round down, where N is the number of channels contained in a single vector register, and R... start This is the identifier for the starting vector register.

[0012] Optionally, the constant data loading method further includes: if it is detected that the target data is not stored in the target storage space, then read the target data from the constant cache based on the data access instruction.

[0013] The present invention also provides a graphics processor, comprising: a storage unit for storing at least a portion of data units in a constant cache into a target storage space; the target storage space including at least one vector register; an instruction fetch unit for acquiring a data access instruction for accessing target data in the constant cache; a compilation unit for detecting that the target storage space stores the target data and compiling the data access instruction into an arithmetic logic unit instruction; the target storage space for storing constant data and including at least one vector register; and a data loading unit for reading the target data from the target storage space based on the arithmetic logic unit instruction.

[0014] The present invention also provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, on which a computer program is stored, and the computer program is executed by a processor to perform the steps of any of the constant data loading methods described above.

[0015] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0016] When a data access instruction is obtained, it is checked whether the target data is stored in the target memory space. If the target data is stored in the target memory space, the data access instruction is compiled into an arithmetic logic unit (ALU) instruction, and the target data is read from the target memory space based on the ALU instruction. By pre-storing at least a portion of the constant data in the constant cache in the target memory space, and then checking whether the target data exists in the target memory space based on the obtained data access instruction, and if so, reading the target data from the target memory space, the loading speed of constant data can be effectively improved, thereby enhancing the execution efficiency of the shader. Attached Figure Description

[0017] Figure 1 This is a flowchart of a constant data loading method according to an embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram illustrating the mapping relationship between data units in a constant cache and channels in a vector register in an embodiment of the present invention.

[0019] Figure 3 This is a schematic diagram of the structure of a graphics processor according to an embodiment of the present invention. Detailed Implementation

[0020] In existing technologies, when compiling a shader, the shader compiler translates data accesses to specific coordinates in the shader's constant cache into corresponding data loading instructions. Before the shader runs, the driver updates the constant cache with the necessary constant data for this execution. During shader runtime, the data loading instructions read the corresponding data from the constant cache to complete the specific functional calculations of the shader.

[0021] However, reading constant data from the constant cache via data loading instructions is a memory access operation, which has high latency. Furthermore, the data loaded from the constant cache is usually used as the source operand for subsequent instructions, creating data dependencies. This means that the compiler's instruction scheduling cannot hide the latency, resulting in low shader execution efficiency.

[0022] In this embodiment of the invention, at least a portion of the constant data in the constant cache is pre-stored in the target storage space. Based on the obtained data access instruction, the target data is first checked in the target storage space. If the target data exists, it is read from the target storage space. This can effectively improve the speed of constant data loading and thus improve the execution efficiency of the shader.

[0023] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] This invention provides a method for loading constant data, referring to... Figure 1 The following will provide a detailed explanation through specific steps.

[0025] In this invention, the following constant data loading method can be executed by a shader.

[0026] Step 101: Store at least a portion of the data units in the constant cache into the target storage space.

[0027] Step 102: Obtain data access instructions.

[0028] In practice, the shader can receive data access instructions, which are used to access the target data at the corresponding coordinates in the constant cache.

[0029] In practical applications, a constant cache can include multiple data units, with constant data stored within each unit. The target data can correspond to data stored in one data unit, or data stored in multiple data units.

[0030] Typically, each data unit in a constant cache corresponds to the same amount of storage space. For example, in a constant cache, each data unit corresponds to 4 bytes of storage space, or 32 bits. In other words, each data unit can store constant data of length 4 bytes.

[0031] It is understandable that, for different types / models of constant caches, the storage space corresponding to a data unit can also be other values, such as 8 bytes. In this embodiment of the invention, no specific limitation is made on the storage space corresponding to the data unit.

[0032] Step 103: If target data is detected in the target storage space, the data access instruction is compiled into an arithmetic logic unit instruction.

[0033] In this embodiment of the invention, the target storage space may include at least one vector register.

[0034] A single vector register can include N channels, each with a certain amount of storage space. Currently, the storage space corresponding to one channel can be 4 bytes. It is understandable that the size of the storage space corresponding to one channel can also be other values.

[0035] In the existing examples, a vector register typically includes 32 channels, with each channel corresponding to 4 bytes of storage. Understandably, as technology advances, the number of channels in a vector register can be expanded to other numbers, such as 64 channels, 128 channels, etc. The storage space corresponding to each channel can also be expanded to other values, such as 8 bytes.

[0036] In this embodiment of the invention, a mapping relationship between data units and free channels in the target storage space can be established first. Before the shader runs, the pipeline unit stores the data in the corresponding data units into the corresponding free channels in the target storage space based on the above mapping relationship.

[0037] When the shader compiler receives a data access instruction at runtime, it can determine whether the target data is stored in the target memory space. If the target data is stored in the target memory space, the shader compiler can compile the data access instruction into an Arithmetic Logic Unit (ALU) instruction. An ALU instruction can point to a channel in a vector register.

[0038] In other words, when a shader receives a data access instruction, it can obtain the target data unit corresponding to the target data indicated by the data access instruction. If an available channel corresponding to the target data unit is found in the above mapping relationship, the data access instruction can be converted into an arithmetic logic unit instruction; if no available channel corresponding to the target data unit is found in the above mapping relationship, the target data is read from the constant cache according to the existing data loading method.

[0039] The following section provides a detailed explanation of how to establish the mapping relationship between data units and idle channels.

[0040] In practice, the total amount of data in the constant cache and the remaining storage space in the target storage space can be obtained in advance. The total amount of data in the constant cache can refer to the sum of all data currently stored in the constant cache. There are two scenarios between the total amount of data in the constant cache and the remaining storage space in the target storage space: the remaining storage space in the target storage space is not less than the total amount of data in the constant cache, and the remaining storage space in the target storage space is less than the total amount of data in the constant cache.

[0041] If the remaining storage space in the target storage space is not less than the total data size of the constant cache, it means that the remaining storage space in the target storage space can store all the data in the constant cache. In this scenario, a mapping relationship can be established between each data unit in the constant cache and the free channels in the target storage space.

[0042] In other words, if the total amount of data in the constant cache is not less than the remaining storage space of the target storage space, then each data unit in the constant cache has a corresponding vector register and free channel.

[0043] For example, the total data size of the constant cache is 256 bytes, stored in data units 0 to 63, with each data unit storing 4 bytes of constant data. The target storage space includes 10 vector registers, each vector register having 32 channels, and each vector register is in an unoccupied state (i.e., each channel of each vector register is a free channel), with each channel corresponding to 4 bytes of storage space. Therefore, the remaining storage space in the target storage space is greater than the total data size of the constant cache.

[0044] A mapping relationship is established between all data units in the constant cache and the free channels in the target storage space. Each data unit (data unit 0 to data unit 63) has a corresponding vector register and free channel.

[0045] Understandably, if the remaining storage space of the target storage space is not less than the total amount of data in the constant cache, it is also possible to establish a mapping relationship between only a portion of the data units and the free channels.

[0046] Continuing with the example above, a mapping relationship is established between the data units 0 to 31 of the constant cache and the free channels in the target storage space.

[0047] If the remaining storage space in the target storage space is less than the total data size of the constant cache, it means that the remaining storage space in the target storage space cannot store all the data in the constant cache. In this scenario, a mapping relationship can be established between some data units in the constant cache and the free channels in the target storage space.

[0048] In other words, if the remaining storage space in the target storage space is less than the total amount of data in the constant cache, then only a portion of the data units in the constant cache can be mapped to the free channels. Because there are insufficient free channels, the remaining data units cannot be mapped to any free channels.

[0049] Specifically, if the remaining storage space of the target storage space is less than the total data volume of the constant cache, then a mapping relationship is established between M data units in the constant cache and the free channel, where M is a positive integer and the sum of the data volume of the M data units is not greater than the remaining storage space.

[0050] The M data units can be the top M data units with the smallest address identifiers in the constant cache, or the M data units can be the top M data units with the largest address identifiers in the constant cache.

[0051] For example, the total data size of the constant cache is 256 bytes, stored in data units 0 to 63, with each data unit storing 4 bytes of constant data. The target storage space includes 10 vector registers, numbered 0 to 9. Each vector register includes 32 channels, with each channel corresponding to 4 bytes of storage space. Vector registers 0 to 8 are all occupied, while only vector register 9 is unoccupied. Therefore, the remaining storage space in the target storage space is less than the total data size of the constant cache.

[0052] Establish a mapping relationship between the data units 0 to 31 of the constant cache and the 32 channels in the vector register 9.

[0053] In practical implementation, when establishing the mapping relationship between data units and idle channels, the identification information of the data units to be mapped can be obtained, as well as the starting vector register of the idle channel in the target storage space can be determined. Based on the address identifier of each data unit and the starting vector register, the channel and vector register corresponding to each data unit are determined.

[0054] In practical implementation, the identifier of the channel corresponding to the data unit with address 'c' in the constant cache can be represented as 'lane'.index And lane index The index in is c- ×N;

[0055] The identifier of the vector register corresponding to the data unit with address identifier c is: R index = R （start + ） ;in, To Round down, where N is the number of channels contained in a single vector register, and R... start This is the identifier for the starting vector register.

[0056] For example, a channel corresponds to 32 bits of storage space; in the constant cache, a data unit corresponds to 32 bits of storage space. The starting vector register is identified as R0. For the data unit with address 34 in the constant cache, its corresponding vector register is identified as: R index =R （0 + ） =R1; its corresponding channel identifier is lane. index The index in is: c- ×N=34-32=2.

[0057] Therefore, a mapping relationship is established between the data unit with address identifier 34 and channel lane2 of vector register R1. In other words, the data in the constant buffer with address identifier 32 can be mapped to channel lane2 of vector register R1.

[0058] It should be noted that the mapping relationship between the data unit with address identifier c and the vector register and channel described above is only an example of a specific implementation. The mapping relationship between the data unit with address identifier c and the vector register and channel can also be represented by other methods or rules.

[0059] For example, for a data unit with address identifier 'c', its corresponding channel identifier is 'lane'. index The index in the vector register is cmod N, and its corresponding identifier is R. （start + ） .

[0060] In this embodiment, after establishing a mapping relationship between at least some data units and the free channels in the target storage space, before the shader runs, the pipeline unit can store at least some data in the constant cache into the remaining storage space of the target storage space according to the above mapping relationship.

[0061] Reference Figure 2 This paper presents a schematic diagram illustrating the mapping relationship between data units in a constant cache and channels in a vector register, according to an embodiment of the present invention. The constant cache includes 64 data units, with corresponding address identifiers ranging from 0 to 63. Each data unit stores 4 bytes of data, meaning the total data volume of the constant cache is 256 bytes. The target storage space includes 10 vector registers, numbered R0 to R9. The channels in the vector registers within the target storage space are all unoccupied. Each channel corresponds to 4 bytes of storage space.

[0062] Based on the calculation method provided above, the mapping relationship between each data unit in the constant cache and the channel in the vector register is determined as follows: the data unit with address identifier 0 is associated with channel lane0 in vector register R0, the data unit with address identifier 1 is associated with channel lane1 in vector register R0, ..., the data unit with address identifier 32 is associated with channel lane0 in vector register R1, the data unit with address identifier 33 is associated with channel lane1 in vector register R1, ..., the data unit with address identifier 63 is associated with channel lane in vector register R1. 31 .

[0063] It is understandable that the above Figure 2 The mapping relationships depicted are for illustrative purposes only. In specific applications, some vector registers in the target storage space may store constant data, therefore the starting vector register may not be R0. The number of data units included in the constant buffer can also be other values. The size of the data stored in the data unit may also differ from the storage space corresponding to the channel.

[0064] If some vector registers in the target memory space may store constant data, the starting vector register can be determined from all unoccupied vector registers. Specifically, the vector register with the smallest identifier among all unoccupied vector registers can be selected as the starting vector register.

[0065] For example, the target memory space includes 10 vector registers, numbered R0 to R9. If vector registers R0 and R1 are occupied, and the remaining vector registers are not occupied, then vector register R2 is selected as the starting vector register.

[0066] In this scenario, for the data unit with address identifier 34 mentioned above, the identifier of its corresponding vector register is: R index = R （0 + ） =R3; its corresponding channel identifier is lane. index The index in is: c- ×N=34-32=2. That is to say, the data unit with address identifier 34 is mapped to lane2 of vector register R3.

[0067] If the storage space of a single data unit is smaller than the storage space corresponding to a single channel, then each data unit can be mapped to a channel.

[0068] For example, if a single data unit has a storage space of 2 bytes and a single channel has a storage space of 4 bytes, then a data unit can be mapped to a single channel. The specific mapping relationship can also be: lane. index The index in is c- ×N;R index = R （start + ） .

[0069] If the storage space of a single data unit is larger than the storage space corresponding to a single channel, then each data unit can be mapped to two or more channels. In this scenario, the number of channels mapped to a single data channel can be X = , To The value is rounded up.

[0070] For example, if a single data unit has 8 bytes of storage space and a single channel has 4 bytes of storage space, then one data unit can be mapped to two channels. The mapping relationship between a data unit and a channel can be: lane index The index in is c- ×N;R index = R （start + ） .

[0071] Since the channels in the vector register store data, the arithmetic logic unit (ALU) can essentially point to the target data stored in the channels. During runtime, the shader can read the target data from the corresponding channels based on the ALU. Therefore, in this invention, by pre-storing at least a portion of the constant data in the constant cache in the target storage space, and based on the acquired data access instruction, first checking if the target data exists in the target storage space, and if so, reading the target data from the target storage space, the speed of constant data loading can be effectively improved, thereby enhancing the shader's execution efficiency.

[0072] Reference Figure 3The present invention provides a graphics processor 30 according to an embodiment of the invention, including a storage unit 301, an instruction fetching unit 302, and a compilation unit 303, wherein:

[0073] Storage unit 301 stores at least a portion of the data units in the constant cache into a target storage space; the target storage space includes at least one vector register.

[0074] The instruction reading unit 302 is used to acquire a data access instruction, which is used to access target data in a constant cache.

[0075] The compilation unit 303 is used to detect that the target data is stored in the target storage space and compile the data access instruction into an arithmetic logic unit instruction; the target storage space is used to store constant data, including at least one vector register; the arithmetic logic unit instruction indicates the location of the target data in the target storage space.

[0076] In specific implementation, the specific execution process of the above-mentioned storage unit 301, instruction reading unit 302 and compilation unit 303 can be referred to steps 101 to 103, which will not be elaborated here.

[0077] This invention also provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, on which a computer program is stored. When the computer program is run by a processor, it performs the constant data loading step in any of the above-described graphics processors.

[0078] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be performed by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include ROM, RAM, disk, or optical disk, etc.

[0079] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of constant data loading, characterized by, The method comprises the following steps: storing data of at least part of data units in a constant cache into a target storage space; the target storage space comprises at least one vector register; obtaining a data access instruction, the data access instruction being used for accessing target data in the constant cache; if it is detected that the target data is stored in the target storage space, then compiling the data access instruction into an arithmetic logic unit instruction, comprising: establishing a mapping relationship between the at least part of data units and free channels in the target storage space; storing data of the at least part of data units into corresponding free channels in the target storage space based on the mapping relationship; the arithmetic logic unit instruction indicating a position of the target data in the target storage space; the establishing of the mapping relationship between the at least part of data units and the free channels in the target storage space comprises: obtaining an address identifier of each data unit in the at least part of data; determining a start vector register in which there is a free channel in the target storage space; determining a corresponding channel and vector register of each data unit based on the address identifier of each data unit and the start vector register.

2. The constant data loading method of claim 1, wherein, the establishing of the mapping relationship between the at least part of data and the free channels in the target storage space comprises: if remaining storage space not occupied in the target storage space is not less than a total data amount of the constant cache, then establishing a mapping relationship between each data unit in the constant cache and a free channel in the target storage space; if the remaining storage space not occupied in the target storage space is less than the total data amount of the constant cache, then establishing a mapping relationship between M data units in the constant cache and a free channel in the target storage space; M is a positive integer, and a total data amount of the M data units is not greater than the remaining storage space.

3. The constant data loading method of claim 2, wherein, the M data units are the first M data units with the smallest address identifier in the constant cache.

4. The constant data loading method of claim 1, wherein, the determining of the corresponding channel and vector register of each data unit based on the address identifier of each data unit and the start vector register comprises: an identifier lane of a lane corresponding to a data unit identified by the address identified by c index index as c- x N; The identification of the vector register corresponding to the data unit identified as c is: R index = R （start + ） ; wherein, is the start vector register, rounded down, N is the number of lanes contained in a single vector register, R start is the identification of the start vector register.

5. The constant data loading method of claim 1, wherein, the method further comprises the following steps: if it is detected that the target data is not stored in the target storage space, then reading the target data from the constant cache based on the data access instruction.

6. A graphics processor, comprising: The method comprises the following steps: a storage unit is configured to store data of at least part of data units in a constant cache into a target storage space; the target storage space comprises at least one vector register; an instruction reading unit is configured to obtain a data access instruction, the data access instruction being used for accessing target data in the constant cache; The compiling unit is configured to detect that the target data is stored in the target storage space, and compile the data access instruction into an arithmetic logic unit instruction, including: establishing a mapping relationship between the at least part of data units and free lanes in the target storage space; and storing data of the at least part of data units into corresponding free lanes in the target storage space based on the mapping relationship; the target storage space is configured to store constant data and includes at least one vector register; the arithmetic logic unit instruction indicates a position of the target data in the target storage space; the establishing of the mapping relationship between the at least part of data units and free lanes in the target storage space includes: obtaining an address identifier of each data unit in the at least part of data; determining a start vector register in which a free lane exists in the target storage space; and determining a corresponding lane and vector register of each data unit based on the address identifier of each data unit and the start vector register.

7. A computer-readable storage medium, which is a non-volatile storage medium or a non-transitory storage medium, on which a computer program is stored, characterized by The computer program is configured to, when executed by a processor, perform the steps of the constant data loading method of any one of claims 1-5.

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