Method and device for realizing DRAM (Dynamic Random Access Memory) access and DRAM controller

Abstract

The invention discloses a method and device for achieving DRAM access and a DRAM controller, and the method comprises the steps that the controller receives an access request, and the access request carries row address information of next access; and executing a data access operation and a pre-charging operation of the current target column, and performing a row activation operation of the next access by using the next row address information.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of semiconductor memory technology, and particularly to a method and apparatus for implementing DRAM access, and a DRAM controller. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a widely used main memory in modern computing systems. Its structure consists of a large number of memory cells arranged in rows and columns. Each memory cell in DRAM represents binary information by storing electrical charge through a capacitor. Due to the leakage characteristics of capacitors, the charge state of the memory cell gradually decays over time. Therefore, DRAM needs to be periodically refreshed to maintain data validity. Here, refreshing refers to periodically revisiting each row of memory cells, and through a row activation and pre-charging process, recharging or restoring the charge in the capacitor to its original state, thereby preventing data loss due to charge leakage.

[0003] Each time a new access request arrives, the DRAM controller (hereinafter referred to as the controller) needs to re-complete the entire process of row activation, column access, and precharge in sequence. Even with multiple consecutive accesses, it is often unavoidable to repeat these time-consuming steps. Especially when the target row is different, the previous row must be precharged before the new row is activated, which undoubtedly increases the overall access latency. Summary of the Invention

[0004] This application provides a method and apparatus for implementing DRAM access, and a DRAM controller, which can at least solve any of the above-mentioned technical problems.

[0005] This invention provides a method for implementing DRAM access, comprising: The controller receives an access request, which carries the row address information for the next access. Perform data access and precharge operations on the target column being accessed, and activate the row for the next access using the next row address information.

[0006] In one exemplary instance, prior to performing the data access operation and precharge operation on the currently accessed target column, the method further includes: Based on the row address information of the next access, determine whether the row address of the next access is the same as the row address of the current access; When it is determined that the row address of the next access is different from the row address of the current access, the steps of performing the data access operation and pre-charge operation of the target column of the current access are continued, and the row activation operation of the next access is performed using the next row address information.

[0007] In one exemplary instance, when it is determined that the row address of the next access is the same as the row address of the current access, the steps of performing the data access operation and precharge operation of the target column of the current access are skipped, and the row activation operation of the next access is performed using the next row address information, and the data access operation and precharge operation of the target column of the current access are performed.

[0008] In one exemplary instance, the access request received by the controller is an initial access request; prior to performing the data access operation and precharge operation on the target column of the current access, the process further includes: Activate the currently accessed row.

[0009] This application also provides a computer-readable storage medium storing computer-executable instructions for performing any of the above-described methods for implementing DRAM access.

[0010] This application embodiment further provides a DRAM controller, including a memory and a processor, wherein the memory stores the following instructions executable by the processor: steps for performing the DRAM access method described in any of the preceding claims.

[0011] This application embodiment further provides an apparatus for implementing DRAM access, including: a receiving module and a processing module; wherein, The receiving module is configured to receive access requests, which carry the row address information for the next access. The processing module is configured to perform data access operations and precharge operations on the target column currently being accessed, and to initiate row activation operations for the next access using the next row address information.

[0012] In one exemplary instance, a judgment module is further included, configured to determine, based on the row address information of the next access, that the row address of the next access is different from the row address of the current access, and continue to execute the processing of the processing module.

[0013] In one exemplary instance, the determining module is further configured to: determine, based on the row address information of the next access, that the row address of the next access is the same as the row address of the current access; The processing module is further configured to perform data access operations and precharge operations on the currently accessed target column.

[0014] In one exemplary instance, the processing module is further configured to: activate the currently accessed row if the access request is the first access request.

[0015] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0016] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0017] Figure 1 This is a schematic diagram of a typical DRAM system architecture; Figure 2 This is a first schematic diagram of the timing of a typical DRAM read operation; Figure 3 This is a second schematic diagram illustrating the timing of a typical DRAM read operation; Figure 4 This is a waveform diagram of a typical DRAM read timing. Figure 5 This is a waveform diagram of a typical DRAM write timing. Figure 6 This is a flowchart illustrating the method for implementing DRAM access in an embodiment of this application; Figure 7 This is a flowchart illustrating an embodiment of the method for implementing DRAM access in this application. Figure 8 This is a schematic diagram of a typical DRAM access process; Figure 9 This is a schematic diagram of the DRAM access process in an embodiment of this application; Figure 10 This is a schematic diagram of the structural composition of the device for implementing DRAM access in the embodiments of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0019] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0021] It is understood that the terms "first" and "second" used in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0022] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0023] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0024] The steps illustrated in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases the steps shown or described may be performed in a different order than that presented here.

[0025] Figure 1 A schematic diagram of a typical DRAM system architecture, such as Figure 1 As shown, the controller typically connects to multiple independent DRAM memory blocks (DRAM Banks, or simply Banks), such as... Figure 1 DRAM Bank0, DRAM Bank1...DRAM BankN. Figure 1In this system, the DRAM controller is responsible for receiving read and write requests from the CPU / main system and scheduling access operations to each Bank, including address decoding, row and column selection, refresh scheduling, and timing control. Each Bank is a storage unit with independent access capabilities, internally configured with its own row buffer and access status register; multiple Banks can process different access requests in parallel to improve memory bandwidth utilization.

[0026] A typical DRAM access process usually includes three stages: Row Activation, Column Access, and Precharge. In the Row Activation stage, the controller selects and opens the word line of the target row based on the row address, connecting the memory cell in that row to the corresponding bit line, and transferring its charge state to the sense amplifier. In the Column Access stage, the controller performs read / write operations based on the column address. After the access is completed, since the bit line voltage has deviated from the intermediate level, a precharge process is needed to close the current row and restore the bit line to the intermediate potential, preparing for the next access.

[0027] Taking read operations as an example, such as Figure 2 As shown, activate commands from the row (such as...) Figure 2 ACT in the command to read the column (e.g.) Figure 2 There is a mandatory wait period between the READ command and the row-to-column delay (tRCD) to ensure stable bit line voltage and proper signal amplification by the sensitive amplifier. After the READ command, the data is output from the DQ port only after a column access delay (CL). Figure 2 In this architecture, each READ operation corresponds to one DOUT output, and valid data is returned over multiple consecutive clock cycles. For example... Figure 4 As shown, this further illustrates the details of signal changes during the actual read operation. Figure 4 In the middle, the interface first provides the row address (such as... Figure 4 (RADD in the middle), and then activation signals are emitted sequentially (such as Figure 4 WLACT in the middle), select amplifier (such as ... Figure 4 SASET in the middle), then send the column address (such as Figure 4 CADD and CRADD in the column. When column access control signals (such as...) Figure 4 After the arrival of COLEN, RDQS, etc., data begins to be output on the data line (e.g., ...). Figure 4 (DOUT in the text). For example... Figure 4In the embodiment shown, after reading four data points, a certain number of clock cycles are still reserved for processing and preparing for pre-charging.

[0028] like Figure 3 As shown, after a complete read operation is completed, a precharge (tRP) phase is required. During the precharge phase, the current row is closed by issuing a PRECH command and the bit line is restored to the intermediate potential. Only after the precharge is completed can the controller start the next row activation. Figure 3 It emphasizes that precharge operations cannot be skipped between read operations, especially when the target row is switched, the overhead of tRP time is unavoidable.

[0029] The timing for writing to DRAM differs from that for reading DRAM, but it can also be divided into three parts: row activation, column access, and precharge. For example... Figure 5 As shown, in the DRAM write operation interface timing, the row address is provided first (e.g., ... Figure 5 (RADD in the middle) and activate the target row, then by column address (such as Figure 5 Select the target column using CADD or CRADD, then use write control signals (such as...) Figure 5 COLEN and WE in the middle) write the input data to the target storage unit (such as COLEN and WE). Figure 5 (DIN in the code). After writing is complete, a precharge phase is also required to close the current row and restore the bit line state.

[0030] In practical applications, when consecutive read / write requests frequently switch target rows (i.e., the row hit rate is low), the redundant overhead of tRCD (row-to-column delay) and tRP (precharge time) will inevitably introduce timing holes, thus affecting the overall DRAM access efficiency. If the controller only determines whether to close the current row and activate the new row based on its target address after receiving a new access request, then the idle time between two access requests cannot be fully utilized, which will lead to increased access latency and decreased bandwidth utilization.

[0031] To make reasonable use of these idle times and improve DRAM access efficiency, embodiments of this application propose a method for implementing DRAM access, such as... Figure 6 As shown, it may include: Step 600: The controller receives an access request, which carries the row address information for the next access.

[0032] The access request received by the controller can be a read request or a write request. In addition to the information necessary to perform the current access, the access request also carries the row address corresponding to the next access. That is, in this embodiment, the row address corresponding to the next access is embedded as an additional field in the current access request.

[0033] Step 602: Perform the data access operation and precharge operation of the target column currently being accessed, and use the next row address information to perform the row activation operation for the next access.

[0034] The row activation operation for the next access using the next row address information in step 602 means that after the current access operation is completed, the controller uses the row address information for the next access carried in the current access request to actively execute the activation operation of the next row in advance without waiting for a new access request to arrive. This effectively hides the originally exposed tRCD time. In other words, in this embodiment, the waiting process of tRCD overlaps with the activation operation of the next row, so the delay caused by tRCD time is not visible in the overall access timing.

[0035] The DRAM access method provided in this application, by carrying the row address information of the next access in the access request, enables the controller to plan resources in advance and perform preparation operations across access request cycles. Compared with the traditional responsive scheduling mechanism, it effectively utilizes the idle time between two access requests, significantly reduces the idle waiting time between two access requests, and improves the continuity of access timing. In other words, this application embodiment completes the row activation process in the traditional access flow in advance, thereby significantly improving DRAM access efficiency and reducing access latency under the condition that the system bandwidth is not yet saturated. This application embodiment achieves the purpose of improving access efficiency without changing the DRAM physical structure and standard interface protocol, only by extending the access request structure and optimizing the control strategy. It has the characteristics of low implementation cost, flexible deployment, and strong adaptability, which is very conducive to its promotion and application in existing DRAM storage systems.

[0036] In one exemplary instance, step 602 may also include: Step 601: Based on the row address information of the next access, determine that the row address of the next access is different from the row address of the current access.

[0037] In one exemplary instance, if the next accessed row address is the same as the currently accessed row address, step 603 may also be included: Perform data access operations and precharge operations on the current target column.

[0038] In this embodiment, when the target row of the next access is the same as the current access, the controller does not perform unnecessary pre-charging and row activation operations, but directly maintains the activation state of the current row. When the next access request arrives, the column access is quickly completed, thus preserving the access efficiency advantage when the row is hit.

[0039] In one exemplary instance, if the access request received by the controller is a first access request, then before performing the data access operation and precharge operation of the current target column, it may also include: activating the currently accessed row.

[0040] This application also provides a computer-readable storage medium storing computer-executable instructions for performing any of the above-described methods for implementing DRAM access.

[0041] This application embodiment further provides a DRAM controller, including a memory and a processor, wherein the memory stores the following instructions executable by the processor: steps for performing the DRAM access method described in any of the preceding claims.

[0042] In one exemplary instance, Figure 7 This is a flowchart illustrating an embodiment of the method for implementing DRAM access in this application, which may include: Step 700: The controller receives a first access request, which carries the row address information for the next access.

[0043] The first access request received by the controller (the initial access request) can be either a read request or a write request. In addition to the information necessary to execute the current access, the first access request also carries the row address corresponding to the next access. That is, the row address corresponding to the next access (such as the second access request) is embedded as an additional field in the current first access request for subsequent scheduling by the controller.

[0044] In one embodiment, the information necessary to perform the current access generally includes at least the following: The access type of the current access operation, i.e., read or write; The target address includes the row address used to select the row containing the target storage unit, and the column address used to select the column containing the target data in that row; Data length or burst length information; Bank number, used to identify the target bank.

[0045] Step 701: Based on the row address information of the next access, determine that the row address of the next access is different from the row address of the current access, execute the first access operation, and after the first access is completed, use the row address information of the next access to perform the row activation operation of the next access.

[0046] In one exemplary instance, performing the first access operation in step 701 may include: The controller executes the corresponding access process based on the first access request, including activating the current row, completing the data read or write operation of the current target column, and performing a precharge operation on the current row after the data transmission is completed.

[0047] In one exemplary instance, step 701, which involves initiating the row activation operation for the next access using the next row address information, means that after the first access operation is completed, the controller can proactively execute the activation operation for the next row in advance by utilizing the row address information for the next access carried in the first access request, without waiting for a new access request (such as a second access request). In this embodiment, when the row address of the next access is different from that of the current access, the controller can proactively execute the row activation operation for the next access based on the known next row address after the current access is completed, without waiting for the arrival of a second access request. This completes the access preparation in advance and effectively hides the originally exposed tRCD time. In other words, in this embodiment, the tRCD waiting process overlaps with the activation operation of the next row, so the delay caused by the tRCD time is not visible in the overall access timing.

[0048] In one exemplary instance, if it is determined, based on the row address information of the next access, that the row address of the next access is the same as the row address of the current access, then step 701 may further include: performing a second access operation. Performing the second access operation may include: The controller executes the corresponding access process based on the first access request, including activating the current row, completing the data reading or writing operation of the corresponding column, and keeping the current row in an active state, waiting for the next access request.

[0049] Step 702: Receive the second access request, which carries the row address information for the next access. Based on the row address information for the next access, determine that the row address for the next access is different from the row address for the current access, execute the third access operation, and after the third access is completed, use the row address information for the next access to perform the row activation operation.

[0050] In one exemplary instance, performing the third access operation in step 702 may include: The controller executes the corresponding access process based on the second access request, including reading or writing data to the current target column and performing a pre-charge operation on the current row after the data transmission is completed. At this time, when the second access request actually arrives, since its corresponding row address has been activated in step 701, the tRCD waiting period can be skipped, and the column access operation can be initiated directly based on the column address provided by the second access request, thereby effectively shortening the request response delay.

[0051] Similar to the first access request, the second access request (such as a read or write request) received by the controller also carries the row address information corresponding to the next access (such as a third access request). In other words, the row address corresponding to the next access is embedded as an additional field in the current second access request. In this way, while completing the second access request, the controller can continue to perform advance scheduling by referring to the row address information corresponding to the next access, thereby achieving continuous optimization across multiple access cycles.

[0052] Similarly, in an exemplary instance, if it is determined, based on the row address information of the next access, that the row address of the next access is the same as the row address of the current access, then step 702 further includes: performing a fourth access operation. Performing the fourth access operation may include: The controller executes the corresponding access process based on the second access request, including completing the data reading or writing operation of the corresponding column, keeping the current row in an active state, and waiting for the next access request.

[0053] Figure 8 This is a typical DRAM access process diagram, such as... Figure 8 As shown, the typical implementation process of reading and writing DRAM usually includes: the main system sends a read / write request to the controller, and the controller issues corresponding control commands to the DRAM in sequence according to the address and length information contained in the request, thus completing one access process. This access process includes three main stages: row activation, which selects and activates the target row according to the row address; column access and data operation, which reads or writes data according to the column address; and precharge, which closes the current row and restores the bit line state after the access is completed, in preparation for the next access. Figure 8 This demonstrates a typical access sequence in this conventional implementation process. Figure 8 In the process, after the first read / write request arrives, the controller starts with row activation, proceeds through column access, and finally performs precharge until the access is complete. After the first read / write request is completed, the controller enters an idle waiting state until the second request actually arrives. When the second read / write request arrives, the entire process needs to be executed again. Figure 7 It is evident that the row activation and pre-charging processes occupy the first and second halves of the access cycle, respectively, and their delays are not negligible. At the same time, there is a significant idle period (also known as the inter-request waiting period) between the two access requests. During this period, the controller is in a passive state of waiting for new requests and does not actively initiate any pre-processing operations, resulting in reduced system bandwidth utilization and increased access response time.

[0054] Compared to Figure 8 The typical DRAM access process shown is as follows: The DRAM access process in the embodiments of this application is as follows: Figure 9As shown, in the DRAM access process of this application embodiment, each access request (such as the first read / write request) carries the target row address information for the next access request. When the controller receives the request, while completing the current access (i.e., row activation, column access, precharge) operation, it can use the row address information for the next access provided in the request to initiate the activation operation of the next access row in advance during the idle time period. Figure 9 It is clear from this that before the second read / write request officially arrives, the controller has already activated the row for the next access during the idle period; when the second request actually arrives, the controller does not need to wait for tRCD (row activation delay) and skips the row activation delay, immediately entering the column access phase. Figure 8 In comparison, the overall response time for the second request, from the moment it was initiated to the completion of data processing, was significantly shorter.

[0055] This application embodiment significantly reduces the time overhead caused by row switching by embedding the next row address information in the access request and activating the row in advance after the current access is completed. This shortens the response time of read / write requests, improves the overall access efficiency and system bandwidth utilization, makes fuller use of DRAM resource idle periods, and enhances the foresight and flexibility of access scheduling.

[0056] Figure 10 This is a schematic diagram of the structural composition of the apparatus for implementing DRAM access in the embodiments of this application, as shown below. Figure 10 As shown, it may include: a receiving module and a processing module; wherein, The receiving module is configured to receive access requests, which carry the row address information for the next access. The processing module is configured to perform data access operations and precharge operations on the target column currently being accessed, and to initiate row activation operations for the next access using the next row address information.

[0057] In one exemplary instance, a judgment module is also included, configured to determine, based on the row address information of the next access, that the row address of the next access is different from the row address of the current access, and continue to execute the processing module's processing.

[0058] In one exemplary instance, the judgment module is further configured to: determine that the row address to be accessed next is the same as the row address to be accessed currently, based on the row address information of the next access; correspondingly, the processing module is further configured to: perform data access operation and precharge operation on the target column to be accessed currently.

[0059] In one exemplary instance, for the case where the access request is the first access request, the processing module is also configured to activate the currently accessed row.

[0060] The DRAM access apparatus provided in this application, by carrying the row address information of the next access in the access request, enables the controller to plan resources in advance and perform preparation operations across access request cycles. Compared with the traditional responsive scheduling mechanism, it effectively utilizes the idle time between two access requests, significantly reduces the idle waiting time between two access requests, and improves the continuity of access timing. In other words, this application embodiment completes the row activation process in the traditional access flow in advance, thereby significantly improving DRAM access efficiency and reducing access latency under the condition that the system bandwidth is not yet saturated. This application embodiment achieves the purpose of improving access efficiency without changing the DRAM physical structure and standard interface protocol, only by extending the access request structure and optimizing the control strategy. It has the characteristics of low implementation cost, flexible deployment, and strong adaptability, which is very conducive to its promotion and application in existing DRAM storage systems.

[0061] Although the embodiments disclosed in this application are as described above, the content described is merely for the purpose of understanding this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A method for implementing DRAM access, characterized in that, include: The controller receives an access request, which carries the row address information for the next access. Perform data access and precharge operations on the target column being accessed, and activate the row for the next access using the next row address information.

2. The method according to claim 1, further comprising, before performing the data access operation and precharge operation of the currently accessed target column: Based on the row address information of the next access, determine whether the row address of the next access is the same as the row address of the current access; When it is determined that the row address of the next access is different from the row address of the current access, the steps of performing the data access operation and pre-charge operation of the target column of the current access are continued, and the row activation operation of the next access is performed using the next row address information.

3. The method according to claim 2, wherein when it is determined that the row address of the next access is the same as the row address of the current access, the steps of skipping the data access operation and precharge operation of the target column of the current access, and using the next row address information to perform the row activation operation of the next access, are performed, and the data access operation and precharge operation of the target column of the current access are executed.

4. The method according to any one of claims 1-3, wherein the access request received by the controller is a first access request; prior to performing the data access operation and precharge operation of the target column currently accessed, the method further includes: Activate the currently accessed row.

5. A computer-readable storage medium storing computer-executable instructions for performing the method for implementing DRAM access as described in any one of claims 1-4.

6. A DRAM controller, comprising a memory and a processor, wherein, The memory stores the following instructions that can be executed by a processor: steps for performing the method for implementing DRAM access as described in any one of claims 1-4.

7. An apparatus for implementing DRAM access, characterized in that, include: Receive module, processing module; among which, The receiving module is configured to receive access requests, which carry the row address information for the next access. The processing module is configured to perform data access operations and precharge operations on the target column currently being accessed, and to initiate row activation operations for the next access using the next row address information.

8. The apparatus according to claim 7 further includes a judgment module, configured to determine, based on the row address information of the next access, that the row address of the next access is different from the row address of the current access, and continue to execute the processing of the processing module.

9. The apparatus according to claim 8, wherein the determining module is further configured to: determine, based on the row address information of the next access, that the row address of the next access is the same as the row address of the current access; The processing module is further configured to perform data access operations and precharge operations on the currently accessed target column.

10. The apparatus according to any one of claims 7-9, wherein the processing module is further configured to: activate the currently accessed row if the access request is the first access request.

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