Inverter wireless parallel control system

Abstract

The application relates to the technical field of inverters, and discloses an inverter wireless parallel control system which comprises a microcontroller and a digital signal processor. The microcontroller acquires the output current and capacity ratio of an inverter to be paralleled, adjusts the clock of a current inverter according to a preset protocol to realize clock synchronization, and periodically broadcasts a system reference frequency. The digital signal processor acquires the pulse modulation signal of the inverter to be paralleled, adjusts the phase of the pulse modulation signal of the current inverter according to the pulse modulation signal to realize phase synchronization, adjusts the output frequency of the current inverter according to the system reference frequency to realize frequency synchronization, and adjusts the output current of the current inverter according to the output current and capacity ratio of the inverter to be paralleled to realize current synchronization. The technical scheme avoids the problems of complex wiring and poor expansibility of traditional wired parallel connection, realizes the consistency of voltage, frequency and phase among inverters and the reasonable distribution of current, and significantly improves the stability of the system.

Description

Technical Field

[0001] This invention relates to the field of inverter technology, and more particularly to a wireless parallel control system for inverters. Background Technology

[0002] With the development of distributed power sources, photovoltaic energy storage systems, and microgrids, the demand for parallel operation of inverters is increasing. When multiple inverters operate in parallel, they need to maintain a high degree of consistency in voltage, frequency, and phase, while achieving reasonable distribution of output current to ensure system stability and energy efficiency.

[0003] Existing inverter parallel control typically relies on a single digital signal processor (DSP) for centralized control. While this approach can perform real-time tasks such as current loop and PWM control, the DSP's low clock frequency and limited computing power mean that it must simultaneously handle communication protocols and complex calculations, easily leading to a decline in control performance. To address the insufficient computing power of DSPs, some solutions introduce external wired communication modules (such as CAN or RS485). However, this approach involves complex wiring, poor scalability, and is not conducive to the rapid connection and flexible deployment of multi-node inverters. Summary of the Invention

[0004] This invention provides a wireless parallel control system for inverters to solve the above-mentioned technical problems.

[0005] A first aspect of this invention provides a wireless parallel control system for inverters, the wireless parallel control system for inverters comprising:

[0006] The microcontroller is used to establish a wireless connection with the inverter to be paralleled, obtain the output current and capacity ratio of the inverter to be paralleled, adjust the clock of the current inverter according to the preset protocol for clock synchronization, and periodically broadcast the system reference frequency.

[0007] The digital signal processor is used to acquire the pulse modulation signal of the inverter to be paralleled, adjust the phase of the pulse modulation signal of the current inverter according to the pulse modulation signal to achieve phase synchronization, adjust the output frequency of the current inverter according to the system reference frequency to achieve frequency synchronization, and adjust the output current of the current inverter according to the output current and capacity ratio of the inverter to be paralleled to achieve current synchronization.

[0008] Optionally, the microcontroller performs millisecond-level clock synchronization according to the IEEE 1588 protocol.

[0009] Optionally, the digital signal processor adjusts the phase of the pulse modulation signal of the current inverter based on the rising edge of the pulse modulation signal to achieve phase synchronization.

[0010] Optionally, the digital signal processor includes a phase-locked loop (PLL) module that tracks and adjusts the current inverter's output frequency to synchronize it with the system reference frequency.

[0011] Optionally, the phase-locked loop module includes: a phase comparison unit, a filtering unit, and a numerically controlled oscillation unit. The phase comparison unit is used to compare the phase difference between the current inverter's output frequency and the system reference frequency. The filtering unit is used to smooth the phase difference. The numerically controlled oscillation unit is used to adjust the current inverter's output frequency based on the smoothed phase difference.

[0012] Optionally, the digital signal processor calculates the current inverter adjustment amount according to the following formula:

[0013] I ref_new =I ref +γ∑ j∈N (I) j / SOC j -I local / SOC local );

[0014] Among them, I ref I is the reference current of the current inverter. j The actual output current of the inverter to be paralleled, SOC j I is the capacity ratio of the inverters waiting to be paralleled. local The current output current of the inverter, SOC local γ represents the current inverter capacity ratio, and γ is the convergence coefficient.

[0015] Optionally, the microcontroller periodically transmits data to the digital signal processor via a serial peripheral interface.

[0016] Optionally, the digital signal processor is configured with multiple interrupt levels, among which the overcurrent protection interrupt has the highest priority and the interrupt received by the serial peripheral interface has the second highest priority.

[0017] Optionally, the microcontroller uploads runtime data to the cloud at preset intervals via the MQTT or HTTP protocol and wakes up intermittently in low-power mode.

[0018] Optionally, the digital signal processor calculates the voltage correction based on the virtual impedance parameter when performing current synchronization, and adds the voltage correction to the current inverter voltage reference value to form a new voltage control command.

[0019] The technical effects of this invention are as follows: By introducing the division of labor and cooperation between a microcontroller and a digital signal processor in the inverter parallel system, the microcontroller realizes wireless communication and clock synchronization, and the digital signal processor performs phase, frequency and current synchronization control. This not only reduces the computational burden of the DSP and improves the real-time control performance, but also avoids the problems of complex wiring and poor scalability in traditional wired parallel systems. As a result, the consistency of voltage, frequency and phase between inverters and the reasonable distribution of current are achieved, which significantly improves the stability, energy efficiency and flexibility of the system. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of a wireless parallel control system for an inverter provided in Embodiment 1 of the present invention;

[0022] Figure 2 This is a schematic diagram of the structure of a digital signal processor in a wireless parallel control system for an inverter provided in Embodiment 1 of the present invention;

[0023] Figure 3 This is a schematic diagram of the phase-locked loop module in the digital signal processor of an inverter wireless parallel control system provided in Embodiment 1 of the present invention;

[0024] In the diagram: 101, Microcontroller; 102, Digital Signal Processor; 103, Current Inverter; 104, Inverter to be Parallelized; 111, Phase-Locked Loop Module; 112, Phase Comparison Unit; 113, Filtering Unit; 114, Digitally Controlled Oscillation Unit. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0027] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0029] To fully understand this invention, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0030] Example 1

[0031] This embodiment provides a wireless parallel control system for inverters, such as... Figure 1 As shown, the inverter wireless parallel control system includes:

[0032] The microcontroller 101 is used to establish a wireless connection with the inverter 104 to be paralleled, obtain the output current and capacity ratio of the inverter 104 to be paralleled, adjust the clock of the current inverter 103 according to the preset protocol for clock synchronization, and periodically broadcast the system reference frequency.

[0033] The digital signal processor 102 is used to acquire the pulse modulation signal of the inverter 104 to be paralleled, adjust the phase of the pulse modulation signal of the current inverter 103 according to the pulse modulation signal to perform phase synchronization, adjust the output frequency of the current inverter 103 according to the system reference frequency to perform frequency synchronization, and adjust the output current of the current inverter 103 according to the output current and capacity ratio of the inverter 104 to be paralleled to perform current synchronization.

[0034] The microcontroller 101 establishes a connection with the inverter 104 to be paralleled via a wireless communication module (such as WiFi, ZigBee, Bluetooth, or a self-organizing network protocol) and periodically receives its operating parameters. After obtaining the output current and capacity ratio data, the microcontroller 101 corrects its own clock pulse according to the synchronization strategy in the protocol. Simultaneously, the microcontroller 101 broadcasts a unified reference frequency at a fixed period, allowing all connected inverters to share this reference. Through the microcontroller 101, a unified clock and frequency reference are achieved among the inverters, eliminating operational instability caused by clock drift and frequency differences, and improving the overall synchronization of the parallel system. The digital signal processor 102 (DSP) reads the pulse modulation signal of the inverter 104 to be paralleled via a sampling interface. After comparing and analyzing its carrier phase, it adjusts the trigger phase of its own PWM pulse to achieve phase alignment. The DSP also receives the reference frequency signal broadcast by the microcontroller 101 and corrects its own output frequency in real time to keep it consistent with the system. In terms of current distribution, the DSP dynamically allocates the output current according to the capacity ratio algorithm, allowing smaller capacity inverters to output less current and larger capacity inverters to handle more load, ultimately achieving current balance. The DSP achieves phase synchronization, frequency synchronization, and current synchronization of the inverter output, ensuring output waveform consistency and avoiding circulating current and overload phenomena, thereby improving the stability and reliability of parallel power supply. This implementation achieves multi-dimensional synchronous control of the inverter in a wireless environment through the collaboration of the microcontroller 101 and the DSP. Interconnection is established through wireless communication, the microcontroller 101 manages the clock and frequency reference, and the DSP performs real-time synchronous adjustment of phase, frequency, and current.

[0035] The technical advantages of this embodiment are as follows: Through the collaboration of the microcontroller 101 and the digital signal processor 102, clock synchronization, frequency synchronization, phase synchronization, and current synchronization among inverters can be achieved, ensuring the overall coordinated operation of the parallel system. While maintaining consistent phase and frequency, current distribution is performed based on capacity ratio, allowing inverters of different capacities to output power proportionally, avoiding overload or loss problems caused by circulating current and uneven current distribution. By periodically broadcasting the reference frequency and adjusting the modulation phase in real time, the consistency of the output voltage waveform is ensured, thereby effectively reducing harmonics and waveform distortion, and improving the stability and power quality of parallel power supply. This solution is particularly suitable for applications such as distributed power sources, microgrids, and energy storage systems, and can easily expand or reduce the number of parallel inverters while maintaining the reliable operation of the overall system.

[0036] As one implementation, the microcontroller 101 performs millisecond-level clock synchronization according to the IEEE 1588 protocol.

[0037] The microcontroller 101's built-in wireless communication module receives IEEE 1588 protocol messages from the parallel inverter 104, including the master clock timestamp information. Upon receiving the message, the microcontroller 101 uses the master-slave clock synchronization mechanism defined by the IEEE 1588 protocol to obtain the network transmission delay by exchanging Sync, Follow_Up, Delay_Req, and Delay_Resp messages. It then calculates the deviation between the local clock and the master clock based on the delay-corrected timestamp. After obtaining the time deviation information, the microcontroller 101 adjusts its internal oscillator to correct the clock frequency and phase, ensuring that the local clock and master clock remain synchronized within a millisecond-level accuracy range. Subsequently, using the synchronized clock as a reference, the microcontroller 101 periodically broadcasts the system reference frequency for other parallel inverters to receive and correct their own outputs.

[0038] The technical advantages of this implementation are as follows: by utilizing the timestamp comparison and delay compensation mechanism of the IEEE 1588 protocol, millisecond-level clock synchronization between inverters is achieved, which is significantly better than the traditional wireless broadcasting method; on the basis of high clock consistency, the frequency, phase and current synchronization between inverters are more accurate, reducing power oscillation and circulating current caused by clock deviation.

[0039] In one implementation, the digital signal processor 102 adjusts the phase of the pulse modulation signal of the current inverter 103 according to the rising edge of the pulse modulation signal to perform phase synchronization.

[0040] The digital signal processor 102 detects the pulse modulation signal through a sampling circuit and identifies the rising edge position of the pulse modulation signal. The digital signal processor 102 compares the detected rising edge with the rising edge of the pulse modulation signal of the current inverter 103. When a phase deviation exists, the digital signal processor 102 adjusts the trigger time of the pulse modulation signal of the current inverter 103 according to the deviation value to align the rising edges of the two, thereby achieving phase synchronization between the inverters. In specific implementation, the digital signal processor 102 can correct the phase by adjusting the phase register or trigger delay parameter of the PWM control signal to ensure that the phase of the output voltage waveform of the current inverter 103 is consistent with that of the inverter 104 to be paralleled. This process can be repeated periodically to compensate for phase errors caused by device drift or communication delay, ensuring the real-time performance and stability of phase synchronization.

[0041] The technical advantages of this implementation are as follows: by detecting and comparing the rising edge of the pulse modulation signal, the consistency of the output waveforms of the inverters on the time axis is ensured; phase synchronization avoids the problem of circulating current caused by phase difference when the inverters are running in parallel, thus improving the stability and safety of the system operation. Maintaining strict synchronization of the voltage waveforms output by multiple inverters helps reduce harmonic distortion and improve the power quality on the load side.

[0042] As one implementation method, such as Figure 2 As shown, the digital signal processor 102 includes a phase-locked loop module 111, which tracks and adjusts the output frequency of the current inverter 103 to synchronize the output frequency with the system reference frequency.

[0043] The digital signal processor 102 (DSP) includes a phase-locked loop (PLL) module. The PLL module 111 is used to track and adjust the output frequency of the current inverter 103 in real time. Specifically, the PLL module 111 uses the system reference frequency as a reference signal and the current inverter 103's output frequency as an input signal. A phase detector detects the frequency and phase differences between the reference and input signals and outputs an error signal. This error signal is smoothed by a loop filter and then drives a voltage-controlled oscillator to adjust the pulse modulation frequency of the current inverter 103. During continuous closed-loop adjustment, the PLL module gradually reduces the deviation between the current inverter 103's output frequency and the system reference frequency until they are synchronized. When external environmental factors (such as temperature drift or communication delay) cause minor fluctuations in the output frequency, the PLL module 111 can also compensate for the deviation in real time, thereby ensuring the stability and continuity of frequency synchronization.

[0044] The technical advantages of this implementation are as follows: through the tracking and adjustment of the phase-locked loop module 111, the output frequency of the current inverter 103 is strictly aligned with the system reference frequency, ensuring the consistency of parallel operation of multiple inverters. While maintaining frequency synchronization, it effectively avoids inverter power oscillations or unstable power supply caused by frequency differences. With the output frequencies of all inverters unified, the power waveform on the load side is more stable, harmonic content is reduced, and power supply quality is improved.

[0045] As one implementation method, such as Figure 3 As shown, the phase-locked loop module 111 includes a phase comparison unit 112, a filtering unit 113, and a numerically controlled oscillation unit 114. The phase comparison unit 112 is used to compare the phase difference between the current output frequency of the inverter 103 and the system reference frequency. The filtering unit 113 is used to smooth the phase difference. The numerically controlled oscillation unit 114 is used to adjust the current output frequency of the inverter 103 according to the smoothed phase difference.

[0046] The phase comparison unit 112 compares the current output frequency signal of the inverter 103 with the system reference frequency signal to obtain the phase difference between them. The filtering unit 113 filters the phase difference signal output by the phase comparison unit to eliminate high-frequency jitter or transient interference, thereby obtaining a smooth phase difference signal. The numerically controlled oscillation unit 114 dynamically adjusts the current output frequency of the inverter 103 according to the filtered phase difference signal, gradually approaching and locking it to the system reference frequency. In specific implementation, the phase comparison unit 112 can adopt a digital phase detector structure to obtain an accurate phase difference value through logical operations; the filtering unit 113 can be a low-pass filter or a digital integrator to reduce noise components; the numerically controlled oscillation unit 114 can adopt a numerically controlled oscillator (NCO) or a digital phase-locked oscillator to achieve frequency correction by adjusting the output period of the oscillator. Through the coordinated work of the above three units, the phase-locked loop module 111 can continuously correct the output frequency under closed-loop control to ensure that the inverter output is consistent with the system reference frequency.

[0047] The technical advantages of this implementation are as follows: High-precision synchronization of the inverter output frequency is achieved through a closed-loop mechanism of phase comparison, filtering, and oscillation adjustment. The filtering unit smooths the phase difference signal, effectively eliminating the impact of transient disturbances on frequency synchronization accuracy. The numerically controlled oscillation unit can quickly correct the frequency based on the real-time phase difference, adapting to changes in the system environment (such as temperature drift and communication delay). Multiple inverters operating at a unified frequency avoid power oscillations and circulating currents caused by frequency deviations, improving system stability and power supply quality.

[0048] As one implementation, the digital signal processor 102 calculates the adjustment amount of the current inverter 103 according to the following formula:

[0049] I ref_new =I ref +γ∑ j∈N (I) j / SOC j -I local / SOC local );

[0050] Among them, I ref I is the reference current of the current inverter 103. j The actual output current of the inverter 104 in parallel operation, SOC j For the capacity ratio of the inverter 104 to be connected in parallel, I local The current output current of inverter 103, SOC local γ represents the capacity ratio of the current inverter 103, and γ is the convergence coefficient.

[0051] Using the aforementioned formula, the digital signal processor 102 can compare the unit capacity current of the current inverter 103 with that of the inverter 104 to be paralleled, and correct its own reference current value in each control cycle. When the unit capacity current of the current inverter 103 is higher than that of the inverter 104 to be paralleled, the reference current decreases accordingly; when the unit capacity current of the current inverter 103 is lower than that of the inverter 104 to be paralleled, the reference current increases accordingly. After multiple iterations, the unit capacity current of each inverter eventually converges to a consistent value, achieving a reasonable load distribution among inverters of different capacities, thereby avoiding overload or idleness of some inverters.

[0052] The technical advantages of this implementation method are: it can ensure dynamic current sharing when multiple inverters are operating in parallel wirelessly, with large-capacity inverters automatically sharing more load and small-capacity inverters sharing less load, which improves the fairness of power distribution and reduces the risk of circulating current, thereby improving the energy efficiency and reliability of the entire system.

[0053] In one implementation, the digital signal processor 102 is provided with multiple interrupt levels, among which the overcurrent protection interrupt has the highest priority and the interrupt received by the serial peripheral interface has the second highest priority.

[0054] The digital signal processor 102 (DSP) internally has multiple interrupt levels for graded responses to different events during system operation. The overcurrent protection interrupt is set as the highest priority interrupt. When the inverter output current exceeds a preset threshold, the DSP immediately triggers this interrupt, prioritizing the execution of the overcurrent protection procedure to shut down relevant power devices or reduce output power in the shortest possible time, thereby preventing device damage or system failure. Furthermore, the Serial Peripheral Interface (SPI) receive interrupt is set as a secondary priority interrupt. When the microcontroller 101 transmits operating data to the DSP via the SPI interface, the DSP responds to this interrupt even if the overcurrent protection interrupt is not triggered, and completes data reception and parsing. Through this priority mechanism, the DSP can ensure both safety protection and real-time data communication. In the specific implementation, the multiple interrupt levels can be managed by the DSP's internal interrupt controller, implementing graded processing logic for different events by setting interrupt vector tables and priority registers.

[0055] The technical advantages of this implementation are as follows: setting the overcurrent protection interrupt to the highest priority ensures that abnormal current can be quickly cut off or suppressed in extreme cases, avoiding hardware damage; although the SPI receive interrupt has a secondary priority, it can still be responded to in a timely manner when the overcurrent protection is not triggered, ensuring that the data transmitted by the microcontroller 101 can be delivered to the DSP in real time. Through multi-level interrupt management, the DSP can allocate the response order according to the importance of the event, avoiding the delayed execution of critical protection logic and enhancing the reliability of the system under complex operating conditions.

[0056] In one implementation, the microcontroller 101 uploads operating data to the cloud at preset intervals via the MQTT or HTTP protocol and wakes up intermittently in low-power mode.

[0057] The microcontroller 101 is further used to implement cloud monitoring functionality. Specifically, during normal inverter operation, the microcontroller 101 establishes a connection with the cloud server via its built-in wireless communication module and uploads operational data at preset intervals based on the MQTT or HTTP protocol. This operational data includes, but is not limited to, the inverter's output current, voltage, frequency, capacity ratio, operating status, and fault information. In this way, the cloud can obtain the real-time operating status of each inverter, enabling remote monitoring and centralized management. To reduce energy consumption, the microcontroller 101 is equipped with a low-power operating mode. After data upload is complete, the microcontroller 101 enters a low-power sleep state, only waking up when the preset upload cycle is reached or a specific wake-up signal is received. This intermittent wake-up mechanism ensures that the wireless parallel control of the inverter is not affected, significantly reducing the energy consumption of the microcontroller 101 and improving the overall energy efficiency of the system.

[0058] The technical advantages of this implementation are as follows: by integrating cloud data upload and low-power intermittent wake-up mechanism into microcontroller 101, not only is remote visualization and intelligent management of inverter operation data realized, but also energy consumption during wireless communication is effectively reduced, the service life of the system is extended, and the operation and maintenance capabilities and reliability of the inverter cluster are enhanced.

[0059] In one implementation, the digital signal processor 102 calculates a voltage correction based on virtual impedance parameters when performing current synchronization, and adds the voltage correction to the current voltage reference value of the inverter 103 to form a new voltage control command.

[0060] In this process, the digital signal processor 102 further introduces virtual impedance compensation during current synchronization. Specifically, the digital signal processor 102 calculates a voltage correction based on preset virtual impedance parameters and adds this voltage correction to the current voltage reference value of the inverter 103 to obtain a new voltage control command. The virtual resistance parameter is used to introduce an equivalent voltage drop when the current increases, making the inverter behave as a power supply with certain damping characteristics. Through this method, the digital signal processor 102 can actively adjust the voltage reference value on the basis of current synchronization, so that the inverters exhibit equivalent impedance characteristics when operating in parallel. This equivalent impedance characteristic can effectively suppress circulating current phenomena caused by line impedance differences, sampling errors, or control delays, and make the current distribution of each inverter more balanced.

[0061] The technical advantages of this implementation method are as follows: by adopting this implementation method, while maintaining the current synchronization accuracy, the parallel circulating current can be further reduced, thereby improving the stability and reliability of the system; at the same time, by introducing a combination of virtual resistance and virtual inductance control, the current sharing performance of multiple inverters under dynamic operating conditions can also be improved.

[0062] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A wireless parallel control system for inverters, characterized in that, The inverter wireless parallel control system includes: The microcontroller is used to establish a wireless connection with the inverter to be paralleled, obtain the output current and capacity ratio of the inverter to be paralleled, adjust the clock of the current inverter according to a preset protocol for clock synchronization, and periodically broadcast the system reference frequency. A digital signal processor is configured to acquire the pulse modulation signal of the inverter to be paralleled, adjust the phase of the pulse modulation signal of the current inverter according to the pulse modulation signal to perform phase synchronization, adjust the output frequency of the current inverter according to the system reference frequency to perform frequency synchronization, and adjust the output current of the current inverter according to the output current and capacity ratio of the inverter to be paralleled to perform current synchronization. The digital signal processor includes a phase-locked loop module, which tracks and adjusts the output frequency of the current inverter to synchronize the output frequency with the system reference frequency. The phase-locked loop module includes: a phase comparison unit, a filtering unit, and a numerically controlled oscillation unit. The phase comparison unit is used to compare the phase difference between the current inverter's output frequency and the system reference frequency. The filtering unit is used to smooth the phase difference. The numerically controlled oscillation unit is used to adjust the current inverter's output frequency according to the smoothed phase difference. The digital signal processor calculates the adjustment amount of the current inverter according to the following formula: I ref_new =I ref +γ∑ j∈N ( I j / SOC j -I local / SOC local ); Among them, I ref I is the reference current of the current inverter. j The actual output current of the inverter to be paralleled, SOC j I represents the capacity ratio of the inverters to be paralleled. local The current output current of the current inverter, SOC local The capacity ratio of the current inverter is γ, and the convergence coefficient is γ. Using the above formula, the digital signal processor compares the unit capacity current of the current inverter with that of the inverter to be paralleled, and corrects its own reference current value in each control cycle; when the unit capacity current of the current inverter is higher than that of the inverter to be paralleled, the reference current decreases accordingly; when the unit capacity current of the current inverter is lower than that of the inverter to be paralleled, the reference current increases accordingly; after multiple iterations, the unit capacity current of each inverter eventually converges to be consistent; The microcontroller periodically transmits data to the digital signal processor through a serial peripheral interface; The digital signal processor (DSP) internally has multiple interrupt levels for graded responses to different events during system operation. The overcurrent protection interrupt is set as the highest priority interrupt; when the inverter output current exceeds a preset threshold, the DSP immediately triggers this interrupt, prioritizing the execution of the overcurrent protection procedure. The serial peripheral interface receive interrupt is set as the second-highest priority interrupt; when the microcontroller transmits operating data to the DSP through the serial peripheral interface, the DSP responds to this interrupt even if the overcurrent protection interrupt is not triggered, and completes data reception and parsing. These multiple interrupt levels are managed by an internal interrupt controller within the DSP, which implements graded processing logic for different events by setting an interrupt vector table and a priority register.

2. The inverter wireless parallel control system as described in claim 1, characterized in that, The microcontroller performs millisecond-level clock synchronization according to the IEEE 1588 protocol.

3. The inverter wireless parallel control system as described in claim 1, characterized in that, The digital signal processor adjusts the phase of the pulse modulation signal of the current inverter according to the rising edge of the pulse modulation signal to perform phase synchronization.

4. The inverter wireless parallel control system as described in claim 1, characterized in that, The microcontroller uploads its operating data to the cloud at preset intervals via the MQTT or HTTP protocol and wakes up intermittently in low-power mode.

5. The inverter wireless parallel control system as described in claim 1, characterized in that, When performing current synchronization, the digital signal processor calculates the voltage correction based on the virtual impedance parameter and adds the voltage correction to the current inverter voltage reference value to form a new voltage control command.

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