A 5kV superjunction silicon carbide VDMOS and its fabrication method

Abstract

This invention provides a 5kV superjunction silicon carbide VDMOS and its fabrication method. The method includes: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to obtain a drift layer; forming a barrier layer above the drift layer; etching the barrier layer to form vias; ion implantation to form a first isolation layer and a second isolation layer; ion implantation to form a shielding layer; depositing a first insulating dielectric region, a gate metal layer, a second insulating dielectric region, a low-resistivity region, a P-type well region, an N-type source region, a P-type source region, and a source metal layer; removing the barrier layer to complete the fabrication; and achieving both high gate reliability and low on-resistance through a combined planar gate and trench gate structure.

Description

Technical Field

[0001] This invention relates to a 5kV superjunction silicon carbide VDMOS and its fabrication method. Background Technology

[0002] Due to its wide bandgap characteristics, silicon carbide VDMOS devices naturally have higher voltage withstand capability compared to other silicon carbide VDMOS devices. However, due to limitations in oxide layer quality, the reliability of trench silicon carbide VDMOS devices has always been a problem. The on-resistance of planar gate silicon carbide VDMOS devices is larger than that of trench gate silicon carbide VDMOS devices. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a 5kV superjunction silicon carbide VDMOS and its fabrication method. Through the design of a combined structure of planar gate and trench gate, both high gate reliability and low on-resistance are achieved.

[0004] In a first aspect, the present invention provides a method for fabricating a 5kV superjunction silicon carbide VDMOS, comprising the following steps:

[0005] Step 1: Deposit metal on the lower side of a silicon carbide substrate to form a drain metal layer; grow an epitaxial layer on the upper side of the silicon carbide substrate to obtain a drift layer;

[0006] Step 2: Form a barrier layer above the drift layer, etch the barrier layer to form a via, and implant ions to form a first isolation layer and a second isolation layer;

[0007] Step 3: Ion implantation to form a shielding layer;

[0008] Step 4: Deposition to form the first insulating dielectric region;

[0009] Step 5: Deposit to form the gate metal layer;

[0010] Step 6: Deposit to form a second insulating dielectric region, the insulating dielectric layer including the first insulating dielectric region and the second insulating dielectric region;

[0011] Step 7: Deposition to form a low-resistivity region;

[0012] Step 8: Deposition to form a P-type well region;

[0013] Step 9: Deposition to form an N-type source region;

[0014] Step 10: Deposition to form a P-type source region;

[0015] Step 11: Deposit metal to form a source metal layer, remove the barrier layer, and complete the fabrication;

[0016] Before steps 3 to 7 and 9 to 11, the barrier layer from the previous step needs to be removed, a new barrier layer needs to be formed, and the barrier layer needs to be etched to form a via.

[0017] Secondly, the present invention provides a 5kV superjunction silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the preparation method of the 5kV superjunction silicon carbide VDMOS described in the first aspect.

[0018] The advantages of this invention are:

[0019] I. The gate structure of the present invention combines the high reliability of a planar gate with the low resistivity of a longitudinal conductive channel.

[0020] Second, the present invention constructs a first isolation layer to achieve isolation between and within the conductive channels of the cells, avoid current crosstalk within and between cells, avoid reverse isolation inside the device, and improve the reliability of the device.

[0021] Third, the second isolation layer and the superjunction structure of this invention share the same potential transfer, which ensures the superjunction structure of the device and can effectively improve the device's withstand voltage capability.

[0022] Fourth, the shielding layer of this invention isolates the gate and drain capacitances, effectively reduces Miller capacitance, reduces device drive losses, and improves device switching speed. Attached Figure Description

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] Figure 1 This is a schematic diagram of a 5kV superjunction silicon carbide VDMOS according to the present invention.

[0025] Figure 2 A cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to the present invention. Figure 1 .

[0026] Figure 3 A cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to the present invention. Figure 2 .

[0027] Figure 4 A cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to the present invention. Figure 3 .

[0028] Figure 5 A cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to the present invention. Figure 4 .

[0029] Figure 6 A cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to the present invention. Figure 5 .

[0030] Figure 7 A cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to the present invention. Figure 6 .

[0031] Figure 8 A cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to the present invention. Figure 7 .

[0032] Figure 9 A cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to the present invention. Figure 8 .

[0033] Figure 10 A cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to the present invention. Figure 9 .

[0034] Figure 11 A cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to the present invention. Figure 10 .

[0035] Figure 12 A cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to the present invention. Figure 10 one.

[0036] Figure 13 A cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to the present invention. Figure 10 two.

[0037] Figure 14 A cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to the present invention. Figure 10 three. Detailed Implementation

[0038] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0040] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0041] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0042] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0043] like Figures 1 to 14 As shown in the figure, this application provides a method for fabricating a 5kV superjunction silicon carbide VDMOS, which includes the following steps:

[0044] Step 1: Deposit metal on the lower side of silicon carbide substrate 101 to form drain metal layer 110; grow epitaxially on the upper side of silicon carbide substrate 101 to obtain drift layer 102;

[0045] Step 2: Form a barrier layer 200 above the drift layer 102, etch the barrier layer 200 to form a via, and implant ions to form a first isolation layer 1021 and a second isolation layer 1022; the drift layer 102, the first isolation layer 1021 and the second isolation layer 1022 in steps 1 and 2 can be formed in two steps, that is, a part is formed first and then the other part is formed.

[0046] Step 3: Ion implantation to form shielding layer 1023;

[0047] Step 4: Deposition to form the first insulating dielectric region 1072;

[0048] Step 5: Deposit to form the gate metal layer 108;

[0049] Step 6: Deposit to form a second insulating dielectric region 1073. The insulating dielectric layer 107 includes a first insulating dielectric region 1072 and a second insulating dielectric region 1073.

[0050] Step 7: Deposition to form low-resistivity region 103;

[0051] Step 8: Deposition to form P-type well region 104;

[0052] Step 9: Deposition to form N-type source region 106;

[0053] Step 10: Deposition to form P-type source region 105;

[0054] Step 11: Deposit metal to form source metal layer 109, remove barrier layer 200, and complete the preparation;

[0055] Before steps 3 to 7 and 9 to 11, the barrier layer 200 from the previous step needs to be removed, the barrier layer 200 needs to be re-formed, and the barrier layer 200 needs to be etched to form a via. The low-resistivity region 103, the P-type well region 104, the N-type source region 106, and the P-type source region 105 can also be formed by epitaxially forming an epitaxial layer on the drift layer 102, and then by ion implantation.

[0056] In this embodiment, preferably, the doping concentration of the shielding layer 1023 is greater than the doping concentration of the drift layer 102, and the doping concentration of the shielding layer 1023 is greater than the doping concentration of the second isolation layer 1022.

[0057] In this embodiment, preferably, the doping concentration of the low-resistivity region 103 is greater than the doping concentration of the first isolation layer 1021, and the doping concentration of the low-resistivity region 103 is greater than the doping concentration of the drift layer 102.

[0058] In this embodiment, preferably, the width of the shielding layer 1023 is greater than the width of the second isolation layer 1022.

[0059] In this embodiment, preferably, the width of the insulating dielectric layer 107 is equal to the width of the shielding layer 1023.

[0060] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0061] Silicon carbide substrate 101,

[0062] A drift layer 102 is provided, the lower side of which is connected to the upper side of the silicon carbide substrate 101. The drift layer 102 contains a first isolation layer 1021, a second isolation layer 1022, and a shielding layer 1023. The second isolation layer 1022 is located directly below the shielding layer 1023. The lower sides of both the first isolation layer 1021 and the second isolation layer 1022 are connected to the upper side of the silicon carbide substrate 101.

[0063] Low-resistivity region 103, the lower side of which is connected to the drift layer 102 and the first isolation layer 1021;

[0064] P-type well region 104, the lower side of which is connected to the low-resistivity region 103;

[0065] P-type source region 105, the lower side of which is connected to P-type well region 104;

[0066] N-type source region 106, the lower side of N-type source region 106 is connected to P-type well region 104, and the inner side of P-type source region 105 is connected to the outer side of N-type source region 106;

[0067] An insulating dielectric layer 107 is provided, the lower side of which is connected to a shielding layer 1023, and the outer side of which is connected to the inner side of the low-resistivity region 103, the inner side of the P-type well region 104, and the inner side of the N-type source region 106, respectively; a trench 1071 is provided in the insulating dielectric layer 107.

[0068] A gate metal layer 108 is disposed within the trench 1071;

[0069] Source metal layer 109, which is connected to the P-type source region 105 and the N-type source region 106 respectively;

[0070] And a drain metal layer 110, which is connected to the lower side of the silicon carbide substrate 101.

[0071] In another embodiment of the present invention, the silicon carbide substrate, the drift layer, and the low-resistivity region are all N-type; the first isolation layer, the second isolation layer, and the shielding layer are all P-type; the doping concentration of the N-type silicon carbide substrate 101 is 2-8e18cm. -3 The doping concentration of the N-type drift layer 102 is 1-5e17cm. -3 The doping concentration of the first isolation layer 1021 and the second isolation layer 1022 is 1-5e17cm. -3 The doping concentration of the P-type shielding layer 1023 is 1-5e18cm. -3 The doping concentration of the N-type low-resistivity region 103 is 6-10e17cm. -3 The doping concentration of the P-type well region 104 is 6-10e16cm. -3 The doping concentration of the N-type source region 106 is 2-8e18cm. -3 The doping concentration of the P-type source region 105 is 2-8e19cm. -3 The insulating dielectric layer 107 can be made of silicon dioxide, and the gate metal layer 108 and the source metal layer 109 can be made of one or more alloys of copper, nickel, and aluminum.

[0072] The doping concentration of the N-type silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 110, reducing the overall on-resistance of the device. The doping concentration of the N-type drift layer 102 is mainly to comprehensively consider the device's breakdown voltage and on-resistance. The doping concentration of the first isolation layer 1021 is to achieve isolation between and within device cells. Its doping concentration is a trade-off between the degree of isolation and improving the doping concentration and breakdown voltage of the device's drift region; the higher the doping concentration, the better. The second isolation layer 1022 forms a superjunction structure with the N-type drift layer 102. The doping concentration of the P-type shielding layer 1023 is to shield the capacitance from the device's gate to the drain and protect the device's gate structure. The doping concentration of the P-type well region 104 is to comprehensively ensure low gate charge, reduce device switching losses, and improve device switching speed.

[0073] The N-type silicon carbide substrate 101 of the device is 1 μm thick to ensure support during the device fabrication process. The N-type drift layer 102 is 50 μm thick, which is a trade-off between the doping concentration of the superjunction structure device and the on-resistance and epitaxial thickness.

[0074] The width of the P-type source region 105 of the device cell is 1μm and the thickness is 200nm. This is because the device adopts a deposition process, and the structural thickness is controllable. Therefore, the thickness is designed to be 200nm to reduce the thickness while ensuring the structural capability of the device, so as to reduce the parasitic diode loss of the device.

[0075] The width of the N-type source region 106 of the device cell is 1μm and the thickness is 200nm. This is because the device adopts a deposition process, and the structural thickness is controllable. Therefore, the thickness is designed to be 200nm to reduce the thickness while ensuring the structural capability of the device, so as to reduce the on-resistance of the device.

[0076] The width of the P-type well region 104 is 2μm and the thickness is 600nm. This is to ensure the drain-source voltage withstand capability during reverse breakdown and to ensure the gate control capability of the device.

[0077] The N-type low-resistivity region 103 has a width of 2μm and a thickness of 200nm. This is to form a low-resistivity conductive channel for the device, and this conductive channel will not affect the protection of the P-type well region for the device source when the device is reverse breakdown voltage.

[0078] The P-type shielding layer 1023 is distributed directly below the insulating dielectric layer 107 of the device. Its width is equal to that of the insulating dielectric layer 107. The shielding layer 1023 has a width of 2μm and a thickness of 300nm. This is the minimum thickness that can be controlled by ion implantation, which can ensure the protection of the device gate.

[0079] The thickness of the gate metal layer 108 is 1.1 μm. This is to ensure that the bottom of the gate metal layer 108 is lower than the bottom of the corresponding P-type well regions 104 on the left and right sides, thereby ensuring the gate control capability of the device and ensuring the low resistance of the conductive channel.

[0080] The bottom thickness of the insulating dielectric layer 107 of the device is 100nm, and the thickness on the left and right sides is 50nm. This is to ensure the gate control capability of the device. At the same time, the process conditions determine that when the thickness on the left and right sides is 50nm, the thickness of the bottom insulating dielectric layer is 100nm.

[0081] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a 5kV super junction silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS comprises: a silicon carbide substrate, a drift layer, the lower side of the drift layer being connected to the upper side of the silicon carbide substrate, the drift layer being provided with a first isolation layer, a second isolation layer and a shielding layer; the second isolation layer being located directly below the shielding layer, the lower sides of the first isolation layer and the second isolation layer being connected to the upper side of the silicon carbide substrate; a low-resistance region, the lower side of the low-resistance region being connected to the drift layer and the first isolation layer; a P-type well region, the lower side of the P-type well region being connected to the low-resistance region; a P-type source region, the lower side of the P-type source region being connected to the P-type well region; an N-type source region, the lower side of the N-type source region being connected to the P-type well region, the inner side of the P-type source region being connected to the outer side of the N-type source region; an insulating medium layer, the lower side of the insulating medium layer being connected to the shielding layer, the outer side of the insulating medium layer being connected to the inner side of the low-resistance region, the inner side of the P-type well region and the inner side of the N-type source region respectively; the insulating medium layer being provided with a groove; a gate metal layer, the gate metal layer being provided in the groove; a source metal layer, the source metal layer being connected to the P-type source region and the N-type source region respectively; and a drain metal layer, the drain metal layer being connected to the lower side of the silicon carbide substrate. The preparation method comprises the following steps: Step 1, depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to obtain a drift layer; Step 2, forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, ion implantation to form a first isolation layer and a second isolation layer; Step 3, ion implantation to form a shielding layer; Step 4, depositing to form a first insulating medium region; Step 5, depositing to form a gate metal layer; Step 6, depositing to form a second insulating medium region, the insulating medium layer comprising the first insulating medium region and the second insulating medium region; Step 7, depositing to form a low-resistance region; Step 8, depositing to form a P-type well region; Step 9, depositing to form an N-type source region; Step 10, depositing to form a P-type source region; Step 11, depositing metal to form a source metal layer, and removing the barrier layer to complete the preparation; Before each of steps 3 to 7, 9 to 11, the barrier layer of the previous step needs to be removed, and a new barrier layer is formed, and the barrier layer is etched to form a through hole.

2. The method of claim 1, wherein the 5kV super junction silicon carbide VDMOS is prepared by the steps of: The doping concentration of the shielding layer is greater than the doping concentration of the drift layer, and the doping concentration of the shielding layer is greater than the doping concentration of the second isolation layer. ​ 3. The method of claim 1, wherein the 5kV super junction silicon carbide VDMOS is prepared by the steps of: The doping concentration of the low-resistance region is greater than the doping concentration of the first isolation layer, and the doping concentration of the low-resistance region is greater than the doping concentration of the drift layer. ​ 4. The method of claim 1, wherein the 5kV super junction silicon carbide VDMOS is prepared by the steps of: The width of the shielding layer is greater than the width of the second isolation layer. ​ 5. The method of claim 1, wherein the 5kV super junction silicon carbide VDMOS is prepared by the steps of: The width of the insulating medium layer is equal to the width of the shielding layer. ​ 6. A 5 kV super junction silicon carbide VDMOS, characterized in that, The silicon carbide VDMOS is prepared by the preparation method of any one of claims 1 to 5.

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