High electron mobility transistors and methods of making the same

Abstract

Embodiments of the present application relate to a high electron mobility transistor and a preparation method thereof, wherein the high electron mobility transistor comprises: a substrate; a plurality of heterojunction layers stacked in sequence on the substrate, each heterojunction layer comprising a channel layer and a barrier layer formed by epitaxial growth on the channel layer, and a two-dimensional electron gas being able to be induced in at least a part of the channel layer close to the barrier layer; and a gate trench extending from a surface of a topmost heterojunction layer in a direction towards the substrate, and penetrating at least one heterojunction layer, and the bottom wall of the gate trench further comprising at least one heterojunction layer which is not penetrated. Thus, the relationship between the performance / reliability of the device and the number of stacked layers is well balanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a high electron mobility transistor and a preparation method thereof. BACKGROUND

[0002] A high electron mobility transistor (HEMT) is a field effect transistor based on the high mobility characteristics of a two-dimensional electron gas (2DEG) in a heterojunction, which has high electron mobility at low temperature and low electric field, and can realize high speed and low noise operation. A multi-channel structure HEMT device internally manufactures multiple parallel conductive channels by cyclically growing channel layers and barrier layers on a substrate, which is equivalent to connecting multiple field effect transistors in parallel, and can simultaneously conduct more current, thereby having the advantage of significantly reducing on-resistance.

[0003] However, if the channel layer and the barrier layer are respectively a GaN layer and an AlGaN layer, in order to form sufficient 2DEG density at the GaN / AlGaN interface, a relatively thick GaN / AlGaN single layer film thickness is required. When the total film thickness is too thick, the etching difficulty of the gate trench increases, which is not conducive to fine etching of the channel layer and the barrier layer, and ultimately will affect the device performance and reliability. At the same time, due to the increase in the number of stacked layers, the film layer growth quality of each channel layer and each barrier layer cyclically grown also seriously restricts the performance of the device. Therefore, how to balance the performance / reliability of the multi-channel structure HEMT device and the number of stacked layers has become a technical problem to be solved in the field. SUMMARY

[0004] Therefore, the embodiments of the present application provide a high electron mobility transistor and a preparation method thereof to solve at least one problem in the background art.

[0005] In a first aspect, the embodiments of the present application provide a high electron mobility transistor, comprising:

[0006] a substrate;

[0007] a plurality of heterojunction stacks stacked in sequence on the substrate, each of the heterojunction stacks comprising a channel layer and a barrier layer formed by epitaxial growth on the channel layer, and a two-dimensional electron gas being induced in at least a portion of the channel layer close to the barrier layer;

[0008] a gate trench extending from the surface of the topmost heterojunction stack to the substrate, at least penetrating one heterojunction stack, and the bottom wall of the gate trench further comprising at least one unpenetrated heterojunction stack.

[0009] In an optional implementation of the first aspect of the present application, the number of the heterojunction stacks is greater than or equal to 3; and the bottom wall of the gate trench further comprises a heterojunction stack which is not penetrated by the gate trench.

[0010] In an optional implementation of the first aspect of the present application, the barrier layer in the at least one heterojunction stack is a B x Al 1-x N layer, 0 < x < 1.

[0011] In an optional implementation of the first aspect of the present application, the barrier layer in the at least one heterojunction stack is a B x Al 1-x N layer and the channel layer is an Al y Ga 1-y N layer, where y = 1 - kx, 6 ≤ k ≤ 8.5, 0 < kx < 1.

[0012] In an optional implementation of the first aspect of the present application, the barrier layer in the at least one heterojunction stack is a B x Al 1-x N layer and the channel layer is a B z Ga 1-z N layer, where z = mx - n, 1.13 ≤ m ≤ 1.2, 0.13 ≤ n ≤ 0.2, 0 < z < 1.

[0013] In a second aspect, the embodiments of the present application provide a method for manufacturing a high electron mobility transistor, and the method comprises:

[0014] providing a substrate;

[0015] forming a plurality of heterojunction stacks which are sequentially stacked on the substrate, each of the heterojunction stacks comprising a channel layer and a barrier layer which is epitaxially grown on the channel layer, and the channel layer is capable of inducing a two-dimensional electron gas in at least a portion of the region close to the barrier layer;

[0016] forming a gate trench which extends from the surface of the topmost heterojunction stack to the substrate, the gate trench penetrating at least one of the heterojunction stacks, and the bottom wall of the gate trench further comprises at least one heterojunction stack which is not penetrated.

[0017] In an optional implementation of the second aspect of the present application, the number of the heterojunction stacks is greater than or equal to 3; and the bottom wall of the gate trench further comprises a heterojunction stack which is not penetrated by the gate trench.

[0018] In an optional implementation of the second aspect of the present application, the barrier layer in the at least one heterojunction stack is a B x Al 1-x N layer, 0 < x < 1.

[0019] In an optional embodiment in combination with the second aspect of the present application, the barrier layer in the at least one heterojunction stack is B x Al 1-x N layer and the channel layer is Al y Ga 1-y N layer, wherein y = 1 - kx, 6 ≤ k ≤ 8.5, 0 < kx ≤ 1.

[0020] In an optional embodiment in combination with the second aspect of the present application, the barrier layer in the at least one heterojunction stack is B x Al 1-x N layer and the channel layer is B z Ga 1-z N layer, wherein z = mx - n, 1.13 ≤ m ≤ 1.2, 0.13 ≤ n ≤ 0.2, 0 < z < 1.

[0021] The high electron mobility transistor and the preparation method thereof provided by the embodiments of the present application, the high electron mobility transistor includes a plurality of heterojunction stacks, at least part of the channel layer in each heterojunction stack can induce a two-dimensional electron gas in the region close to the barrier layer, thereby forming a multi-channel structure; a gate trench extends from the surface of the topmost heterojunction stack to the direction of the substrate, at least penetrates one heterojunction stack, and the bottom wall of the gate trench further includes at least one heterojunction stack which is not penetrated, thereby reducing the etching depth of the gate trench, reducing the etching difficulty, and being conducive to accurately controlling the etching depth and morphology in the case of the same number of stacked heterojunction stacks; or, in the case of the same etching depth, it is conducive to stacking a larger number of heterojunction stacks; in addition, the bottom wall of the gate trench further includes at least one heterojunction stack which is not penetrated, thereby the unpenetrated part can still induce a two-dimensional electron gas, reducing the loss of the two-dimensional electron gas; finally, the relationship between the performance / reliability of the device and the number of stacked layers is well balanced.

[0022] Additional aspects and advantages of the present application will be given in part in the following description, become apparent from the following description, or be understood by practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0023] The drawings described herein are used to provide further understanding of the present application, constitute a part of the present application, the illustrative embodiments of the present application and the description thereof are used to explain the present application, and do not constitute improper limitation on the present application. In the drawings:

[0024] Figure 1 The planar structure schematic diagram of the high electron mobility transistor provided by the embodiments of the present application;

[0025] Figure 2A cross-sectional structure schematic diagram of a high electron mobility transistor provided by an embodiment of the present application;

[0026] Figure 3 A flowchart of a preparation method of a high electron mobility transistor provided by an embodiment of the present application;

[0027] Figures 4 to 13 A cross-sectional structure schematic diagram of a high electron mobility transistor in a preparation process provided by an embodiment of the present application.

[0028] Legend of reference signs:

[0029] 100, substrate; 110, nucleation layer; 120, buffer layer; 130, heterojunction stack; 131, channel layer; 132, barrier layer; 1530, gate trench; 141, passivation layer; 1510, source trench; 1520, drain trench; 151, source; 152, drain; 153, gate. DETAILED DESCRIPTION

[0030] Exemplary embodiments of the present application will be described in detail with reference to the drawings. Although specific embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0031] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail in order to avoid obscuring aspects of the present application.

[0032] In the drawings, the size of layers, regions, elements and the relative sizes among them can be exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0033] When an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. While the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are simply used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application, and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0034] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0035] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] For a thorough understanding of the present application, reference should be made to the following detailed description together with the accompanying drawings wherein: There are shown and will be described specific embodiments of the present application. It will be apparent, however, that the application can be practiced in other ways than those specifically set forth herein without departing from the scope and spirit of the present application.

[0037] Please refer to Figure 1 and Figure 2 ,in, Figure 1 This is a schematic diagram of the planar structure of a high electron mobility transistor provided in an embodiment of this application. Figure 2 This is a schematic cross-sectional view of a high electron mobility transistor provided in an embodiment of this application. Figure 2 (a) is along Figure 1 Schematic diagram of the cross-sectional structure of line AA in the middle. Figure 2 (b) is along Figure 1 A cross-sectional view of the BB line is shown in the figure. As shown, the high electron mobility transistor provided in this application embodiment includes: a substrate 100; a plurality of heterojunction stacks 130 sequentially stacked on the substrate 100, each heterojunction stack 130 including a channel layer 131 and a barrier layer 132 epitaxially grown on the channel layer 131, wherein at least a portion of the channel layer 131 near the barrier layer 132 is capable of inducing a two-dimensional electron gas; a gate trench 1530 extending from the surface of the top heterojunction stack 130 toward the substrate 100, penetrating at least one heterojunction stack 130, and the bottom wall of the gate trench 1530 also includes at least one heterojunction stack 130 that is not penetrated.

[0038] Understandably, the high electron mobility transistor provided in this application embodiment includes multiple heterojunction stacks 130. At least a portion of the channel layer 131 in each heterojunction stack 130 near the barrier layer 132 can induce a two-dimensional electron gas, thereby forming a multi-channel structure. Unlike conventional multi-channel HEMT devices, in this application embodiment, the gate trench 1530 does not penetrate all heterojunction stacks 130, but retains at least one unpenetrated heterojunction stack 130 below its bottom wall, thus creating a multi-channel structure within the stacked heterojunction stacks. With the same number of 130 layers, the etching depth of the gate trench 1530 is reduced, which reduces the etching difficulty and facilitates precise control of etching depth and morphology; or, with the etching depth unchanged, it is beneficial to stack more heterojunction layers 130; moreover, the bottom wall of the gate trench 1530 also includes at least one heterojunction layer 130 that is not penetrated, so that the unpenetrated part can still induce two-dimensional electron gas, reducing the loss of two-dimensional electron gas; ultimately, it achieves a good balance between the device performance / reliability and the number of stacked layers.

[0039] Based on this, the embodiments of this application also provide a method for fabricating a high electron mobility transistor, please refer to... Figure 3 The method includes:

[0040] Step S01, providing a substrate;

[0041] Step S02, forming a plurality of heterojunction stacks which are sequentially stacked on the substrate, each of the heterojunction stacks comprising a channel layer and a barrier layer formed by epitaxial growth on the channel layer, at least part of the channel layer being capable of inducing a two-dimensional electron gas in a region close to the barrier layer;

[0042] Step S03, forming a gate trench extending from the surface of the topmost heterojunction stack in the direction towards the substrate, the gate trench penetrating at least one of the heterojunction stacks, and the bottom wall of the gate trench further comprising at least one of the heterojunction stacks which is not penetrated.

[0043] In the following, the high electron mobility transistor and the method for manufacturing the same according to the embodiments of the present application will be described in detail. Figures 4 to 13 The high electron mobility transistor and the method for manufacturing the same according to the embodiments of the present application will be described in detail.

[0044] First, refer to Figure 4 , a substrate 100 is provided.

[0045] In the embodiments of the present application, the term "substrate" refers to a carrier on which subsequent material layers are added. The stacking direction of the subsequent material layers is the thickness direction of the substrate, or the height direction of the device, and the third direction and the opposite direction thereof in the figure are the thickness direction of the substrate. The substrate 100 comprises two surfaces opposite to each other in the thickness direction. According to the formation position of the device, the two surfaces can also be referred to as the top surface and the bottom surface, or the upper surface and the lower surface, respectively. The top surface of the substrate 100 is usually the side on which the device is formed, so the high electron mobility transistor is formed on the top side of the substrate 100, unless otherwise specified. According to the upper surface and the lower surface of the substrate 100, or strictly speaking, according to the central plane of the substrate 100 in the thickness direction, the substrate plane can be determined; the direction parallel to the substrate plane is the direction along the substrate plane. Refer to Figure 1 and Figure 4 , two first and second directions intersecting with each other are defined in the substrate plane direction; the first and second directions are, for example, two directions perpendicular to each other.

[0046] The substrate 100 is specifically a growth substrate, and each of the heterojunction stacks 130 is an epitaxial layer formed on the growth substrate by an epitaxial growth process.

[0047] The material of the substrate 100 can be any suitable material known to those skilled in the art, such as a silicon (Si) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, an aluminum nitride (AlN) substrate, and a series of semiconductor material substrates.

[0048] In actual manufacture, before performing the epitaxial growth process, a step of cleaning the surface of the substrate 100 can also be included, for example, cleaning with HF.

[0049] Next, refer to Figure 5 andFigure 6 In order to make the heterojunction stack 130 have better crystal quality, a step of forming a nucleation layer 110 and a buffer layer 120 can also be included before epitaxially growing the channel layer 131; the nucleation layer 110 is located between the substrate 100 and the buffer layer 120. In addition, other epitaxial layers can also be included on the substrate 100, which are not limited in the present application.

[0050] Next, a plurality of heterojunction stacks 130 are formed on the substrate 100 in sequence. Understandably, each heterojunction stack 130 is formed on the upper surface of the substrate 100 by an epitaxial growth process, for example, on the buffer layer 120. The plurality of heterojunction stacks 130 are sequentially stacked along the third direction (the thickness direction of the substrate).

[0051] Wherein, "plurality" refers to two or more. As an optional embodiment, the number of heterojunction stacks 130 is greater than or equal to 3. Further optionally, the number of heterojunction stacks 130 is, for example, 4, 5, 6, 8, 10, etc., which are not limited in the present application.

[0052] Each heterojunction stack 130 includes a channel layer 131 and a barrier layer 132. Forming a plurality of heterojunction stacks 130 on the substrate 100 in sequence is equivalent to alternately stacking channel layers 131 and barrier layers 132 on the substrate 100, and each channel layer 131 and the barrier layer 132 located on the side away from the substrate 100 form a heterojunction stack 130.

[0053] In order to form a plurality of heterojunction stacks 130, first refer to Figure 7 The channel layer 131 is grown.

[0054] The material of the channel layer 131 can be an N-group alloy material, including but not limited to GaN, AlGaN, BGaN, etc. Further, the channel layer 131 can be a non-doped material layer (for example, a non-doped GaN layer), so that at least the part of the channel layer 131 below the two-dimensional electron gas presents a high resistance value.

[0055] Optionally, the thickness of the channel layer 131 is in the range of 3nm~50nm. Further optionally, the thickness of the channel layer 131 is in the range of 3nm~10nm.

[0056] Next, refer to Figure 8 The barrier layer 132 is grown.

[0057] The material of the barrier layer 132 includes any material that can form a two-dimensional electron gas channel with the channel layer 131. Specifically, the material of the barrier layer 132 can be an Al-containing group-N alloy material. Further, the material of the barrier layer 132 can be an undoped material (e.g., an undoped AlGaN layer); or, the barrier layer 132 can also be an N-type doped material layer (e.g., an N-type doped AlGaN layer), so as to facilitate inducing a higher density of two-dimensional electron gas.

[0058] To solve the balance between the increase of the number of stacked layers and the increase of the difficulty of the gate trench etching, the present application further proposes an improved scheme of reducing the film thickness of the single heterojunction stack 130. Specifically, the barrier layer in at least one heterojunction stack is a B x Al 1-x N layer, 0 < x < 1.

[0059] In this way, by growing a BAlN layer, on the one hand, the energy band at the bottom of the channel is improved, thereby strengthening the confinement characteristics of the channel to electrons; on the other hand, the spontaneous polarization of the BAlN material is strong, and compared with the commonly used AlGaN barrier layer, the BAlN barrier layer can obtain a higher electron density under the same thickness, in other words, under the same electron density, the BAlN barrier layer can be designed to grow a thinner film thickness. In addition, compared with InAlN material, BAlN is not prone to agglomeration at high temperature, so that the high temperature condition used in the further upward growth of the heterojunction stack 130 will not cause the quality of the barrier layer 132 in the heterojunction stack 130 formed to deteriorate. It can be seen that the material of the barrier layer is BAlN, which can be suitable for a multi-channel structure HEMT device.

[0060] Optionally, the thickness of the barrier layer 132 is in the range of 1 nm to 30 nm. Further optionally, the thickness of the barrier layer 132 is in the range of 2 nm to 8 nm. Compared with the conventional AlGaN barrier layer, the thickness is greatly reduced under the same electron density.

[0061] After the inventors proposed to use BAlN material as the barrier layer material in the multi-channel structure HEMT device, in order to improve the device performance, the inventors further explored how to epitaxially grow a high-quality BAlN barrier layer on the channel layer.

[0062] As an optional specific embodiment, the barrier layer 132 in at least one heterojunction stack 130 is a B x Al 1- x N layer and the channel layer 131 is an Al y Ga 1-y N layer, wherein y = 1-kx, 6 ≤ k ≤ 8.5, 0 < kx ≤ 1.

[0063] It is found that when k = 9, although B x Al 1-x N and Al y Ga 1-y N, the calculated lattice constant of B x Al 1-x N barrier layer is still poor; while after k≤8.5, the lattice quality of B x Al 1-x N barrier layer is even better.

[0064] In the art, the lattice constant of B x Al 1-x N and Al y Ga 1-y N needs to be calculated respectively using the lattice constant of each binary component. Specifically, a(B x Al 1-x N) = x*a(BN) + (1-x)*a(AlN), a(Al y Ga 1-y N) = y*a(AlN) + (1-y)*a(GaN). When the lattice constant of B x Al 1-x N is equal to that of Al y Ga 1-y N, the lattice of B x Al 1-x N layer is matched with that of Al y Ga 1-y N layer, the stress between the two layers is minimal, and the epitaxial quality is best. k = 9 is calculated by x*a(BN) + (1-x)*a(AlN) = y*a(AlN) + (1-y)*a(GaN). However, the inventors found that for high electron mobility transistors, the spontaneous polarization of two-dimensional electron gas should be along the up and down direction of the c-axis, thereby generating a two-dimensional electron gas channel along the horizontal direction, rather than along the a-axis direction. Therefore, the inventors proposed that the component relationship should be determined by the lattice constant in the c-axis direction. Specifically, c(B x Al 1-x N) = x*c(BN) + (1-x)*c(AlN), c(Al y Ga 1-y N) = y*c(AlN) + (1-y)*c(GaN); let c(B x Al 1-x N) = c(Al y Ga 1-yN), so as to obtain the relationship between x and y through the lattice constant of the c-axis direction of each binary component. Considering that the test result of the lattice constant of the c-axis direction of BN has a certain range, i.e., the known c(BN) has a certain range, according to the calculation result, the value range of k is determined as 6≤k≤8.5, and in the value range, B x Al 1-x The lattice quality of the N barrier layer is obviously improved.

[0065] Further, 6.200≤k≤8.2821. Still further, k≈8.2821 or k≈6.200, at this time, the barrier layer 132 and the underlying channel layer 131 have a stress-free phenomenon, thereby avoiding the problem that the 2DEG suffers from interface scattering to make the mobility decrease; and through the optimization design of the B component, the thickness of the channel layer 131 can also be made thinner under the stress-free condition, so that the total thickness of the stack and the channel density of the device can be considered, and the device performance is further improved.

[0066] Exemplarily, the channel layer 131 is a GaN layer, i.e., y=0; the barrier layer 132 is a BAlN layer, wherein the B component is between 11.76% and 16.67%; further, the B component is between 12.07% and 16.13%.

[0067] As another alternative embodiment, the barrier layer 132 in the at least one heterojunction stack 130 is a B x Al 1-x N layer and the channel layer 131 is a B z Ga 1-z N layer, wherein z=mx-n, 1.13≤m≤1.2, 0.13≤n≤0.2, and 0

[0068] Specifically, c(B x Al 1-x N) = x*c(BN) + (1-x)*c(AlN), c(B z Ga 1-z N) = z*c(BN) + (1-z)*c(GaN); let c(B x Al 1-x N) = c(B z Ga 1-z N), so as to obtain the relationship between x and z through the lattice constant of the c-axis direction of each binary component. Similarly, considering that the test result of the lattice constant of the c-axis direction of BN has a certain range, i.e., the known c(BN) has a certain range, according to the calculation result, the value range of m and n is determined as 1.13≤m≤1.2 and 0.13≤n≤0.2, respectively, and in the value range, B x Al1-x The lattice quality of the N barrier layer is obviously improved.

[0069] Further, 1.13≤m≤1.14, 0.13≤n≤0.14; or 1.19≤m≤1.2, 0.19≤n≤0.2. Still further, m≈1.1375 and n≈0.1374 or m≈1.1926 and n≈0.1926, which makes the barrier layer 132 and the underlying channel layer 131 have a stress-free phenomenon, thereby avoiding the problem of interface scattering suffered by the 2DEG so as to make the mobility decrease; and through the optimization design of the B component, the thickness of the channel layer 131 can also be made thinner under the stress-free condition, so that the total thickness of the stack and the channel density of the device can be considered, thereby improving the device performance.

[0070] After the growth of the bottommost heterojunction stack 130, next, please refer to Figure 9 , multiple channel layers 131 and barrier layers 132 are grown, thereby forming multiple heterojunction stacks 130 stacked in sequence.

[0071] Among them, the bottommost heterojunction stack 130 refers to the heterojunction stack 130 closest to the substrate 100 in the multiple heterojunction stacks 130; correspondingly, the topmost heterojunction stack 130 refers to the heterojunction stack 130 farthest from the substrate 100 in the multiple heterojunction stacks 130.

[0072] In some embodiments, the materials of each channel layer 131 in the multiple heterojunction stacks 130 correspond to the same, and the materials of each barrier layer 132 correspond to the same. In other embodiments, a part of the barrier layers 132 in a part of the multiple heterojunction stacks 130 are B x Al 1-x N layers and the channel layers 131 are Al y Ga 1-y N layers, wherein y=1-kx, 6≤k≤8.5, 0 x Al 1-x N layers and the channel layers 131 are B z Ga 1-z N layers, wherein z=mx-n, 1.13≤m≤1.2, 0.13≤n≤0.2, 0

[0073] In some embodiments, the thicknesses of each channel layer 131 in the multiple heterojunction stacks 130 correspond to the same, and the thicknesses of each barrier layer 132 correspond to the same. In other embodiments, the thicknesses of each channel layer 131 in the multiple heterojunction stacks 130 can also be different, and the thicknesses of each barrier layer 132 can also be different.

[0074] Next, please refer toFigure 10 The gate trench 1530 is formed to extend from the surface of the topmost heterojunction stack 130 to the substrate 100.

[0075] It should be noted that, Figures 10 to 13 In the drawings, the left part (a) corresponds to the cross-sectional structure along the AA line in Figure 1 In the drawings, the left part (a) corresponds to the cross-sectional structure along the AA line in Figure 1 In the drawings, the left part (a) corresponds to the cross-sectional structure along the AA line in

[0076] In actual production, the heterojunction stack 130 is etched from the side where the topmost heterojunction stack 130 is located. The etching does not penetrate through the entire heterojunction stack 130, but stops on at least one heterojunction stack 130, so that the etching depth is less than the total thickness of the entire heterojunction stack 130, which reduces the difficulty of etching and is conducive to accurately controlling the etching depth and morphology; or, in the case of a constant etching depth, it is conducive to stacking a larger number of heterojunction stacks 130.

[0077] By forming the gate trench 1530, the gate in the embodiment of the present application can apply an electric field to the channel from multiple directions, has extremely strong control ability, and can more thoroughly deplete the electrons in the channel. Specifically, please refer to Figure 2 In the drawings, the left part (a) corresponds to the cross-sectional structure along the AA line in

[0078] Furthermore, the bottom wall of the gate trench 1530 further includes at least one unpenetrated heterojunction stack 130, so that the unpenetrated part can still induce a two-dimensional electron gas, reducing the loss of the two-dimensional electron gas, and the part of the gate 153 located in the gate trench 1530 can also apply a vertical electric field to the top of the unpenetrated heterojunction stack 130, thereby further increasing the on-current.

[0079] It should be understood that the unpenetrated heterojunction stack 130 at least includes the bottommost heterojunction stack 130, and in addition, can include the second bottommost heterojunction stack 130, or a plurality of heterojunction stacks 130 from the bottommost heterojunction stack 130. Whether the penetrated heterojunction stack 130 or the unpenetrated heterojunction stack 130 located below the bottom wall of the gate trench 1530, both are heterojunction stacks that act as channels.

[0080] As an optional implementation, the number of the heterojunction stacks 130 is greater than or equal to 3; the bottom wall of the gate trench 1530 further comprises a heterojunction stack 130 which is not penetrated by the gate trench 1530. In this way, only the bottommost heterojunction stack 130 is not penetrated by the gate trench 1530, and the gate 153 applies control to the bottommost heterojunction stack 130 from the side of the top surface of the bottommost heterojunction stack 130.

[0081] Optionally, the number of the gate trenches 1530 is a plurality. Further, the plurality of gate trenches 1530 are arranged in parallel and spaced apart.

[0082] Next, please refer to Figure 11 , and grow the passivation layer 141.

[0083] As shown, the passivation layer 141 covers at least the side wall and the bottom wall of the gate trench 1530; in addition, the passivation layer 141 also covers the top surface of the heterojunction stack 130 between the plurality of gate trenches 1530.

[0084] Next, please refer to Figure 12 and Figure 13 , form the source 151 and the drain 152.

[0085] Please further refer to Figure 1 , the source 151 and the drain 152 are respectively located on the two sides of the gate 153. Specifically, the plurality of gate trenches 1530 extend in parallel to the first direction and are arranged in the second direction; the source 151 and the drain 152 are respectively located on the two sides of the gate 153 along the first direction and are arranged in the second direction. In actual application, the distance between the source 151 and the gate 153 is less than the distance between the drain 152 and the gate 153.

[0086] Further, the source 151 and the drain 152 are respectively located in the source trench 1510 and the drain trench 1520. Specifically, please refer to Figure 12 , form the source trench 1510 and the drain trench 1520 extending from the surface of the topmost heterojunction stack 130 to the substrate 100; next, please refer to Figure 13 , form the source 151 and the drain 152 in the source trench 1510 and the drain trench 1520 respectively.

[0087] One or more of the source trench 1510, the drain trench 1520, and the gate trench 1530 can be formed by photolithography and etching process. Specifically, a patterned mask layer (not shown in the figure) can be formed on the side where the topmost heterojunction stack 130 is located; the patterned mask layer can be formed by steps in the photolithography process such as coating, exposure, and development; then, the heterojunction stack 130 is etched using the patterned mask layer to form the trenches.

[0088] Please continue to refer to Figure 1 The number of source trenches 1510 and drain trenches 1520 is also multiple, respectively. Further, the multiple source trenches 1510 are arranged in parallel and at intervals; the multiple drain trenches 1520 are arranged in parallel and at intervals. Still further, the multiple source trenches 1510, the multiple drain trenches 1520 and the multiple gate trenches 1530 are formed in one-to-one correspondence.

[0089] As an optional embodiment, at least one of the source trenches 1510 and the drain trenches 1520 penetrates at least one heterojunction stack 130, and the bottom wall of the source trench 1510 and / or the drain trench 1520 further comprises at least one heterojunction stack 130 which is not penetrated. Further, both the source trenches 1510 and the drain trenches 1520 penetrate at least one heterojunction stack 130, and the bottom wall of the source trench 1510 and the drain trench 1520 further comprises at least one heterojunction stack 130 which is not penetrated. Still further, the number of the heterojunction stacks 130 penetrated by the source trenches 1510 and the drain trenches 1520 is the same as the number of the heterojunction stacks 130 penetrated by the gate trenches 1530.

[0090] Next, please refer to Figure 13 The source 151 is formed in the source trench 1510 and the drain 152 is formed in the drain trench 1520.

[0091] In actual preparation, the source 151 and the drain 152 are formed by filling metal material into the source trench 1510 and the drain trench 1520, respectively. The source 151 and the drain 152 are not only located in the source trench 1510 and the drain trench 1520, respectively, but also can be partially located on the topmost heterojunction stack 130. After filling the metal material, steps of patterning, etching and annealing can be further included.

[0092] Finally, please refer to Figure 2 The gate 153 is formed.

[0093] In actual preparation, the gate 153 is formed by depositing gate material in the gate trench 1530 and on the topmost heterojunction stack 130 between the gate trenches 1530. The material of the gate 153 can be metal (such as Ti, W, etc.); or p-type nitride (such as p-GaN) or p-type oxide (such as p-NiO), etc. The present application does not make specific limitation thereon. After depositing the gate material, steps of patterning, etching and annealing can be further included.

[0094] It should be noted that the high electron mobility transistor embodiments and the high electron mobility transistor manufacturing method embodiments provided in the present application belong to the same concept; in the technical solutions recorded in each embodiment, the technical features are combinable in any manner without conflict.

[0095] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes can also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, various technical features of the above embodiments can also be combined in any manner to form additional embodiments of the present application that can not have been explicitly described. Therefore, the above embodiments only express several implementations of the present application, and do not limit the protection scope of the patent of the present application.

Claims

1. A high electron mobility transistor, characterized by, The method comprises: providing a substrate; forming a plurality of heterojunction layers on the substrate in sequence, each of the heterojunction layers comprising a channel layer and a barrier layer formed by epitaxial growth on the channel layer, a two-dimensional electron gas being able to be induced in a region of the channel layer close to the barrier layer; forming a gate trench extending from a surface of a topmost heterojunction layer in a direction towards the substrate, the gate trench penetrating at least one of the heterojunction layers, and at least one unpenetrated heterojunction layer being further included below a bottom wall of the gate trench; The barrier layer in the at least one heterojunction stack is B x Al 1-x The N layer and the channel layer are Al y Ga 1-y N layer, wherein y = 1 - kx, 6 ≤ k ≤ 8.5, 0 < kx ≤ 1.

2. The high electron mobility transistor of claim 1, wherein, the number of the heterojunction layers is greater than or equal to 3; and the gate trench further includes one unpenetrated heterojunction layer below the bottom wall of the gate trench.

3. A high electron mobility transistor, characterized by, The method comprises: providing a substrate; forming a plurality of heterojunction layers on the substrate in sequence, each of the heterojunction layers comprising a channel layer and a barrier layer formed by epitaxial growth on the channel layer, a two-dimensional electron gas being able to be induced in a region of the channel layer close to the barrier layer; forming a gate trench extending from a surface of a topmost heterojunction layer in a direction towards the substrate, the gate trench penetrating at least one of the heterojunction layers, and at least one unpenetrated heterojunction layer being further included below a bottom wall of the gate trench; The barrier layer in the at least one heterojunction stack is B x Al 1-x The N layer and the channel layer are B z Ga 1-z N layer, wherein z = mx - n, 1.13 ≤ m ≤ 1.2, 0.13 ≤ n ≤ 0.2, 0 < z < 1.

4. The high electron mobility transistor of claim 3, wherein, the number of the heterojunction layers is greater than or equal to 3; and the gate trench further includes one unpenetrated heterojunction layer below the bottom wall of the gate trench.

5. A method of fabricating a high electron mobility transistor, characterized by, The method comprises: providing a substrate; forming a plurality of heterojunction layers on the substrate in sequence, each of the heterojunction layers comprising a channel layer and a barrier layer formed by epitaxial growth on the channel layer, a two-dimensional electron gas being able to be induced in a region of the channel layer close to the barrier layer; forming a gate trench extending from a surface of a topmost heterojunction layer in a direction towards the substrate, the gate trench penetrating at least one of the heterojunction layers, and at least one unpenetrated heterojunction layer being further included below a bottom wall of the gate trench; In the at least one heterojunction stack, the barrier layer is B x Al 1-x In the at least one heterojunction stack, the barrier layer is B y Ga 1-y In the at least one heterojunction stack, the barrier layer is B 6. The method of fabricating a high electron mobility transistor according to claim 5, wherein the number of the heterojunction layers is greater than or equal to 3; and the gate trench further includes one unpenetrated heterojunction layer below the bottom wall of the gate trench.

7. A method of fabricating a high electron mobility transistor, characterized by, The method comprises: providing a substrate; forming a plurality of heterojunction layers on the substrate in sequence, each of the heterojunction layers comprising a channel layer and a barrier layer formed by epitaxial growth on the channel layer, a two-dimensional electron gas being able to be induced in a region of the channel layer close to the barrier layer; forming a gate trench extending from a surface of a topmost heterojunction layer in a direction towards the substrate, the gate trench penetrating at least one of the heterojunction layers, and at least one unpenetrated heterojunction layer being further included below a bottom wall of the gate trench; The barrier layer in the at least one heterojunction stack is B x Al 1-x The N layer and the channel layer are B z Ga 1-z N layer, wherein z = mx - n, 1.13 ≤ m ≤ 1.2, 0.13 ≤ n ≤ 0.2, 0 < z < 1.

8. The method of fabricating a high electron mobility transistor according to claim 7, wherein the number of the heterojunction layers is greater than or equal to 3; and the gate trench further includes one unpenetrated heterojunction layer below the bottom wall of the gate trench.

Images