Annealing temperature control method based on differentiated ohmic contact material

Abstract

The application discloses an annealing temperature control method based on differential ohmic contact materials. In view of the problems of inaccurate annealing temperature monitoring, uneven temperature field detection difficulty and abnormal response lag of the N face Au / Ge ohmic contact layer of an existing AlGaInP-based red light Micro-LED, the method is prepared through seven processes (twice patterning, twice metal plating, twice adhesive removal, annealing and observation), and an Au / Ge first ohmic contact layer (functional) and an Au / Ge / Ni second ohmic contact layer (detection) are prepared on the N face of a wafer. By utilizing the characteristic of Ni in inhibiting Au / Ge agglomeration, the temperature is judged by observing the agglomeration state difference of the two layers through an optical microscope (the former agglomerates and the latter does not agglomerate under normal circumstances). The method is convenient for detection, supports batch detection, can find temperature abnormalities in real time, improves process stability, and is suitable for industrial mass production.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of Micro-LED chip preparation, in particular to an N-face ohmic contact preparation process of AlGaInP-based red Micro-LED, especially to an annealing temperature control method based on differential ohmic contact materials, which is suitable for the industrialized production of AlGaInP-based red Micro-LED. BACKGROUND

[0002] In the preparation process of AlGaInP-based red Micro-LED, the N-pole (negative pole) surface material is usually gallium arsenide (GaAs); due to the poor interface contact characteristics of GaAs and conventional transparent electrode materials such as indium tin oxide (ITO), it is difficult to directly form a low-resistance ohmic contact, and the industry generally uses gold-germanium (Au / Ge) alloy as the N-face ohmic contact material, and through a high-temperature annealing process to promote the interface reaction between Au / Ge and the GaAs surface, and finally form an ohmic contact structure that meets the performance requirements of the device.

[0003] However, the existing annealing temperature control scheme of the Au / Ge ohmic contact layer has significant technical defects, resulting in poor process stability and large product yield fluctuations. The specific problems are as follows:

[0004] 1. Temperature detection deviation problem: The temperature control probe of the annealing machine is usually installed inside the machine cavity, not directly contacting the wafer surface, so there is an unavoidable deviation (deviation range up to ±10-20℃) between the "cavity temperature" displayed by the machine and the "actual process temperature" of the wafer surface, which cannot truly reflect the reaction temperature of Au / Ge and GaAs;

[0005] 2. Temperature field uniformity defect: Even if a single-point calibration is established to establish a correspondence between the "machine display temperature" and the "wafer surface single-point temperature", due to the heating method of the annealing machine (such as infrared heating, resistance heating), the temperature field distribution of different areas (such as the center and the edge) of the wafer surface is still not uniform, and some areas may not form an effective ohmic contact due to insufficient temperature, or the metal layer may be over-dispersed due to excessive temperature;

[0006] 3. Abnormal response lag: The annealing machine is a high-temperature and high-frequency working device, and its heating module and temperature control module are prone to stability decline after long-term use, which may result in temperature out of control (such as temperature overshoot, temperature instability), but the existing scheme can only be detected through subsequent electrical tests (such as four-probe resistance test), which has a "time difference" from the completion of annealing to the detection of abnormality, which may lead to large quantities of wafer scrap and cause serious economic losses.

[0007] In summary, the prior art lacks a scheme capable of directly, quickly and batch verifying the annealing temperature of the N-face Au / Ge ohmic contact layer of the AlGaInP-based red Micro-LED, and it is urgent to break through this technical bottleneck through process design. SUMMARY

[0008] The purpose of the present application is to solve the technical problems that the annealing temperature of the N-face Au / Ge ohmic contact layer of the existing AlGaInP-based red Micro-LED is difficult to accurately monitor, and there is a lack of convenient and batch detection means, and to provide an annealing temperature control method based on differential ohmic contact materials.

[0009] To solve the above technical problems, the technical scheme adopted by the present application is:

[0010] An annealing temperature control method based on differential ohmic contact materials, comprising the following steps:

[0011] S1, graphic process 1: spin-coating photoresist on the N-face of the AlGaInP-based red Micro-LED wafer to be processed, after curing the photoresist, using mask A for ultraviolet exposure, and then using developing solution to remove the photoresist in the exposed area to obtain a patterned substrate;

[0012] S2, metal plating 1: evaporating a first ohmic contact layer composed of gold Au and germanium Ge on the surface of the patterned substrate obtained in step S1;

[0013] S3, peeling 1: using an organic solvent to rinse the surface of the sample obtained in step S2 to peel off the metal attached to the photoresist at the bottom, and retain the first ohmic contact layer in the normal ohmic contact area;

[0014] S4, graphic process 2: spin-coating photoresist again on the surface of the sample treated in step S3, after curing the photoresist, using mask B for ultraviolet exposure, and then using developing solution to remove the photoresist in the exposed area to obtain a patterned substrate in the reserved test area;

[0015] S5, metal plating 2: evaporating a second ohmic contact layer composed of gold Au, germanium Ge and nickel Ni on the surface of the patterned substrate obtained in step S4;

[0016] S6, peeling 2: using the same organic solvent as step S3 to rinse the surface of the sample obtained in step S5 to peel off the metal attached to the photoresist at the bottom, and retain the second ohmic contact layer in the reserved test area;

[0017] S7, annealing and temperature judgment: placing the sample obtained in step S6 in an annealing device for annealing treatment, observing the agglomeration state of the first ohmic contact layer and the second ohmic contact layer after annealing through an optical observation device, and judging whether the annealing temperature is normal according to the difference in the agglomeration state.

[0018] Preferably, in steps S1 and S4, the photoresist is a positive photoresist, the developer is a tetramethylammonium hydroxide aqueous solution, and the developing time is 2 minutes.

[0019] Preferably, in steps S1 and S4, the thickness of the photoresist is 500-3000 nm.

[0020] Preferably, in step S1, the structure of the mask A includes periodically arranged circular opaque regions for forming a Micro-LED mesa structure, and 1 ohmic ring test region is arranged in each exposure period.

[0021] Preferably, in the mask A, the hole diameter of the periodically arranged circular opaque regions is 1-3 μm, and the center-to-center distance of the holes is 3-5 μm.

[0022] Preferably, in step S4, the mask B is provided with a pattern only near the ohmic ring test region of the mask A, and the pattern is another ohmic ring adjacent to the ohmic ring.

[0023] Preferably, in steps S2 and S5, the evaporation process uses an electron beam evaporation process, the deposition rate is 1 nm / s, and the purity of the target material used for evaporation is 99.999%; wherein the target material of step S2 is gold and germanium, and the target material of step S5 is gold, germanium and nickel.

[0024] Preferably, in step S2, the layer sequence of the first ohmic contact layer from the side close to the N surface of the wafer to the outside is a 20-nm Au layer-20-nm Ge layer-20-nm Au layer; and in step S5, the layer sequence of the second ohmic contact layer from the side close to the N surface of the wafer to the outside is a 20-nm Au layer-3-nm Ni layer-20-nm Ge layer-20-nm Au layer.

[0025] Preferably, in steps S3 and S6, the organic solvent is acetone or isopropyl alcohol; and the degumming operation specifically includes: ultrasonic treatment of the sample in the organic solvent, rinsing with deionized water, and blowing the sample surface dry with nitrogen.

[0026] Preferably, in step S7, the annealing equipment is a rapid annealing furnace, and the annealing process parameters are: heating to 370℃ and maintaining for 6 minutes, and the cooling rate is 5℃ / s; and the temperature judgment logic is: if the first ohmic contact layer agglomerates and the second ohmic contact layer does not agglomerate, the annealing temperature is normal; if both agglomerate, the annealing temperature is too high; and if both do not agglomerate, the annealing temperature is too low.

[0027] Thanks to the use of the above technical solutions, the present application has the following beneficial effects compared with the prior art:

[0028] 1. High convenience of temperature monitoring: No need to rely on complex electrical test equipment (such as four-probe tester), visual judgment can be realized through optical microscope only, the operation threshold is low, a single person can complete the detection, and the detection efficiency is improved;

[0029] 2. Strong batch detection capability: Supports "full-face inspection" of large-size wafers (such as 4-8 inches), which can cover all areas of the wafer at one time, avoiding the problem of uneven temperature field missing detection caused by single-point detection, and has high detection coverage;

[0030] 3. Good real-time response to abnormality: The annealing can be observed immediately after completion, without waiting for subsequent electrical test, the temperature can be judged within 1 minute whether it is abnormal or not, the abnormal detection time is significantly shortened, avoiding large batch wafer scrap, and reducing economic loss;

[0031] 4. Good process stability: Through "double verification" of differentiated contact layer, the actual temperature of the annealing machine can be accurately calibrated, the temperature deviation caused by machine aging is reduced, the resistance fluctuation range of Au / Ge ohmic contact layer is reduced, and the device performance consistency is improved;

[0032] 5. Strong compatibility: The seven-step process of the method can be seamlessly integrated into the existing preparation process of AlGaInP-based red Micro-LED, without the need to add special equipment, only the mask plate needs to be replaced, the modification cost is low, and it is suitable for industrialized mass production and promotion. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0034] Fig. 1 The flowchart of the annealing temperature control method based on differentiated ohmic contact material of the present application;

[0035] Fig. 2 The schematic diagram of the ohmic contact layer without agglomeration;

[0036] Fig. 3 The schematic diagram of the ohmic contact layer with agglomeration. DETAILED DESCRIPTION

[0037] In order to better understand the present application by those skilled in the art, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present application.

[0038] It should be noted that the terms "first", "second", and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0039] In the present application, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe the present application and its embodiments, and are not intended to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation.

[0040] In addition, in addition to indicating the orientation or positional relationship, the above-mentioned part of the terms can also be used to indicate other meanings, for example, the term "upper" can also be used to indicate a certain dependent relationship or connection relationship in some cases. For those skilled in the art, the specific meaning of these terms in the present application can be understood according to the specific circumstances.

[0041] In addition, the terms "mount", "set", "provided with", "connected", "connected", "sleeved" should be broadly understood. For example, it can be fixedly connected, detachably connected, or integrally constructed; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate medium, or internal communication between two devices, elements or components. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0042] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other in the case of no conflict. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0043] Embodiment one

[0044] Please see Figs. 1-3 The present application provides an annealing temperature control method based on differential ohmic contact materials, the core idea of which is: by using the material characteristics that Au / Ge alloy is easy to agglomerate at a conventional annealing temperature, and the agglomeration can be significantly inhibited after the addition of nickel (Ni), through a seven-step process of "two times of patterning, two times of metal plating, two times of stripping, one time of annealing and observation", a "first ohmic contact layer (Au / Ge) with normal function" and a "second ohmic contact layer (Au / Ge / Ni) for temperature detection only" are constructed on the wafer surface, the agglomeration state difference of the two layers of materials is observed by optical equipment, and the visual control of the annealing temperature is realized. The specific technical solution is as follows:

[0045] 1, overall process framework:

[0046] The method includes seven core steps (S1-S7), which are closely connected, forming a complete process of "defining area-preparing contact layer-stripping excess metal-annealing detection", which is as follows:

[0047] S1, patterning process 1: through spin coating, exposure and development of photoresist, "normal ohmic contact area" and "ohmic ring test area" required for subsequent electrical verification are defined on the N surface of the wafer;

[0048] S2, metal plating 1: depositing an Au / Ge alloy layer (first ohmic contact layer) in the defined normal ohmic contact area to provide ohmic contact function for the device;

[0049] S3, stripping 1: stripping the metal layer in the undefined area, and only keeping the first ohmic contact layer in the normal ohmic contact area;

[0050] S4, patterning process 2: patterning the wafer surface again to define a "reserved test area" (adjacent to the ohmic ring test area);

[0051] S5, metal plating 2: depositing an Au / Ge / Ni alloy layer (second ohmic contact layer) in the reserved test area for annealing temperature detection;

[0052] S6, stripping 2: stripping the metal layer outside the reserved test area, and only keeping the second ohmic contact layer for detection;

[0053] S7, annealing and temperature judgment: annealing the wafer, observing the agglomeration state of the two contact layers by optical equipment, and judging whether the annealing temperature is normal.

[0054] 2. Key process details and design basis:

[0055] (1) Patterning process (S1, S4);

[0056] Photoresist selection: Positive photoresist (preferably type 5214) is used due to its high exposure resolution and neat pattern edge after development, which can accurately define the deposition area of the contact layer; the thickness of the photoresist is set to 500-3000 nm (optimal 1500 nm), and a thickness that is too thin can easily lead to pattern defects, while a thickness that is too thick can not be fully developed, and 1500 nm can balance pattern accuracy and process stability.

[0057] Development scheme: Use tetramethylammonium hydroxide (TMAH) aqueous solution as the developing solution, and the developing time is 2 minutes; TMAH has a uniform dissolution rate for positive photoresist and does not chemically react with the GaAs wafer surface, which can avoid damaging the wafer; a developing time of 2 minutes can ensure that the photoresist in the exposed area is completely removed, while avoiding over-etching of the unexposed area.

[0058] Mask design:

[0059] Mask A: includes "periodically arranged circular light shielding areas" and "ohmic ring test areas"; the circular light shielding areas are used to form the mesa structure of the Micro-LED, and the through-hole aperture is set to 1-3 μm (optimal 2 μm) and the center spacing is 3-5 μm (optimal 4 μm), which matches the device design requirements of AlGaInP-based red Micro-LEDs and can balance the light emitting area and current density; the ohmic ring test areas are used for subsequent electrical performance verification after annealing to ensure that the ohmic contact characteristics of the contact layer meet the standards.

[0060] Mask B: only "adjacent ohmic ring patterns" are designed near the ohmic ring test areas of mask A, which can place the second ohmic contact layer and the first ohmic contact layer in a similar annealing environment (consistent temperature field), avoid detection errors caused by temperature field differences, and ensure the accuracy of temperature judgment.

[0061] (2) Metal plating process (S2, S5);

[0062] Evaporation method: Electron beam evaporation (EB) process is used, which can accurately control the deposition rate of the metal (set to 1 nm / s) compared to thermal evaporation, and the deposited metal layer has high purity and good density, which can reduce internal defects of the contact layer and improve the stability of the ohmic contact.

[0063] Target purity: 99.999% high-purity Au, Ge, and Ni targets are selected, with impurity content less than 0.001%, which can avoid the reaction of impurities (such as oxygen and carbon) with GaAs during annealing to form high-resistance phases, ensuring the low-resistance characteristics of the contact layer.

[0064] Contact layer sequence design:

[0065] First ohmic contact layer (S2): The sequence is "20nm Au-20nm Ge-20nm Au" (from the N surface of the wafer outward), the bottom 20nm Au can enhance the adhesion to GaAs, the middle 20nm Ge is the core layer for forming ohmic contact (reacting with GaAs to form low-resistance Au-Ge-GaAs alloy phase), and the top 20nm Au can protect the middle Ge layer from oxidation. The three-layer structure cooperates to realize low-resistance ohmic contact.

[0066] Second ohmic contact layer (S5): Increase "3nm Ni layer" on the basis of the first contact layer sequence (sequence: 20nm Au-3nm Ni-20nm Ge-20nm Au); The role of Ni is to inhibit agglomeration: the eutectic point of Au and Ge is about 361°C, and liquid Au-Ge alloy is easily formed during annealing, which is prone to agglomeration due to poor wettability on the GaAs surface; while Ni can form high-melting-point intermetallic compounds (such as , GeNi) with Au and Ge, and at the same time, Ni has strong affinity with GaAs, which can be adsorbed on the GaAs surface to inhibit the contraction of liquid Au-Ge alloy, thereby significantly reducing the probability of agglomeration.

[0067] (3) Debinding process (S3, S6);

[0068] Organic solvent selection: Acetone or isopropyl alcohol is used, both of which are polar organic solvents that can quickly dissolve the photoresist, and have no corrosive effect on the Au, Ge, and Ni metal layers; ultrasonic treatment (preferably 3-5 minutes) can enhance the penetration of the organic solvent to the photoresist, ensuring that the metal layer with the photoresist attached at the bottom is completely peeled off; subsequent deionized water rinsing and nitrogen blowing can remove residual organic solvents, avoiding affecting the subsequent process.

[0069] (4) Annealing and temperature judgment (S7);

[0070] Annealing equipment and parameters: Use a rapid annealing furnace, heat to 370°C and keep for 6 minutes, and the cooling rate is 5°C / s; 370°C is the optimal temperature for Au / Ge and GaAs to form ohmic contact (higher than the Au-Ge eutectic point to ensure sufficient reaction, and lower than the thermal damage temperature of GaAs); The 6-minute holding time can ensure uniform reaction of each area on the wafer surface; The cooling rate of 5°C / s can avoid the generation of internal stress in the metal layer due to sudden temperature change, reducing the risk of cracking.

[0071] Temperature judgment logic:

[0072] Normal temperature (about 370°C): The first ohmic contact layer (Au / Ge) forms a liquid alloy due to the Au-Ge eutectic, and obvious agglomeration occurs; the second ohmic contact layer (Au / Ge / Ni) is almost not agglomerated due to the inhibitory effect of Ni, and the state of the two layers is significantly different.

[0073] Temperature too high (> 390°C): At high temperature, the inhibitory effect of Ni is invalid, and the Au-Ge-Ni alloy also forms a liquid phase, resulting in agglomeration of both contact layers.

[0074] Temperature too low (< 350°C): The Au-Ge eutectic point is not reached, and both contact layers remain solid and do not agglomerate.

[0075] Observation equipment: Optical microscope (magnification 200x), 200x magnification can clearly observe the agglomeration state of the metal layer (after agglomeration, it presents "spherical protrusions", and without agglomeration, it is "flat film"), and can realize "whole surface observation", single observation time < 1 minute, suitable for rapid detection of large quantities of wafers.

[0076] (5) Material property mechanism;

[0077] Au / Ge agglomeration mechanism: Au-Ge eutectic point is low (361°C), after the annealing temperature reaches the eutectic point, Ge is dissolved into Au to form a liquid Au-Ge alloy; due to the large contact angle of liquid Au-Ge with GaAs surface (about 85°), the surface energy is high, and the alloy tends to shrink into a spherical shape to reduce the surface energy, showing "agglomeration phenomenon".

[0078] Ni anti-agglomeration mechanism: Ni has similar atomic radius to Au and Ge, and can be embedded into the Au-Ge lattice to form an Au-Ni-Ge ternary alloy, whose eutectic point is raised to above 420°C, and remains solid at the annealing temperature (370°C); at the same time, Ni and Ga atoms on the GaAs surface can form a Ge-Ni-Ga compound, which is adsorbed on the GaAs surface, can reduce the contact angle of liquid Au-Ge alloy with GaAs (to below 45°), and inhibit the agglomeration of the alloy.

[0079] Example two

[0080] The present application provides an AlGaInP-based red light Micro-LED annealing temperature control based on the method, specifically as follows:

[0081] 1. Experimental preparation.

[0082] Wafer: 4-inch AlGaInP-based red light Micro-LED epitaxial wafer, N face is GaAs layer (thickness 500 nm), standard cleaning (acetone ultrasonic 5 minutes → isopropyl alcohol ultrasonic 5 minutes → deionized water rinse 3 minutes → nitrogen blowing dry) to remove surface impurities;

[0083] Equipment: Electron beam evaporator (Model: Kurt J. Lesker PVD75), Rapid thermal annealing furnace (Model: AG Associates Heatpulse 610), Optical microscope (Model: Olympus BX53), Spin coater (Model: Karl Suss RC8);

[0084] Materials: 5214 positive photoresist, 2.38wt% TMAH aqueous solution, 99.999% Au target, 99.999% Ge target, 99.999% Ni target, Acetone, Isopropyl alcohol.

[0085] 2. Process steps are as follows:

[0086] S1, Pattern 1:

[0087] Spin photoresist: Put the wafer on the spin coater, drop 5214 positive photoresist, spin at 3000 rpm for 30 seconds to form a 1500 nm thick photoresist layer; then pre-bake on a 105°C hot plate for 120 seconds to cure the photoresist;

[0088] UV exposure: Cover mask A (aperture 2 μm, center spacing 4 μm, containing ohmic ring test area) on the surface of the photoresist, use UV lithography machine (wavelength 365 nm) to expose, exposure dose 110 ;

[0089] Development: Soak the wafer in 2.38wt% TMAH aqueous solution, develop at room temperature for 2 minutes; then rinse with deionized water for 30 seconds to remove residual developer; finally post-bake on a 125°C hot plate for 80 seconds to obtain a patterned substrate.

[0090] S2, Metal plating 1:

[0091] Vacuum preparation: Put the patterned substrate into the electron beam evaporator, close the chamber and vacuumize to Pa;

[0092] Metal deposition: Evaporate Au (20 nm, rate 1 nm / s), Ge (20 nm, rate 1 nm / s), Au (20 nm, rate 1 nm / s) in sequence, control the deposition thickness in real time by a quartz crystal monitor during the evaporation process to ensure an error of <±0.5 nm.

[0093] S3, Photoresist removal 1:

[0094] Metal stripping: Soak the plated wafer in acetone, ultrasonic treatment for 4 minutes (power 300 W), so that the metal layer attached to the bottom of the photoresist dissolves with the photoresist;

[0095] Cleaning and drying: The wafer was transferred to isopropanol for 3 minutes to remove residual acetone, then rinsed with deionized water for 1 minute, and finally dried by nitrogen (purity 99.999%) at a flow rate of 5 L / min.

[0096] S4, patterning process 2:

[0097] Repeat spin coating: After the wafer was removed, 1500 nm of 5214 positive resist was spin-coated on the wafer surface at a speed of 3000 rpm, with the same pre-baking and post-baking parameters as S1.

[0098] Exposure and development: After covering mask B (ohmic ring adjacent pattern) and ultraviolet exposure (dose 110 ), the wafer was developed in TMAH aqueous solution for 2 minutes, rinsed with deionized water, and dried with nitrogen to obtain a patterned substrate with a reserved test area.

[0099] S5, metal plating 2:

[0100] Vacuum preparation: same as S2, vacuum degree Pa;

[0101] Metal deposition: Au (20 nm, 1 nm / s), Ni (3 nm, 1 nm / s), Ge (20 nm, 1 nm / s), Au (20 nm, 1 nm / s) were evaporated in sequence, with a deposition thickness error of <±0.5 nm.

[0102] S6, stripping 2:

[0103] Repeat the stripping process of S3: acetone ultrasonic for 4 minutes, isopropanol soaking for 3 minutes, deionized water rinsing, and nitrogen drying, only leaving the second ohmic contact layer of the reserved test area.

[0104] S7, annealing and temperature judgment:

[0105] Annealing treatment: The wafer was placed in a rapid annealing furnace, and the process parameters were set as follows: heating rate 10°C / s, heating to 370°C and holding for 6 minutes, cooling rate 5°C / s, and annealing atmosphere nitrogen (flow rate 10 L / min);

[0106] Observation and judgment: The wafer surface was observed under an optical microscope (200x magnification), and it was found that the first ohmic contact layer (Au / Ge) was obviously spherical and aggregated (aggregated particles were about 0.5-1 μm in diameter), and the second ohmic contact layer (Au / Ge / Ni) was smooth and had no aggregation;

[0107] Electrical verification: The contact resistance of the ohmic ring test area was tested using a four-probe tester, and the result was , which meets the ohmic contact requirements of AlGaInP-based red Micro-LEDs (< ), proving that the annealing temperature is normal.

[0108] Example Three

[0109] The application provides an annealing temperature card control of an AlGaInP-based red Micro-LED based on the method, wherein the lower limit of the photoresist thickness is 500 nm.

[0110] 1. Variable design

[0111] Only the photoresist thickness in S1 and S4 is adjusted to 500 nm, and the remaining parameters are the same as in Example Two.

[0112] 2. Process and results

[0113] Patterning effect: the edge accuracy of 500 nm thin photoresist after development is slightly lower than that of 1500 nm, but there is no pattern defect;

[0114] Coating and photoresist stripping: the adhesion between the metal layer and the photoresist layer is good, and there is no metal residue after photoresist stripping;

[0115] Annealing judgment: the observation result is the same as in Example Two (Au / Ge agglomeration, Au / Ge / Ni no agglomeration);

[0116] Electrical performance: contact resistance , which meets the requirements.

[0117] Example Four

[0118] The application provides an annealing temperature card control of an AlGaInP-based red Micro-LED based on the method, wherein the upper limit of the photoresist thickness is 3000 nm.

[0119] 1. Variable design

[0120] Only the photoresist thickness in S1 and S4 is adjusted to 3000 nm, and the remaining parameters are the same as in Example Two.

[0121] 2. Process and results

[0122] Patterning effect: 3000 nm thick photoresist needs to extend the pre-baking to 180 s, and the pattern edge after development is neat without excessive erosion;

[0123] Coating and photoresist stripping: the ultrasonic time is extended to 5 min to ensure that the thick photoresist is completely stripped, and the metal layer is reserved intact;

[0124] Annealing judgment: the observation result is the same as in Example Two;

[0125] Electrical performance: contact resistance , which meets the requirements.

[0126] Example Five

[0127] The application provides an annealing temperature card control of an AlGaInP-based red Micro-LED based on the method, wherein the lower limit of the aperture of the through hole of mask A is 1 μm.

[0128] 1. Variable design;

[0129] Only the aperture of the through hole of mask A is adjusted to 1 μm, the center interval is 3 μm, and the rest of the parameters are the same as in example two.

[0130] 2. Process and result;

[0131] The exposure dose of 1 μm small aperture needs to be increased to 120 , and there is no blockage after development;

[0132] Plating effect: EB process can accurately cover the 1 μm aperture area, and the metal layer is not broken;

[0133] Annealing judgment: the observation result is the same as in example two (the diameter of the agglomerated particles of the small size contact layer is about 0.3-0.5 μm, and it is still clear and distinguishable);

[0134] Electrical performance: contact resistance , which meets the requirements.

[0135] Example six

[0136] The application provides an annealing temperature card control of an AlGaInP-based red Micro-LED based on the method, wherein the upper limit of the aperture of the through hole of mask A is 3 μm.

[0137] 1. Variable design;

[0138] Only the aperture of the through hole of mask A is adjusted to 3 μm, the center interval is 5 μm, and the rest of the parameters are the same as in example two.

[0139] 2. Process and result;

[0140] The exposure dose of 3 μm large aperture is 100 , and there is no edge roughness after development;

[0141] Plating effect: the metal layer uniformly covers the 3 μm aperture area without voids;

[0142] Annealing judgment: the observation result is the same as in example two (the diameter of the agglomerated particles is about 1-1.2 μm, and the recognition degree is high);

[0143] Electrical performance: contact resistance , which meets the requirements.

[0144] Example seven

[0145] The application provides an annealing temperature card control of an AlGaInP-based red light Micro-LED based on the method, wherein the thickness of the Ni layer is adjusted to 5 nm.

[0146] 1. Variable design;

[0147] Only the thickness of the Ni layer in S5 is adjusted to 5 nm, and the rest of the parameters are the same as in Example Two.

[0148] 2. Process and results;

[0149] Coating effect: The 5 nm Ni layer is deposited uniformly without pinhole defects;

[0150] Annealing judgment: The Au / Ge layer agglomeration state is the same as in Example Two, and the Au / Ge / Ni layer has stronger anti-agglomeration effect and smoother surface due to the thickening of the Ni layer;

[0151] Electrical performance: contact resistance , which meets the requirements;

[0152] Conclusion: The thickness of the Ni layer in the range of 3-5 nm can effectively inhibit agglomeration, and the method has parameter flexibility.

[0153] Comparative experiment:

[0154] High temperature group: the annealing temperature is set to 400℃, and the rest of the parameters are the same as in Example Two;

[0155] Observation results: both the first and second contact layers are severely agglomerated; the electrical test contact resistance is , which does not meet the requirements.

[0156] Low temperature group: the annealing temperature is set to 320℃, and the rest of the parameters are the same as in the example;

[0157] Observation results: both contact layers are not agglomerated; electrical test shows that ohmic contact is not formed, and the resistance is greater than .

[0158] The above examples and comparative verification show that the method can effectively work in the range of photoresist thickness 500-3000 nm, via hole diameter 1-3 μm, Ni layer thickness 3-5 nm, etc., the annealing temperature is accurately judged, and qualified ohmic contact layers can be stably prepared.

[0159] Finally, it should be noted that the above is only a preferred embodiment of the application and is not intended to limit the application, although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent replacements for some technical features, and any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the application shall be included in the protection scope of the application.

Claims

1. A method for controlling the annealing temperature based on differentiated ohmic contact materials, characterized in that, Includes the following steps: S1, Patterning process 1: Photoresist is spin-coated on the N side of the AlGaInP-based red Micro-LED wafer to be processed. After the photoresist is cured, it is exposed to ultraviolet light using mask A. Then, the photoresist in the exposed area is removed with a developer to obtain a patterned substrate. S2, Metal coating 1: A first ohmic contact layer composed of gold (Au) and germanium (Ge) is vapor-deposited on the patterned substrate surface obtained in step S1; S3, Resin Removal 1: Rinse the sample surface obtained in step S2 with organic solvent, peel off the metal with photoresist attached to the bottom, and retain the first ohmic contact layer of the normal ohmic contact area; S4, Patterning process 2: Photoresist is spin-coated again on the sample surface after step S3. After the photoresist is cured, it is exposed to ultraviolet light using mask B. Then, the photoresist in the exposed area is removed with a developer to obtain a patterned substrate with reserved test area. S5, Metal coating 2: A second ohmic contact layer composed of gold Au, germanium Ge and nickel Ni is vapor-deposited on the patterned substrate surface obtained in step S4. S6, Resin Removal 2: Rinse the sample surface obtained in step S5 with the same organic solvent as in step S3, peel off the metal with photoresist attached to the bottom, and retain the second ohmic contact layer of the reserved test area; S7, Annealing and Temperature Judgment: Place the sample obtained in step S6 into an annealing device for annealing treatment. After annealing, observe the aggregation state of the first ohmic contact layer and the second ohmic contact layer through an optical observation device. Determine whether the annealing temperature is normal based on the difference in aggregation state.

2. The annealing temperature control method based on differentiated ohmic contact materials according to claim 1, characterized in that, In steps S1 and S4, the photoresist is a positive photoresist, the developer is a tetramethylammonium hydroxide aqueous solution, and the development time is 2 minutes.

3. The annealing temperature control method based on differentiated ohmic contact materials according to claim 2, characterized in that, In steps S1 and S4, the thickness of the photoresist is 500-3000 nm.

4. The annealing temperature control method based on differentiated ohmic contact materials according to claim 1, characterized in that, In step S1, the structure of the mask A includes: a periodically arranged circular light-shielding area for forming the Micro-LED mesa structure, and an ohm ring test area set in each exposure cycle.

5. The annealing temperature control method based on differentiated ohmic contact materials according to claim 4, characterized in that, The aperture of the periodically arranged circular light-shielding areas in the mask A is 1-3 μm, and the center-to-center spacing of the through holes is 3-5 μm.

6. The annealing temperature control method based on differentiated ohmic contact materials according to claim 4, characterized in that, In step S4, the mask B has a pattern only near the ohm ring test area of ​​the mask A, and the pattern is another ohm ring adjacent to the ohm ring.

7. The annealing temperature control method based on differentiated ohmic contact materials according to claim 1, characterized in that, In steps S2 and S5, the vapor deposition process adopts electron beam evaporation, the deposition rate is 1 nm / s, and the purity of the target material used for vapor deposition is 99.999%; wherein, the target material in step S2 is gold and germanium, and the target material in step S5 is gold, germanium and nickel.

8. The annealing temperature control method based on differentiated ohmic contact materials according to claim 7, characterized in that, In step S2, the first ohmic contact layer has a layer sequence from the side closest to the N-side of the wafer to the outside as a 20nm Au layer - a 20nm Ge layer - a 20nm Au layer; in step S5, the second ohmic contact layer has a layer sequence from the side closest to the N-side of the wafer to the outside as a 20nm Au layer - a 3nm Ni layer - a 20nm Ge layer - a 20nm Au layer.

9. The annealing temperature control method based on differentiated ohmic contact materials according to claim 1, characterized in that, In steps S3 and S6, the organic solvent is acetone or isopropanol; the degumming operation specifically involves immersing the sample in the organic solvent for ultrasonic treatment, rinsing it with deionized water, and drying the sample surface with nitrogen gas.

10. The annealing temperature control method based on differentiated ohmic contact materials according to claim 1, characterized in that, In step S7, the annealing equipment is a rapid annealing furnace, and the annealing process parameters are: heating to 370°C and maintaining for 6 minutes, and cooling rate of 5°C / s; the temperature judgment logic is: if the first ohmic contact layer agglomerates and the second ohmic contact layer does not agglomerate, the annealing temperature is normal; if both agglomerate, the annealing temperature is too high; if neither agglomerate, the annealing temperature is too low.

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