A thermopile sensor based on single crystal silicon and metasurface and a preparation method thereof

Abstract

The application discloses a kind of based on single crystal silicon and super surface thermoelectric sensor and its preparation method, the preparation method includes to the silicon wafer on insulating layer is washed and dried and top layer single crystal silicon is etched to form strip-shaped thermocouple strip;Interconnection via hole is etched to form in the upper layer of thermocouple strip, after first metal layer is deposited and fills interconnection via hole, etching and remaining the part of interconnection with the thermocouple strip and the part located in thermocouple area, passivation layer and second metal layer are sequentially deposited on first metal layer, second metal layer is etched to form super surface and passivation layer is etched to form local opening, cavity etching is carried out to the silicon wafer under insulating layer to obtain thermoelectric sensor with thermoelectric suspension film structure.The above preparation method, by preparing single crystal silicon thermocouple structure to improve Seebeck coefficient, preparation super surface structure increases infrared absorption efficiency, while increasing the output voltage of detection without increasing chip size and process complexity.

Description

Technical Field

[0001] This invention relates to the field of sensor technology, and in particular to a thermopile sensor based on single-crystal silicon and metasurface and its fabrication method. Background Technology

[0002] In traditional thermopile devices based on MEMS (Micro-Electro-Mechanical System) technology, monocrystalline silicon is typically used as the substrate, and doped polycrystalline silicon is used as the thermocouple structure. Because the crystal structure of polycrystalline silicon consists of multiple grains, it contains numerous grain boundaries. These grain boundaries scatter charge carriers during migration, reducing their mobility and affecting thermoelectric transport performance. Simultaneously, the defect states introduced by the grain boundaries in polycrystalline silicon trap charge carriers, reducing the effective carrier concentration and mobility, thereby lowering the Seebeck coefficient and resulting in a smaller output voltage (signal response) under the same conditions.

[0003] To address the aforementioned issues and improve the output signal of thermopile devices under the same environmental conditions, common methods include increasing the number of thermocouple pairs (e.g., using double-layer polysilicon, reducing thermocouple width to accommodate more thermocouple pairs), increasing chip size (increasing energy receiving area), and adding an infrared absorption layer (increasing chip infrared absorptivity). These methods all aim to improve the signal while maintaining the same Seebeck coefficient. However, these techniques require increasing chip size or adding additional processes, and each method has its own problems. Increasing the number of thermocouple pairs increases the resistance of the thermopile device; excessively high resistance can reduce the signal-to-noise ratio due to thermal noise. Increasing chip size directly increases the energy of infrared radiation received by the sensor, but reduces the number of chips per wafer. Furthermore, excessively increasing chip size and film area increases the risk of film breakage and reduces chip yield. While the added infrared absorbing materials (Au-Black, Pt-Black) have an absorptivity greater than 90%, their porous structure cannot withstand photolithography, etching, and dicing processes, making them unsuitable for wafer-level mass packaging. Therefore, existing thermopile devices suffer from problems such as large chip size and complex manufacturing processes. Summary of the Invention

[0004] This invention provides a thermopile sensor based on single-crystal silicon and metasurface and its fabrication method, aiming to solve the problems of large chip size and complex manufacturing process of thermopile devices in existing technologies.

[0005] In a first aspect, embodiments of this application provide a method for fabricating a thermopile sensor based on single-crystal silicon and a metasurface, wherein the fabrication method includes:

[0006] The silicon wafer on the insulating layer is cleaned and dried using a cleaning solution. The silicon wafer on the insulating layer includes a silicon substrate, a dielectric layer and a top layer of element-doped single-crystal silicon stacked sequentially.

[0007] Etching is performed on the single-crystal silicon located in the non-thermocouple region to form strip-shaped thermocouple strips;

[0008] A silicon dioxide layer is deposited on the upper layer of the thermocouple strip, and interconnecting vias are etched in the silicon dioxide layer;

[0009] A first metal layer is deposited on top of the silicon dioxide layer and the interconnect vias are filled;

[0010] The first metal layer is etched to retain the portion of the first metal layer that is interconnected with the thermocouple strip and the portion located in the thermocouple region. The portion located in the thermocouple region serves as the bottom metal of the metasurface.

[0011] A passivation layer is deposited on the first metal layer and completely covers the first metal layer, serving as an intermediate dielectric layer for the metasurface.

[0012] A second metal layer is deposited on top of the passivation layer and etched, retaining the portion of the second metal layer that is located above the first metal layer and serves as the top metal layer of the metasurface;

[0013] The passivation layer is etched to form local openings for wire bonding on the passivation layer;

[0014] Cavity etching is performed on the silicon wafer on the insulating layer to etch a cavity into the silicon substrate below the dielectric layer, thereby obtaining a thermopile sensor with a thermopile suspension film structure.

[0015] Secondly, embodiments of this application also provide a thermopile sensor based on single-crystal silicon and metasurfaces. The thermopile sensor is fabricated by the fabrication method of a thermopile sensor based on single-crystal silicon and metasurfaces as described in the first aspect above. The thermopile sensor includes a silicon wafer on an insulating layer, a silicon dioxide layer, a first metal layer, a passivation layer, and a second metal layer.

[0016] The silicon wafer on the insulating layer includes a silicon substrate, a dielectric layer and a top layer of element-doped single-crystal silicon stacked sequentially.

[0017] The silicon dioxide layer is disposed on top of the top monocrystalline silicon layer; the silicon dioxide layer has at least one interconnecting via; the first metal layer is disposed on top of the silicon dioxide layer; the first metal layer fills the interconnecting via and is electrically connected to the underlying top monocrystalline silicon layer.

[0018] The passivation layer is disposed on top of the first metal layer, and at least one local opening for wire bonding is formed on the passivation layer; the second metal layer is disposed on top of the passivation layer, and the second metal layer is located above the first metal layer; the second metal layer is composed of regularly arranged metasurface microstructures.

[0019] The silicon substrate beneath the dielectric layer is etched to form a substrate cavity.

[0020] This invention provides a thermopile sensor based on single-crystal silicon and a metasurface, and its fabrication method. The method includes cleaning and drying a silicon wafer on an insulating layer, and etching the top single-crystal silicon layer to form strip-shaped thermocouple strips. A silicon dioxide layer is deposited on top of the thermocouple strips and etched to form interconnecting vias. A first metal layer is deposited and filled with the interconnecting vias, followed by etching to retain the portion interconnected with the thermocouple strips and the portion located in the thermocouple region. A passivation layer and a second metal layer are sequentially deposited on the first metal layer. The second metal layer is etched to form a metasurface, and the passivation layer is etched to form localized openings. Cavity etching is performed on the silicon wafer on the insulating layer to obtain a thermopile sensor with a thermopile suspended film structure. This fabrication method improves the Seebeck coefficient by fabricating a single-crystal silicon thermocouple structure, and by fabricating a second metal layer with a specific structure that forms a metasurface structure with the first metal layer and the passivation layer, thereby increasing the infrared absorption efficiency of the thermopile device. This significantly increases the detection output voltage without increasing chip size or process complexity. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A flowchart illustrating the fabrication method of a thermopile sensor based on single-crystal silicon and metasurface provided in an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram illustrating the fabrication process of a thermopile sensor based on single-crystal silicon and metasurface provided in an embodiment of the present invention.

[0024] Figure 3 This is an overall structural diagram of a thermopile sensor based on single-crystal silicon and metasurface provided in an embodiment of the present invention;

[0025] Reference numerals: 1. Silicon substrate; 2. Dielectric layer; 3. Top single-crystal silicon; 4. Silicon dioxide layer; 5. First metal layer; 6. Passivation layer; 7. Second metal layer; 8. Substrate cavity. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0028] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0029] This application discloses a method for fabricating a thermopile sensor based on single-crystal silicon and a metasurface, wherein the method is used to fabricate a thermopile sensor based on single-crystal silicon and a metasurface; please refer to... Figure 1 As shown in the figure, this application provides a method for fabricating a thermopile sensor based on single-crystal silicon and metasurface, which includes steps S1 to S9.

[0030] S1. The silicon wafer on the insulating layer is cleaned and dried using a cleaning solution. The silicon wafer on the insulating layer includes a silicon substrate, a dielectric layer and a top layer of element-doped single-crystal silicon stacked sequentially.

[0031] First, prepare a silicon-on-insulator (SOI) wafer. This SOI wafer consists of a silicon substrate, a dielectric layer, and a top layer of monocrystalline silicon, stacked sequentially. The thicknesses of these layers are determined according to the chip design requirements. The dielectric layer is composed of one or two of SiO2, Si3N4, and Al2O3. Cleaning can be done with deionized water or 75% alcohol. After cleaning, the SOI wafer is dried in an oven.

[0032] In this process, a group III or group V element is doped onto the top monocrystalline silicon layer to obtain element-doped top monocrystalline silicon. In one specific embodiment, a silicon-on-insulator (STI) wafer with monocrystalline silicon can be prepared, and a group III or group V element is doped onto the surface monocrystalline silicon to obtain element-doped top monocrystalline silicon. Alternatively, an STI wafer containing element-doped top monocrystalline silicon can be used directly, such as by in-situ doping during the preparation of the STI wafer. The specific structure of an undoped STI wafer is as follows... Figure 2 As shown in Figure (a), after elemental doping, a silicon wafer with an insulating layer containing element-doped top monocrystalline silicon is obtained, as shown in Figure (a). Figure 2 As shown in Figure (b).

[0033] In specific embodiments, the top monocrystalline silicon layer is doped with phosphorus or boron. For example, in one embodiment, phosphorus can be doped onto the surface monocrystalline silicon layer to introduce charge carriers, thereby forming a top monocrystalline silicon layer with a specific resistance value.

[0034] S2. Etch the single-crystal silicon located in the non-thermocouple region to form strip-shaped thermocouple strips.

[0035] Furthermore, the top layer of single-crystal silicon located in the non-thermocouple region is etched, while the single-crystal silicon located in the thermocouple region is retained, and strip-shaped thermocouple strips are formed through etching. The specific processing procedure is as follows: Figure 2 As shown in Figure (c). Specifically, a 5-10 μm thick photoresist can be used as a mask on the surface of the top single-crystal silicon layer, and a strip-shaped thermocouple strip can be formed by plasma etching. The flow rates of SF6 and CHF3 in the etching gas used in the plasma etching process are 20-40 sccm and 5-10 sccm, respectively, the flow rate of He gas is 50-200 sccm, the chamber pressure is 300-500 mTorr, the radio frequency power is 300-500 W, and the etching rate of the top single-crystal silicon is 100-200 nm / min.

[0036] S3. A silicon dioxide layer is deposited on the upper layer of the thermocouple strip, and interconnecting vias are etched in the silicon dioxide layer.

[0037] A silicon dioxide layer is further deposited on top of the thermocouple strip. In a specific embodiment, plasma-enhanced chemical vapor deposition (PECVD) can be used to deposit the silicon dioxide layer. The reaction gases in the PECVD process include a mixture of SiH4 and N2 and N2O. The volume percentage of SiH4 in the SiH4 and N2 mixture is 5%. The flow rate of the SiH4 and N2 mixture is 100-200 sccm, the flow rate of the N2O gas is 600-800 sccm, the chamber pressure is 800-900 mTorr, the reaction temperature is 250-350℃, the radio frequency (RF) power is 15-25 W, and the deposition rate of the silicon dioxide layer is 50-70 nm / min.

[0038] Etching is performed on the deposited silicon dioxide layer to form interconnect vias. For example, a plasma dry etching process can be used to etch the silicon dioxide layer. Specifically, a 1-5 μm photoresist can be used as the dry etching mask. The flow rates of CF4 and CHF3 in the etching gas are 10-20 sccm and 30-40 sccm, respectively, and the Ar flow rate is 200-300 sccm. The chamber pressure is 200-300 mTorr, the radio frequency (RF) power is 400-500 W, and the etching rate of the silicon dioxide layer is 400-800 nm / min. The specific processing procedure is as follows: Figure 2 As shown in Figure (d).

[0039] S4. A first metal layer is deposited on the upper layer of the silicon dioxide layer and the interconnect vias are filled.

[0040] A first metal layer is deposited on top of the silicon dioxide layer. The first metal layer fills the interconnect vias and contacts the thermocouple strip below the interconnect vias, that is, the first metal layer is electrically connected to the thermocouple strip below the interconnect vias. Specifically, the first metal layer is composed of one or more metals selected from Al, Au, Ag, Ti, and W.

[0041] Specifically, the first metal layer can be obtained by metal magnetron sputtering deposition. Al material can be used to prepare the first metal layer. The magnetron sputtering power is 100-200W, the chamber pressure is 2.6-3.5 mTorr, the Ar gas flow rate is 50-100 sccm, and the Al film deposition rate is 5-10 nm / min. If only one metal is used to prepare the first metal layer, only that metal material can be used for metal magnetron sputtering. If multiple metals are used to prepare the first metal layer, a mixture of multiple metals can be used for metal magnetron sputtering. The specific processing procedure is as follows... Figure 2 As shown in Figure (e).

[0042] S5. Etch the first metal layer, retaining the portion of the first metal layer that is interconnected with the thermocouple strip and the portion located in the thermocouple region, with the portion located in the thermocouple region serving as the bottom metal of the metasurface.

[0043] The first metal layer is etched, retaining the portion interconnected with the thermocouple strip to ensure this interconnection. Simultaneously, to avoid short circuits, the portion of the first metal layer located in the thermocouple region is retained, serving as the bottom metal layer of the metasurface. Specifically, photoresist can be used as a mask, and plasma etching is employed. The etching process uses Cl2, BCl3, and Ar as etching gases. Cl2 etches the metal to form metal salts (e.g., using Cl2 to etch Al metal to form volatile AlCl3), BCl3 enhances plasma stability and reduces polymer deposition, and Ar bombards the metal to improve etching uniformity. A mixture of 60-100 cC of Cl2 and 20-60 cC of BCl3 / Ar gas can be introduced into the cavity, with the reaction time controlled at 120-200 s. The specific processing procedure is as follows... Figure 2 As shown in Figure (f).

[0044] S6. Deposit a passivation layer on the first metal layer and completely cover the first metal layer, serving as the intermediate dielectric layer of the metasurface.

[0045] Next, a passivation layer is deposited on top of the first metal layer to completely cover it. This dielectric layer serves as the intermediate dielectric layer of the metasurface. The passivation layer is composed of one or two of SiO2, Si3N4, and Al2O3. For example, if the passivation layer is composed of SiO2 and Si3N4, it can be deposited using a thermo-oxidative deposition process. First, a SiO2 film with a thickness of 600-2000 nm is processed on top of the first metal layer using a thermo-oxidative deposition process. The oxygen flow rate in the thermo-oxidative deposition process is 3-5 L / min, and the reaction temperature is 1020-1150 °C; preferably, the reaction temperature is 1070-1120 °C, and the optimal reaction temperature is 1100 °C. A Si3N4 film with a thickness of 500-1600 nm is further processed on top of the SiO2 film using a low-pressure chemical vapor deposition (LPVCD) process. The LPVCD process involves a reaction gas with a SiH2Cl2 to NH3 volumetric flow rate ratio of 1:3-1:4, a reaction temperature of 750-830℃, a chamber pressure of 300 mTorr, and a Si3N4 film formation rate of 3-6 nm / min. Specifically, the reaction gas used in the LPVCD process consists of SiH2Cl2 and NH3, with a SiH2Cl2 to NH3 volumetric flow rate ratio of 1:3-1:4; the preferred reaction temperature is 780-815℃, with an optimal reaction temperature of 800℃. The specific processing procedure is as follows: Figure 2 As shown in Figure (g).

[0046] S7. Deposit a second metal layer on the passivation layer and etch it, retaining the portion of the second metal layer that is located above the first metal layer and serves as the top metal layer of the metasurface.

[0047] A second metal layer is deposited on the passivation layer and etched, with the deposition and etching processes similar to steps S4 and S5 above. The second metal layer is composed of one or more metals selected from Al, Au, Ag, Ti, and W. During the etching process of the deposited second metal layer, only the portion of the second metal layer that lies above the first metal layer and serves as the bottom metal layer of the metasurface is retained. The specific processing steps are as follows... Figure 2 As shown in Figure (i), the second metal layer consists of regularly arranged metasurface microstructures. These metasurface microstructures can be rectangular, cylindrical, or other microstructures with dimensions of 0.5-2 micrometers. For example, the metasurface microstructures can be arranged in a matrix to form the second metal layer.

[0048] S8. Etch the passivation layer to form local openings for wire bonding on the passivation layer.

[0049] Etching the passivation layer creates localized openings, exposing the underlying second metal layer. Subsequent wires can be inserted into these openings to bond with the second metal layer. Specifically, a plasma dry etching process can be used to etch the passivation layer. A 1-5 μm photoresist is used as the dry etching mask. The flow rates of CF4 and CHF3 in the etching gas are 10-20 sccm and 30-40 sccm, respectively, and the Ar flow rate is 200-300 sccm. The chamber pressure is 200-300 mTorr, the RF power is 400-500 W, and the etching rate of the passivation layer is 400-800 nm / min. The specific processing steps are as follows: Figure 2 As shown in Figure (h).

[0050] In practical applications, the execution order of S7 and S8 can be interchanged. That is, S7 can be executed first, followed by S8; or S8 can be executed first, followed by S7.

[0051] S9. Cavity etching is performed on the silicon wafer on the insulating layer to etch a cavity in the silicon substrate below the dielectric layer, thereby obtaining a thermopile sensor with a thermopile suspension film structure.

[0052] Furthermore, cavity etching can be performed on the silicon wafer on the insulating layer to etch cavities into the silicon substrate below the dielectric layer. The etched cavities then suspend the upper thermopile film, resulting in a thermopile sensor with a suspended film structure. In specific embodiments, cavity etching of the silicon wafer on the insulating layer can be performed using either back-side etching or front-side etching. Specifically, cavity etching of the silicon wafer on the insulating layer can be performed using either dry etching or wet etching processes; the specific processing steps are as follows... Figure 2 As shown in Figure (j).

[0053] For example, cavity etching is performed using front-side etching and wet etching processes to form cavities. A 5-10 μm thick photoresist is used as a mask on the front side of the silicon wafer on the insulating layer, and a window is etched using a plasma etching process. Then, based on the etched window, the central region of the silicon substrate is etched using a TMAH (tetramethylammonium hydroxide) process.

[0054] For example, cavity etching is performed using back-side etching and dry etching processes. A 5-10 μm thick photoresist is used as a mask on the back side of the silicon wafer on the insulating layer, and DRIE (Deep Reactive Ion Etching) is used directly to etch the central region of the silicon substrate. During the etching of the bulk silicon substrate, the reaction chamber pressure is 50-100 mTorr, the flow rates of C4F8 and SF6 in the reaction gases are both set to 150-250 sccm, the Src RF power is 1600-2500 W, the Bias RF power is 15-50 W, and the etching rate of the central region of the substrate is 0.5-1.5 μm / min. The etching time is controlled according to the thickness of the silicon substrate, so that the bulk silicon in the thermocouple region of the silicon substrate is completely etched. At this time, the dielectric layer of the silicon wafer on the insulating layer directly serves as the bottom surface of the etched cavity, and the etched cavity region corresponds to the thermocouple region.

[0055] This invention also provides a thermopile sensor based on single-crystal silicon and a metasurface. The thermopile sensor is fabricated using the method described in the above embodiments for fabricating a thermopile sensor based on single-crystal silicon and a metasurface. Figure 3 As shown, the thermopile sensor includes a silicon-on-insulator wafer, a silicon dioxide layer 4, a first metal layer 5, a passivation layer 6, and a second metal layer 7. The silicon-on-insulator wafer includes a silicon substrate 1, a dielectric layer 2, and a top single-crystal silicon layer 3 that is element-doped, stacked sequentially. The silicon dioxide layer 4 covers the top single-crystal silicon layer 3. The silicon dioxide layer 4 has at least one interconnecting via. The first metal layer 5 covers the top of the silicon dioxide layer 4, fills the interconnecting via, and is electrically connected to the bottom single-crystal silicon layer 3. The passivation layer 6 covers the top of the first metal layer 5, and has at least one partial opening for wire bonding. The second metal layer 7 covers the top of the passivation layer 6 and is located above the first metal layer 5. The second metal layer 7 is composed of regularly arranged metasurface microstructures. The silicon substrate 1 below the dielectric layer 2 is etched to form a substrate cavity 8.

[0056] The innovation of this invention lies in using the intermediate layer (dielectric layer) of the SOI wafer as the supporting film structure and the top layer (single-crystal silicon) as the thermocouple material to simplify the thermopile fabrication process; using single-crystal silicon as the thermocouple constituent material, leveraging the high Seebeck coefficient, high conductivity, and low noise of single-crystal silicon to improve the output signal of the thermopile device; and using the interconnect metal layer and passivation layer constituting the thermopile chip as the two layers constituting the metasurface, depositing a metal layer on the top surface to form a MIM (metal-dielectric-metal) composite material layer based on the metasurface structure, thereby improving the chip's infrared absorption capability and adding signal output.

[0057] This invention proposes a method based on existing thermopile technology to improve the Seebeck coefficient through a single-crystal silicon thermocouple structure without introducing non-CMOS materials. Simultaneously, a second metal layer with a specific structure is added to the original thermopile structure, forming a metasurface structure with the original first metal layer (interconnect metal layer) and dielectric layer, thereby increasing the infrared absorption rate of the thermopile device. Compared with existing technologies, this invention is based on SOI wafers, using the dielectric layer as the support film structure and single-crystal silicon as the thermocouple material. Compared with traditional polycrystalline silicon thermopile devices, it eliminates the need for support film deposition, polycrystalline silicon deposition, and annealing steps, reducing process complexity. Furthermore, by using single-crystal silicon as the thermocouple base material, the high carrier mobility of single-crystal silicon is utilized to reduce the thermopile sheet resistance, increase the number of thermocouple pairs, and leverage the high Seebeck coefficient of single-crystal silicon. Combined with the metasurface structure, the output signal of the thermopile chip is effectively improved by adding only one metal layer (i.e., the second metal layer), providing a high-response chip for infrared temperature measurement, NDIR gas detection, and other applications.

[0058] This invention provides a thermopile sensor based on single-crystal silicon and a metasurface, and its fabrication method. The method includes cleaning and drying a silicon wafer on an insulating layer, and etching the top single-crystal silicon layer to form strip-shaped thermocouple strips. A silicon dioxide layer is deposited on top of the thermocouple strips and etched to form interconnecting vias. A first metal layer is deposited and filled with the interconnecting vias, followed by etching to retain the portion interconnected with the thermocouple strips and the portion located in the thermocouple region. A passivation layer and a second metal layer are sequentially deposited on the first metal layer. The second metal layer is etched to form a metasurface, and the passivation layer is etched to form localized openings. Cavity etching is performed on the silicon wafer on the insulating layer to obtain a thermopile sensor with a thermopile suspended film structure. This fabrication method improves the Seebeck coefficient by fabricating a single-crystal silicon thermocouple structure, and by fabricating a second metal layer with a specific structure that forms a metasurface structure with the first metal layer and the passivation layer, thereby increasing the infrared absorption efficiency of the thermopile device. This significantly increases the detection output voltage without increasing chip size or process complexity.

[0059] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a thermopile sensor based on single-crystal silicon and metasurface, characterized in that, The preparation method includes: The silicon wafer on the insulating layer is cleaned and dried using a cleaning solution. The silicon wafer on the insulating layer includes a silicon substrate, a dielectric layer and a top layer of element-doped single-crystal silicon stacked sequentially. Etching is performed on the single-crystal silicon located in the non-thermocouple region to form strip-shaped thermocouple strips; A silicon dioxide layer is deposited on the upper layer of the thermocouple strip, and interconnecting vias are etched in the silicon dioxide layer; A first metal layer is deposited on top of the silicon dioxide layer and the interconnect vias are filled; The first metal layer is etched to retain the portion of the first metal layer that is interconnected with the thermocouple strip and the portion located in the thermocouple region. The portion located in the thermocouple region serves as the bottom metal of the metasurface. A passivation layer is deposited on the first metal layer and completely covers the first metal layer, serving as an intermediate dielectric layer for the metasurface. A second metal layer is deposited on top of the passivation layer and etched, retaining the portion of the second metal layer that is located above the first metal layer and serves as the top metal layer of the metasurface; The passivation layer is etched to form local openings for wire bonding on the passivation layer; Cavity etching is performed on the silicon wafer on the insulating layer to etch a cavity into the silicon substrate below the dielectric layer, thereby obtaining a thermopile sensor with a thermopile suspension film structure.

2. The method for fabricating a thermopile sensor based on single-crystal silicon and metasurface according to claim 1, characterized in that, The top monocrystalline silicon is doped with group III or group V elements to obtain element-doped top monocrystalline silicon.

3. The method for fabricating a thermopile sensor based on single-crystal silicon and metasurface according to claim 2, characterized in that, The top layer of single-crystal silicon is doped with phosphorus or boron.

4. The method for fabricating a thermopile sensor based on single-crystal silicon and metasurface according to claim 1, characterized in that, The cavity etching of the silicon wafer on the insulating layer can be performed using either back-side etching or front-side etching.

5. The method for fabricating a thermopile sensor based on single-crystal silicon and metasurface according to claim 4, characterized in that, The cavity etching of the silicon wafer on the insulating layer is performed using either a dry etching process or a wet etching process.

6. The method for fabricating a thermopile sensor based on single-crystal silicon and metasurface according to any one of claims 1-5, characterized in that, The passivation layer is composed of one or two of SiO2, Si3N4, and Al2O3.

7. The method for fabricating a thermopile sensor based on single-crystal silicon and metasurface according to claim 6, characterized in that, The dielectric layer is composed of one or two of SiO2, Si3N4, and Al2O3.

8. The method for fabricating a thermopile sensor based on single-crystal silicon and metasurface according to claim 6, characterized in that, The first metal layer is composed of one or more metals selected from Al, Au, Ag, Ti, and W.

9. The method for fabricating a thermopile sensor based on single-crystal silicon and metasurface according to claim 6, characterized in that, The second metal layer is composed of one or more metals selected from Al, Au, Ag, Ti, and W.

10. A thermopile sensor based on single-crystal silicon and metasurface, said thermopile sensor being fabricated by the method for fabricating a thermopile sensor based on single-crystal silicon and metasurface as described in any one of claims 1-9, characterized in that, The thermopile sensor includes a silicon wafer on an insulating layer, a silicon dioxide layer, a first metal layer, a passivation layer, and a second metal layer; The silicon wafer on the insulating layer includes a silicon substrate, a dielectric layer and a top layer of element-doped single-crystal silicon stacked sequentially. The silicon dioxide layer is disposed on top of the top monocrystalline silicon layer; the silicon dioxide layer has at least one interconnecting via; the first metal layer is disposed on top of the silicon dioxide layer; the first metal layer fills the interconnecting via and is electrically connected to the underlying top monocrystalline silicon layer. The passivation layer is disposed on top of the first metal layer, and at least one local opening for wire bonding is formed on the passivation layer; the second metal layer is disposed on top of the passivation layer, and the second metal layer is located above the first metal layer; the second metal layer is composed of regularly arranged metasurface microstructures. The silicon substrate beneath the dielectric layer is etched to form a substrate cavity.

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