Satellite-borne high-speed storage system and working method thereof

Abstract

The embodiment of the invention provides a satellite-borne high-speed storage system and a working method thereof, and is applied to the technical field of remote sensing satellites. The system comprises a control module, and a data receiving module, a data caching module and a data storage module which are respectively connected with the control module, wherein the data receiving module is used for receiving N paths of load data which are input in parallel; the data caching module uses two RDIMMs as a caching medium; the data storage module is used for persistently storing the written load data; and the control module takes the FPGA as a core controller and is used for receiving and buffering the load data through the FIFO data buffer, writing the buffered load data into the data caching module through the RDIMM controller and writing the load data in the data caching module into the working area of the data storage module through the SATA IP core. In this way, accurate prediction and management of the SSD state can be achieved, data loss caused by sudden failure of the SSD is prevented, and the service life of the system is prolonged.

Description

Technical Field

[0001] This disclosure relates to the field of remote sensing satellite technology, and in particular to a spaceborne high-speed storage system and its working method. Background Technology

[0002] With the rapid development of commercial remote sensing satellites, high-resolution, wide-swath optical and SAR satellites are being rapidly deployed, resulting in increasingly higher payload data rates. Therefore, developing a high-capacity, high-bandwidth, and high-reliability onboard storage unit is essential. Traditional high-speed, high-capacity onboard storage systems mainly employ FPGA+SSD, FPGA+NANDFLASH, and FPGA+EMMC methods. The core storage medium in these systems is NANDFLASH. However, as the number of write cycles increases, NANDFLASH chips generate more and more bad blocks, leading to a decrease in usable storage space and eventually rendering them unreadable and writable. Furthermore, the increase in bad blocks reduces read / write speeds, ultimately failing to meet the demands of high-speed storage. When a storage medium fails or its speed drops below the minimum standard, the overall storage function malfunctions or the overall storage speed decreases, failing to meet the current requirements for high-capacity, high-speed onboard storage. Summary of the Invention

[0003] This disclosure provides a spaceborne high-speed storage system and its working method, which solves the technical problem that traditional spaceborne storage systems are unable to meet the large amount of high-speed data storage requirements generated by the high-resolution and wide-swath payloads of current commercial remote sensing satellites. Once the storage medium fails or the speed is lower than the minimum standard, the entire storage function is prone to failure or speed reduction, affecting the continuity and stability of spaceborne missions.

[0004] According to a first aspect of this disclosure, a spaceborne high-speed storage system is provided. The system includes a control module and a data receiving module, a data buffering module, and a data storage module, each respectively connected to the control module; wherein...

[0005] The data receiving module is used to receive N parallel input load data channels; where N is a positive integer;

[0006] The data caching module uses two RDIMMs as the caching medium for payload data.

[0007] The data storage module includes a working area and a spare area, and is used to persistently store the written payload data.

[0008] The control module uses an FPGA as its core controller and integrates N FIFO data buffers, an RDIMM controller, and i SATA IP cores on the FPGA. It is used to receive and buffer payload data from the data receiving module through the FIFO data buffers, write the buffered payload data into the data cache module through the RDIMM controller, and write the payload data in the data cache module into the working area of ​​the data storage module for persistent storage through the SATA IP cores; where i is a positive integer.

[0009] In addition to the aspects and any possible implementations described above, a further implementation is provided in which the workspace is used for persistent storage of data written from the data cache module, including i SSDs, and supports single-disk, dual-disk, or quad-disk RAID 0 working modes;

[0010] The spare area is used to dynamically replace the faulty SSD in the working area, and includes k inactive SSDs; where k is a positive integer.

[0011] In addition to the aspects described above and any possible implementation, a further implementation is provided in which the number of FIFO data buffers is determined according to the number of payload data paths, and the number of SATA IP cores is determined according to the number of SSDs in the data storage module's working area.

[0012] In addition to the aspects described above and any possible implementations, a further implementation is provided in which the control module further includes:

[0013] The lifespan detection unit is used to collect and record the read and write speed, total data write volume, CRC check error rate and response latency of the working area SSD in real time through FRAM, and input the collected parameter data into the trained lifespan prediction model to predict the remaining lifespan of the SSD.

[0014] The failover unit is used to automatically activate the first available SSD from the k inactive SSDs in the spare area in sequence to replace the failed SSD and reassemble the RAID 0 array when any failover condition is triggered by the SSD in the working area.

[0015] The compression direct transmission unit is used to start the compression direct transmission mode when all SSDs in the working area and the spare area are abnormal, to compress the data in the data cache module and transmit it directly to the satellite data transmission device.

[0016] In addition to the aspects described above and any possible implementations, a further implementation is provided in which the SSD in the spare area is activated in the following manner:

[0017] During power-on initialization, a self-test is performed on the SSDs in the working area. If the self-test fails, the first available SSD from the k inactive SSDs in the spare area is activated sequentially to replace the faulty SSD, and the faulty SSD is marked. In the initial state, the working area consists of SSD1 to SSD2. i The array is configured as a RAID 0 array, with the spare area consisting of SSDs. 1+i SSD i+k ;

[0018] During operation, the status of the working area SSD is continuously monitored. If any switching condition is triggered, the first available SSD from the remaining SSDs in the spare area is activated in sequence to replace the faulty SSD, and the faulty SSD is marked.

[0019] In addition to the aspects and any possible implementations described above, a further implementation is provided in which the reconfigured RAID 0 array includes:

[0020] When a faulty SSD is detected in the working area, the data flow is paused, the SATA link of the faulty SSD is disconnected, and the first available SSD in the spare area is activated in sequence to replace the faulty SSD, and the faulty SSD is marked.

[0021] A new RAID 0 array configuration is generated based on the location of the faulty SSD, the data stream splicing order is dynamically adjusted, the SATA links are reinitialized after replacement, and the data stream is restored after the integrity verification of the new array is completed.

[0022] In addition to the aspects described above and any possible implementations, an implementation is further provided in which the switching condition includes at least one of the following:

[0023] The remaining lifespan of the SSD in the work area is less than a preset lifespan threshold.

[0024] The CRC check error rate or write latency of the SSD in the working area exceeds a preset threshold;

[0025] The SSD in the work area either times out or returns an error status.

[0026] The SSD in the work area suffered physical damage.

[0027] According to a second aspect of this disclosure, a method for operating a spaceborne high-speed storage system is provided.

[0028] The method includes:

[0029] The data receiving module receives N parallel input payload data channels;

[0030] The control module has N FIFO data buffers that receive and buffer N payload data streams from the data receiving module.

[0031] The RDIMM controller in the control module writes the N-channel load data into the data cache module;

[0032] The N SATA IP cores in the control module write the N load data from the data cache module to the N SSDs in the working area of ​​the data storage module for persistent storage.

[0033] In addition to the aspects and any possible implementations described above, a further implementation is provided, wherein the method further includes:

[0034] The control module monitors the health status of the SSD in the work area in real time.

[0035] When the working SSD triggers any switching condition, the data flow is paused, and the first available SSD is activated sequentially from the k inactive SSDs in the spare area to replace the faulty SSD. The faulty SSD is marked, and the RAID 0 array is reassembled.

[0036] When all SSDs in the working area and the backup area are abnormal, the compression direct transmission mode is activated to compress the data in the data cache module and transmit it directly to the satellite data transmission device.

[0037] In addition to the aspects described above and any possible implementation, a further implementation is provided in which the number of FIFO data buffers is determined according to the number of payload data paths, and the number of SATA IP cores is determined according to the number of SSDs in the data storage module's working area.

[0038] In addition to the aspects described above and any possible implementations, a further implementation is provided in which the control module further includes:

[0039] The lifespan detection unit is used to collect and record the read and write speed, total data write volume, CRC check error rate and response latency of the working area SSD in real time through FRAM, and input the collected parameter data into the trained lifespan prediction model to predict the remaining lifespan of the SSD.

[0040] The failover unit is used to automatically activate the first available SSD from the k inactive SSDs in the spare area in sequence to replace the failed SSD and reassemble the RAID 0 array when any failover condition is triggered by the SSD in the working area.

[0041] The compression direct transmission unit is used to start the compression direct transmission mode when all SSDs in the working area and the spare area are abnormal, to compress the data in the data cache module and transmit it directly to the satellite data transmission device.

[0042] In addition to the aspects described above and any possible implementations, a further implementation is provided in which the SSD in the spare area is activated in the following manner:

[0043] During power-on initialization, a self-test is performed on the SSDs in the working area. If the self-test fails, the first available SSD from the k inactive SSDs in the spare area is activated sequentially to replace the faulty SSD, and the faulty SSD is marked. In the initial state, the working area consists of SSD1 to SSD2. i The array is configured as a RAID 0 array, with the spare area consisting of SSDs. 1+i SSD i+k ;

[0044] During operation, the status of the working area SSD is continuously monitored. If any switching condition is triggered, the first available SSD from the remaining SSDs in the spare area is activated in sequence to replace the faulty SSD, and the faulty SSD is marked.

[0045] In addition to the aspects and any possible implementations described above, a further implementation is provided in which the reconfigured RAID 0 array includes:

[0046] When a faulty SSD is detected in the working area, the data flow is paused, the SATA link of the faulty SSD is disconnected, and the first available SSD in the spare area is activated in sequence to replace the faulty SSD, and the faulty SSD is marked.

[0047] A new RAID 0 array configuration is generated based on the location of the faulty SSD, the data stream splicing order is dynamically adjusted, the SATA links are reinitialized after replacement, and the data stream is restored after the integrity verification of the new array is completed.

[0048] In addition to the aspects described above and any possible implementations, an implementation is further provided in which the switching condition includes at least one of the following:

[0049] The remaining lifespan of the SSD in the work area is less than a preset lifespan threshold.

[0050] The CRC check error rate or write latency of the SSD in the working area exceeds a preset threshold;

[0051] The SSD in the work area either times out or returns an error status.

[0052] The SSD in the work area suffered physical damage.

[0053] According to a third aspect of this disclosure, an electronic device is provided. The electronic device includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the program to implement the method described above.

[0054] According to a fourth aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the methods according to the first and / or second aspects of this disclosure.

[0055] In this disclosure, firstly, the data receiving module can receive N parallel input payload data channels, giving the system a powerful parallel data receiving capability. It can process multiple data inputs simultaneously, greatly improving data receiving efficiency and meeting the needs of rapid data inflow in a spaceborne environment. Secondly, the data caching module uses two RDIMM chips as cache media. Compared to a single cache chip, two RDIMM chips provide a larger cache capacity and higher read / write speed, effectively buffering multiple parallel input data channels, reducing the waiting time before data is written to the storage module, avoiding data loss, and improving the overall data processing smoothness of the system. Thirdly, the data storage module, through the configuration of working and spare areas, can combine multiple SSDs, improving data read / write speed, ensuring efficient and large-capacity data storage, while ensuring the continuity and integrity of data storage, avoiding data loss or storage interruption due to single-disk failure, and enhancing system reliability. Finally, the control module integrates N FIFO data buffers, an RDIMM controller, and i SATA... The IP core enables real-time monitoring and accurate prediction of SSD health status, allowing the system to understand the lifespan of the storage media in advance. This provides a basis for timely replacement or adjustment of storage strategies, improves system maintainability and reliability, and prevents data loss due to sudden SSD failure.

[0056] It should be understood that the description in the Summary of the Invention is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0057] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. The drawings are provided for a better understanding of the invention and are not intended to limit the scope of this disclosure. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0058] Figure 1 A schematic block diagram of a spaceborne high-speed storage system provided by an embodiment of the present disclosure is shown;

[0059] Figure 2A flowchart illustrating a method of operating a spaceborne high-speed storage system provided by an embodiment of this disclosure is shown.

[0060] Figure 3 A block diagram of an exemplary electronic device capable of implementing embodiments of the present disclosure is shown. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0062] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0063] In this disclosure, firstly, the data receiving module can receive N parallel input payload data channels, giving the system a powerful parallel data receiving capability. It can process multiple data inputs simultaneously, greatly improving data receiving efficiency and meeting the needs of rapid data inflow in a spaceborne environment. Secondly, the data caching module uses two RDIMM chips as cache media. Compared to a single cache chip, two RDIMM chips provide a larger cache capacity and higher read / write speed, effectively buffering multiple parallel input data channels, reducing the waiting time before data is written to the storage module, avoiding data loss, and improving the overall data processing smoothness of the system. Thirdly, the data storage module, through the configuration of working and spare areas, can combine multiple SSDs, improving data read / write speed, ensuring efficient and large-capacity data storage, while ensuring the continuity and integrity of data storage, avoiding data loss or storage interruption due to single-disk failure, and enhancing system reliability. Finally, the control module integrates N FIFO data buffers, an RDIMM controller, and i SATA... The IP core enables real-time monitoring and accurate prediction of SSD health status, allowing the system to understand the lifespan of the storage media in advance. This provides a basis for timely replacement or adjustment of storage strategies, improves system maintainability and reliability, and prevents data loss due to sudden SSD failure.

[0064] Example 1

[0065] The following reference Figure 1This embodiment describes a spaceborne high-speed storage system, such as... Figure 1 As shown, a spaceborne high-speed storage system 100 includes a control module 140, and a data receiving module 110, a data buffer module 120, and a data storage module 130, all connected to the control module; wherein,

[0066] The data receiving module 110 is used to receive N parallel input load data channels; where N is a positive integer;

[0067] The data caching module 120 uses two RDIMMs as the caching medium for payload data.

[0068] The data storage module 130 includes a working area and a spare area, and is used to persistently store the written payload data.

[0069] The control module 140 uses an FPGA as its core controller and integrates N FIFO data buffers, an RDIMM controller, and i SATA IP cores on the FPGA. It is used to receive and buffer payload data from the data receiving module 110 through the FIFO data buffers, write the buffered payload data into the data cache module 120 through the RDIMM controller, and write the payload data in the data cache module 120 into the working area of ​​the data storage module 130 for persistent storage through the SATA IP cores; where i is a positive integer.

[0070] For example, before data enters the FIFO, preliminary data verification functions, such as CRC (Cyclic Redundancy Check), are implemented using the FPGA's hardware resources. By performing rapid verification calculations on the received data, errors that may occur during data transmission can be detected in a timely manner, and erroneous data can be marked so that subsequent processing modules can handle the data appropriately according to its importance and reliability requirements, such as discarding erroneous data or requesting a retransmission.

[0071] For example, to facilitate time-series analysis and management of data, the FPGA can add precise timestamps to each payload data stream during the data preprocessing stage. The timestamp generation is based on the high-precision clock signal of the onboard equipment, ensuring the traceability and correlation of the data in the time dimension, providing crucial time reference information for subsequent data processing and analysis.

[0072] For example, since the operating clock of the data receiving module 110 may differ from the clock of the subsequent processing module, cross-clock domain processing logic needs to be implemented inside the FPGA. A multi-level FIFO buffer technique is employed to safely transfer data from the receiving clock domain to the processing clock domain, avoiding data loss or errors caused by metastability or other issues during clock domain transitions.

[0073] For example, the two RDIMMs in the data caching module 120 are organized into two independent "Banks" (Bank A and Bank B). During data writing, when one Bank (such as Bank A) receives data from the data receiving module 110 and becomes full (or reaches a predetermined threshold), the control module 140 immediately switches to the other Bank (Bank B) for data reception. Simultaneously, the data in Bank A is read out and written to the working area SSD of the data storage module 130. This Ping-Pong buffering method achieves seamless data buffering, ensuring the continuity of the data writing and reading process and effectively improving the overall system performance.

[0074] For example, the RDIMM controller inside the FPGA is responsible for precisely managing the read / write pointers, start / end addresses, and bank switching logic for the two banks. To handle potential conflicts between write requests from the data receiving module 110 and read requests from the data storage module 130 for the same bank, arbitration logic is employed. During data writing and reading, priority allocation and timing control ensure that the two requests can access the RDIMM in an orderly manner, avoiding resource conflicts and data errors.

[0075] In some embodiments, the workspace is used for persistent storage of data written from the data cache module 120, including i SSDs, and supports single-disk, dual-disk, or quad-disk RAID 0 working modes;

[0076] The spare area is used to dynamically replace the faulty SSD in the working area, and includes k inactive SSDs; where k is a positive integer.

[0077] In some embodiments, the number of FIFO data buffers is determined according to the number of payload data paths, and the number of SATA IP cores is determined according to the number of SSDs in the working area of ​​the data storage module 130.

[0078] For example, the RAID 0 implementation is entirely based on FPGA logic. The FPGA divides data blocks from the data cache module 120 into fixed-size stripes (such as 64KB, 128KB, or 256KB) and writes these stripes sequentially to the various SSDs in the working area using a polling method. In this way, RAID 0 can fully utilize the parallel read and write capabilities of multiple SSDs, significantly improving data write and read speeds and meeting the performance requirements of onboard high-speed storage systems.

[0079] The FPGA maintains a logical address mapping table, translating logical block addresses (LBAs) into physical SSDs and their internal LBAs. During data writing, the FPGA distributes data across multiple SSDs according to the mapping table, achieving parallel writing. Simultaneously, multiple SATAIP cores within the FPGA (or through time-division multiplexing) send write operation commands to each SSD in parallel, maximizing write bandwidth and improving the overall storage performance of the system.

[0080] The SATA IP core inside the FPGA handles link management tasks such as SATA PHY interface, link training, protocol layer (FIS processing), and command queuing (NCQ), ensuring stable and high-speed communication with the SSD. Bad block management within the SSD is primarily handled by the SSD's own controller. The system monitors the spare block exhaustion alarm information reported by the SSD to promptly detect and address potential bad block issues, ensuring the reliability and integrity of data storage.

[0081] For example, all spare SSDs are physically connected to the FPGA's SATA ports, but initially, these spare SSDs are powered off or in a PHY layer power-off / reset state, and their SATA links are forcibly disabled by the FPGA logic. The FPGA maintains a status table for the spare SSD pool, recording the status information of each spare SSD (such as available, faulty, activated, etc.) so that when a working SSD fails, a spare SSD can be quickly and accurately selected and activated for replacement.

[0082] For example, when a failure of an SSD in the working area triggers a failover condition, the FPGA logic activates the first available spare SSD sequentially according to the status table of the spare SSD pool. After the spare SSD is activated, the RAID 0 logic inside the FPGA updates the configuration table, removes the failed SSD from the array, and adds the newly activated spare SSD to the array. Simultaneously, the updated logic stripe to the physical SSD mapping table reallocates data write paths, ensuring that data can be correctly written to the new RAID 0 array, achieving seamless failover and continuous system operation.

[0083] In some embodiments, the control module 140 further includes:

[0084] The lifespan detection unit is used to collect and record the read and write speed, total data write volume, CRC check error rate and response latency of the working area SSD in real time through FRAM, and input the collected parameter data into the trained lifespan prediction model to predict the remaining lifespan of the SSD.

[0085] The failover unit is used to automatically activate the first available SSD from the k inactive SSDs in the spare area in sequence to replace the failed SSD and reassemble the RAID 0 array when any failover condition is triggered by the SSD in the working area.

[0086] The compression direct transmission unit is used to start the compression direct transmission mode when all SSDs in the working area and the spare area are abnormal, to compress the data in the data cache module 120 and transmit it directly to the satellite data transmission device.

[0087] For example, the FPGA connects to the SSD via a SATA link and collects parameters such as read / write speed, total data write volume (TBW) (by accumulating the total amount of data written to each SSD), CRC error rate (the ratio of the number of CRC error frames detected by the receiver to the total number of frames in the SATA link layer transmission), and response latency (recording the SSD's response time to the write command, from the time the command is issued to the time the response FIS is received) in real time, and stores these parameters in FRAM.

[0088] The inputs to the lifetime prediction model include acquired parameters (read / write rate, total data written, CRC error rate, response latency) and possible environmental parameters (such as temperature, obtained via onboard telemetry). The model type can be a rule-based model, a simple linear / exponential decay model, or a more complex machine learning model (trained on the ground and then its parameters stored in an FPGA or FRAM). The model's output is the remaining lifetime percentage or status label (health / warning / danger) for each SSD, providing a basis for decision-making by the failover unit.

[0089] In some embodiments, the SSD in the spare area is activated in the following manner:

[0090] During power-on initialization, a self-test is performed on the SSDs in the working area. If the self-test fails, the first available SSD from the k inactive SSDs in the spare area is activated sequentially to replace the faulty SSD, and the faulty SSD is marked. In the initial state, the working area consists of SSD1 to SSD2. i The array is configured as a RAID 0 array, with the spare area consisting of SSDs. 1+i SSD i+k ;

[0091] During operation, the status of the working area SSD is continuously monitored. If any switching condition is triggered, the first available SSD from the remaining SSDs in the spare area is activated in sequence to replace the faulty SSD, and the faulty SSD is marked.

[0092] In some embodiments, the reconfiguration of the RAID 0 array includes:

[0093] When a faulty SSD is detected in the working area, the data flow is paused, the SATA link of the faulty SSD is disconnected, and the first available SSD in the spare area is activated in sequence to replace the faulty SSD, and the faulty SSD is marked.

[0094] A new RAID 0 array configuration is generated based on the location of the faulty SSD, the data stream splicing order is dynamically adjusted, the SATA links are reinitialized after replacement, and the data stream is restored after the integrity verification of the new array is completed.

[0095] In some embodiments, the switching conditions include at least one of the following:

[0096] The remaining lifespan of the SSD in the work area is less than a preset lifespan threshold.

[0097] The CRC check error rate or write latency of the SSD in the working area exceeds a preset threshold;

[0098] The SSD in the work area either times out or returns an error status.

[0099] The SSD in the work area suffered physical damage.

[0100] Example 2

[0101] This embodiment provides a working method for the system of Embodiment 1, such as... Figure 2 As shown, it includes the following steps:

[0102] S210, the data receiving module receives N parallel input load data;

[0103] S220, the N FIFO data buffers in the control module receive and buffer the N payload data from the data receiving module;

[0104] S230, the RDIMM controller in the control module writes the load data into the data cache module;

[0105] S240, the i SATA IP cores in the control module write the payload data from the data cache module to the i SSDs in the working area of ​​the data storage module for persistent storage.

[0106] In some embodiments, the method further includes:

[0107] The control module monitors the health status of the SSD in the work area in real time.

[0108] When the working SSD triggers any switching condition, the data flow is paused, and the first available SSD is activated sequentially from the k inactive SSDs in the spare area to replace the faulty SSD. The faulty SSD is marked, and the RAID 0 array is reassembled.

[0109] When all SSDs in the working area and the backup area are abnormal, the compression direct transmission mode is activated to compress the data in the data cache module and transmit it directly to the satellite data transmission device.

[0110] In some embodiments, the health status of the workspace SSD is detected in the following ways:

[0111] The FRAM is used to collect and record the read and write speed, total data write volume, CRC check error rate and response latency of the SSD in the working area in real time, and the collected parameter data is input into the trained life prediction model to predict the remaining life of the SSD.

[0112] In some embodiments, the spare SSD is activated in the following manner:

[0113] During power-on initialization, a self-test is performed on the SSDs in the working area. If the self-test fails, the first available SSD from the k inactive SSDs in the spare area is activated sequentially to replace the faulty SSD, and the faulty SSD is marked. In the initial state, the working area consists of SSD1 to SSD2. i The array is configured as a RAID 0 array, with the spare area consisting of SSDs. 1+i SSD i+k ;

[0114] During operation, the status of the working area SSD is continuously monitored. If any switching condition is triggered, the first available SSD from the remaining SSDs in the spare area is activated in sequence to replace the faulty SSD, and the faulty SSD is marked.

[0115] In some embodiments, the reconfiguration of the RAID 0 array includes:

[0116] When a faulty SSD is detected in the working area, the data flow is paused, the SATA link of the faulty SSD is disconnected, the first available SSD in the spare area is activated in sequence to replace the faulty SSD, and the faulty SSD is marked.

[0117] A new RAID 0 array configuration is generated based on the location of the faulty SSD, the data stream splicing order is dynamically adjusted, the SATA links are reinitialized after replacement, and the data stream is restored after the integrity verification of the new array is completed.

[0118] The following describes in detail the working method of a spaceborne high-speed storage system provided in this disclosure embodiment, taking the scenario of "4+4 disk redundancy working mode" as an example:

[0119] The FPGA integrates N FIFO data buffers, an RDIMM controller, and i SATA IP cores. The capacity of the FIFO data buffers can be determined based on the actual load data flow and processing rate to ensure effective buffering of the load data from the data receiving module. The RDIMM controller is used to control the read and write operations of the RDIMMs in the data cache module. The number of SATA IP cores is determined based on the number of SSDs in the working area of ​​the data storage module and is used to establish communication connections with the SSDs in the data storage module.

[0120] Based on the number of parallel input channels N of the load data (for example, assuming N is 12 channels), configure the corresponding data receiving interface circuits. These interfaces can receive parallel data from different load sources and transmit it to the corresponding N FIFO data buffers of the control module.

[0121] Two RDIMMs are used as cache media for payload data. The RDIMM capacity is ensured to be large enough to temporarily store large amounts of payload data in the event of a data storage module failure or other abnormal conditions.

[0122] In the 4+4 disk redundancy working mode, four SSDs are in working state, while the other four are not powered on and are in backup state.

[0123] After the FPGA in the control module is powered on, it first initializes and configures the entire system. Then the data receiving module starts working, ready to receive 12 parallel input load data channels.

[0124] After receiving 12 channels of payload data, the data receiving module transmits them to 12 FIFO data buffers for buffering.

[0125] The RDIMM controller in the control module writes the buffered data into the RDIMM of the data cache module. Once the data in the RDIMM reaches a certain threshold, it is written from the RDIMM to the RAID 0 array (SSD1 to SSD4) in the data storage module's working area via four SATA IP cores for persistent storage. At this time, the data from each interface is read out simultaneously after passing through the respective FIFO cache, and assembled into a 128-bit data stream {data4, data3, data2, data1}, where the data stream positions of the four disks are fixed.

[0126] The lifespan detection unit in the control module continuously collects parameters such as read / write speed, total data write volume, CRC check error rate, and response latency of the working area SSD through FRAM, and periodically inputs them into the lifespan prediction model to predict the remaining lifespan.

[0127] Meanwhile, the control module continuously monitors whether the SSD in the working area triggers a switching condition, such as remaining lifetime being less than a threshold, CRC check error rate or write latency exceeding a threshold, response timeout, return of error status, or physical damage.

[0128] If a failure is detected in the working area SSD, such as SSD1, the control module pauses data stream write operations, disconnects the SATA link of the failed SSD1, and replaces the failed SSD1 through SSD4 with one of SSDs (starting from SSD5 by default). There are four possible combinations, each corresponding to a number: {data4,data3,data2,data5}, {data4,data3,data5,data1}, {data4,data5,data2,data1}, with corresponding numbers 1, 2, 3, and 4. The faulty disk is marked. Assuming that after a period of operation, another faulty disk appears in the new combination, an SSD6 from SSD6 to SSD8 is selected to replace the faulty disk. This results in 16 possible combinations: {data4,data3,data2,data6}{data4,data3,data6,data5}{data4,data6,data2,data5}{data6,data3,data2,data5}{data4,data3,data5,data6}{data4,data3,data6,data1}{data4,data6,data5,data 1}{data6,data3,data5,data1}{data4,data5,data2,data6}{data4,data5,data6,data1}{data4,data6,data2,data1}{data6,data5,data2,data1}{data5,data3,data2,data6}{data5,data3,data6,data1}{data5,data6,data2,data1}{data6,data3,data2,data1}, the corresponding codes are 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20. Assuming that after working for a period of time, the new combination has problems again, then SSD7 is taken from SSD7 to SSD8 to replace the faulty disk. There are 16*4=64 possible combinations, with corresponding numbers 21 to 84. When SSD8 is the faulty disk, there are 64*4=256 possible combinations, with corresponding numbers 85 to 340. Since a self-test is performed after each recombination, the situation of multiple disk failures at the same time is also included in these 340 combinations. The processor will select the corresponding hard drive to form a RAID array based on the faulty disk mark and the current faulty disk number.

[0129] If all eight SSDs fail, the system will activate the compression direct transmission mode, which compresses the data cached in the RDIMM and then transmits it to the data transmission device. This mode does not rely solely on the SSDs for operation and ensures that data can be effectively transmitted back to the ground in extreme cases, thus improving system reliability.

[0130] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this disclosure is not limited to the described order of actions, because according to this disclosure, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this disclosure.

[0131] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the described module can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0132] The acquisition, storage, and application of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0133] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0134] Figure 3 A structural diagram of an exemplary electronic device capable of implementing embodiments of the present disclosure is shown. Electronic device 300 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic device 300 may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0135] like Figure 3As shown, the electronic device 300 may include a computing unit 301, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 302 or a computer program loaded from a storage unit 308 into a random access memory (RAM) 303. The RAM 303 may also store various programs and data required for the operation of the electronic device 300. The computing unit 301, ROM 302, and RAM 303 are interconnected via a bus 304. An input / output (I / O) interface 305 is also connected to the bus 304.

[0136] Multiple components in electronic device 300 are connected to I / O interface 305, including: input unit 306, such as keyboard, mouse, etc.; output unit 307, such as various types of displays, speakers, etc.; storage unit 308, such as disk, optical disk, etc.; and communication unit 309, such as network card, modem, wireless transceiver, etc. Communication unit 309 allows electronic device 300 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0137] The computing unit 301 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 301 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 301 performs the various methods and processes described above, such as method 100. For example, in some embodiments, method 200 may be implemented as a computer program product, including a computer program tangibly contained in a computer-readable medium, such as storage unit 308. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 300 via ROM 302 and / or communication unit 309. When the computer program is loaded into RAM 303 and executed by the computing unit 301, one or more steps of method 100 described above may be performed. Alternatively, in other embodiments, the computing unit 301 may be configured to perform method 200 by any other suitable means (e.g., by means of firmware).

[0138] The various embodiments described above can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), payload programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0139] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0140] In the context of this disclosure, a computer-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of computer-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0141] It should be noted that this disclosure also provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute method 200 and achieve the corresponding technical effects achieved by the embodiments of this disclosure in executing the method. For the sake of brevity, further details are omitted here.

[0142] In addition, this disclosure also provides a computer program product including a computer program that implements method 200 when executed by a processor.

[0143] To provide interaction with a user, the embodiments described above can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0144] The embodiments described above can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with the implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication (e.g., a communication network) of any form or medium. Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0145] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0146] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0147] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A spaceborne high-speed storage system, characterized in that, The system includes a control module and a data receiving module, a data buffering module, and a data storage module, all connected to the control module. The data receiving module is used to receive N parallel input load data channels; where N is a positive integer; The data caching module uses two RDIMMs as the caching medium for payload data. The data storage module includes a working area and a spare area, and is used to persistently store the written payload data. The control module uses an FPGA as its core controller and integrates N FIFO data buffers, an RDIMM controller, and i SATA IP cores on the FPGA. It is used to receive and buffer payload data from the data receiving module through the FIFO data buffers, write the buffered payload data into the data cache module through the RDIMM controller, and write the payload data in the data cache module into the working area of ​​the data storage module for persistent storage through the SATA IP cores; where i is a positive integer.

2. The system according to claim 1, characterized in that, The working area is used for persistent storage of data written from the data cache module, including i SSDs, and supports single-disk, dual-disk, or quad-disk RAID 0 working modes; The spare area is used to dynamically replace the faulty SSD in the working area, and includes k inactive SSDs; where k is a positive integer.

3. The system according to claim 2, characterized in that, The number of FIFO data buffers is determined based on the number of payload data paths, and the number of SATA IP cores is determined based on the number of SSDs in the data storage module's working area.

4. The system according to claim 3, characterized in that, The control module also includes: The lifespan detection unit is used to collect and record the read and write speed, total data write volume, CRC check error rate and response latency of the working area SSD in real time through FRAM, and input the collected parameter data into the trained lifespan prediction model to predict the remaining lifespan of the SSD. The failover unit is used to automatically activate the first available SSD from the k inactive SSDs in the spare area in sequence to replace the failed SSD and reassemble the RAID 0 array when any failover condition is triggered by the SSD in the working area. The compression direct transmission unit is used to start the compression direct transmission mode when all SSDs in the working area and the spare area are abnormal, to compress the data in the data cache module and transmit it directly to the satellite data transmission device.

5. The system according to claim 4, characterized in that, The SSDs in the spare area are activated in the following way: During power-on initialization, a self-test is performed on the SSDs in the working area. If the self-test fails, the first available SSD from the k inactive SSDs in the spare area is activated sequentially to replace the faulty SSD, and the faulty SSD is marked. In the initial state, the working area consists of SSD1 to SSD2. i The array is configured as a RAID 0 array, with the spare area consisting of SSDs. 1+i SSD i+k ; During operation, the status of the working area SSD is continuously monitored. If any switching condition is triggered, the first available SSD from the remaining SSDs in the spare area is activated in sequence to replace the faulty SSD, and the faulty SSD is marked.

6. The system according to claim 5, characterized in that, The reconfigured RAID 0 array includes: When a faulty SSD is detected in the working area, the data flow is paused, the SATA link of the faulty SSD is disconnected, and the first available SSD in the spare area is activated in sequence to replace the faulty SSD, and the faulty SSD is marked. A new RAID 0 array configuration is generated based on the location of the faulty SSD, the data stream splicing order is dynamically adjusted, the SATA links are reinitialized after replacement, and the data stream is restored after the integrity verification of the new array is completed.

7. The system according to claim 6, characterized in that, The switching conditions include at least one of the following: The remaining lifespan of the SSD in the work area is less than a preset lifespan threshold. The CRC check error rate or write latency of the SSD in the working area exceeds a preset threshold; The SSD in the work area either times out or returns an error status. The SSD in the work area suffered physical damage.

8. A method of operating the spaceborne high-speed storage system according to any one of claims 1-7, characterized in that, The method includes: The data receiving module receives N parallel input payload data channels; The control module has N FIFO data buffers that receive and buffer N payload data streams from the data receiving module. The RDIMM controller in the control module writes the load data into the data cache module; The i SATA IP cores in the control module write the payload data from the data cache module to the i SSDs in the working area of ​​the data storage module for persistent storage.

9. The working method according to claim 8, characterized in that, The method further includes: The control module monitors the health status of the SSD in the work area in real time. When the working SSD triggers any switching condition, the data flow is paused, and the first available SSD is activated sequentially from the k inactive SSDs in the spare area to replace the faulty SSD. The faulty SSD is marked, and the RAID 0 array is reassembled. When all SSDs in the working area and the backup area are abnormal, the compression direct transmission mode is activated to compress the data in the data cache module and transmit it directly to the satellite data transmission device.

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