Asynchronous first-in first-out device and chip

Abstract

The invention relates to an asynchronous first-in first-out device and a chip. The asynchronous first-in first-out device is characterized in that a write control module obtains a current write vector in a one-hot binary format by querying a null vector data structure, generates a current write address according to the current write vector, controls a memory to write data to be written into the current write address, and transmits the current write vector to a read control module in a delayed manner; the read control module updates an occupied vector data structure according to the current write vector transmitted in a delayed manner; the read control module queries the occupied vector data structure to obtain a current sequential read vector in a one-hot binary format, generates a current sequential read address according to the current sequential read vector, and controls the memory to read read data according to the current sequential read address; the read interface module sends the read data and the current sequential read address to downstream external equipment together, and the downstream external equipment can perform backward reading subsequently by using the current sequential read address; by means of the asynchronous FIFO device, the asynchronous function and the read-back function of the FIFO device can be achieved, and the area of the asynchronous FIFO device is reduced.

Description

Technical Field

[0001] This application relates to the field of First In First Out (FIFO) structure technology, specifically to an asynchronous FIFO device and chip. Background Technology

[0002] First-In-First-Out (FIFO) is a commonly used circuit structure in modern digital circuits. Its core function is to sequentially store and retrieve data, ensuring the timing consistency of the data flow. Unlike traditional memories (such as RAM), FIFOs do not require external address lines to control the read and write positions. Instead, they manage data by automatically incrementing internal read and write pointers. This characteristic makes them widely used in scenarios involving cross-clock data transmission, data buffering, and data bit width matching. Asynchronous FIFOs are the standard solution for cross-clock data transmission. Their core is to ensure reliable data transmission through a secure pointer synchronization mechanism.

[0003] The traditional asynchronous FIFO circuit structure is as follows: Figure 1 As shown, the main components include a dual-port memory array (Dualport RAM), a Gray code pointer (Dec2Gray), and a read / write comparison logic. The dual-port RAM is primarily used for data storage, with read / write addresses generated from binary pointers. The Gray code pointer is the core of the asynchronous FIFO design, used to convert the read / write pointers into Gray code and synchronize them to the other clock domain via two stages of flip-flops, reducing the risk of metastability. The read / write comparison logic determines the asynchronous FIFO's read / write state by comparing the binary values ​​of the read / write pointers.

[0004] Figure 1 The asynchronous FIFO shown only supports sequential write and sequential read, and cannot achieve random access or readback of historical data. This necessitates the use of external auxiliary modules in scenarios requiring data verification, retransmission, or backtracking (such as communication protocol retransmission, the Retry function in the PCIe protocol, and industrial automation control). The circuit structure of a FIFO currently supporting readback is shown below. Figure 2 As shown, Figure 2The FIFO achieves readback functionality by introducing redundant hardware resources. It copies a complete data copy (Copy memory array) of the data cached in the dual-port RAM (Dualport memory array) for readback, resulting in a storage resource consumption increase of over 200%, higher hardware costs, and a larger FIFO area. At the same time, since the Copy memory array is only a snapshot of the Dualport memory array, its readback timeline is short. When all the data inside the DualPort memory array is read out, the original data will be overwritten. At this point, it is impossible to read back the data before it was overwritten.

[0005] also, Figure 1 The asynchronous FIFO shown uses a Gray code conversion module to synchronize read and write pointers, but Gray code only supports 2^32. N The depth, in some non-2 N In the application scenarios required, resources will still be wasted as usual, and the larger the N value, the more serious the waste and the less flexible it is. At the same time, the Gray code conversion module needs to convert Gray code to binary and binary to Gray code, and the read and write logic also requires related conversion modules, which makes the hardware cost of the FIFO device high and the FIFO area large. Summary of the Invention

[0006] The purpose of this application is to propose an asynchronous first-in-first-out (FIFO) device and chip to reduce the area of ​​the asynchronous FIFO device.

[0007] To achieve the above objectives, according to the first aspect of this application, an asynchronous first-in-first-out device is proposed, comprising a write interface module, a read interface module, a read control module, a write control module, a first trigger module, and a memory; The write interface module is used to receive the write enable signal and the data to be written from the upstream external device; The write control module is used to query the empty vector data structure according to the write enable signal to obtain the current write vector in one-hot binary format, generate a current write address in a preset format according to the current write vector, control the memory to write the data to be written to the memory address corresponding to the current write address, and transmit the current write vector to the read control module through the first trigger module with a delay; the empty vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses, and each bit is used to identify whether the corresponding memory address is not occupied; The read control module is used to update the occupancy vector data structure according to the current write vector transmitted by the first trigger module with a delay; the occupancy vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses, and each bit is used to identify whether the corresponding memory address can be read sequentially; The read control module is also used to query the occupancy vector data structure to obtain the current sequential read vector in one-hot binary format, generate a current sequential read address in a preset format based on the current sequential read vector, and control the memory to read data from the corresponding memory address based on the current sequential read address. The read interface module is used to send the read data and the current sequential read address to the downstream external device; The read interface module is also used to receive a readback enable signal and a readback address in a preset format sent by a downstream external device, read the corresponding readback data from the memory according to the readback enable signal and the readback address, and send it to the downstream external device.

[0008] In some embodiments, the read interface module is used to cache the read data and the current sequential read address, and when it receives the sequential read enable signal from the downstream external device, it outputs the read data and the current sequential read address to the downstream external device.

[0009] In some embodiments, the asynchronous first-in-first-out device further includes a release address translation vector module and a second trigger module; The read interface module is also used to receive a release address in a preset format input by the downstream external device; The release address conversion vector module is used to convert the preset format release address into a one-hot binary format release vector, and transmit it to the write control module with a delay through the second trigger module; The write control module is also used to update the null vector data structure according to the release vector transmitted by the second trigger module with a delay.

[0010] In some embodiments, the write control module includes a write control unit, an empty vector data structure, a write vector data structure, and a write vector translation address unit; The write control unit is used to query the empty vector data structure according to the write enable signal to obtain the unoccupied bit of the next identifier corresponding to the memory address, and update the write vector data structure according to the unoccupied bit of the next identifier corresponding to the memory address. The write control unit is also used to obtain the current write vector in one-hot binary format according to the updated write vector data structure; The write control unit is also used to transmit the current write vector to the read control module through the first trigger module with a delay; The write vector conversion address unit is used to generate a current write address in a preset format according to the current write vector, and input the current write address into the memory so that the memory writes the data to be written into the storage address corresponding to the current write address.

[0011] In some embodiments, the write control module further includes a release vector data structure and a release vector verification unit; The release vector verification unit is also used to verify the release vector transmitted by the second trigger module with a delay. If the verification passes, the release vector data structure is updated according to the release vector transmitted by the second trigger module with a delay. The write control unit is further configured to obtain a delayed transmission release vector based on the release vector data structure, and update the null vector data structure based on the delayed transmission release vector.

[0012] In some embodiments, the write control unit is further configured to send a memory full signal to the upstream external device according to the null vector data structure.

[0013] In some embodiments, the read control module includes a read control unit, an occupancy vector data structure, a read vector data structure, and a read vector translation address unit; The read control unit is used to query the occupancy vector data structure to obtain the bits that can be read sequentially at the storage address corresponding to the next identifier, and update the read vector data structure according to the bits that can be read sequentially at the storage address corresponding to the next identifier; The read control unit is also used to obtain the current read vector in one-hot binary format according to the updated read vector data structure; The read vector conversion address unit is used to generate a current read address in a preset format according to the current read vector, and input the current read address into the memory so that the memory reads the read data from the corresponding memory address according to the current sequential read address; In some embodiments, the read control module includes a delayed write vector data structure and a delayed write vector verification unit; The delayed write vector verification unit is used to verify the current write vector of the delayed transmission of the first trigger module. If the verification passes, the delayed write vector data structure is updated according to the current write vector of the delayed transmission. The read control unit is further configured to obtain the current write vector of delayed transmission according to the delayed write vector data structure, and update the occupancy vector data structure according to the current write vector of delayed transmission.

[0014] In some embodiments, the read control unit is further configured to send a memory empty signal to the downstream external device according to the occupancy vector data structure.

[0015] According to a second aspect of this application, a chip is provided, including the aforementioned asynchronous first-in-first-out device.

[0016] The above-mentioned asynchronous first-in-first-out device and chip have the following advantages: (1) The occupancy vector data structure records whether each memory address is read sequentially, replacing the traditional read pointer structure; the empty vector data structure records whether each memory address is occupied, replacing the traditional write pointer structure; the occupancy vector data structure can generate the corresponding read address for sequential read operation, and the empty vector data structure can generate the corresponding write address for sequential write operation; at the same time, the write control module can obtain a one-hot binary format current write vector based on the empty vector data structure, and transmit the current write vector to the read control module through the trigger module with a delay. The read control module updates the occupancy vector data structure based on the current write vector. By introducing the one-hot binary format empty vector data structure and the occupancy vector data structure to replace the Gray code pointer mechanism of the traditional asynchronous FIFO device, the cross-clock domain asynchronous processing of the FIFO device is realized, thereby solving the technical problems of the Gray code pointer mechanism of the traditional asynchronous FIFO device and reducing the area of ​​the asynchronous FIFO device.

[0017] (2) When performing a sequential read operation, the read interface module outputs the read data and the corresponding read address to the downstream external device. The downstream external device records the read address to be used as the readback address for subsequent readback of the asynchronous FIFO device. When the downstream external device needs to read back historical data, the downstream external device sends a readback enable signal and a readback address to the read interface module. The read interface module reads the corresponding readback data from the memory according to the readback enable signal and the readback address, and sends it to the downstream external device, thus realizing the historical data readback of the FIFO device. Compared with the traditional FIFO that supports the readback function, the asynchronous FIFO device of this application does not need to copy a complete data copy (Copy MemoryArray) of the data cached in the dual-port RAM (Dualport memory array) for readback, thus greatly reducing the storage resource requirements of the asynchronous FIFO device. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings required in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 The circuit structure diagram of a traditional heterogeneous first-in-first-out device disclosed in the background art is shown.

[0020] Figure 2The circuit diagram of a conventional first-in-first-out device supporting readback, as disclosed in the background art, is shown.

[0021] Figure 3 This is a circuit diagram of a heterogeneous first-in-first-out device according to an embodiment of this application.

[0022] Figure 4 This is a schematic diagram illustrating the application of a heterogeneous first-in-first-out device in an embodiment of this application. Detailed Implementation

[0023] The detailed description of the accompanying drawings is intended to illustrate the present embodiments of this application and is not intended to represent only the forms in which this application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included within the spirit and scope of this application.

[0024] See Figure 3 One embodiment of this application provides an asynchronous first-in-first-out (FIFO) device, including a write interface module, a read interface module, a read control module, a write control module, a first trigger module, and a memory. The first trigger module includes two levels of triggers, and the memory can be a dual-port SRAM (Dual-port memory array).

[0025] The write interface module is used to receive write enable signals and write data input from upstream external devices. Specifically, in this embodiment, upstream and downstream devices are defined based on the data flow direction. The device that writes data to the FIFO device is upstream in the data flow direction, and the device that receives data output from the FIFO device is downstream in the data flow direction.

[0026] The write control module is used to query the empty vector data structure according to the write enable signal to obtain the current write vector in one-hot binary format, generate a current write address in a preset format based on the current write vector, control the memory to write the data to be written to the memory address corresponding to the current write address, and transmit the current write vector to the read control module through the first trigger module with a delay. The empty vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses. Each bit is used to indicate whether the corresponding memory address is not occupied. That is, the empty vector data structure maintains an empty vector. The vector contains multiple bit values; specifically, each bit in the empty vector data structure has a value of 0 or 1. When any bit is 1, it indicates that the memory address corresponding to that bit is not occupied and data can be written. When any bit is 0, it indicates that the memory address corresponding to that bit is occupied and data cannot be written. The write control module determines the memory address corresponding to bit_m as the current write address by finding the next bit with a value of 1 in the empty vector data structure. At any given time, only one bit in the one-hot binary code is "1", and all other bits are "0". For example, for four states, the one-hot code is represented as: 0001, 0010, 0100, 1000. The current write vector includes multiple bit values, of which only the current write address (Write Vector) is specified. The value of the bit corresponding to the Address is 1, and the value of the remaining bits is 0; the preset format can be decimal, octal, hexadecimal, etc., and can be selected according to technical requirements. In this embodiment, no specific limitation is made; for example, when the 0b00001000 vector is received, it is converted into the decimal format address 3; the first trigger module includes two levels of triggers to realize delayed transmission. The current write vector is delayed and then transmitted to obtain the write delay vector; the write control module manages the values ​​of multiple bits in the empty vector data structure according to the read and write operation of the memory.

[0027] The read control module updates the occupancy vector data structure based on the current write delay vector transmitted by the first trigger module. The occupancy vector data structure includes multiple bits corresponding one-to-one with multiple memory addresses. Each bit indicates whether the corresponding memory address can be read sequentially. Specifically, each bit in the occupancy vector data structure has a value of 0 or 1. When any bit is 1, it indicates that the data at the memory address corresponding to that bit can be read sequentially. When any bit is 0, it indicates that the data at the memory address corresponding to that bit cannot be read sequentially. There are two cases: first, the data at the memory address has been read sequentially but has not yet been cleared and can be read back; second, the data at the memory address has been read sequentially and cleared and cannot be read back. Both cases are represented by bit=0. The read control module determines the memory address corresponding to bit_n as the current sequential read address by finding the next bit with a value of 1 in the occupancy vector data structure. That is, the occupancy vector data structure maintains an occupancy vector. A vector, or occupying vector, contains the value of multiple bits. The read control module manages the values ​​of multiple bits in the occupied vector data structure according to the current write vector (Write DelayVector) transmitted by the first trigger module, and sets one bit in the occupied vector data structure corresponding to the current write vector (Write Delay Vector) transmitted by delay to 1.

[0028] The read control module is further configured to query the occupancy vector data structure to obtain the current sequential read vector in one-hot binary format, generate a current sequential read address in a preset format based on the current sequential read vector, and control the memory to read read data from the corresponding memory address based on the current sequential read address. Specifically, the current read vector includes multiple bit values, where only the bit corresponding to the current sequential read address has a value of 1, and the remaining bits have a value of 0. The preset format can be decimal, octal, hexadecimal, etc., and can be selected according to technical requirements; this embodiment does not impose specific limitations. For example, when the 0b00001000 vector is received, it is converted to the decimal address 3.

[0029] The Read Interface module is used to output the Read Data and the current sequential Read Address to the downstream external device.

[0030] The read interface module is also used to receive a read back enable signal and a read back address in a preset format sent by the downstream external device. Based on the read back enable signal and read back address, it reads the corresponding read back data from the memory and sends it to the downstream external device. Specifically, during sequential read operations, the asynchronous FIFO device in this embodiment returns not only the read data to the downstream device but also the current sequential read address. Therefore, the downstream device records the current sequential read address. When it needs to read back the read data, it sends a read back enable signal and a read back address to the read interface module of the FIFO device in this embodiment. When the read interface module receives the read back data output from the memory, it sends the read back data to the downstream device, realizing the historical data readback of the asynchronous FIFO device. At this time, it is not necessary to send the address again, which is different from the sequential read operation.

[0031] The asynchronous FIFO device in this embodiment uses an occupied vector data structure to record whether each memory address is read sequentially, replacing the traditional read pointer structure; and uses an empty vector data structure to record whether each memory address is occupied, replacing the traditional write pointer structure. Based on the occupied vector data structure, corresponding read addresses can be generated for sequential read operations, and based on the empty vector data structure, corresponding write addresses can be generated for sequential write operations. Simultaneously, the write control module obtains a one-hot binary format current write vector based on the empty vector data structure, and transmits this current write vector to the read control module with a delay via a trigger module. The read control module updates the occupied vector data structure based on this current write vector. By introducing the one-hot binary format empty vector data structure and the occupied vector data structure to replace the traditional Gray code pointer mechanism of asynchronous FIFOs, the FIFO device achieves asynchronous processing across clock domains, thereby solving the technical problems of the Gray code pointer mechanism in traditional asynchronous FIFO devices and reducing the area of ​​the asynchronous FIFO device.

[0032] In this embodiment, when the asynchronous FIFO device performs a sequential read operation, the read interface module outputs the read data and the corresponding read address to the downstream external device. The downstream external device records the read address for subsequent readback address to read back the asynchronous FIFO device. When the downstream external device needs to read back historical data, it sends a readback enable signal and a readback address to the read interface module. The read interface module reads the corresponding readback data from the memory according to the readback enable signal and the readback address, and sends it to the downstream external device, thus realizing the historical data readback of the FIFO device. Compared with traditional FIFO devices that support readback function, the asynchronous FIFO device of this application does not need to copy a complete data copy (CopyMemoryArray) of the data cached in the dual-port RAM (Dualport memory array) for readback, thus greatly reducing the storage resource requirements of the asynchronous FIFO device and reducing the area of ​​the asynchronous FIFO device.

[0033] In some embodiments, the Read Interface module is used to cache the read data and the current sequential read address, and when it receives the sequential read enable signal input from the downstream external device, it outputs the read data and the current sequential read address to the downstream external device together.

[0034] Specifically, the Read Interface module includes a register used to cache the read data and the current sequential read address output by the memory. The current sequential read address can be output to the Read Interface module by the memory or by the Read Control module. After sending the read data and the current sequential read address to the downstream device, the Read Control module sets the value of bit_n in the lookup occupancy vector data structure to 0 and continues to prefetch the read data of the next sequential read and store it in the Read Interface module (see the foregoing for details).

[0035] It should be noted that, in this embodiment, since the sequentially read data and the current sequential read address are pre-registered in the read interface module, the sequential read operation and the readback operation can be performed synchronously. That is, while sending the pre-registered read data and the current sequential read address to the downstream device, the memory can normally output the readback data to the read interface module according to the readback address. The sequential read operation and the readback operation will not conflict, thus realizing the synchronous performance of the sequential read operation and the readback operation and reducing the readback latency.

[0036] In some embodiments, the asynchronous first-in-first-out device further includes an address to vector release module and a second trigger module, the second trigger module including two levels of triggers for delayed data transmission; The Read Interface module is also used to receive a release address in a preset format input by the downstream external device. Specifically, when the downstream device determines that it no longer needs to access a certain historical data of the asynchronous FIFO device, the downstream device will send the storage address of the historical data as the release address to the Read Interface module. The Read Interface module needs to send the release address to the release address conversion vector module for address-to-vector conversion because the Write Control module cannot directly update the empty vector data structure based on the release address.

[0037] The Address to Vector module is used to convert the preset release address into a one-hot binary release vector, and then transmit it to the Write Control module with a delay through the second trigger module. Specifically, the release vector includes multiple bit values, where only the bit corresponding to the release address has a value of 1, and the remaining bits have a value of 0.

[0038] The write control module is also used to update the empty vector data structure according to the release delay vector transmitted by the second trigger module. Specifically, the write control module manages the values ​​of multiple bits in the empty vector data structure according to the release delay vector transmitted by the second trigger module, and sets one bit in the empty vector data structure corresponding to the release delay vector to 1 to indicate that the released address is not occupied and data can be written.

[0039] In some embodiments, the write control module includes a write control unit, an empty vector data structure, a write vector data structure, and a write vector to address unit. The empty vector data structure is used to maintain the empty vector, the write vector data structure is used to maintain the write vector, and the release vector data structure is used to maintain the release delay vector. The empty vector, write vector, and release delay vector each contain a value of multiple bits (0 / 1) that correspond one-to-one with multiple memory addresses. The write control unit is used to query the empty vector data structure according to the write enable signal to obtain the next unoccupied bit corresponding to the memory address of the identifier, and update the write vector data structure according to the next unoccupied bit corresponding to the memory address of the identifier. Specifically, in the empty vector data structure, the value of the bit corresponding to the occupied memory address is 0, and the value of the bit corresponding to the unoccupied memory address is 0. The data reading / writing of the FIFO device is sequential, and the search for the next unoccupied bit corresponding to the memory address of the identifier is also sequential, that is, the next bit with a value of 1 is found sequentially. Then, according to the next unoccupied bit corresponding to the memory address of the identifier, the value of one corresponding bit in the write vector data structure is set to 1, and the values ​​of the remaining bits are set to 0, generating a one-hot binary format write vector. The write control unit is also used to obtain the current write vector in one-hot binary format according to the updated write vector data structure. The write control unit is further configured to transmit the current write vector to the read control module via the first trigger module after a delay; the write vector to address unit is configured to generate a current write address in a preset format based on the current write vector, and input the current write address into the memory, so that the memory writes the data to be written into the memory address corresponding to the current write address according to the write enable signal; In some embodiments, the write control module further includes a release vector data structure and a release vector validation unit (RV Valid). The release vector verification unit is used to verify the release vector (Release Delay Vector) transmitted by the second trigger module with delay. If the verification passes, the release vector data structure (Release delay Vector) is updated according to the release vector transmitted by the second trigger module with delay. Specifically, the verification of the release vector (Release Delay Vector) is to determine whether there is a unique bit in the release vector (Release Delay Vector) with a value of 1. If so, the verification passes; otherwise, the verification fails. The write control unit is further configured to obtain the release delay vector based on the release vector data structure, and update the null vector data structure based on the release delay vector.

[0040] In some embodiments, the write control unit is further configured to send a memory full signal (Full) to the upstream external device according to the null vector data structure, so as to notify the upstream device that it is currently unable to continue writing data to the asynchronous FIFO device; specifically, when the upstream device receives the memory full signal (Full), it will suspend sending write operation requests to the asynchronous FIFO device.

[0041] In some embodiments, the Read Control module includes a Read Control unit, a occupancy vector data structure, a Read Vector data structure, and a Read Vector to Address unit. The read control unit is used to query the occupancy vector data structure to obtain the bit that can be sequentially read from the next identifier corresponding to the storage address, and update the read vector data structure according to the bit that can be sequentially read from the next identifier corresponding to the storage address. Specifically, in the occupancy vector data structure, the bit corresponding to the storage address that can be sequentially read has a value of 1, and the bit corresponding to the storage address that is read out of sequence (readback) has a value of 0. The data reading / writing of the FIFO device is sequential, and the search for the bit that can be sequentially read from the next identifier corresponding to the storage address is also sequential, that is, the next bit with a value of 1 is found sequentially. Then, according to the bit that can be sequentially read from the next identifier corresponding to the storage address, the value of one corresponding bit in the read vector data structure is set to 1, and the values ​​of the remaining bits are all set to 0, generating a one-hot binary format read vector.

[0042] The read control unit is also used to obtain the current read vector in one-hot binary format according to the updated read vector data structure. The Read Vector to Address unit is used to generate a current read address in a preset format based on the current read vector, and input the current read address into the memory so that the memory reads read data from the corresponding memory address based on the current sequential read address. In some embodiments, the read control module includes a delayed write vector data structure and a delayed write vector verification unit; The delayed write vector verification unit is used to verify the current write delay vector of the delayed transmission of the first trigger module. If the verification passes, the delayed write vector data structure is updated according to the current write delay vector. Specifically, the verification of the current write delay vector is to determine whether there is a unique bit with a value of 1 in the current write delay vector. If so, the verification passes; otherwise, the verification fails. The read control unit is further configured to obtain the current write delay vector for delayed transmission based on the delayed write vector data structure, and update the occupancy vector data structure based on the current write delay vector for delayed transmission.

[0043] In some embodiments, the read control unit is further configured to send a memory empty signal to the downstream external device according to the occupancy vector data structure, so as to notify the downstream device that there is currently no data to read in the asynchronous FIFO device; specifically, when the downstream device receives the memory empty signal, it will suspend sending read operation requests to the asynchronous FIFO device.

[0044] The application of the asynchronous FIFO device in this embodiment will be illustrated with examples below, such as... Figure 4 As shown, this embodiment (the part within the dashed box in the figure) is applied to an upper-level buffer module that implements AXI protocol transmission. This AXI output transmission module operates in the r_clk clock domain, while its upstream module operates in the w_clk clock domain. Therefore, cross-clock domain processing needs to be implemented before data transmission. Additionally, this solution also needs to implement data retransmission functionality (e.g., implementing the PCIe protocol's Retry function). The preset format is decimal, and its specific workflow is as follows: At the start of operation, all vectors in the asynchronous FIFO device of this embodiment will be initialized as follows (assuming the designed FIFO depth is 8): Empty Vector = 0b1111 1111; Write Vector = 0b0000 0001; Release Delay Vector = 0b0000 0000; Write Address = 0; Full = 0; Occupy Vector = 0b0000 0000; Read Vector = 0b0000 0000; Write Delay Vector = 0b0000 0000; Read Address = 0; Empty = 1; When an application needs to transmit data downstream via the AXI protocol, it first writes the data into the asynchronous FIFO device in this embodiment. At this time, all vectors inside the asynchronous FIFO device will become: Empty Vector = 0b1111 1110; Write Vector = 0b0000 0010; Release Delay Vector = 0b0000 0000; Write Address = 1; Full = 0; Occupy Vector = 0b0000 0000; Read Vector = 0b0000 0000; Write Delay Vector = 0b0000 0000; Read Address = 0; Empty = 1; At this point, the old value of Write Vector (0b00000001) will be synchronized to Write DelayVector through two levels of triggers, and the relevant variables in the Read Control module will be updated: Empty Vector = 0b1111 1110; Write Vector = 0b0000 0010; Release Delay Vector = 0b0000 0000; Write Address = 1; Full = 0; Occupy Vector = 0b0000 0001; Read Vector = 0b0000 0001; Write Delay Vector = 0b0000 0001; Read Address = 0; Empty = 0; At this point, the written data will be immediately read into Read Data and registered in the read interface module. The read interface module will then set the Read Data Valid bit to 1. When the downstream AXIMaster detects Empty=0, it learns that there is valid data in the asynchronous FIFO device. When the AXI bus is idle, it can set Read Enable to 1. At this time, the read interface module detects Read Data Valid=1, indicating that it should immediately use the Read Address and Read Data registered in the read interface module and send the Read Address and Read Data to the AXIMaster.

[0045] After the AXIMaster obtains the Read Address and Read Data, it can map the ReadAddress to an AWID using the AddrMapID module. Here, the AddrMapID module is used to record the readback address. In practical applications, other technologies can be used to achieve this. The Read Data is then sent downstream. After the AXIMaster obtains the Read Address and Read Data, the internal states of the asynchronous FIFO device in this embodiment are as follows: EmptyVector = 0b1111 1110; WriteVector = 0b0000 0010; ReleaseDelayVector = 0b0000 0000; Write Address = 1; Full = 0; OccupyVector = 0b0000 0000; ReadVector = 0b0000 0001 (The original value is maintained because there is no valid data inside the asynchronous FIFO device) WriteDelayVector = 0b0000 0001; Read Address = 0; Empty = 1; When the upstream device writes data again, the internal state of the asynchronous FIFO device changes as follows: Empty Vector = 0b1111 1100; Write Vector = 0b0000 0100; Release Delay Vector = 0b0000 0000; Write Address = 2; Full = 0; Occupy Vector = 0b0000 0000; Read Vector = 0b0000 0001; Write Delay Vector = 0b0000 0001; Read Address = 0; Empty = 1; After asynchronous operation across clock domains: Empty Vector = 0b1111 1100; Write Vector = 0b0000 0100; Release Delay Vector = 0b0000 0000; Write Address = 2; Full = 0; Occupy Vector = 0b0000 0010; Read Vector = 0b0000 0010; Write Delay Vector = 0b0000 0010; Read Address = 1; Empty = 0; Suppose that AXIMaster decides not to transmit the data at this point; Suppose that the AXIMaster encounters an error when sending the first piece of data, and needs to retransmit the data, the AXIMaster maps the corresponding Read Address that needs to be sent back based on the AXIBID, places it on the Read Back Address, and sets the Read Back Enable signal to 1. In the next cycle, the asynchronous FIFO device in this embodiment will place the read-back data on the Read Back Data, and the AXI can then retransmit the data. Assuming the second AXIMaster retransmission of data is successful, the AXIMaster can release the corresponding FIFO space. At this point, the AXIMaster can map the corresponding Read Address using AXIBID and place it at the Release Address. After the cross-clock domain asynchronous operation, the internal states of this embodiment become: Empty Vector = 0b1111 1101; Write Vector = 0b0000 0100; Release Delay Vector = 0b0000 0001; Write Address = 2; Full = 0; Occupy Vector = 0b0000 0010; Read Vector = 0b0000 0010; Write Delay Vector = 0b0000 0010; Read Address = 1; Empty = 0.

[0046] Another embodiment of this application provides a chip including the asynchronous first-in-first-out device described in the above embodiments.

[0047] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An asynchronous first-in-first-out (FIFO) device, characterized in that, It includes a write interface module, a read interface module, a read control module, a write control module, a first trigger module, and a memory; The write interface module is used to receive the write enable signal and the data to be written from the upstream external device; The write control module is used to query the empty vector data structure according to the write enable signal to obtain the current write vector in one-hot binary format, generate a current write address in a preset format according to the current write vector, control the memory to write the data to be written to the storage address corresponding to the current write address, and transmit the current write vector to the read control module through the first trigger module with a delay. The empty vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses, and each bit is used to identify whether the corresponding memory address is not occupied; The read control module is used to update the occupancy vector data structure according to the current write vector transmitted by the first trigger module with a delay; the occupancy vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses, and each bit is used to identify whether the corresponding memory address can be read sequentially; The read control module is also used to query the occupancy vector data structure to obtain the current sequential read vector in one-hot binary format, generate a current sequential read address in a preset format based on the current sequential read vector, and control the memory to read data from the corresponding memory address based on the current sequential read address. The read interface module is used to send the read data and the current sequential read address to downstream external devices; The read interface module is also used to receive a readback enable signal and a readback address in a preset format sent by a downstream external device, read the corresponding readback data from the memory according to the readback enable signal and the readback address, and send it to the downstream external device.

2. The asynchronous first-in-first-out device according to claim 1, characterized in that, The read interface module is used to cache the read data and the current sequential read address, and when it receives the sequential read enable signal from the downstream external device, it outputs the read data and the current sequential read address to the downstream external device.

3. The asynchronous first-in-first-out device according to claim 1, characterized in that, The asynchronous first-in-first-out device also includes a release address translation vector module and a second trigger module; The read interface module is also used to receive a release address in a preset format input by the downstream external device; The release address conversion vector module is used to convert the preset format release address into a one-hot binary format release vector, and transmit it to the write control module with a delay through the second trigger module; The write control module is also used to update the null vector data structure according to the release vector transmitted by the second trigger module with a delay.

4. The asynchronous first-in-first-out device according to claim 3, characterized in that, The write control module includes a write control unit, an empty vector data structure, a write vector data structure, and a write vector translation address unit; The write control unit is used to query the empty vector data structure according to the write enable signal to obtain the unoccupied bit of the next identifier corresponding to the memory address, and update the write vector data structure according to the unoccupied bit of the next identifier corresponding to the memory address. The write control unit is also used to obtain the current write vector in one-hot binary format according to the updated write vector data structure; The write control unit is also used to transmit the current write vector to the read control module through the first trigger module with a delay; The write vector conversion address unit is used to generate a current write address in a preset format according to the current write vector, and input the current write address into the memory so that the memory writes the data to be written into the storage address corresponding to the current write address.

5. The asynchronous first-in-first-out device according to claim 4, characterized in that, The write control module also includes a release vector data structure and a release vector verification unit; The release vector verification unit is also used to verify the release vector transmitted by the second trigger module with a delay. If the verification passes, the release vector data structure is updated according to the release vector transmitted by the second trigger module with a delay. The write control unit is further configured to obtain a delayed transmission release vector based on the release vector data structure, and update the null vector data structure based on the delayed transmission release vector.

6. The asynchronous first-in-first-out device according to claim 4, characterized in that, The write control unit is also used to send a memory full signal to the upstream external device according to the null vector data structure.

7. The asynchronous first-in-first-out device according to claim 1, characterized in that, The read control module includes a read control unit, an occupancy vector data structure, a read vector data structure, and a read vector translation address unit; The read control unit is used to query the occupancy vector data structure to obtain the bits that can be read sequentially at the storage address corresponding to the next identifier, and update the read vector data structure according to the bits that can be read sequentially at the storage address corresponding to the next identifier; The read control unit is also used to obtain the current read vector in one-hot binary format according to the updated read vector data structure; The read vector conversion address unit is used to generate a current read address in a preset format according to the current read vector, and input the current read address into the memory so that the memory reads the read data from the corresponding memory address according to the current sequential read address.

8. The asynchronous first-in-first-out device according to claim 7, characterized in that, The read control module includes a delayed write vector data structure and a delayed write vector verification unit; The delayed write vector verification unit is used to verify the current write vector of the delayed transmission of the first trigger module. If the verification passes, the delayed write vector data structure is updated according to the current write vector of the delayed transmission. The read control unit is further configured to obtain the current write vector of delayed transmission according to the delayed write vector data structure, and update the occupancy vector data structure according to the current write vector of delayed transmission.

9. The asynchronous first-in-first-out device according to claim 8, characterized in that, The read control unit is also used to send a memory empty signal to the downstream external device according to the occupancy vector data structure.

10. A chip, characterized in that, Includes the asynchronous first-in-first-out device according to any one of claims 1 to 9.

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