An asynchronous first-in-first-out device, chip

Abstract

The application relates to an asynchronous first-in-first-out device and a chip, which comprises a write control module, a read control module and a read interface module. The write control module obtains a current write vector in a one-hot binary format by inquiring an empty vector data structure, generates a current write address according to the current write vector, controls a memory to write to-be-written data into the current write address, and delays and transmits the current write vector to the read control module. The read control module updates an occupation vector data structure according to the delayed and transmitted current write vector. The read control module inquires the occupation vector data structure to obtain a current sequential read vector in a one-hot binary format, generates a current sequential read address according to the current sequential read vector, and controls the memory to read out read data according to the current sequential read address. The read interface module sends the read data and the current sequential read address to a downstream external device. The downstream external device can utilize the current sequential read address to perform readback in the subsequent stage. According to the application, the asynchronous function and the readback function of the FIFO device can be realized, and the area of the asynchronous FIFO device is reduced.

Description

Technical Field

[0001] This application relates to the field of First In First Out (FIFO) structure technology, specifically to an asynchronous FIFO device and chip. Background Technology

[0002] First-In-First-Out (FIFO) is a commonly used circuit structure in modern digital circuits. Its core function is to sequentially store and retrieve data, ensuring the timing consistency of the data flow. Unlike traditional memories (such as RAM), FIFOs do not require external address lines to control the read and write positions. Instead, they manage data by automatically incrementing internal read and write pointers. This characteristic makes them widely used in scenarios involving cross-clock data transmission, data buffering, and data bit width matching. Asynchronous FIFOs are the standard solution for cross-clock data transmission. Their core is to ensure reliable data transmission through a secure pointer synchronization mechanism.

[0003] The traditional asynchronous FIFO circuit structure is as follows: Figure 1 As shown, the main components include a dual-port memory array (Dualport RAM), a Gray code pointer (Dec2Gray), and a read / write comparison logic. The dual-port RAM is primarily used for data storage, with read / write addresses generated from binary pointers. The Gray code pointer is the core of the asynchronous FIFO design, used to convert the read / write pointers into Gray code and synchronize them to the other clock domain via two stages of flip-flops, reducing the risk of metastability. The read / write comparison logic determines the asynchronous FIFO's read / write state by comparing the binary values ​​of the read / write pointers.

[0004] Figure 1 The asynchronous FIFO shown only supports sequential write and sequential read, and cannot achieve random access or readback of historical data. This necessitates the use of external auxiliary modules in scenarios requiring data verification, retransmission, or backtracking (such as communication protocol retransmission, the Retry function in the PCIe protocol, and industrial automation control). The circuit structure of a FIFO currently supporting readback is shown below. Figure 2 As shown, Figure 2The FIFO of the prior art realizes the read-back function by introducing redundant hardware resources, copies a complete data copy (Copy memory array) for read-back in the data buffered in a dual-port memory array (Dualport memory array), and thus increases the storage resource occupation by more than 200%, which is high in hardware cost and large in FIFO area; meanwhile, since the Copy memory array is only a snapshot of the Dualport memory array, the read-back timeline is short, and after the data in the Dualport memory array is read out, the original data is overwritten, at this time, it is impossible to read back the data before the overwriting.

[0005] In addition, Figure 1 The asynchronous FIFO shown in the prior art uses a Gray code conversion module to synchronize the read and write pointers, but the Gray code only supports 2 N depth, and in some application scenarios that do not require 2 N , resources are wasted, and the larger the N value, the more serious the waste, and the flexibility is insufficient; meanwhile, the Gray code conversion module needs to convert the Gray code to binary and also needs to convert the binary to Gray code, and the read and write logics all need related conversion modules, so that the hardware cost of the FIFO device is high and the FIFO area is large. SUMMARY

[0006] The present application aims to provide an asynchronous first-in-first-out device and a chip to reduce the area of the asynchronous FIFO device.

[0007] To achieve the above-mentioned purpose, according to the first aspect of the present application, an asynchronous first-in-first-out device is provided, comprising a write interface module, a read interface module, a read control module, a write control module, a first flip-flop module and a memory;

[0008] The write interface module is configured to receive a write enable signal and to-be-written data input by an upstream external device;

[0009] The write control module is configured to query a current write vector in one-hot binary format from an empty vector data structure according to the write enable signal, generate a current write address in a preset format according to the current write vector, control the memory to write the to-be-written data into a storage address corresponding to the current write address, and transmit the current write vector to the read control module through the first flip-flop module; the empty vector data structure comprises a plurality of bits corresponding one-to-one to a plurality of storage addresses of the memory, and each bit is configured to identify whether the corresponding storage address is unoccupied;

[0010] The read control module is configured to update an occupancy vector data structure according to a current write vector transmitted by the first flip-flop module in a delayed manner; the occupancy vector data structure comprises a plurality of bits corresponding to a plurality of storage addresses of the memory, and each bit is used to identify whether the corresponding storage address can be sequentially read;

[0011] The read control module is further configured to query the occupancy vector data structure to obtain a current sequential read vector in a one-hot binary format, generate a current sequential read address in a preset format according to the current sequential read vector, and control the memory to read out read data from the corresponding storage address according to the current sequential read address;

[0012] The read interface module is configured to send the read data and the current sequential read address to the downstream external device;

[0013] The read interface module is further configured to receive a read-back enable signal and a read-back address in a preset format sent by the downstream external device, read corresponding read-back data from the memory according to the read-back enable signal and the read-back address, and send the read-back data to the downstream external device.

[0014] In some embodiments, the read interface module is configured to buffer the read data and the current sequential read address, and output the read data and the current sequential read address to the downstream external device when a sequential read enable signal of the downstream external device is received.

[0015] In some embodiments, the asynchronous first-in-first-out device further comprises a release address conversion vector module and a second flip-flop module;

[0016] The read interface module is further configured to receive a release address in a preset format input by the downstream external device;

[0017] The release address conversion vector module is configured to convert the release address in the preset format into a release vector in a one-hot binary format, and transmit the release vector to the write control module in a delayed manner through the second flip-flop module;

[0018] The write control module is further configured to update the empty vector data structure according to the release vector transmitted by the second flip-flop module in a delayed manner.

[0019] In some embodiments, the write control module comprises a write control unit, an empty vector data structure, a write vector data structure, and a write vector conversion address unit;

[0020] The write control unit is configured to query the empty vector data structure to obtain a next bit identifying that the corresponding storage address is not occupied according to the write enable signal, and update the write vector data structure according to the next bit identifying that the corresponding storage address is not occupied;

[0021] The write control unit is further configured to obtain a current write vector in a one-hot binary format according to the updated write vector data structure.

[0022] The write control unit is further configured to transmit the current write vector to the read control module through the first flip-flop module.

[0023] The write vector conversion address unit is configured to generate a current write address in a preset format according to the current write vector, and input the current write address into the memory, so that the memory writes the to-be-written data into a storage address corresponding to the current write address.

[0024] In some embodiments, the write control module further includes a release vector data structure and a release vector check unit.

[0025] The release vector check unit is further configured to check the release vector transmitted by the second flip-flop module, and if the check is passed, update the release vector data structure according to the release vector transmitted by the second flip-flop module.

[0026] The write control unit is further configured to obtain a delayed transmission release vector according to the release vector data structure, and update the empty vector data structure according to the delayed transmission release vector.

[0027] In some embodiments, the write control unit is further configured to send a memory full signal to the upstream external device according to the empty vector data structure.

[0028] In some embodiments, the read control module includes a read control unit, an occupancy vector data structure, a read vector data structure, and a read vector conversion address unit.

[0029] The read control unit is configured to query the occupancy vector data structure to obtain a bit corresponding to a next identifier corresponding storage address that can be sequentially read, and update the read vector data structure according to the bit corresponding to the next identifier corresponding storage address that can be sequentially read.

[0030] The read control unit is further configured to obtain a current read vector in a one-hot binary format according to the updated read vector data structure.

[0031] The read vector conversion address unit is configured to generate a current read address in a preset format according to the current read vector, and input the current read address into the memory, so that the memory reads read data from a corresponding storage address according to the current sequential read address.

[0032] In some embodiments, the read control module includes a delayed write vector data structure and a delayed write vector check unit.

[0033] The delay write vector checking unit is configured to check the current write vector delayed transmitted by the first flip-flop module, and if the checking passes, update the delay write vector data structure according to the current write vector delayed transmitted.

[0034] The read control unit is further configured to obtain a current write vector delayed transmitted according to the delay write vector data structure, and update the occupancy vector data structure according to the current write vector delayed transmitted.

[0035] In some embodiments, the read control unit is further configured to send a memory empty signal to the downstream external device according to the occupancy vector data structure.

[0036] According to the second aspect of the present application, a chip is provided, comprising the asynchronous first-in-first-out device.

[0037] The asynchronous first-in-first-out device and the chip have the following beneficial effects:

[0038] (1) The occupancy vector data structure is used to record whether each storage address of the memory is sequentially read, instead of the traditional read pointer structure; the empty vector data structure is used to record whether each storage address of the memory is occupied, instead of the traditional write pointer structure; the corresponding read address for performing the sequential read operation can be generated based on the occupancy vector data structure; the corresponding write address for performing the sequential write operation can be generated based on the empty vector data structure; at the same time, the write control module can obtain a current write vector in the one-hot binary format based on the empty vector data structure, and the current write vector is transmitted to the read control module through the flip-flop module; the read control module updates the occupancy vector data structure based on the current write vector; by introducing the empty vector data structure and the occupancy vector data structure in the one-hot binary format, the Gray code pointer mechanism of the traditional asynchronous FIFO device is replaced, the cross-clock domain asynchronous processing of the FIFO device is realized, and thus the technical problems existing in the Gray code pointer mechanism of the traditional asynchronous FIFO device are solved, and the area of the asynchronous FIFO device is reduced.

[0039] (2) In the execution of the sequential read operation, the read interface module will output the read data and the corresponding read address to the downstream external device, and the downstream external device records the read address as the subsequent read address for reading back the asynchronous FIFO device. When the downstream external device needs to read back the historical data, the downstream external device sends a read back enable signal and a read back address to the read interface module. The read interface module reads the corresponding read back data from the memory according to the read back enable signal and the read back address, and sends it to the downstream external device, realizing the read back of the historical data of the FIFO device. Compared with the traditional FIFO supporting the read back function, the asynchronous FIFO device of the present application can greatly reduce the storage resource requirement of the asynchronous FIFO device, because it does not need to copy a complete data copy (Copy Memory Array) for read back from the data buffered in the dual-port RAM (Dualport memory array). BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0041] Figure 1 The circuit structure diagram of the traditional heterogeneous first-in-first-out device disclosed in the background art.

[0042] Figure 2 The circuit structure diagram of the traditional first-in-first-out device supporting read back disclosed in the background art.

[0043] Figure 3 The circuit structure diagram of a heterogeneous first-in-first-out device in the embodiments of the present application.

[0044] Figure 4 The application diagram of a heterogeneous first-in-first-out device in the embodiments of the present application. DETAILED DESCRIPTION

[0045] The detailed description of the drawings is intended to illustrate the current embodiments of the present application, and is not intended to represent the only form that the present application can be implemented. It should be understood that the same or equivalent functions can be completed by different embodiments intended to be included in the spirit and scope of the present application.

[0046] REFERENCE Figure 3One embodiment of the present application provides an asynchronous first-in-first-out device (FIFO), comprising a write interface module (Write Interface), a read interface module (Read Interface), a read control module (Read Control), a write control module (Write Control), a first flip-flop module and a memory, the first flip-flop module comprising two-stage flip-flops, and the memory can be a dual port memory array.

[0047] The write interface module (Write Interface) is used to receive a write enable signal (Write Enable) and write data (Write Data) input by an upstream external device; specifically, the upstream device and the downstream device in this embodiment are defined based on the data flow direction, and the device writing data into the FIFO device is upstream in the data flow direction, and the device receiving the output data of the FIFO device is downstream in the data flow direction.

[0048] The write control module is configured to query an empty vector data structure according to the write enable signal to obtain a current write vector in a one-hot binary format, generate a current write address in a preset format according to the current write vector, control the memory to write the to-be-written data into a storage address corresponding to the current write address, and transmit the current write vector to the read control module through the first flip-flop module; the empty vector data structure includes a plurality of bits corresponding to a plurality of storage addresses of the memory one by one, each bit is configured to identify whether the corresponding storage address is unoccupied, that is, the empty vector data structure maintains an empty vector, and the empty vector includes values of the plurality of bits; specifically, the value of each bit of the empty vector data structure is 0 or 1, when any bit is 1, it indicates that the storage address corresponding to the any bit is unoccupied and can write data, and when any bit is 0, it indicates that the storage address corresponding to the any bit is occupied and cannot write data; the write control module determines that the storage address corresponding to the bit_m is the current write address by searching for the next bit with a value of 1 in the empty vector data structure, the one-hot binary code has only one bit of "1" and all other bits of "0" at any time, for example, for four states, the one-hot code is represented as: 0001, 0010, 0100, and 1000; the current write vector includes values of a plurality of bits, only the value of the bit corresponding to the current write address is 1, and the values of the other bits are 0; the preset format can be decimal, octal, hexadecimal, etc., which can be selected according to technical requirements, and is not specifically limited in the embodiment; for example, when a 0b00001000 vector is received, it is converted into an address 3 in the decimal format; the first flip-flop module includes two flip-flops to realize delay transmission, and the current write vector is transmitted with a delay to obtain a Write Delay Vector; the write control module manages the values of the plurality of bits in the empty vector data structure according to the read and write operation of the memory.

[0049] The read control module (Read Control) is configured to update an occupancy vector data structure according to a current write delay vector transmitted by the first flip-flop module; the occupancy vector data structure includes a plurality of bits (Bit) corresponding to a plurality of storage addresses of the memory, and each bit (Bit) is configured to identify whether the corresponding storage address can be sequentially read; specifically, the value of each bit of the occupancy vector data structure is 0 or 1, when any bit is 1, it indicates that the data on the storage address corresponding to the bit can be sequentially read, when any bit is 0, it indicates that the data on the storage address corresponding to the bit cannot be sequentially read, there are two cases, the first is that the data on the storage address has been sequentially read but not emptied, which can be read back, the second is that the data on the storage address has been sequentially read and emptied, which cannot be read back, both of which are represented by bit=0 corresponding to the storage address; the read control module determines the storage address corresponding to the bit_n as the current sequential read address (Read Address) by searching for the next bit with a value of 1 in the occupancy vector data structure, that is, the occupancy vector data structure maintains an occupancy vector (Occupy Vector) containing the values of a plurality of bits (Bit);

[0050] The read control module manages the values of a plurality of bits in the occupancy vector data structure according to the current write delay vector transmitted by the first flip-flop module, and sets one bit in the occupancy vector data structure corresponding to the current write delay vector to 1.

[0051] The read control module (Read Control) is further configured to query the occupancy vector data structure to obtain a current sequential read vector (Read Vector) in a one-hot binary format, generate a current sequential read address (Read Address) in a preset format according to the current sequential read vector (Read Vector), and control the memory to read read data (Read Data) from the corresponding storage address according to the current sequential read address (Read Address); specifically, the current read vector (Read Vector) includes a plurality of bit values, wherein only the bit value corresponding to the current sequential read address (Read Address) is 1, and the bit values of the remaining bits are 0; the preset format can be decimal, octal, hexadecimal, etc., which can be selected according to technical requirements, and is not specifically limited in the embodiment; for example, when receiving a 0b00001000 vector, it is converted into a decimal format address 3.

[0052] The read interface module (Read Interface) is used to output the read data (Read Data) and the current sequential read address (Read Address) to the downstream external device.

[0053] The read interface module (Read Interface) is also used to receive the read back enable signal (Read Back Enable) and the preset format of read back address (Read Back Address) sent by the downstream external device, read the corresponding read back data from the memory according to the read back enable signal (Read Back Enable) and the read back address (Read Back Address), and send it to the downstream external device; Specifically, when performing a sequential read operation, the asynchronous FIFO device of the embodiment returns the read data (Read Data) to the downstream device, and also returns the current sequential read address (Read Address) to the downstream device, so that the downstream device records the current sequential read address (Read Address). When it is necessary to read back the read data (Read Data), the read back enable signal (Read Back Enable) and the read back address (Read Back Address) are sent to the read interface module of the FIFO device of the embodiment; When the read interface module (Read Interface) receives the read back data (Read Back Data) output by the memory, it sends the read back data (Read Back Data) to the downstream device, realizing the history data read back of the asynchronous FIFO device. At this time, there is no need to send the address again, which is different from the sequential read operation.

[0054] The asynchronous FIFO device of the embodiment records whether each storage address of the memory is sequentially read by occupying a vector data structure, instead of a conventional read pointer structure; records whether each storage address of the memory is occupied by an empty vector data structure, instead of a conventional write pointer structure; generates a corresponding read address for performing a sequential read operation based on the occupation vector data structure, and generates a corresponding write address for performing a sequential write operation based on the empty vector data structure; at the same time, the write control module can obtain a current write vector in a one-hot binary format based on the empty vector data structure, and the current write vector is transmitted to the read control module through a flip-flop module, and the read control module updates the occupation vector data structure based on the current write vector. By introducing the one-hot binary format of the empty vector data structure and the occupation vector data structure, the traditional asynchronous FIFO gray code pointer mechanism is replaced, the cross-clock domain asynchronous processing of the FIFO device is realized, thereby solving the technical problems existing in the traditional asynchronous FIFO gray code pointer mechanism, and reducing the area of the asynchronous FIFO device.

[0055] When the asynchronous FIFO device of the embodiment performs a sequential read operation, the read interface module outputs the read data and the corresponding read address to the downstream external device, and the downstream external device records the read address for subsequent read-back address read-back to the asynchronous FIFO device. When the downstream external device needs to read back the historical data, the downstream external device sends a read-back enable signal and a read-back address to the read interface module, and the read interface module reads the corresponding read-back data from the memory according to the read-back enable signal and the read-back address, and sends it to the downstream external device, thereby realizing the historical data read-back of the FIFO device. Compared with the conventional FIFO device supporting the read-back function, the asynchronous FIFO device of the present application does not need to copy a complete data copy (CopyMemoryArray) from the data buffered in the dual-port RAM for read-back, so that the storage resource demand of the asynchronous FIFO device can be greatly reduced, and the area of the asynchronous FIFO device can be reduced.

[0056] In some embodiments, the read interface module (Read Interface) is used to buffer the read data (Read Data) and the current sequential read address (Read Address), and when the sequential read enable signal (Read Enable) input by the downstream external device is received, the read data (Read Data) and the current sequential read address (Read Address) are output to the downstream external device.

[0057] Specifically, the read interface module (Read Interface) includes a register for buffering the read data (Read Data) and the current sequential read address (Read Address) output by the memory, which can be output to the read interface module by the memory or output to the read interface module by the read control module (Read Control). After the read data and the current sequential read address are sent to the downstream device, the read control module (Read Control) sets the value of bit_n in the lookup occupancy vector data structure to 0 and continues to prefetch the read data of the next sequential read and register the read data to the read interface module (see the foregoing for details).

[0058] It should be noted that, in the embodiment, the read data (Read Data) and the current sequential read address (Read Address) of the sequential read are pre-registered in the read interface module, so that the sequential read operation and the read-back operation can be performed synchronously, i.e., while the pre-registered read data (Read Data) and the current sequential read address (Read Address) are being sent to the downstream device, the memory can normally output the read-back data (Read Back Data) to the read interface module according to the read-back address (Read Back Address), and the sequential read operation and the read-back operation do not conflict, thereby realizing synchronous sequential read operation and read-back operation and reducing read-back delay.

[0059] In some embodiments, the asynchronous first-in-first-out device further includes a release address to vector module (Address to Vector) and a second flip-flop module, the second flip-flop module including two-stage flip-flops for delaying transmission of data.

[0060] The read interface module (Read Interface) is also configured to receive a release address (Release Address) of a preset format input by the downstream external device. Specifically, when the downstream device determines that it no longer needs to access a certain historical data of the asynchronous FIFO device, the downstream device sends a storage address of the certain historical data to the read interface module (Read Interface) as the release address (Release Address). The read interface module needs to send the release address to the release address to vector module for address-to-vector conversion, because the write control module (Write Control) cannot directly update the empty vector data structure according to the release address.

[0061] The release address conversion vector module (Address to Vector) is configured to convert the release address (Release Address) in the preset format into a release vector (Release Vector) in a one-hot binary format, and transmit the release vector to the write control module (Write Control) through the second flip-flop module; specifically, the release vector includes values of multiple bits, wherein only the bit corresponding to the release address has a value of 1, and the values of the remaining bits are 0.

[0062] The write control module (Write Control) is further configured to update the empty vector data structure according to the release delay vector (Release Delay Vector) transmitted by the second flip-flop module; specifically, the write control module manages the values of multiple bits in the empty vector data structure according to the release delay vector (Release Delay Vector) transmitted by the second flip-flop module, sets one bit in the empty vector data structure corresponding to the release delay vector (Release Delay Vector) to 1, to indicate that the release address is not occupied and data can be written.

[0063] In some embodiments, the write control module (Write Control) includes a write control unit, an empty vector data structure, a write vector data structure, and a write vector conversion address unit (Write Vector to Address);

[0064] The empty vector data structure is configured to maintain an empty vector (Empty Vector), the write vector data structure is configured to maintain a write vector (Write Vector), and the release delay vector data structure is configured to maintain a release delay vector (Release delay Vector); the empty vector (Empty Vector), the write vector (Write Vector), and the release delay vector (Release delay Vector) all include values (0 / 1) of multiple bits corresponding to multiple storage addresses of a memory;

[0065] The write control unit is configured to query the empty vector data structure according to the write enable signal to obtain a next identification corresponding to a storage address unoccupied bit, and update the write vector data structure according to the next identification corresponding to the storage address unoccupied bit; specifically, in the empty vector data structure, the value of the bit corresponding to the occupied storage address is 0, the value of the bit corresponding to the unoccupied storage address is 0, the data reading / writing of the FIFO device is in order, and the query of the next identification corresponding to the storage address unoccupied bit is also in order, that is, the next bit with a value of 1 is found in order; then according to the next identification corresponding to the storage address unoccupied bit, the value of a corresponding bit in the write vector data structure is set to 1, and the values of the remaining bits are set to 0, to generate a write vector (Write Vector) in a one-hot binary format;

[0066] The write control unit is further configured to obtain a current write vector (Write Vector) in a one-hot binary format according to the updated write vector data structure;

[0067] The write control unit is further configured to transmit the current write vector (Write Vector) to the read control module (Read Control) through the first flip-flop module; and the write vector to address unit (Write Vector to Address) is configured to generate a current write address (Write Address) in a preset format according to the current write vector, and input the current write address (Write Address) into the memory, so that the memory writes the write data (Write Data) into a storage address corresponding to the current write address (Write Address) according to the write enable signal (Write Enable);

[0068] In some embodiments, the write control module further includes a release vector data structure and a release vector validation unit (RV Valid);

[0069] The release vector validation unit is configured to validate the release delay vector transmitted by the second flip-flop module, and if the validation is passed, update the release vector data structure (Release delay Vector) according to the release delay vector transmitted by the second flip-flop module; specifically, the validation of the release delay vector (Release Delay Vector) is to determine whether there is only one bit with a value of 1 in the release delay vector (Release Delay Vector); if yes, the validation is passed, otherwise, the validation is not passed;

[0070] The write control unit is further configured to obtain a release delay vector from the release vector data structure, and update the empty vector data structure according to the release delay vector.

[0071] In some embodiments, the write control unit is further configured to send a memory full signal to the upstream external device according to the empty vector data structure, to inform the upstream device that the asynchronous FIFO device is currently unable to continue writing data, and in particular, when the upstream device receives the memory full signal, the upstream device will pause sending a request for a write operation to the asynchronous FIFO device.

[0072] In some embodiments, the read control module includes a read control unit, an occupancy vector data structure, a read vector data structure, and a read vector to address unit.

[0073] The read control unit is configured to query the occupancy vector data structure to obtain a bit corresponding to a next identified storage address that can be sequentially read, and update the read vector data structure according to the bit corresponding to the next identified storage address that can be sequentially read. In particular, in the occupancy vector data structure, a bit corresponding to a storage address that can be sequentially read has a value of 1, and a bit corresponding to a storage address that is not sequentially read (back read) has a value of 0. Data read / write of the FIFO device is sequential, and the bit corresponding to the next identified storage address that can be sequentially read is also sequentially found, i.e., the next bit with a value of 1 is sequentially found. Then, according to the bit corresponding to the next identified storage address that can be sequentially read, a value of a corresponding bit in the read vector data structure is set to 1, and values of the remaining bits are set to 0, to generate a read vector in a one-hot binary format.

[0074] The read control unit is further configured to obtain a current read vector in a one-hot binary format from the updated read vector data structure.

[0075] The read vector to address unit is configured to generate a current read address in a preset format from the current read vector, and input the current read address to the memory, so that the memory reads read data from a corresponding storage address according to the current sequential read address.

[0076] In some embodiments, the read control module includes a delayed write vector data structure and a delayed write vector verification unit;

[0077] The delayed write vector verification unit is used to verify the current write delay vector of the delayed transmission of the first trigger module. If the verification passes, the delayed write vector data structure is updated according to the current write delay vector. Specifically, the verification of the current write delay vector is to determine whether there is a unique bit with a value of 1 in the current write delay vector. If so, the verification passes; otherwise, the verification fails.

[0078] The read control unit is further configured to obtain the current write delay vector for delayed transmission based on the delayed write vector data structure, and update the occupancy vector data structure based on the current write delay vector for delayed transmission.

[0079] In some embodiments, the read control unit is further configured to send a memory empty signal to the downstream external device according to the occupancy vector data structure, so as to notify the downstream device that there is currently no data to read in the asynchronous FIFO device; specifically, when the downstream device receives the memory empty signal, it will suspend sending read operation requests to the asynchronous FIFO device.

[0080] The application of the asynchronous FIFO device in this embodiment will be illustrated with examples below, such as... Figure 4 As shown, this embodiment (the part within the dashed box in the figure) is applied to an upper-level buffer module that implements AXI protocol transmission. This AXI output transmission module operates in the r_clk clock domain, while its upstream module operates in the w_clk clock domain. Therefore, cross-clock domain processing needs to be implemented before data transmission. Additionally, this solution also needs to implement data retransmission functionality (e.g., implementing the PCIe protocol's Retry function). The preset format is decimal, and its specific workflow is as follows:

[0081] At the start of operation, all vectors in the asynchronous FIFO device of this embodiment will be initialized as follows (assuming the designed FIFO depth is 8):

[0082] Empty Vector = 0b1111 1111;

[0083] Write Vector = 0b0000 0001;

[0084] Release Delay Vector = 0b0000 0000;

[0085] Write Address = 0;

[0086] Full = 0;

[0087] Occupy Vector = 0b0000 0000;

[0088] Read Vector = 0b0000 0000;

[0089] Write Delay Vector = 0b0000 0000;

[0090] Read Address = 0;

[0091] Empty = 1;

[0092] When the application has data to be transmitted to the downstream through the AXI protocol, the data will be written into the asynchronous FIFO device of the embodiment first, at this time all the vectors in the asynchronous FIFO device will become:

[0093] Empty Vector = 0b1111 1110;

[0094] Write Vector = 0b0000 0010;

[0095] Release Delay Vector = 0b0000 0000;

[0096] Write Address = 1;

[0097] Full = 0;

[0098] Occupy Vector = 0b0000 0000;

[0099] Read Vector = 0b0000 0000;

[0100] Write Delay Vector = 0b0000 0000;

[0101] Read Address = 0;

[0102] Empty = 1;

[0103] The old value of Write Vector (0b00000001) is synchronized to Write Delay Vector through two flip-flops and the related variable in Read Control is updated:

[0104] Empty Vector = 0b1111 1110;

[0105] Write Vector = 0b0000 0010;

[0106] Release Delay Vector = 0b0000 0000;

[0107] Write Address = 1;

[0108] Full = 0;

[0109] Occupy Vector = 0b0000 0001;

[0110] Read Vector = 0b0000 0001;

[0111] Write Delay Vector = 0b0000 0001;

[0112] Read Address = 0;

[0113] Empty = 0;

[0114] The write data is read to Read Data immediately and stored in the read interface module, and the read data valid bit (Read Data Valid) of the read interface module is set to 1.

[0115] When the downstream AXI Master detects that Empty = 0, it understands that there is valid data in the asynchronous FIFO device, and can set Read Enable to 1 when the AXI bus is idle. At this time, the read interface module detects that Read Data Valid = 1, indicating that the Read Address and Read Data stored in the read interface module are used immediately, and the Read Address and Read Data are sent to the AXI Master.

[0116] After the AXI Master acquires the Read Address and the Read Data, the Read Address can be mapped into the AWID through the AddrMapID module, the AddrMapID module is used here to record the read address, in actual applications other techniques can be used to achieve the same, and the Read Data is sent to the downstream, after the AXI Master acquires the Read Address and the Read Data, the states of each part in the asynchronous FIFO device in the embodiment are as follows:

[0117] Empty Vector = 0b1111 1110;

[0118] Write Vector = 0b0000 0010;

[0119] Release Delay Vector = 0b0000 0000;

[0120] Write Address = 1;

[0121] Full = 0;

[0122] Occupy Vector = 0b0000 0000;

[0123] Read Vector = 0b0000 0001 (since there is no valid data in the asynchronous FIFO device, the original value is maintained)

[0124] Write Delay Vector = 0b0000 0001;

[0125] Read Address = 0;

[0126] Empty = 1;

[0127] The upstream device writes data again, and the states in the asynchronous FIFO device change as follows:

[0128] Empty Vector = 0b1111 1100;

[0129] Write Vector = 0b0000 0100;

[0130] Release Delay Vector = 0b0000 0000;

[0131] Write Address = 2;

[0132] Full = 0;

[0133] Occupy Vector = 0b0000 0000;

[0134] Read Vector = 0b0000 0001;

[0135] Write Delay Vector = 0b0000 0001;

[0136] Read Address = 0;

[0137] Empty = 1;

[0138] Cross clock domain asynchronous later:

[0139] Empty Vector = 0b1111 1100;

[0140] Write Vector = 0b0000 0100;

[0141] Release Delay Vector = 0b0000 0000;

[0142] Write Address = 2;

[0143] Full = 0;

[0144] Occupy Vector = 0b0000 0010;

[0145] Read Vector = 0b0000 0010;

[0146] Write Delay Vector = 0b0000 0010;

[0147] Read Address = 1;

[0148] Empty = 0;

[0149] Suppose AXI Master decides not to transmit this data at this time;

[0150] Suppose AXIMaster sends the first data error, at this time the need to retransmit the data, AXIMaster according to AXIBID mapping out the corresponding need to return the Read Address, and put it on the Read Back Address, and Read Back Enable signal (Read Back Enable) is 1. In the next beat this embodiment asynchronous FIFO device will be placed on the Read Back Data, AXI at this time can retransmit the data;

[0151] Suppose AXIMaster retransmit data success, at this time AXIMaster can release the corresponding FIFO space, at this time AXIMaster can be mapped out by AXIBID corresponding Read Address, and put it on the release address (Release Address). After cross clock domain asynchronous, the various states of this embodiment become:

[0152] Empty Vector = 0b1111 1101;

[0153] Write Vector = 0b0000 0100;

[0154] Release Delay Vector = 0b0000 0001;

[0155] Write Address = 2;

[0156] Full = 0;

[0157] Occupy Vector = 0b0000 0010;

[0158] Read Vector = 0b0000 0010;

[0159] Write Delay Vector = 0b0000 0010;

[0160] Read Address = 1;

[0161] Empty = 0.

[0162] Another embodiment of the application proposes a chip, comprising the above-mentioned embodiment described asynchronous first-in first-out device.

[0163] Having described various embodiments of the application, it is to be understood that the above description is meant not to limit and not to encompass all of the possible embodiments. Many modifications and variations of this application can be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. It is intended that the scope of the application be defined by the scope of the patent and by the claims as allowed by the patent office, which can include adaptations based on the description, equivalents, and / or substitutions of elements individually or collectively to the entire disclosure.

Claims

1. An asynchronous first-in-first-out (FIFO) device, characterized in that, It includes a write interface module, a read interface module, a read control module, a write control module, a first trigger module, and a memory; The write interface module is used to receive the write enable signal and the data to be written from the upstream external device; The write control module is used to query the empty vector data structure according to the write enable signal to obtain the current write vector in one-hot binary format, generate a current write address in a preset format according to the current write vector, control the memory to write the data to be written to the storage address corresponding to the current write address, and transmit the current write vector to the read control module through the first trigger module with a delay. The empty vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses, and each bit is used to identify whether the corresponding memory address is not occupied; The read control module is used to update the occupancy vector data structure according to the current write vector transmitted by the first trigger module with a delay; the occupancy vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses, and each bit is used to identify whether the corresponding memory address can be read sequentially; The read control module is also used to query the occupancy vector data structure to obtain the current sequential read vector in one-hot binary format, generate a current sequential read address in a preset format based on the current sequential read vector, and control the memory to read data from the corresponding memory address based on the current sequential read address. The read interface module is used to send the read data and the current sequential read address to downstream external devices; The read interface module is also used to receive a readback enable signal and a readback address in a preset format sent by a downstream external device, read the corresponding readback data from the memory according to the readback enable signal and the readback address, and send it to the downstream external device.

2. The asynchronous first-in-first-out device according to claim 1, characterized in that, The read interface module is used to cache the read data and the current sequential read address, and when it receives the sequential read enable signal from the downstream external device, it outputs the read data and the current sequential read address to the downstream external device.

3. The asynchronous first-in-first-out device according to claim 1, characterized in that, The asynchronous first-in-first-out device also includes a release address translation vector module and a second trigger module; The read interface module is also used to receive a release address in a preset format input by the downstream external device; The release address conversion vector module is used to convert the preset format release address into a one-hot binary format release vector, and transmit it to the write control module with a delay through the second trigger module; The write control module is also used to update the null vector data structure according to the release vector transmitted by the second trigger module with a delay.

4. The asynchronous first-in-first-out device according to claim 3, characterized in that, The write control module includes a write control unit, an empty vector data structure, a write vector data structure, and a write vector translation address unit; The write control unit is used to query the empty vector data structure according to the write enable signal to obtain the unoccupied bit of the next identifier corresponding to the memory address, and update the write vector data structure according to the unoccupied bit of the next identifier corresponding to the memory address. The write control unit is also used to obtain the current write vector in one-hot binary format according to the updated write vector data structure; The write control unit is also used to transmit the current write vector to the read control module through the first trigger module with a delay; The write vector conversion address unit is used to generate a current write address in a preset format according to the current write vector, and input the current write address into the memory so that the memory writes the data to be written into the storage address corresponding to the current write address.

5. The asynchronous first-in-first-out device according to claim 4, characterized in that, The write control module also includes a release vector data structure and a release vector verification unit; The release vector verification unit is used to verify the release vector transmitted by the second trigger module with a delay. If the verification passes, the release vector data structure is updated according to the release vector transmitted by the second trigger module with a delay. The write control unit is further configured to obtain a delayed transmission release vector based on the release vector data structure, and update the null vector data structure based on the delayed transmission release vector.

6. The asynchronous first-in-first-out device according to claim 4, characterized in that, The write control unit is also used to send a memory full signal to the upstream external device according to the null vector data structure.

7. The asynchronous first-in-first-out device according to claim 1, characterized in that, The read control module includes a read control unit, an occupancy vector data structure, a read vector data structure, and a read vector translation address unit; The read control unit is used to query the occupancy vector data structure to obtain the bits that can be read sequentially at the storage address corresponding to the next identifier, and update the read vector data structure according to the bits that can be read sequentially at the storage address corresponding to the next identifier; The read control unit is also used to obtain the current read vector in one-hot binary format according to the updated read vector data structure; The read vector conversion address unit is used to generate a current read address in a preset format according to the current read vector, and input the current read address into the memory so that the memory reads the read data from the corresponding memory address according to the current sequential read address.

8. The asynchronous first-in-first-out device according to claim 7, characterized in that, The read control module includes a delayed write vector data structure and a delayed write vector verification unit; The delayed write vector verification unit is used to verify the current write vector of the delayed transmission of the first trigger module. If the verification passes, the delayed write vector data structure is updated according to the current write vector of the delayed transmission. The read control unit is further configured to obtain the current write vector of delayed transmission according to the delayed write vector data structure, and update the occupancy vector data structure according to the current write vector of delayed transmission.

9. The asynchronous first-in-first-out device according to claim 8, characterized in that, The read control unit is also used to send a memory empty signal to the downstream external device according to the occupancy vector data structure.

10. A chip, characterized in that, Includes the asynchronous first-in-first-out device according to any one of claims 1 to 9.

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