Data acquisition systems and electronic devices

Abstract

This application discloses a data acquisition system and electronic device, relating to the field of server technology. The data acquisition system includes a motherboard and a switch. The motherboard includes a baseboard management controller, a programmable controller, and a processor. The switch includes a processing unit and a first memory. The processor is connected to the programmable controller, the processing unit is connected to the programmable controller, the baseboard management controller is connected to the processing unit, and the processing unit is connected to the first memory. The programmable controller is used to send a data acquisition signal to the processing unit when the processor crashes. The processing unit is used to acquire log information and register data corresponding to the processing unit based on the data acquisition signal, and store the log information and register data corresponding to the processing unit in the first memory. The baseboard management controller is used to retrieve the log information and register data corresponding to the processing unit from the first memory, enabling maintenance personnel to locate the cause of the server crash.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to data acquisition systems and electronic devices. Background Technology

[0002] Failure or malfunction of devices connected via the high-speed serial computer expansion bus (PCIe) is one of the major causes of server downtime. Therefore, obtaining the status information of PCIe devices when a server crashes is of great importance.

[0003] Currently, when a server crashes, the baseboard management controller (BMC) first waits for a crash indication signal from the system. Upon receiving this signal, the BMC then instructs the processor to begin data acquisition, and the processor controls the processing unit to perform this process. However, this method is time-consuming, which may prevent the BMC from obtaining relevant data from the PCIe devices in a timely manner, thus making it difficult for maintenance personnel to determine the cause of the server crash. Summary of the Invention

[0004] This application provides a data acquisition system and electronic equipment to at least solve the problem in related technologies where maintenance personnel cannot determine the cause of server downtime.

[0005] In a first aspect, this application provides a data acquisition system, comprising: a motherboard and a switch; the motherboard includes a baseboard management controller, a programmable controller, and a processor; the switch includes a processing unit and a first memory, wherein...

[0006] The processor is connected to the programmable controller, the processing unit is connected to the programmable controller, the baseboard management controller is connected to the processing unit, and the processing unit is connected to the first memory;

[0007] Programmable controllers are used to send data acquisition signals to the processing unit when the processor crashes;

[0008] The processing unit is used to collect log information and register data corresponding to the processing unit based on the data acquisition signal, and store the log information and register data corresponding to the processing unit in the first memory;

[0009] The baseboard management controller is used to obtain log information and register data corresponding to the processing unit from the first memory through the processing unit.

[0010] In some embodiments, the motherboard further includes a second memory, wherein...

[0011] The second memory is connected to the baseboard management controller;

[0012] The second memory is used to provide log information and register data corresponding to the processing unit to external devices.

[0013] In some embodiments, after the baseboard management controller obtains the log information and register data corresponding to the processing unit from the first memory through the processing unit, the baseboard management controller is further configured to store the log information and register data corresponding to the processing unit in the second memory.

[0014] In some embodiments, the switch further includes hardware devices, wherein...

[0015] The hardware devices and the processing unit are connected through the processing unit's preset interface;

[0016] The processing unit is also used to collect log information and register data of the hardware device through a preset interface, and store the log information and register data of the hardware device in the first memory. The log information and register data corresponding to the processing unit also include the log information and register data of the hardware device.

[0017] In some embodiments, the programmable controller is also configured to send a data acquisition signal to the baseboard management controller when the processor crashes;

[0018] The data acquisition signal is used to instruct the baseboard management controller to enter the preparation state, which is used to prepare the log information and register data corresponding to the acquisition processing unit.

[0019] In some embodiments, the baseboard management controller is further configured to send a first signal to the processing unit when a data acquisition signal is received, and to receive a feedback signal corresponding to the first signal. The first signal is used to detect whether the processing unit has completed collecting the corresponding log information and register data.

[0020] In some embodiments, when the feedback signal indicates that the log information and register data corresponding to the processing unit have been acquired, the baseboard management controller is further configured to obtain the log information and register data corresponding to the processing unit from the first memory through the processing unit.

[0021] In some embodiments, the processor is configured to send a crash signal to the programmable controller when the processor crashes.

[0022] In some embodiments, the programmable controller is used to perform logical operations on the crash signal to obtain a data acquisition signal, and then send the data acquisition signal to the processing unit.

[0023] Secondly, this application also provides an electronic device, including: a data acquisition system as described in any one of the first aspects.

[0024] The data acquisition system and electronic device provided in this application embodiment, when the processor crashes, the programmable controller sends a data acquisition signal to the processing unit. The processing unit collects the log information and register data corresponding to the processing unit based on the data acquisition signal. This can quickly notify the processing unit to perform data acquisition, shorten the time interval between the processor crash and the triggering of data acquisition, thereby reducing the time consumption of the data acquisition process and improving the efficiency of data acquisition. As a result, before the processor restarts, the processing unit can collect its corresponding complete log information and register data as soon as possible, so that maintenance personnel can access the complete log information and register data corresponding to the processing unit and thus locate the cause of the server crash. Attached Figure Description

[0025] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the server structure provided in this application;

[0027] Figure 2 Schematic diagram of the data acquisition system provided in the embodiments of this application Figure 1 ;

[0028] Figure 3 Schematic diagram of the data acquisition system provided in the embodiments of this application Figure 2 ;

[0029] Figure 4 Schematic diagram of the data acquisition system provided in the embodiments of this application Figure 3 ;

[0030] Figure 5 Schematic diagram of the data acquisition system provided in the embodiments of this application Figure 4 ;

[0031] Figure 6 This is a flowchart illustrating the data acquisition method provided in an embodiment of this application. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0033] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0034] Failure or malfunction of devices connected via the high-speed Serial Computer Expansion Bus (PCIe) is a significant cause of server downtime. Therefore, obtaining the status information of PCIe devices during server downtime is crucial. Devices connected via the PCIe bus can include network interface cards (NICs), solid-state drives (SSDs), graphics processing units (GPUs), redundant arrays of independent disks (RAID) cards, and field-programmable gate arrays (FPGAs), among others.

[0035] Currently, when a server crashes, the baseboard management controller first waits for the system to send a crash indication signal. After receiving the crash indication signal, the baseboard management controller then notifies the processor to start data acquisition. The processor can control the processing unit to acquire data. Here, server crash can be understood as the Central Processing Unit (CPU) crashing or the processor crashing, as mentioned in the following embodiments.

[0036] Figure 1 The schematic diagram of the server provided in this application should be noted as follows: Figure 1 Let's take a server with two processors as an example. Figure 1 As shown, it includes: connector, processor A, processor B, programmable controller, baseboard management controller, memory A, processing unit A, processing unit B, memory B, memory C, GPU0-GPU7.

[0037] Among them, processor A and processor B are connected, processor A is connected to programmable controller, processor B is connected to programmable controller, baseboard management controller is connected to processor A, baseboard management controller is connected to processor B, baseboard management controller is connected to memory A, processor A is connected to processing unit A, processor B is connected to processing unit B, processing unit A is connected to memory B, processing unit B is connected to memory C, processing unit A is connected to GPU0, GPU1, GPU2, and GPU3 respectively, processing unit B is connected to GPU4, GPU5, GPU6, and GPU7 respectively, connector is connected to processor A, and connector is connected to processor B.

[0038] In related technologies, one implementation method for obtaining status information is as follows: When processor A or processor B crashes, processor A and processor B send a signal to the programmable controller. The baseboard management controller determines, via the Inter-Integrated Circuit (I2C) bus, that it has received this signal during programmable control. Upon receiving this signal, the baseboard management controller then uses the Platform Environment Control interface... The PCIe Interface (PECI) bus sends a status acquisition signal to processors A and B. When processors A and B receive this status acquisition signal, processor A sends an instruction to processing unit A via the PCIe bus, and processor B sends an instruction to processing unit B via the PCIe bus. After receiving the instruction, processing unit A collects the status information of processing unit A, GPU0, GPU1, GPU2, and GPU3. After receiving the instruction, processing unit B collects the status information of processing unit B, GPU4, GPU5, GPU6, and GPU7. After processing units A and B complete the collection of status information, they return the status information to processors A and B via the PCIe bus. Then, the board management controller obtains the status information from processors A and B via the PECI bus and stores the status information in memory A.

[0039] In related technologies, another implementation method for obtaining status information is as follows: When processor A or processor B fails, maintenance personnel can connect one end of the debug box to a connector and the other end to their own device. The maintenance personnel then send commands to the connector from the device. The connector sends commands to processor A and processor B via the Joint Test Action Group (JTAG) bus, thereby obtaining the status information. The connector can be an eXtended Debug Port (XDP) connector, and the device can be a device that includes XDP tools.

[0040] However, the data acquisition process in the above method is time-consuming, which may cause the baseboard management controller to fail to obtain relevant data from the PCIe device in a timely manner, thus making it impossible for maintenance personnel to determine the cause of the server downtime.

[0041] To address the aforementioned issues, in this embodiment of the application, the data acquisition system includes: a motherboard and a switch. The motherboard includes a baseboard management controller, a programmable controller, and a processor. The switch includes a processing unit and a first memory. The processor is connected to the programmable controller, the processing unit is connected to the programmable controller, the baseboard management controller is connected to the processing unit, and the processing unit is connected to the first memory. The programmable controller is used to send a data acquisition signal to the processing unit when the processor crashes. The processing unit is used to acquire log information and register data corresponding to the processing unit based on the data acquisition signal, and store the log information and register data corresponding to the processing unit in the first memory. The baseboard management controller is used to obtain the log information and register data corresponding to the processing unit from the first memory through the processing unit.

[0042] In the above method, when the processor crashes, the programmable controller sends a data acquisition signal to the processing unit. The processing unit collects the corresponding log information and register data based on the data acquisition signal. This allows for rapid notification of the processing unit to perform data acquisition, shortening the time interval between processor crash and triggering data acquisition, thereby reducing the time consumption of the data acquisition process and improving the efficiency of data acquisition. As a result, before the processor restarts, the processing unit can collect its corresponding complete log information and register data as soon as possible, enabling maintenance personnel to access the complete log information and register data corresponding to the processing unit and thus locate the cause of the server crash.

[0043] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] refer to Figure 2 , Figure 2 Schematic diagram of the data acquisition system provided in the embodiments of this application Figure 1 ,like Figure 2 As shown, it includes: a motherboard and a switch. The motherboard includes a baseboard management controller, a programmable controller, and a processor. The switch includes a processing unit and a first memory.

[0045] The processor is connected to the programmable controller, the processing unit is connected to the programmable controller, the baseboard management controller is connected to the processing unit, and the processing unit is connected to the first memory;

[0046] Programmable controllers are used to send data acquisition signals to the processing unit when the processor crashes;

[0047] The processing unit is used to collect log information and register data corresponding to the processing unit based on the data acquisition signal, and store the log information and register data corresponding to the processing unit in the first memory;

[0048] The baseboard management controller is used to obtain log information and register data corresponding to the processing unit from the first memory through the processing unit.

[0049] For example, programmable controllers include FPGAs, complex programmable logic devices (CPLDs), and microcontroller units (MCUs).

[0050] In one possible implementation, the first memory can be a storage device with non-volatile characteristics. For example, the first memory can be an electrically erasable programmable read-only memory (EEPROM), NAND flash memory, Serial Peripheral Interface Nor Flash Memory (SPI Nor Flash), etc.

[0051] In one possible implementation, the processing unit and the programmable controller can be connected via a general purpose input / output (GPIO) port, the board management controller and the processing unit can be connected via an I2C interface, the processing unit and the first memory can be connected via a serial peripheral interface (SPI), and the processor and the processing unit can be connected via a PCIe interface.

[0052] In one possible implementation, the data acquisition signal can be either high or low. A low data acquisition signal indicates that the processor in the data acquisition system has crashed; a high data acquisition signal indicates that the processor in the data acquisition system has not crashed.

[0053] In one possible implementation, when the processing unit detects that the data acquisition signal is low, it acquires the log information and register data corresponding to the processing unit and stores the log information and register data corresponding to the processing unit in the first memory.

[0054] In one possible implementation, the baseboard management controller can obtain the log information and register data corresponding to the processing unit from the first memory connected to the processing unit via the I2C bus.

[0055] In this embodiment, when the processor crashes, the programmable controller sends a data acquisition signal to the processing unit. The processing unit collects the log information and register data corresponding to the processing unit based on the data acquisition signal. This allows for rapid notification of the processing unit to perform data acquisition, shortening the time interval between processor crash and triggering data acquisition, thereby reducing the time consumption of the data acquisition process and improving the efficiency of data acquisition. As a result, the processing unit can collect its corresponding complete log information and register data as soon as possible before the processor restarts, enabling maintenance personnel to access the complete log information and register data corresponding to the processing unit and thus locate the cause of the server crash.

[0056] Based on the above embodiments, the motherboard further includes a second memory, which is connected to the baseboard management controller; the second memory is used to provide log information and register data corresponding to the processing unit to external devices.

[0057] Next, combined Figure 3 The data acquisition system provided in the embodiments of this application will be further described below. Figure 3 Schematic diagram of the data acquisition system provided in the embodiments of this application Figure 2 ,like Figure 3 As shown, the motherboard also includes a second memory.

[0058] In one possible implementation, the second memory and the baseboard management controller can be connected via an SPI bus.

[0059] In some implementations, after the baseboard management controller obtains the log information and register data corresponding to the processing unit from the first memory through the processing unit, the baseboard management controller is also used to store the log information and register data corresponding to the processing unit in the second memory.

[0060] In one possible implementation, the second memory can be a memory device with non-volatile characteristics.

[0061] In this embodiment, the log information and register data corresponding to the processing unit are provided to external devices through the second memory without relying on the state of the processor or the first memory. That is, when the processor is unavailable due to a crash, the external device (such as a debugging computer or maintenance terminal) can also obtain data through the second memory without disassembling the server or connecting to special tools (such as XDP tools), which greatly simplifies the data acquisition process and improves maintenance efficiency.

[0062] Based on the above embodiments, the switch also includes a hardware device, wherein the hardware device is connected to the processing unit through a preset interface of the processing unit.

[0063] Next, combined Figure 4 The data acquisition system provided in the embodiments of this application will be further described below. Figure 4 Schematic diagram of the data acquisition system provided in the embodiments of this application Figure 3 ,like Figure 4 As shown, the switch also includes hardware devices.

[0064] In some implementations, the processing unit is also used to collect log information and register data of the hardware device through a preset interface, and store the log information and register data of the hardware device in the first memory. The log information and register data corresponding to the processing unit also include the log information and register data of the hardware device.

[0065] In one possible implementation, the default interface can be a PCIe interface.

[0066] In one possible implementation, the hardware device could be a network card, SSD, GPU, RAID card, or FPGA.

[0067] For example, if the hardware devices connected to the processing unit through a preset interface include device 1 and device 2, then the log information and register data corresponding to the processing unit include: the log information and register data of the processing unit, the log information and register data of device 1, and the log information and register data of device 2.

[0068] In this embodiment of the application, since the cause of server crash may come from the processing unit itself or from any hardware device connected to the processing unit (such as GPU link interruption or network card offline), by collecting the log information and register data of each hardware device, the situation of crash caused by focusing only on the processing unit data and ignoring peripheral failures can be avoided, thereby completely restoring the hardware operating state before the crash.

[0069] Furthermore, by storing the log information and register data of the hardware devices in the first memory, the baseboard management controller can obtain the data of each hardware device from the first memory and store it in the second memory. This eliminates the need for maintenance personnel to extract data from the processing unit and the independent storage of each hardware device. Instead, they can access the second memory to obtain the data, which greatly simplifies the data acquisition process, shortens the time for locating the cause of downtime, and improves maintenance efficiency.

[0070] Based on the above embodiments, the programmable controller is also used to send a data acquisition signal to the baseboard management controller when the processor crashes; the data acquisition signal is used to instruct the baseboard management controller to enter a ready state, and the ready state is used to prepare log information and register data corresponding to the processing unit.

[0071] Based on the above embodiments, the baseboard management controller is also used to send a first signal to the processing unit when it receives a data acquisition signal, and to receive a feedback signal corresponding to the first signal. The first signal is used to detect whether the processing unit has completed collecting the corresponding log information and register data.

[0072] In one possible implementation, the baseboard management controller entering the ready state means that the baseboard management controller polls the processing unit, that is, the baseboard management controller continuously and sequentially determines whether the processing unit has collected the corresponding log information and register data based on a preset period or logic, where the preset period is, for example, 200 milliseconds.

[0073] In one possible implementation, the baseboard management controller can determine whether the processing unit has finished collecting the corresponding log information and register data by sending a first signal to the processing unit.

[0074] In one possible implementation, the feedback signal obtained by the processing unit based on the received first signal can be either high or low. When the feedback signal is high, it can instruct the processing unit to complete the collection of the corresponding log information and register data. Alternatively, when the feedback signal is low, it can instruct the processing unit to complete the collection of the corresponding log information and register data. This application embodiment does not limit this.

[0075] In this embodiment, when the processor crashes, the programmable controller can synchronously send a data acquisition signal to the baseboard management controller, triggering the baseboard management controller to enter the preparation state. This enables the baseboard management controller to complete preparatory work such as hardware communication link initialization and data reception buffer configuration in advance, allowing the processing unit to immediately acquire data after completing data acquisition. This avoids data acquisition delays caused by insufficient preparation, and enables the baseboard management controller to acquire data (log information and register data) in a timely manner before the processor restarts.

[0076] Based on the above embodiments, when the feedback signal indicates that the log information and register data corresponding to the processing unit have been acquired, the baseboard management controller is also used to obtain the log information and register data corresponding to the processing unit from the first memory through the processing unit.

[0077] In one possible implementation, the baseboard management controller can obtain the log information and register data corresponding to the processing unit from the first memory of the processing unit via the I2C interface.

[0078] If the baseboard management controller acquires data before the processing unit has completed its acquisition, it may result in missing key anomaly records in the logs (such as error codes at the moment of the crash) and register data that is not synchronized with the real-time hardware status (such as parameters before the PCIe link interruption), thereby affecting the accuracy of fault location. In this embodiment, however, the baseboard management controller acquires data only after the processing unit has completed its acquisition, ensuring that the baseboard management controller obtains complete and real-time crash data. This avoids debugging deviations caused by incomplete data from the outset and provides a reliable data foundation for accurate subsequent fault location.

[0079] Based on the above embodiments, the processor can be used to send a crash signal to the programmable controller when the processor crashes.

[0080] Based on the above embodiments, the programmable controller is used to perform logical operations on the crash signal to obtain a data acquisition signal, and then send the data acquisition signal to the processing unit.

[0081] In one possible implementation, there can be one or more processors. When a processor crashes, each processor can send a crash signal to the programmable controller. The crash signal can be a high level or a low level. The programmable controller can perform a logical AND operation on the crash signal to obtain a data acquisition signal. For example, if there is only one processor, the data acquisition signal can be the result of a logical AND operation between the crash signal sent by that processor and a high-level base. If there are multiple processors, the data acquisition signal can be the result of a logical AND operation between the crash signals sent by multiple processors.

[0082] In this embodiment of the application, by performing logical operations on the crash signal to obtain the data acquisition signal, and sending the data acquisition signal to the processing unit, the processing unit can be triggered to perform data acquisition as long as any processor crashes. This allows the data acquisition system provided in this embodiment of the application to be adapted to the hardware structure of a multi-processor system.

[0083] Next, combined Figure 5 Taking an example where both the number of processors and the number of processing units are 2, the data acquisition system provided in this application embodiment will be described. For example, Figure 5 Schematic diagram of the data acquisition system provided in the embodiments of this application Figure 4 ,like Figure 5 As shown, it includes: a motherboard and a switch. The motherboard includes processor 1, processor 2, programmable controller, baseboard management controller and memory 1. The switch includes processing unit 1, processing unit 2, memory 2, memory 3, GPU A-GPU H.

[0084] In the motherboard, processor 1 and processor 2 are connected, processor 1 is connected to a programmable controller, processor 2 is connected to a programmable controller, the baseboard management controller is connected to the programmable controller, and the baseboard management controller is connected to memory 1.

[0085] In the switch, processing unit 1 and processing unit 2 are connected, processing unit 1 is connected to memory 2, processing unit 2 is connected to memory 3, processing unit 1 is connected to GPU A, GPU B, GPU C, and GPU D through preset interfaces respectively, and processing unit 2 is connected to GPU E, GPU F, GPU G, and GPU H through preset interfaces respectively.

[0086] In addition, the programmable controller is connected to processing unit 1 and processing unit 2, and the board management controller is connected to processing unit 1 and processing unit 2.

[0087] In one possible implementation, the switch also includes a programmable controller 1. The programmable controller 1 is connected to the programmable controller. Processor 1 and / or processor 2 can send a reset signal to the programmable controller. The programmable controller can send the reset signal to the programmable controller 1. The programmable controller 1 then sends the reset signal to the PCIe device connected to the processing unit 1 and the processing unit 2. After receiving the reset signal, the PCIe device can initialize its parameters.

[0088] An implementation method for obtaining log information and register data corresponding to processing units (including processing unit 1 and processing unit 2) is as follows:

[0089] When processor 1 or processor 2 fails, the maintenance personnel can connect one end of the debugging box to the connector and the other end to the maintenance personnel's device. Then, the maintenance personnel send instructions to the connector on the device. The connector sends instructions to processor 1 and processor 2 through the JTAG bus, thereby obtaining the log information and register data corresponding to the processing units (including processing unit 1 and processing unit 2).

[0090] Another implementation method for obtaining log information and register data corresponding to processing units (including processing unit 1 and processing unit 2) is as follows: Figure 6 , Figure 6 This is a flowchart illustrating a data acquisition method provided in an embodiment of this application. The method includes:

[0091] The S601, motherboard, and switch are powered on and enter the operating system.

[0092] In one possible implementation, the operating system (OS) can be Linux or Windows, etc., but this application does not limit this.

[0093] S602. When the processor crashes, the processor sends a crash signal to the programmable controller.

[0094] In one possible implementation, when processor 1 or processor 2 crashes, processor 1 and processor 2 can send a crash signal to the programmable controller.

[0095] S603 The programmable controller obtains data acquisition signals and data acquisition signals based on the crash signal, and sends the data acquisition signal to processing unit 1 and processing unit 2, and sends the data acquisition signal to the board management controller.

[0096] In one possible implementation, the data acquisition signal and the data acquisition signal can be the same, and can be the result of a logical AND operation on the crash signal.

[0097] In one possible implementation, the programmable controller can send data acquisition signals to the baseboard management controller via the I2C bus, and the programmable controller can send data acquisition signals to processing unit 1 and processing unit 2 via the GPIO interface.

[0098] S604, the substrate management controller sends a first signal to processing unit 1 and processing unit 2 based on the data acquisition signal, and receives a feedback signal corresponding to the first signal sent by processing unit 1 and processing unit 2.

[0099] In one possible implementation, the feedback signal corresponding to the first signal sent by processing unit 1 can indicate whether processing unit 1 has completed collecting the log information and register data corresponding to processing unit 1; the feedback signal corresponding to the first signal sent by processing unit 2 can indicate whether processing unit 2 has completed collecting the log information and register data corresponding to processing unit 2.

[0100] S605, the baseboard management controller, based on the feedback signal, obtains the log information and register data corresponding to the processing unit 1 and / or the processing unit 2 from the memory 2 and / or the memory 3.

[0101] In one possible implementation, when the feedback signal received by the baseboard management controller indicates that the processing unit 1 has completed collecting the log information and register data corresponding to the processing unit 1, the baseboard management controller can send a data upload command to the processing unit 1 via the I2C bus. When the processing unit 1 receives the data upload command, the processing unit 1 will send the log information and register data corresponding to the processing unit 1 stored in the memory 2 to the baseboard management controller.

[0102] S606, the baseboard management controller stores the log information and register data corresponding to processing unit 1 and / or processing unit 2 in memory 1.

[0103] In one possible implementation, memory 1, memory 2, and memory 3 are all non-volatile memories.

[0104] S607, processing unit 1 and processing unit 2 collect log information and register data corresponding to processing unit 1 and processing unit 2 respectively based on the data acquisition signal.

[0105] In one possible implementation, when processing unit 1 receives a data acquisition signal, it begins to acquire the log information and register data corresponding to processing unit 1, that is, it begins to acquire the log information and register data corresponding to processing unit 1, as well as the log information and register data of the PCIe device connected to processing unit 1.

[0106] S608, Processing unit 1 stores the collected log information and register data corresponding to processing unit 1 in memory 2, and processing unit 2 stores the collected log information and register data corresponding to processing unit 2 in memory 3.

[0107] In one possible implementation, processing unit 1 can store the collected log information and register data corresponding to processing unit 1 in memory 2 via the SPI bus, and processing unit 2 can store the collected log information and register data corresponding to processing unit 2 in memory 3 via the SPI bus.

[0108] It should be noted that S604-S606 and S607-S608 can be executed in parallel.

[0109] In this embodiment, the baseboard management controller determines whether the processing unit has completed data acquisition and executes the data acquisition simultaneously with the processing unit. This reduces the time spent acquiring data and avoids data loss due to excessive time consumption. In addition, the baseboard management controller can obtain the log information and register data corresponding to processing unit 1 and processing unit 2 through the memory. This allows maintenance personnel to obtain full-domain data from memory 1 without having to access the memory of multiple processing units separately, simplifying the data acquisition process, reducing the complexity of cross-component maintenance, and shortening the fault diagnosis cycle.

[0110] Based on the above embodiments, an Artificial Intelligence (AI) model can also be deployed on the processor. This AI model can be used to predict the processor's operating state. If a potential processor crash is predicted, the processor can send a crash signal to the programmable controller (PCC), enabling the PCC to control the processing unit to collect data. This allows log information and register data from the processing unit to be collected before a crash occurs, shortening the time required to determine the cause of the crash.

[0111] This application also provides an electronic device that includes the data acquisition system provided in any of the above embodiments. The electronic device may be, for example, a computer, a server, a cloud server, an AI server, etc.

[0112] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0113] The data acquisition system and electronic device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A data acquisition system, characterized by, The data acquisition system comprises a mainboard and a switch, the mainboard comprises a baseboard management controller and a programmable controller device and a processor, and the switch comprises a processing unit and a first memory, wherein, the processor is connected with the programmable controller device, the processing unit is connected with the programmable controller device, the baseboard management controller is connected with the processing unit, and the processing unit is connected with the first memory; the programmable controller device is configured to send a data acquisition signal to the processing unit when the processor is down; the processing unit is configured to acquire log information and register data corresponding to the processing unit based on the data acquisition signal, and store the log information and register data corresponding to the processing unit in the first memory; the baseboard management controller is configured to acquire the log information and register data corresponding to the processing unit in the first memory through the processing unit; the programmable controller device is further configured to send a data acquisition signal to the baseboard management controller when the processor is down, and the data acquisition signal is configured to instruct the baseboard management controller to enter a preparation state, and the preparation state is configured to prepare for acquiring the log information and register data corresponding to the processing unit the baseboard management controller is further configured to send a first signal to the processing unit when the data acquisition signal is received, and receive a feedback signal corresponding to the first signal, and the first signal is configured to detect whether the processing unit has completed acquisition of the corresponding log information and register data; in a case where the feedback signal indicates that the log information and register data corresponding to the processing unit are acquired, the baseboard management controller is further configured to acquire the log information and register data corresponding to the processing unit in the first memory through the processing unit.

2. The system of claim 1, wherein, The mainboard further comprises a second memory, wherein, the second memory is connected with the baseboard management controller; the second memory is configured to provide the log information and register data corresponding to the processing unit to an external device.

3. The system of claim 2, wherein, After the baseboard management controller acquires the log information and register data corresponding to the processing unit in the first memory through the processing unit, the baseboard management controller is further configured to store the log information and register data corresponding to the processing unit in the second memory.

4. The system of claim 1, wherein, The switch further comprises a hardware device, wherein, the hardware device is connected with the processing unit through a preset interface of the processing unit; the processing unit is further configured to acquire log information and register data of the hardware device through the preset interface, and store the log information and register data of the hardware device in the first memory, and the log information and register data corresponding to the processing unit further comprise the log information and register data of the hardware device.

5. The system of claim 1, wherein, The processor is configured to send a down signal to the programmable controller device when the processor is down.

6. The system of claim 5, wherein, The programmable controller device is configured to perform logical operation on the down signal to obtain the data acquisition signal, and send the data acquisition signal to the processing unit.

7. An electronic device, comprising: comprising: The data acquisition system of any one of claims 1 to 6.

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