SiC mosfet behavior modeling method based on physical mechanism optimization

Abstract

The application provides a SiC MOSFET behavior modeling method based on physical mechanism optimization, comprising: for a SiC MOSFET output characteristic curve, constructing a static electrical model structure of the SiC MOSFET on the basis of considering a drain-induced barrier lowering effect of the SiC MOSFET; based on the static electrical model structure, adopting a voltage function to describe nonlinear behavior of an interelectrode capacitance varying with a bias voltage, and constructing a dynamic characteristic model structure of the SiC MOSFET; adopting a method combining experimental data and structure function analysis to perform physical mechanism optimization on the static electrical model structure and the dynamic characteristic model structure, and obtaining a final required SiC MOSFET behavior model. The application can accurately reflect static and dynamic characteristics of the SiC MOSFET device, improve precision, applicability and convenience of parameter extraction of the model, and meet design requirements of a new generation of high-performance power electronic systems.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor device modeling, in particular to a SiC MOSFET behavior modeling method based on physical mechanism optimization, and relates to a corresponding modeling system, a computer terminal and a computer readable storage medium. BACKGROUND

[0002] With the rapid development of new energy, electric vehicles, high-efficiency power supply and other application fields, higher requirements are put forward for the performance of power semiconductor devices under complex working conditions such as high voltage, high frequency and high temperature. Compared with traditional silicon (Si) devices, silicon carbide (SiC) MOSFETs gradually become the mainstream choice of the next generation of high-performance power devices due to their high breakdown field, high thermal conductivity and high electron saturation drift rate. In order to effectively apply SiC devices in circuit simulation, system design and optimization control, an accurate device model must be established, especially an electrical model that can fully reflect the static and dynamic behavior of the device.

[0003] The widely used power device modeling methods, such as SPICE modeling or physical equivalent circuit modeling, mostly originate from the modeling ideas of silicon-based MOSFETs. Such models generally assume a linear or simplified relationship between device parameters and factors such as temperature and voltage, and their static and dynamic characteristics are modeled independently, ignoring the essential differences in material physical properties. For example, SiC MOSFETs have stronger temperature sensitivity, asymmetric conduction characteristics and complex junction capacitance variation behavior, which are not fully reflected in traditional models, resulting in simulation results deviating from the actual device performance under actual working conditions such as high voltage, large current and fast switching, seriously affecting the reliability of system design.

[0004] Specifically:

[0005] Modeling methods based on the SPICE platform, such as SiC MOSFET SPICE models provided by mainstream device manufacturers such as Infineon and ROHM, usually adopt Level 1 or Level 3 model structures, and set the key parameters of the device (such as threshold voltage, mobility, capacitance, etc.) through experimental fitting. Although such models are better in terms of universality, the parameters are highly dependent on experimental fitting, lack direct correlation with physical structure, and the model is difficult to accurately reflect the nonlinear variation behavior of the junction capacitance with bias voltage.

[0006] Based on the physical equivalent modeling mathematical model, the model is usually established from the physical structure, and the static current conduction model and the dynamic switching model are established. The equivalent circuit is often used to describe the parasitic capacitance behavior in the switching process. However, due to the complex electric field distribution and capacitance variation characteristics of SiC material, these models have obvious deficiencies in precision, especially in high-frequency working state, which cannot accurately predict the switching loss and EMI characteristics of the device. Some researches try to introduce a nonlinear junction capacitance model (for example, using a voltage function to fit Cgs, Cgd and Cds, etc.), but the parameter extraction process is complex, and the model structure is not uniform, which makes it difficult to promote and apply.

[0007] In summary, the existing modeling method has not fully considered the uniqueness of SiC MOSFET material and structure, and the model precision and application range still have a large space for improvement, especially in the aspects of device dynamic behavior, inter-electrode capacitance nonlinearity characterization and model parameter extraction method, there is still a lack of systematic and effective solution. Therefore, the existing modeling method usually has the following technical problems:

[0008] 1. Insufficient static characteristic modeling precision: The existing SiC MOSFET modeling method mostly follows the modeling structure and parameter setting of traditional silicon-based MOSFET, and fails to fully reflect the particularity of SiC material in carrier mobility, threshold voltage drift, breakdown field and conduction characteristics, etc., resulting in low simulation precision of the model under high temperature, high voltage and large current conditions, which cannot meet the demand of fine modeling of high-performance devices.

[0009] 2. Limited dynamic characteristic modeling capability: The inter-electrode capacitance (Cgs, Cgd and Cds) of SiC MOSFET has significant nonlinear characteristics, especially under different voltage bias. However, the existing model often uses simplified linear approximation or empirical fitting method, which is difficult to truly reproduce the switching dynamic behavior of the device, thereby affecting the accurate prediction of the switching loss, electromagnetic interference (EMI) and other key performances of the circuit.

[0010] 3. Complex model parameter extraction and poor practicability: The key parameters required in the current modeling process are mostly obtained through complex mathematical fitting or high-cost experiments, and there is a lack of a simple and standardized parameter extraction process. This not only increases the difficulty of model construction, but also limits its promotion and application in different design platforms and actual engineering projects. SUMMARY

[0011] The present application provides a SiC MOSFET behavior modeling method based on physical mechanism optimization, and provides a corresponding modeling system, computer terminal and computer readable storage medium.

[0012] According to one aspect of the present application, a SiC MOSFET behavior modeling method based on physical mechanism optimization is provided, comprising:

[0013] For SiC MOSFET output characteristic curve, on the basis of considering the drain induced barrier lowering (DIBL) effect of SiC MOSFET, a static electrical model structure of SiC MOSFET is constructed;

[0014] Based on the static electrical model structure, a voltage function is used to describe the nonlinear behavior of the inter-electrode capacitance with bias voltage, and a dynamic characteristic model structure of SiC MOSFET is constructed;

[0015] A method combining experimental data and structural function analysis is used to optimize the static electrical model structure and dynamic characteristic model structure, and the final required SiC MOSFET behavior model is obtained.

[0016] Preferably, for SiC MOSFET output characteristic curve, on the basis of considering the drain induced barrier lowering (DIBL) effect of SiC MOSFET, a static electrical model structure of SiC MOSFET is constructed, comprising:

[0017] The drain induced barrier lowering (DIBL) effect of SiC MOSFET is considered;

[0018] For the drain induced barrier lowering (DIBL) effect, the following static electrical model structure is constructed:

[0019]

[0020] In the formula: is the transconductance; is the threshold voltage; is the drain-source voltage; is the gate voltage; is the drain current; is the threshold voltage under different drain-source voltages; is the threshold voltage when the drain-source voltage is zero; is the threshold voltage decay coefficient.

[0021] Preferably, based on the static electrical model structure, a voltage function is used to describe the nonlinear behavior of the inter-electrode capacitance with bias voltage, and a dynamic characteristic model structure of SiC MOSFET is constructed, comprising:

[0022] The inter-electrode capacitance includes: gate-source capacitance , gate-drain capacitance and drain-source capacitance ;

[0023] Gate-drain capacitance described by voltage function The nonlinear behavior that varies with bias voltage is expressed as:

[0024]

[0025] When V GS When =0, V GD =-V DS , where V GS V is the gate voltage. DS This is the drain-source voltage;

[0026] In the formula, S represents the steepness of the curve, which determines the rate at which the capacitance decreases; k1 describes the degree of deviation of the capacitance at low voltage; k2 controls the capacitance as it changes with the gate-drain voltage V. GD The rate of change; C is the depletion region capacitance of the drain region below the gate; oxd The gate oxide capacitance can be extracted from the measurement results; V t This represents the center voltage of the capacitance change, i.e., from C. oxd Towards The inflection point of the transition; C b Indicates the reference capacitance value, i.e. The value tends to stabilize at high voltage;

[0027] Drain-source capacitance is described using a voltage function. The nonlinear behavior that varies with bias voltage is expressed as:

[0028]

[0029] In the formula, D r A is used to describe the decay rate of the capacitor in the low-voltage range; B is used to describe the decay magnitude of the capacitor in the high-voltage range; m is the gradient factor; V j For junction potential; C j0 Indicates the zero-bias PN junction capacitance; C fixed Indicates the progressive capacitance value for the high voltage range; V split Indicates the voltage at the dividing point;

[0030] Gate-source capacitance is described using a voltage function. The nonlinear behavior that varies with bias voltage is expressed as:

[0031]

[0032] In the formula, Parameters used to control the slope of capacitance change; This is the maximum capacitance value in the inversion state; V is the minimum capacitance value in the depletion state; V b V is the center voltage of the capacitance change.

[0033] Preferably, the method of combining experimental data and structure function analysis is used to optimize the static electrical model structure and the dynamic characteristic model structure in terms of physical mechanism, and a final required SiC MOSFET behavior model is obtained, including:

[0034] By experimental data fitting and structure function analysis, the static electrical model structure is optimized in terms of the drain-induced barrier lowering effect of the SiC MOSFET, so that the threshold voltage of the static electrical model structure presents dynamic changes under different drain-source voltages, thereby describing the working characteristics of the device under high voltage;

[0035] By experimental data fitting and structure function analysis, the physical model of the inter-electrode capacitance is optimized for the dynamic characteristic behavior model, so that the dynamic characteristic behavior model accurately describes the non-linear characteristics of the inter-electrode capacitance.

[0036] According to another aspect of the present application, a SiC MOSFET behavior modeling system based on physical mechanism optimization is provided, including:

[0037] A static characteristic model construction module, which, based on the drain-induced barrier lowering effect of the SiC MOSFET, constructs a static electrical model structure of the SiC MOSFET for the output characteristic curve of the SiC MOSFET;

[0038] A dynamic characteristic model construction module, which, based on the static electrical model structure, uses a voltage function to describe the non-linear behavior of the inter-electrode capacitance with respect to the bias voltage, and constructs a dynamic characteristic model structure of the SiC MOSFET;

[0039] A physical mechanism optimization module, which uses a method of combining experimental data and structure function analysis to optimize the static electrical model structure and the dynamic characteristic model structure in terms of physical mechanism, and obtains a final required SiC MOSFET behavior model.

[0040] According to a third aspect of the present application, a computer terminal is provided, including a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the computer program, the computer program can be used to execute the method of any one of the above-mentioned aspects of the present application.

[0041] According to a fourth aspect of the present application, a computer readable storage medium is provided, which stores a computer program, and when the processor executes the computer program, the computer program can be used to execute the method of any one of the above-mentioned aspects of the present application.

[0042] Compared with the prior art, the application has at least one of the following beneficial effects:

[0043] The application establishes a static model with more physical basis according to the essential differences between SiC materials and traditional Si materials in carrier characteristics, thermal performance, threshold voltage drift, etc., and can effectively reflect the current-voltage characteristics of SiC MOSFET under high-temperature and high-voltage working conditions. Compared with the traditional Si MOSFET analogy model, the application significantly improves the modeling accuracy, and is particularly suitable for occasions with high accuracy requirements such as new energy vehicles, photovoltaic inverters, high-frequency converters, etc.

[0044] In the dynamic modeling process, the application introduces a nonlinear function relationship capable of expressing the change of the inter-electrode capacitance 、 and with voltage, which can more truly depict the influence of the change of the capacitance on the behavior of the device during switching. This processing method not only improves the simulation accuracy of the model for key dynamic characteristics such as dv / dt, voltage spikes and switching loss, but also helps to improve the reliability of system-level EMI prediction.

[0045] Compared with the traditional model which depends on experience or complex curve fitting, the application proposes a parameter extraction process based on experimental measurement combined with a structure function method, which greatly reduces the dependence of modeling on high-end test equipment and professional experience. The method has the advantages of strong universality, simple implementation and reusable parameters, and can significantly improve the model development efficiency and facilitate engineering application.

[0046] The modeling method proposed by the application is compatible with mainstream simulation platforms (such as PSPICE, Saber, LTspice, etc.), and can be flexibly integrated into the system-level simulation environment of power electronic systems. Compared with the closed black box model provided by traditional manufacturers, the model structure of the application is open and the parameters are clear, which is convenient for users to customize and optimize according to the specific device or system requirements.

[0047] With the high-precision SiC MOSFET model constructed by the application, engineers can more accurately evaluate the performance of the device under different control strategies and topological structures in the early design stage, thereby reducing the number of repeated tests, shortening the development cycle, optimizing the system design, and ultimately reducing the system cost and development risk. BRIEF DESCRIPTION OF DRAWINGS

[0048] Other features, objects and advantages of the application will become more apparent through reading the following detailed description of the non-limiting embodiments with reference to the accompanying drawings:

[0049] Figure 1This is a flowchart illustrating the process of a SiC MOSFET behavior modeling method based on physical mechanism optimization in a preferred embodiment of the present invention.

[0050] Figure 2 (a) represents the voltage at the dividing point. and the gradual value of capacitance in the high voltage range Extract the schematic diagram, (b) is the drain-source capacitance. Fitting results.

[0051] Figure 3 (a) represents the maximum capacitance value in the inversion state. Minimum capacitance value in the depletion state and the center voltage of the gate-source capacitance variation Extract the schematic diagram, (b) is the gate-source capacitance. Fitting results.

[0052] Figure 4 (a) represents the gate oxide capacitance. The center voltage of the gate-drain capacitance variation and reference capacitance value Extract the schematic diagram, (b) is the gate-drain capacitance. Fitting results.

[0053] Figure 5 This is a schematic diagram of the constituent modules of a SiC MOSFET behavior modeling system based on physical mechanism optimization in a preferred embodiment of the present invention.

[0054] Figure 6 This is a static characteristic curve of a SiC MOSFET. Detailed Implementation

[0055] The embodiments of the present invention are described in detail below: These embodiments are implemented based on the technical solution of the present invention, and provide detailed implementation methods and specific operation processes. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention.

[0056] Existing modeling methods for silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) are mostly based on the traditional modeling approach for silicon-based MOSFETs. They fail to fully consider the differences in electrical and thermal properties of SiC materials and device structures, resulting in insufficient accuracy of the models under high voltage, high frequency, and high temperature conditions, making it difficult to meet the requirements of modern power electronic systems for modeling accuracy and practicality.

[0057] Furthermore, existing SiC MOSFET dynamic characteristic models have low accuracy in nonlinear modeling of inter-electrode capacitances Cgs, Cgd, and Cds, and the modeling parameters mostly rely on experience or complex mathematical fitting, lacking simple and accurate parameter extraction methods. This results in high modeling difficulty and poor applicability, limiting its widespread application in practical circuit simulation and design.

[0058] To address the aforementioned issues, one embodiment of the present invention provides a SiC MOSFET behavior modeling method based on physical mechanism optimization. This method accurately reflects the static and dynamic characteristics of SiC MOSFET devices, improves the accuracy, applicability, and ease of parameter extraction of the model, and meets the design requirements of next-generation high-performance power electronic systems.

[0059] Specifically, such as Figure 1 As shown, the SiC MOSFET behavior modeling method based on physical mechanism optimization provided in this embodiment may include:

[0060] S1. Based on the drain-induced barrier lowering (DIBL) effect of SiC MOSFET, a static electrical model structure of SiC MOSFET is constructed for the output characteristic curve of SiC MOSFET. The output characteristic curve of SiC MOSFET can be provided by Infineon's SiC MOSFET single tube IMW65R039M1H.

[0061] S2, based on the aforementioned static electrical model structure, uses a voltage function to describe the inter-electrode capacitance ( , and The nonlinear behavior of SiC MOSFETs as bias voltage changes was investigated, and a dynamic characteristic model structure was constructed.

[0062] S3. Using a method that combines experimental data and structure function analysis, the physical mechanism of the static electrical model structure and the dynamic characteristic model structure is optimized to obtain the final required SiC MOSFET behavior model.

[0063] In some preferred embodiments, S1 above, which involves constructing a static electrical model structure for the SiC MOSFET output characteristic curve, taking into account the drain-induced barrier lowering (DIBL) effect of the SiC MOSFET, may further include:

[0064] S11, Considering the DIBL effect of SiC MOSFETs, including: the DIBL effect is mainly due to the influence of the drain electric field on the channel region caused by the increase of drain-source voltage; when the drain-source voltage... As the voltage increases, the electric field strength between the drain and the channel increases, which leads to a decrease in the potential barrier from the source to the drain. As a result, the threshold voltage decreases with the increase of the drain-source voltage, which in turn affects the static behavior and dynamic response of the device. Therefore, by introducing a dynamic threshold voltage model, the threshold voltage changes dynamically under different drain-source voltages, thereby more accurately describing the operating characteristics of the device under high voltage.

[0065] S12, as Figure 6 The figure shown is a static characteristic curve of a SiC MOSFET. Figure 6 In the saturation region, when the drain-source voltage increases to a value exceeding the threshold voltage, the conductive channel is pinched off, and conduction ceases. At this point, the drain current no longer increases significantly with increasing voltage but tends to stabilize, primarily controlled by the gate voltage. Therefore, the SiC MOSFET behaves as a current source in this region, with the drain current varying with the gate voltage. The cutoff region is when the gate voltage is less than the threshold voltage; the conductive channel beneath the gate oxide layer is not yet fully formed, preventing the device from conducting. Even with a positive drain-source voltage applied between the drain and source, the drain current remains almost zero, and the device is in a blocking state. The linear region is when the gate voltage is greater than the threshold voltage and the drain-source voltage is less than the threshold voltage; a conductive channel forms beneath the gate oxide layer, and the device enters a conducting state. In this region, the device behaves as a variable resistor, with the drain current linearly related to the drain-source voltage. This stage defines the transconductance, reflecting the device's response to changes in gate voltage. The quasi-saturation region is the transition region between the linear and saturation regions. In this region, the relationship between the drain current and the voltage is parabolic, with the drain current increasing slowly and gradually transitioning to the saturation region. For: the change in drain-source voltage. For: the change in drain current. From Figure 6 Preliminary observations can be made regarding the drain current of the SiC MOSFET. With drain-source voltage and gate voltage The drain current changes with the static characteristics of SiC MOSFETs; therefore, the key to modeling the static characteristics of SiC MOSFETs lies in accurately describing the drain current. With drain-source voltage and gate voltage The relationship between them; for the DIBL effect, the following static electrical model structure is constructed:

[0066]

[0067] In the formula: For transconductance; Threshold voltage; This is the drain-source voltage; This is the gate voltage; This is the drain current; It is the threshold voltage under different drain-source voltages; It is the threshold voltage when the drain-source voltage is zero; It is the threshold voltage attenuation coefficient.

[0068] In step S1 above, based on the physical properties of SiC material in terms of mobility, threshold voltage temperature drift, and conduction mechanism, a static current model that differs from that of traditional Si MOSFETs is established, which can accurately reflect the output characteristics of the device under wide temperature range and high voltage.

[0069] In some preferred embodiments, in S2 above, the voltage function is used to describe the inter-electrode capacitance based on the static electrical model structure. , and The nonlinear behavior of SiC MOSFETs as a function of bias voltage can be further incorporated into the dynamic characteristic model structure, which may include:

[0070] S21, using a voltage function to describe the inter-electrode capacitance. The nonlinear behavior that varies with bias voltage is expressed as:

[0071]

[0072] When V GS When =0, V GD =-V DS , where V GS V is the gate voltage. DS This is the drain-source voltage;

[0073] In the formula, S represents the steepness of the curve, which determines the rate at which the capacitance decreases; k1 describes the degree of deviation of the capacitance at low voltage; k2 controls the capacitance as it changes with the gate-drain voltage V. GD The rate of change; all three parameters were obtained by fitting the measurement data. Gate-drain capacitance; C is the depletion region capacitance of the drain region below the gate. oxd The gate oxide capacitance can be extracted from the measurement results; V t This represents the center voltage of the capacitance change, i.e., from C. oxd Towards The inflection point of the transition is also the point where the slope changes significantly; C b Indicates the reference capacitance value, i.e. The value that tends to stabilize at high voltage; C oxd Cb Both of these parameters can be extracted from the measurement results; C oxd V t and C b The extraction diagram is as follows Figure 4 As shown in (a), the fitting results are as follows: Figure 4 As shown in (b);

[0074] S22 uses a voltage function to describe the inter-electrode capacitance. The nonlinear behavior that varies with bias voltage is expressed as:

[0075]

[0076] In the formula, This represents the drain-source capacitance. (D) r A controls the decay rate of the capacitor in the low-voltage range; B controls the decay amplitude of the capacitor in the high-voltage range; m is the gradient factor; V j The junction potential is given; all five parameters were obtained by fitting measurement data. C j0 This represents the zero-bias PN junction capacitance, which can be expressed as V... DS When =0, the output capacitor C oss Subtract the reverse transfer capacitance C rss Calculated; C fixed Indicates the progressive capacitance value for the high voltage range; V split Indicates the voltage at the dividing point; V split and C fixed All of these can be obtained through measurement results, and the extraction diagram is as follows: Figure 2 As shown in (a), the fitting results are as follows: Figure 2 As shown in (b).

[0077] S23 uses a voltage function to describe the inter-electrode capacitance. The nonlinear behavior that varies with bias voltage is expressed as:

[0078]

[0079] In the formula, This represents the gate-source capacitance. The parameters for controlling the slope of capacitance change are obtained by fitting measurement data. This is the maximum capacitance value in the inversion state; V represents the minimum capacitance value in the depletion state. b The center voltage of the capacitance change; all three parameters can be extracted from the measurement results, as shown in the schematic diagram below. Figure 3 As shown in (a), the fitting results are as follows: Figure 3 As shown in (b).

[0080] In step S2 above, the inter-electrode capacitance is described using a voltage function. , and The nonlinear behavior of the device varies with the bias voltage, thereby accurately characterizing the dynamic changes in capacitance during the switching process and improving the simulation's ability to predict dv / dt, voltage spikes, and switching losses.

[0081] In some preferred embodiments, S3 above, which involves optimizing the physical mechanism of the static electrical model structure and the dynamic characteristic model structure by combining experimental data and structure function analysis to obtain the final required SiCMOSFET behavior model, may further include:

[0082] S31, through experimental data fitting and structure function analysis, the static electrical model structure is optimized so that the threshold voltage of the static electrical model structure changes dynamically under different drain-source voltages, thereby describing the operating characteristics of the device under high voltage.

[0083] S32 optimizes the physical model of the inter-electrode capacitance by fitting experimental data and analyzing the structure function, thereby enabling the dynamic characteristic behavior model to accurately describe its nonlinear characteristics. In addition, it makes the key parameters of the model easier to extract, reducing the difficulty of modeling.

[0084] The dynamic characteristics of SiC MOSFETs are mainly related to the inter-electrode capacitance. , and Therefore, the key to establishing a dynamic characteristic model lies in the accurate modeling of the inter-electrode capacitance. However, datasheets only provide the CV curves of the inter-electrode capacitance under specific operating conditions, which cannot fully reflect its nonlinear characteristics. Therefore, to study the nonlinear characteristics of the inter-electrode capacitance in greater depth, it is necessary to measure the CV curves under different operating conditions to provide experimental data support for the subsequent physical mechanism analysis and dynamic characteristic modeling. Parameter extraction is required to address this issue.

[0085] Step S3 above proposes a parameter extraction method that combines experimental data with structure function analysis, which simplifies the model parameter acquisition process, reduces reliance on high-end equipment and complex fitting, and achieves a more efficient and universal model construction method.

[0086] In S31 above, the DIBL effect of the SiC MOSFET is considered. The DIBL effect is mainly due to the influence of the drain electric field on the channel region caused by the increase in drain-source voltage. When the drain-source voltage... As the drain-source voltage increases, the electric field strength between the drain and the channel increases, leading to a decrease in the potential barrier from the source to the drain. Consequently, the threshold voltage decreases with increasing drain-source voltage, thus affecting the static behavior and dynamic response of the device. Therefore, by introducing a dynamic threshold voltage model, the threshold voltage exhibits dynamic changes under different drain-source voltages, thereby more accurately describing the operating characteristics of the device at high voltages.

[0087] In S32 above, the gate-source capacitance is adjusted using an auxiliary function of the dynamic characteristic behavior model. Gate-drain capacitance and drain-source capacitance The calculation is simplified, which reduces the number of fitting parameters while preserving the physical properties, and makes some key parameters easy to extract. This can effectively reduce the fitting error and preserve the physical properties without relying on fitting or empirical determination.

[0088] Through the above static and dynamic modeling and model optimization process, the static characteristics of SiC MOSFETs can be accurately characterized, fully considering their material properties and conduction behavior under different operating temperatures and voltage conditions, thus improving the accuracy and adaptability of the modeling; it can accurately reflect the nonlinear variation characteristics of the inter-electrode capacitance, enhancing the model's ability to describe dynamic switching processes (such as voltage fluctuations, dv / dt characteristics, etc.), and improving the physical reliability of the simulation results; it can simplify the model parameter extraction process by introducing standardized extraction procedures or structural function relationships, lowering the threshold for model establishment, and improving its practicality and engineering promotion value.

[0089] Based on the same inventive concept, an embodiment of the present invention also provides a SiCMOSFET behavior modeling system based on physical mechanism optimization.

[0090] Specifically, such as Figure 5 As shown, the SiC MOSFET behavior modeling system based on physical mechanism optimization provided in this embodiment may include:

[0091] The static characteristic model construction module constructs a static electrical model structure for SiC MOSFETs based on the output characteristic curves of SiC MOSFETs and taking into account the drain-induced barrier lowering (DIBL) effect of SiC MOSFETs.

[0092] The dynamic characteristic model construction module, based on the static electrical model structure, uses a voltage function to describe the inter-electrode capacitance. , and The nonlinear behavior of SiC MOSFETs as bias voltage changes was investigated, and a dynamic characteristic model structure was constructed.

[0093] The physical mechanism optimization module uses a method combining experimental data and structure function analysis to optimize the physical mechanism of the static electrical model structure and the dynamic characteristic model structure, thereby obtaining the final required SiC MOSFET behavior model.

[0094] It should be noted that the steps in the method provided by the present invention can be implemented using corresponding modules, devices, units, etc. in the system. Those skilled in the art can refer to the technical solution of the method to realize the composition of the system. That is, the embodiments in the method can be understood as preferred examples for building the system, and will not be elaborated here.

[0095] The SiC MOSFET behavior modeling method and system based on physical mechanism optimization provided in the above embodiments of the present invention have significant advantages over existing SiC MOSFET modeling techniques in terms of static characteristic modeling accuracy, dynamic characteristic modeling capability, and parameter extraction methods, specifically in the following aspects:

[0096] 1. Improve modeling accuracy and enhance model applicability:

[0097] This invention addresses the fundamental differences between SiC and traditional Si materials in terms of carrier characteristics, thermal performance, and threshold voltage drift. It establishes a more physically grounded static model that effectively reflects the current-voltage characteristics of SiC MOSFETs under high-temperature and high-voltage conditions. Compared to traditional Si MOSFET analog models, this invention significantly improves modeling accuracy, making it particularly suitable for applications requiring high precision, such as new energy vehicles, photovoltaic inverters, and high-frequency converters.

[0098] 2. Accurately describe the nonlinear dynamic characteristics of inter-electrode capacitance:

[0099] This invention introduces a method capable of expressing... , and The nonlinear functional relationship that varies with voltage can more realistically characterize the impact of capacitance changes on device behavior during switching. This approach not only improves the simulation accuracy of key dynamic characteristics such as dv / dt, voltage spikes, and switching losses, but also helps to improve the reliability of system-level EMI prediction.

[0100] 3. Simplify the parameter extraction process and improve modeling efficiency:

[0101] Compared to traditional models that rely on experience or complex curve fitting, this invention proposes a parameter extraction process based on experimental measurement combined with the structure function method, significantly reducing the reliance on high-end testing equipment and professional experience in modeling. This method has advantages such as high versatility, simple implementation, and reusable parameters, which can significantly improve model development efficiency and facilitate engineering application.

[0102] 4. Enhance the versatility and portability of the model in circuit simulation platforms:

[0103] The modeling method proposed in this invention is compatible with mainstream simulation platforms (such as PSPICE, Saber, LTspice, etc.) and can be flexibly integrated into system-level simulation environments for power electronic systems. Compared with the closed black-box models provided by traditional manufacturers, the model structure of this invention is open and the parameters are clear, making it easy for users to customize and optimize according to specific device or system requirements.

[0104] 5. It helps with system design optimization and cost control:

[0105] With the high-precision SiC MOSFET model constructed by this invention, engineers can more accurately evaluate the performance of devices under different control strategies and topologies in the early stages of design, thereby reducing the number of repeated experiments, shortening the development cycle, optimizing system design, and ultimately reducing system costs and development risks.

[0106] The SiC MOSFET behavior modeling method and system based on physical mechanism optimization provided in the above embodiments of the present invention can accurately characterize the static characteristics of SiC MOSFETs, fully consider their material properties and conduction behavior under different operating temperatures and voltage conditions, and improve the accuracy and adaptability of modeling; it can accurately reflect the nonlinear variation characteristics of inter-electrode capacitance, enhance the model's ability to describe dynamic switching processes (such as voltage fluctuations, dv / dt characteristics, etc.), and improve the physical reliability of simulation results; it can simplify the model parameter extraction process by introducing standardized extraction procedures or structure function relationships, lowering the threshold for model establishment, and improving its practicality and engineering application value. By constructing a SiC MOSFET modeling method that balances accuracy, applicability, and simplicity, the aim is to provide more reliable basic model support for the simulation analysis, device selection, and control strategy design of power electronic systems.

[0107] An embodiment of the present invention also provides a computer terminal, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it can be used to perform any of the methods described in the above embodiments of the present invention.

[0108] Optionally, the memory is used to store programs; the memory may include volatile memory, such as random-access memory (RAM), such as static random-access memory (SRAM), double data rate synchronous dynamic random-access memory (DDR SDRAM), etc.; the memory may also include non-volatile memory, such as flash memory. The memory is used to store computer programs (such as application programs and functional modules that implement the above methods), computer instructions, etc., and the aforementioned computer programs and computer instructions can be partitioned and stored in one or more memories. Furthermore, the aforementioned computer programs, computer instructions, data, etc., can be accessed by the processor.

[0109] A processor is used to execute computer programs stored in memory to implement the various steps of the methods or various modules of the systems involved in the above embodiments. For details, please refer to the relevant descriptions in the preceding method and system embodiments.

[0110] The processor and memory can be separate structures or integrated structures. When the processor and memory are separate structures, they can be coupled together via a bus.

[0111] An embodiment of the present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can be used to perform the method of any of the above embodiments of the present invention.

[0112] Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of computer programs from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Alternatively, the ASIC can reside in a user device. Of course, the processor and storage medium can also exist as discrete components in a communication device.

[0113] Those skilled in the art will understand that, in addition to implementing the system and its various devices provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices of this invention function as logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices provided by this invention can be considered as a hardware component, and the devices included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0114] Any matters not covered in the above embodiments of the present invention are well-known in the art.

[0115] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A SiC MOSFET behavior modeling method based on physical mechanism optimization, characterized in that, include: Based on the output characteristic curve of SiC MOSFET, and considering the drain-induced barrier reduction effect of SiC MOSFET, a static electrical model structure of SiC MOSFET is constructed. Based on the static electrical model structure, a voltage function is used to describe the nonlinear behavior of the inter-electrode capacitance as a function of bias voltage, and a dynamic characteristic model structure of SiC MOSFET is constructed. By combining experimental data with structure function analysis, the physical mechanism of the static electrical model structure and the dynamic characteristic model structure is optimized to obtain the final required SiC MOSFET behavior model. Regarding the output characteristic curve of SiC MOSFET, considering the drain-induced barrier reduction effect of SiC MOSFET, a static electrical model structure of SiC MOSFET is constructed, including: Consider the drain-induced barrier reduction effect of SiC MOSFET; To address the leakage-induced barrier reduction effect, the following static electrical model structure is constructed: In the formula: For transconductance; Threshold voltage; This is the drain-source voltage; This is the gate voltage; This is the drain current; Threshold voltages under different drain-source voltages; This is the threshold voltage when the drain-source voltage is zero. It is the threshold voltage attenuation coefficient; Based on the static electrical model structure, a dynamic characteristic model structure for SiC MOSFETs is constructed by using a voltage function to describe the nonlinear behavior of the inter-electrode capacitance as a function of bias voltage, including: The inter-electrode capacitance includes: gate-source capacitance. Gate-drain capacitance and drain-source capacitance ; Gate-drain capacitance described by voltage function The nonlinear behavior that varies with bias voltage is expressed as: When V GS When =0, V GD =-V DS , where V GS V is the gate voltage. DS This is the drain-source voltage; In the formula, S represents the steepness of the curve, which determines the rate at which the capacitance decreases; k1 describes the degree of deviation of the capacitance at low voltage; k2 controls the capacitance as it changes with the gate-drain voltage V. GD The rate of change; C is the depletion region capacitance of the drain region below the gate; oxd The gate oxide capacitance can be extracted from the measurement results; V t This represents the center voltage of the capacitance change, i.e., from C. oxd Towards The inflection point of the transition; C b Indicates the reference capacitance value, i.e. The value tends to stabilize at high voltage; Drain-source capacitance is described using a voltage function. The nonlinear behavior that varies with bias voltage is expressed as: In the formula, D r A is used to describe the decay rate of the capacitor in the low-voltage range; B is used to describe the decay magnitude of the capacitor in the high-voltage range; m is the gradient factor; V j For junction potential; C j0 Indicates the zero-bias PN junction capacitance; C fixed Indicates the progressive capacitance value for the high voltage range; V split Indicates the voltage at the dividing point; Gate-source capacitance is described using a voltage function. The nonlinear behavior that varies with bias voltage is expressed as: In the formula, Parameters used to control the slope of capacitance change; This is the maximum capacitance value in the inversion state; V represents the minimum capacitance value in the depletion state. b This is the center voltage of the capacitance change.

2. The SiC MOSFET behavior modeling method based on physical mechanism optimization according to claim 1, characterized in that, The consideration of the drain-induced barrier reduction effect of SiC MOSFETs includes: The drain-induced barrier reduction effect is caused by the influence of the drain electric field on the channel region due to the increase in drain-source voltage; when the drain-source voltage... As the voltage increases, the electric field strength between the drain and the channel increases, leading to a decrease in the potential barrier from the source to the drain, thereby reducing the threshold voltage. With drain-source voltage The increase in threshold voltage leads to a decrease, which in turn affects the static behavior and dynamic response of SiC MOSFETs; by considering the dynamic threshold voltage... This allows for different drain-source voltages Below, threshold voltage The dynamic changes are presented to describe the operating characteristics of SiC MOSFETs at high voltages.

3. The SiC MOSFET behavior modeling method based on physical mechanism optimization according to claim 1, characterized in that, The zero-bias PN junction capacitance C j0 , through when V DS When =0, the output capacitor C oss Subtract the reverse transfer capacitance C rss Calculated.

4. The SiC MOSFET behavior modeling method based on physical mechanism optimization according to claim 1, characterized in that, The method employs a combination of experimental data and structure function analysis to optimize the physical mechanism of the static electrical model structure and the dynamic characteristic model structure, thereby obtaining the final required SiC MOSFET behavior model, including: By fitting experimental data and analyzing structural functions, the static electrical model structure is optimized to account for the drain-induced barrier reduction effect of SiC MOSFETs. This optimizes the static electrical model structure so that the threshold voltage changes dynamically under different drain-source voltages, thereby describing the operating characteristics of the device under high voltage. By fitting experimental data and analyzing structure functions, the physical model of the inter-electrode capacitance is optimized for the dynamic characteristic behavior model, so that the dynamic characteristic behavior model can accurately describe the nonlinear characteristics of the inter-electrode capacitance.

5. A SiC MOSFET behavior modeling system based on physical mechanism optimization, characterized in that, include: The static characteristic model construction module constructs a static electrical model structure for SiC MOSFETs based on the output characteristic curves of SiC MOSFETs and taking into account the drain-induced barrier reduction effect of SiC MOSFETs. The dynamic characteristic model construction module, based on the static electrical model structure, uses a voltage function to describe the nonlinear behavior of the inter-electrode capacitance as a function of bias voltage, and constructs the dynamic characteristic model structure of SiC MOSFET. The physical mechanism optimization module uses a method combining experimental data and structure function analysis to optimize the physical mechanism of the static electrical model structure and the dynamic characteristic model structure, so as to obtain the final required SiC MOSFET behavior model. Regarding the output characteristic curve of SiC MOSFET, considering the drain-induced barrier reduction effect of SiC MOSFET, a static electrical model structure of SiC MOSFET is constructed, including: Consider the drain-induced barrier reduction effect of SiC MOSFET; To address the leakage-induced barrier reduction effect, the following static electrical model structure is constructed: In the formula: For transconductance; Threshold voltage; This is the drain-source voltage; This is the gate voltage; This is the drain current; Threshold voltages under different drain-source voltages; This is the threshold voltage when the drain-source voltage is zero. It is the threshold voltage attenuation coefficient; Based on the static electrical model structure, a dynamic characteristic model structure for SiC MOSFETs is constructed by using a voltage function to describe the nonlinear behavior of the inter-electrode capacitance as a function of bias voltage, including: The inter-electrode capacitance includes: gate-source capacitance. Gate-drain capacitance and drain-source capacitance ; Gate-drain capacitance described by voltage function The nonlinear behavior that varies with bias voltage is expressed as: When V GS When =0, V GD =-V DS , where V GS V is the gate voltage. DS This is the drain-source voltage; In the formula, S represents the steepness of the curve, which determines the rate at which the capacitance decreases; k1 describes the degree of deviation of the capacitance at low voltage; k2 controls the capacitance as it changes with the gate-drain voltage V. GD The rate of change; C is the depletion region capacitance of the drain region below the gate; oxd The gate oxide capacitance can be extracted from the measurement results; V t This represents the center voltage of the capacitance change, i.e., from C. oxd Towards The inflection point of the transition; C b Indicates the reference capacitance value, i.e. The value tends to stabilize at high voltage; Drain-source capacitance is described using a voltage function. The nonlinear behavior that varies with bias voltage is expressed as: In the formula, D r A is used to describe the decay rate of the capacitor in the low-voltage range; B is used to describe the decay magnitude of the capacitor in the high-voltage range; m is the gradient factor; V j For junction potential; C j0 Indicates the zero-bias PN junction capacitance; C fixed Indicates the progressive capacitance value for the high voltage range; V split Indicates the voltage at the dividing point; Gate-source capacitance is described using a voltage function. The nonlinear behavior that varies with bias voltage is expressed as: In the formula, Parameters used to control the slope of capacitance change; This is the maximum capacitance value in the inversion state; V represents the minimum capacitance value in the depletion state. b This is the center voltage of the capacitance change.

6. A computer terminal, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it can be used to perform the method of any one of claims 1-4.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program can be used to perform the method of any one of claims 1-4.

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