Chip testing and reproduction methods, apparatus, equipment, and computer-readable storage media

Abstract

A chip testing and reproduction method, apparatus, device, and computer-readable storage medium are disclosed. The method includes: parsing chip test logs and register models used in simulation to obtain register configuration information; modifying configuration sequence files and test case files based on the register configuration information to obtain new configuration sequence files and test case files; and simulating the chip on a verification platform based on the new configuration sequence files and test case files. This application automatically generates the required files and performs simulations, reducing manpower, time, and resource costs; furthermore, simulations can obtain more complete waveforms, improving the efficiency and accuracy of problem localization.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a chip test reproduction method, device, equipment and computer readable storage medium. BACKGROUND

[0002] In the process of chip testing, when problems are encountered, verification personnel usually need to reproduce the chip test scene to obtain error information and corresponding waveforms of the verification platform. The waveforms provide very sufficient information, and chip designers can quickly locate the problem in combination with the waveforms. However, the existing chip test reproduction scheme needs to consume a large amount of manpower and time cost, which increases the chip research and development cost and period. SUMMARY

[0003] The present application provides a chip test reproduction method, device, equipment and computer readable storage medium, which can solve the technical problem of consuming a large amount of manpower in the chip test reproduction scheme in the prior art.

[0004] In a first aspect, an embodiment of the present application provides a chip test reproduction method, which comprises:

[0005] analyzing a chip test log and a register model used for simulation to obtain register configuration information;

[0006] modifying a configuration sequence file and a test case file based on the register configuration information to obtain a new configuration sequence file and a new test case file;

[0007] simulating a chip on a verification platform based on the new configuration sequence file and the new test case file.

[0008] In combination with the first aspect, in an implementation mode, the analyzing the chip test log and the register model used for simulation to obtain the register configuration information comprises:

[0009] analyzing the chip test log to obtain each register address and a corresponding value;

[0010] analyzing the register model used for simulation to obtain each register address and a corresponding register name and register domain name.

[0011] In combination with the first aspect, in an implementation mode, the modifying the configuration sequence file based on the register configuration information to obtain the new configuration sequence file comprises:

[0012] determining, according to the register configuration information, a register name, a register domain name and a value corresponding to a same register address;

[0013] For each register address, a register configuration statement is generated according to the register name, the register domain name and the value corresponding to the register address;

[0014] For each register address, the register configuration statement corresponding to the register address is written into the corresponding position of the register address in the configuration sequence file, to obtain a new configuration sequence file.

[0015] With reference to the first aspect, in an implementation manner, the modifying the test case file based on the register configuration information to obtain a new test case file comprises:

[0016] According to the register configuration information, the register domain name and the value corresponding to each register name are determined, wherein each register name, the register domain name and the value corresponding to the register name correspond to a same register address;

[0017] For each register name, a control statement is generated according to the register domain name and the value corresponding to the register name;

[0018] For each register name, the control statement corresponding to the register name is written into the corresponding position of the register name in the test case file, to obtain a new test case file.

[0019] With reference to the first aspect, in an implementation manner, after the simulating and emulating the chip on the verification platform based on the new configuration sequence file and the test case file, the method further comprises:

[0020] When the simulation error information exists, the error configuration information in the register configuration information that causes the simulation error information is located.

[0021] With reference to the first aspect, in an implementation manner, the locating the error configuration information in the register configuration information that causes the simulation error information comprises:

[0022] The simulation error information is input into a prediction model;

[0023] According to a prediction result output by the prediction model based on the simulation error information, the error configuration information in the register configuration information that causes the simulation error information is located.

[0024] With reference to the first aspect, in an implementation manner, before the locating the error configuration information in the register configuration information that causes the simulation error information, the method further comprises:

[0025] A data set is constructed, each data in the data set is composed of a sample and a corresponding label, the label is a preset error configuration information, and the sample is simulation error information caused by the corresponding label;

[0026] A prediction model is obtained by training a to-be-trained model based on the data set.

[0027] In a second aspect, an embodiment of the present application provides a chip test reproduction device, the chip test reproduction device comprising:

[0028] a parsing module configured to parse a chip test log and a register model used for simulation to obtain register configuration information;

[0029] a generating module configured to modify a configuration sequence file and a test case file based on the register configuration information to obtain a new configuration sequence file and a new test case file;

[0030] a verifying module configured to simulate the chip on a verification platform based on the new configuration sequence file and the new test case file.

[0031] In a third aspect, an embodiment of the present application provides a chip test reproduction device, the chip test reproduction device comprising a processor, a memory, and a chip test reproduction program stored in the memory and executable by the processor, wherein the chip test reproduction program, when executed by the processor, implements the steps of the chip test reproduction method according to the first aspect.

[0032] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, the computer readable storage medium storing a chip test reproduction program, wherein the chip test reproduction program, when executed by a processor, implements the steps of the chip test reproduction method according to the first aspect.

[0033] The technical scheme provided by the embodiments of the present application has the following beneficial effects:

[0034] In the embodiments of the present application, the chip test log and the register model used for simulation are parsed to obtain register configuration information, the configuration sequence file and the test case file are modified based on the register configuration information to obtain a new configuration sequence file and a new test case file, and the chip is simulated on a verification platform based on the new configuration sequence file and the new test case file. Through the embodiments of the present application, the required files are automatically generated and simulated, which reduces the cost of human resources, time and resources; and based on the simulation, more complete waveforms can be obtained, which improves the problem positioning efficiency and accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 FIG. 1 is a flowchart of a chip test reproduction method according to an embodiment of the present application;

[0036] Figure 2 FIG. 2 is a functional module diagram of a chip test reproduction device according to an embodiment of the present application;

[0037] Figure 3This is a schematic diagram of the hardware structure of the chip testing and reproduction equipment involved in the embodiments of this application. Detailed Implementation

[0038] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0039] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0040] In a first aspect, embodiments of this application provide a chip testing and reproduction method.

[0041] In one embodiment, reference is made to Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the chip testing and reproduction method of this application. Figure 1 As shown, the chip test reproduction method includes:

[0042] Step S10: Analyze the chip test log and the register model used for simulation to obtain register configuration information;

[0043] In this embodiment, when a problem occurs during chip testing, the chip test log obtained during chip testing is acquired and parsed to obtain partial information.

[0044] The register model is generated in the simulation environment based on the register information provided by the chip designer. It is part of the simulation platform, so it can be directly obtained and parsed to obtain another part of the information.

[0045] By combining the two pieces of information obtained from the analysis, the register configuration information can be obtained.

[0046] Further, in one embodiment, step S10 includes:

[0047] The chip test logs are parsed to obtain the address and corresponding value of each register; the register model used in the simulation is parsed to obtain the address and corresponding register name and register name of each register.

[0048] In this embodiment, the chip test log is parsed using a script to extract keywords of register addresses and corresponding values. The extracted information can be stored in the form of a table.

[0049] Similarly, the register model used in the simulation is parsed through a script, and the keywords of the register address, corresponding register name, and register domain name are extracted. The extracted information can be saved in the form of a table.

[0050] Step S20: Modify the configuration sequence file and test case file based on the register configuration information to obtain new configuration sequence file and test case file;

[0051] In this embodiment, relevant information in the configuration sequence file and test case file is modified based on the register configuration information to obtain new configuration sequence files and test case files that are compatible with the verification environment.

[0052] Further, in one embodiment, step S20 includes:

[0053] Based on the register configuration information, determine the register name, register name, and value corresponding to the same register address; for each register address, generate a register configuration statement based on its corresponding register name, register name, and value; for each register address, write its corresponding register configuration statement into its corresponding position in the configuration sequence file to obtain a new configuration sequence file.

[0054] In this embodiment, as described above, the correspondence between register addresses and values ​​is obtained by parsing the chip test logs; and the correspondence between register addresses, register names, and register domain names is obtained by parsing the register model used in the simulation. By combining these two correspondences, the register name, register domain name, and value corresponding to the same register address can be determined.

[0055] The configuration sequence file `normal_cfg_seq` is divided into blocks. After recognizing the corresponding keywords, the script fills in the corresponding blocks according to the generated register configuration statements. Specifically, each block corresponds to a register address. By writing the register configuration statement corresponding to the register address into its corresponding block, a new configuration sequence file can be obtained. The register configuration statement corresponding to any register address is as follows:

[0056] reg_model.register_name.register_domain.value.

[0057] Furthermore, in one embodiment, step S20 further includes:

[0058] Based on the register configuration information, determine the register name and value corresponding to each register name, wherein each register name and its corresponding register name and value correspond to the same register address; for each register name, generate control statements based on its corresponding register name and value; for each register name, write its corresponding control statements into its corresponding position in the test case file to obtain a new test case file.

[0059] In this embodiment, similar to obtaining a new configuration sequence file, the test case file Normal_test is divided into blocks. After recognizing the corresponding keywords, the script fills in the corresponding blocks according to the generated control statements. Specifically, each block corresponds to a register name. By writing the control statements corresponding to the register names into their respective blocks, a new test case file can be obtained. The register configuration statements corresponding to any register name are as follows:

[0060] m_cfg.control parameter = value of control parameter.

[0061] Among them, the control parameters are related to the domain names of the configured registers, and the values ​​of the control parameters are related to the values ​​configured.

[0062] Step S30: Simulate the chip on the verification platform based on the new configuration sequence file and test case file.

[0063] In this embodiment, a new configuration sequence file and test case file that are compatible with the verification environment and can be run directly are generated, so that the chip can be simulated on the verification platform.

[0064] There are two existing solutions for reproducing problems that occur during chip testing:

[0065] One chip test reproduction scheme is based on an emulation platform, which instantiates modules in the chip design. It uses a scenario consistent with chip testing to reproduce the chip test. However, downloading waveforms using the emulation platform is time-consuming and limits the downloaded waveforms to a specific timeframe, resulting in incomplete waveform information, increasing the difficulty and efficiency of problem localization. Furthermore, the emulation platform is computationally expensive, consuming significant resources over several iterations. In this embodiment, compared to emulation, simulation offers the following advantages: 1. More complete waveform dump information; 2. Based on existing TB (a verification platform for simulation) and error checking mechanisms, it can assist in quickly locating problems; 3. Simulation consumes fewer resources.

[0066] Another chip test reproduction solution is based on a VCS simulation platform. Chip verification personnel extract the configuration parameters of the corresponding modules from the chip test logs and reload the test sequences and test cases in the verification platform to reproduce the problem. However, in this approach, each time the test log file is updated, verification and testing personnel need to repeatedly confirm the configuration and modify the test sequences and test cases. Manual alignment and modification are prone to errors and require a significant amount of manpower and time. In this embodiment, no manual intervention is required; the configuration sequence files and test case files for simulation can be automatically generated, improving the efficiency and accuracy of generating these files.

[0067] In this embodiment, the chip test log and the register model used for simulation are parsed to obtain register configuration information. Based on the register configuration information, the configuration sequence file and test case file are modified to obtain new configuration sequence files and test case files. Based on the new configuration sequence files and test case files, the chip is simulated on a verification platform. Through this embodiment, the required files are automatically generated and simulated, reducing the manpower, time, and resource costs. Furthermore, simulation can obtain more complete waveforms, improving the efficiency and accuracy of problem localization.

[0068] Furthermore, in one embodiment, after step S30, the method further includes:

[0069] When simulation error information exists, the error configuration information in the register configuration information that caused the simulation error information is located.

[0070] In this embodiment, when a simulation error occurs during chip simulation and a simulation error message is reported, the erroneous configuration information in the register configuration information that caused the simulation error message can be located by downloading the simulation waveform.

[0071] For example, using the Verdi tool to open the simulation waveform, first locate the abnormal interrupt corresponding to the simulation error message. Based on the signal driver traced by the abnormal interrupt and combined with the RTL logic, the location of the RTL error can be deduced. For configuration issues, after tracing the corresponding driver signal, the corresponding configuration register can be seen. Based on locating the configuration register, a configuration error will be found; otherwise, no error would occur. Modify the register value and re-run the simulation. If the error persists, continue modifying until the simulation is correct. After this iterative process, the register causing the current error and the corrected values ​​of the registered registers in the simulation can be obtained. The iterative results are summarized and fed back to the chip testing personnel. Based on the feedback, the chip testing personnel modify the register configuration and run the program on the actual chip to see if the problem is resolved. Summarizing and verifying the iterative process helps the chip testing personnel understand the entire troubleshooting process.

[0072] Furthermore, in one embodiment, locating the error configuration information in the register configuration information that causes the simulation error information includes:

[0073] The simulation error information is input into the prediction model; based on the prediction results output by the prediction model based on the simulation error information, the error configuration information in the register configuration information that caused the simulation error information is located.

[0074] In this embodiment, when simulation error information exists, it is necessary to locate the erroneous configuration information that caused the simulation error information. In order to improve the location efficiency, a prediction model is pre-trained. The input of the prediction model is the simulation error information, and the output is the prediction result related to the erroneous configuration information, so as to locate the problem based on the prediction result.

[0075] Furthermore, in one embodiment, before locating the error configuration information in the register configuration information that causes the simulation error information, the method further includes:

[0076] Construct a dataset, in which each data point consists of a sample and a corresponding label. The label is preset error configuration information, and the sample is simulation error information caused by its corresponding label.

[0077] The model to be trained is trained based on the dataset to obtain the prediction model.

[0078] In this embodiment, for the chip to be tested, the chip's register configuration information is extracted as variable 1. Test cases for abnormal scenarios are constructed, and simulations are performed. Error information from all simulations is extracted as variable 2. Specifically, in chip verification, some abnormal scenarios are constructed to verify the error detection mechanism, such as interrupts. Abnormal scenarios refer to specifically configuring registers incorrectly and then checking whether the corresponding interrupts are reported, and whether any errors are reported during the simulation.

[0079] This embodiment primarily uses the location of incorrect configuration information as an example. The chip can be simulated multiple times in advance, with different pre-set error configuration information for the registers used in each simulation, and the simulation error information that occurs in each simulation is recorded. Based on multiple simulations, a dataset can be constructed, where the simulation error information is used as a sample, and the incorrect configuration information that caused the simulation error is used as a label. The sample and its corresponding label constitute a data entry in the dataset.

[0080] The model to be trained is selected based on actual needs, such as using LightGBM. The training process of training the model based on the dataset is a conventional technique and will not be elaborated here.

[0081] Secondly, embodiments of this application also provide a chip testing and reproduction device.

[0082] In one embodiment, reference is made to Figure 2 , Figure 2 This is a functional module diagram of an embodiment of the chip testing and reproduction device of this application. Figure 2 As shown, the chip test reproduction device includes:

[0083] The parsing module 10 is used to parse the chip test logs and the register model used in the simulation to obtain register configuration information;

[0084] The generation module 20 is used to modify the configuration sequence file and the test case file based on the register configuration information to obtain new configuration sequence files and test case files;

[0085] The verification module 30 is used to simulate the chip on the verification platform based on the new configuration sequence file and test case file.

[0086] Furthermore, in one embodiment, the parsing module 10 is used for:

[0087] The chip test logs are parsed to obtain the address of each register and its corresponding value;

[0088] The register model used in the simulation is parsed to obtain the address of each register and its corresponding register name and register name.

[0089] Furthermore, in one embodiment, the generation module 20 is used for:

[0090] The register name, register name, and value corresponding to the same register address are determined based on the register configuration information.

[0091] For each register address, generate register configuration statements based on its corresponding register name, register name field, and value;

[0092] For each register address, its corresponding register configuration statement is written to its corresponding position in the configuration sequence file to obtain a new configuration sequence file.

[0093] Furthermore, in one embodiment, the generation module 20 is used for:

[0094] The register name and value corresponding to each register name are determined based on the register configuration information, wherein each register name and its corresponding register name and value correspond to the same register address;

[0095] For each register name, generate control statements based on its corresponding register name and value;

[0096] For each register name, its corresponding control statement is written to its corresponding position in the test case file to obtain a new test case file.

[0097] Furthermore, in one embodiment, the chip test reproduction apparatus further includes a positioning module, used for:

[0098] When simulation error information exists, the error configuration information in the register configuration information that caused the simulation error information is located.

[0099] Furthermore, in one embodiment, the positioning module is used for:

[0100] Input the simulation error information into the prediction model;

[0101] Based on the prediction results output by the prediction model based on the simulation error information, the error configuration information in the register configuration information that caused the simulation error information is located.

[0102] Furthermore, in one embodiment, the chip test reproducibility apparatus further includes a training module, used for:

[0103] Construct a dataset, in which each data point consists of a sample and a corresponding label. The label is preset error configuration information, and the sample is simulation error information caused by its corresponding label.

[0104] The model to be trained is trained based on the dataset to obtain the prediction model.

[0105] The functions of each module in the chip test reproducibility device correspond to the steps in the chip test reproducibility method embodiment, and their functions and implementation processes will not be described in detail here.

[0106] Thirdly, embodiments of this application provide a chip testing and reproduction device, which can be a personal computer (PC), laptop computer, server, or other device with data processing capabilities.

[0107] Reference Figure 3 , Figure 3 This is a schematic diagram of the hardware structure of the chip testing and reproduction device involved in the embodiments of this application. In the embodiments of this application, the chip testing and reproduction device may include a processor, a memory, a communication interface, and a communication bus.

[0108] The communication bus can be of any type and is used to interconnect the processor, memory, and communication interface.

[0109] Communication interfaces include input / output (I / O) interfaces, physical interfaces, and logical interfaces used for interconnecting devices within the chip test and reproduction equipment, as well as interfaces used for interconnecting the chip test and reproduction equipment with other devices (such as other computing devices or user equipment). Physical interfaces can be Ethernet interfaces, fiber optic interfaces, ATM interfaces, etc.; user equipment can be displays, keyboards, etc.

[0110] Memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0111] The processor can be a general-purpose processor, which can call the chip test reproducibility program stored in the memory and execute the chip test reproducibility method provided in the embodiments of this application. For example, the general-purpose processor can be a central processing unit (CPU). The method executed when the chip test reproducibility program is called can be referred to in the various embodiments of the chip test reproducibility method of this application, and will not be repeated here.

[0112] Those skilled in the art will understand that Figure 3 The hardware structure shown does not constitute a limitation of this application and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0113] Fourthly, embodiments of this application also provide a computer-readable storage medium.

[0114] The present application provides a computer-readable storage medium storing a chip test reproducibility program, wherein when the chip test reproducibility program is executed by a processor, it implements the steps of the chip test reproducibility method described above.

[0115] The method implemented when the chip test reproduction program is executed can be referred to in various embodiments of the chip test reproduction method of this application, and will not be repeated here.

[0116] It should be noted that the sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0117] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.

[0118] In the description of the embodiments of this application, terms such as "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a concrete manner.

[0119] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0120] In some processes described in the embodiments of this application, multiple operations or steps are included in a specific order. However, it should be understood that these operations or steps may not be executed in the order they appear in the embodiments of this application, or they may be executed in parallel. The sequence number of the operation is only used to distinguish different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed sequentially or in parallel, and these operations or steps may be combined.

[0121] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device to execute the methods described in the various embodiments of this application.

[0122] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method of chip test reproduction, characterized by, The chip test reproduction method comprises the following steps: parsing a chip test log and a register model used for simulation to obtain register configuration information; modifying a configuration sequence file and a test case file based on the register configuration information to obtain a new configuration sequence file and a new test case file; simulating and testing the chip on a verification platform based on the new configuration sequence file and the new test case file; the parsing of the chip test log and the register model used for simulation to obtain the register configuration information comprises the following steps: parsing the chip test log to obtain each register address and a corresponding value; parsing the register model used for simulation to obtain each register address, a corresponding register name and a register domain name; the modification of the configuration sequence file based on the register configuration information to obtain the new configuration sequence file comprises the following steps: determining, according to the register configuration information, a register name, a register domain name and a value corresponding to a same register address; generating, for each register address, a register configuration statement according to the register name, the register domain name and the value corresponding to the register address; writing, for each register address, the register configuration statement corresponding to the register address into a corresponding position of the configuration sequence file to obtain the new configuration sequence file; the modification of the test case file based on the register configuration information to obtain the new test case file comprises the following steps: determining, according to the register configuration information, a register domain name and a value corresponding to each register name, wherein each register name, the register domain name and the value corresponding to the register name correspond to a same register address; generating, for each register name, a control statement according to the register domain name and the value corresponding to the register name; writing, for each register name, the control statement corresponding to the register name into a corresponding position of the test case file to obtain the new test case file.

2. The chip test replication method of claim 1, wherein, after the simulating and testing of the chip on the verification platform based on the new configuration sequence file and the new test case file, the method further comprises the following steps: when there is simulation error information, locating error configuration information in the register configuration information that causes the simulation error information.

3. The chip test replication method of claim 2, wherein, the locating of the error configuration information in the register configuration information that causes the simulation error information comprises the following steps: inputting the simulation error information into a prediction model; locating, according to a prediction result output by the prediction model based on the simulation error information, the error configuration information in the register configuration information that causes the simulation error information.

4. The chip test replication method of claim 3, wherein, before the locating of the error configuration information in the register configuration information that causes the simulation error information, the method further comprises the following steps: constructing a data set, each piece of data in the data set being composed of a sample and a corresponding label, the label being a preset error configuration information, and the sample being simulation error information caused by the corresponding label; training a to-be-trained model based on the data set to obtain the prediction model.

5. A chip test reproduction apparatus characterized by comprising: the chip test reproduction device comprises: a parsing module configured to parse a chip test log to obtain each register address and a corresponding value, and parse a register model used for simulation to obtain each register address, a corresponding register name and a register domain name; The generating module is configured to determine register names, register domain names and values corresponding to the same register address; for each register address, generate a register configuration statement according to the register name, the register domain name and the value corresponding to the register address; for each register address, write the register configuration statement corresponding to the register address to a corresponding position of the register address in the configuration sequence file to obtain a new configuration sequence file; determine the register domain name and the value corresponding to each register name, wherein each register name, the register domain name and the value corresponding to the register name correspond to the same register address; for each register name, generate a control statement according to the register domain name and the value corresponding to the register name; and for each register name, write the control statement corresponding to the register name to a corresponding position of the register name in the test case file to obtain a new test case file. The verifying module is configured to simulate and emulate the chip on a verification platform based on the new configuration sequence file and the test case file.

6. A chip test reproduction apparatus characterized by comprising: The chip test reproduction device includes a processor, a memory, and a chip test reproduction program stored on the memory and executable by the processor, wherein the chip test reproduction program, when executed by the processor, implements the steps of the chip test reproduction method according to any one of claims 1 to 4.

7. A computer readable storage medium characterized by The computer readable storage medium stores a chip test reproduction program, wherein the chip test reproduction program, when executed by the processor, implements the steps of the chip test reproduction method according to any one of claims 1 to 4.

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