Shift register circuit and driving method thereof, gate driving circuit and display device

Abstract

The invention provides a shift register circuit and a driving method thereof, a gate driving circuit and a display device, and the shift register circuit comprises an input sub-circuit which is configured to electrically connect an input end with a first node based on a signal of a first clock signal end; the input control sub-circuit is configured to electrically connect a first power supply signal end with a second node based on the potential of the first node; the output sub-circuit is configured to control the on-off of an output end and a first power supply signal end and the on-off of the output end and a second clock signal end based on the potentials of the second node and the first node; and the protection sub-circuit is electrically connected to the first node, the protection control end and the first power supply signal end, and is configured to electrically connect the first power supply signal end with the first node based on a signal of the protection control end. According to the embodiment of the invention, short-circuit electric leakage between the first power signal end and the second power signal end can be avoided.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register circuit and its driving method, a gate driving circuit and a display device. Background Technology

[0002] In organic light-emitting diode (OLED) display products, the shift register circuit is an essential circuit. Its output signal serves as the driving signal for the pixel circuit. Therefore, the output signal of the shift register circuit directly affects the refresh and display of the display panel. Thus, the output stability of the shift register circuit is very important.

[0003] However, current shift register circuits suffer from short circuits at the high and low power supply terminals, leading to unstable power signals, abnormal output, and increased circuit power consumption. Summary of the Invention

[0004] To address at least one of the aforementioned problems, a first aspect of this disclosure provides a shift register circuit, comprising: An input sub-circuit is electrically connected to the input terminal, the first node, and the first clock signal terminal, and is configured to electrically connect the input terminal and the first node based on the signal from the first clock signal terminal. The input control sub-circuit is electrically connected to the first node, the second node, and the first power signal terminal, and is configured to electrically connect the first power signal terminal to the second node based on the potential of the first node. An output sub-circuit, electrically connected to a first node, a second node, a first power supply signal terminal, a second clock signal terminal, and an output terminal, is configured to control the on / off state of the output terminal and the first power supply signal terminal, and the on / off state of the output terminal and the second clock signal terminal, based on the potentials of the second node and the first node; and The protection sub-circuit is electrically connected to the first node, the protection control terminal, and the first power signal terminal, and is configured to electrically connect the first power signal terminal to the first node based on the signal from the protection control terminal.

[0005] Optionally, the protection sub-circuit includes: a first transistor, the first electrode of the first transistor being electrically connected to a first power supply signal terminal, the second electrode being electrically connected to a first node, and the control electrode being electrically connected to a protection control terminal, the protection control terminal being connected to a third clock signal or a signal from the output terminal of the next-stage shift register circuit.

[0006] Optionally, it further includes: a first voltage regulator circuit, which is electrically connected to a first node, a second node, a third node, a first power supply signal terminal and a second clock signal terminal, and is configured to electrically connect the first power supply signal terminal to the third node based on the potential of the first node and to electrically connect the second clock signal terminal to the second node based on the potential of the third node.

[0007] Optionally, the shift register circuit further includes: a second voltage regulator circuit, which is electrically connected to the first node, the second node, the fourth node, the second clock signal terminal, and the first power supply signal terminal, and is configured to electrically connect the first power supply signal terminal to the fourth node based on the potential of the second node and to electrically connect the first node to the fourth node based on the signal of the second clock signal terminal.

[0008] Optionally, the shift register circuit further includes: a third voltage regulator circuit, which is electrically connected to the second node, the second power supply signal terminal, and the third voltage regulation control terminal, and configures the second power supply signal terminal to be electrically connected to the second node based on the signal of the third voltage regulation control terminal.

[0009] Optionally, the input sub-circuit includes a second transistor, the first electrode of the second transistor is electrically connected to the input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal terminal; The input control sub-circuit includes a third transistor, the first electrode of which is electrically connected to the first power signal terminal, the second electrode of which is electrically connected to the second node, and the control electrode of which is electrically connected to the first node. The output sub-circuit includes a fourth transistor, a fifth transistor, a first capacitor, and a second capacitor. The first electrode of the fourth transistor is electrically connected to the first power supply signal terminal, the second electrode is electrically connected to the output terminal, and the control electrode is electrically connected to the second node. The first electrode of the fifth transistor is electrically connected to the second clock signal terminal, the second electrode is electrically connected to the output terminal, and the control electrode is electrically connected to the first node. The first electrode of the first capacitor is electrically connected to the second node, and the second electrode is electrically connected to the first power supply signal terminal. The first electrode of the second capacitor is electrically connected to the first node, and the second electrode is electrically connected to the output terminal.

[0010] Optionally, the first voltage regulator circuit includes a sixth transistor, a seventh transistor, and a third capacitor. The first electrode of the sixth transistor is electrically connected to the second clock signal terminal, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the third node. The first electrode of the seventh transistor is electrically connected to the first power supply signal terminal, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the first node. The first electrode of the third capacitor is electrically connected to the second clock signal terminal, and the second electrode is electrically connected to the third node.

[0011] Optionally, the second voltage regulator circuit includes an eighth transistor and a ninth transistor. The first electrode of the eighth transistor is electrically connected to the first power supply signal terminal, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the second node. The first electrode of the ninth transistor is electrically connected to the fourth node, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the second clock signal terminal.

[0012] Optionally, the third voltage regulator circuit includes a tenth transistor, the first electrode of the tenth transistor is electrically connected to the second node, the second electrode is electrically connected to the second power supply signal terminal, the control electrode is electrically connected to the output terminal of the next-stage shift register circuit, and the third voltage regulator control terminal is electrically connected to the output terminal of the next-stage shift register circuit.

[0013] Optionally, the output sub-circuit is electrically connected to the first node through a fourth voltage regulator sub-circuit. The fourth voltage regulator sub-circuit includes an eleventh transistor, the first electrode of which is electrically connected to the first node, the second electrode of which is electrically connected to the control electrode of the fifth transistor, and the control electrode is electrically connected to the second power supply signal terminal.

[0014] A second aspect of this disclosure provides a gate drive circuit, comprising: a plurality of cascaded shift register circuits as described above.

[0015] Optionally, the protection control terminal can be used as a third clock signal terminal to receive a third clock signal; The first clock signal terminal of the 3n-2 stage shift register circuit is electrically connected to the first clock signal line, the second clock signal terminal is electrically connected to the second clock signal line, and the third clock signal terminal is electrically connected to the third clock signal line. The first clock signal terminal of the 3n-1 stage shift register circuit is electrically connected to the second clock signal line, the second clock signal terminal is electrically connected to the third clock signal line, and the third clock signal terminal is electrically connected to the first clock signal line. The first clock signal terminal of the 3n stage shift register circuit is electrically connected to the third clock signal line, the second clock signal terminal is electrically connected to the first clock signal line, and the third clock signal terminal is electrically connected to the second clock signal line; or The first clock signal terminal of the 4n-3 stage shift register circuit is electrically connected to the first clock signal line, the second clock signal terminal is electrically connected to the second clock signal line, and the third clock signal terminal is electrically connected to the third clock signal line. The first clock signal terminal of the 4n-2 stage shift register circuit is electrically connected to the fourth clock signal terminal, the second clock signal terminal is electrically connected to the first clock signal line, and the third clock signal terminal is electrically connected to the second clock signal line. The first clock signal terminal of the 4n-1 stage shift register circuit is electrically connected to the third clock signal line, the second clock signal terminal is electrically connected to the fourth clock signal line, and the third clock signal terminal is electrically connected to the first clock signal line. The first clock signal terminal of the 4n stage shift register circuit is electrically connected to the second clock signal line, the second clock signal terminal is electrically connected to the third clock signal line, and the third clock signal terminal is electrically connected to the fourth clock signal line. Where n is an integer greater than or equal to 1.

[0016] A third aspect of this disclosure provides a display device including the gate driving circuit described above.

[0017] A fourth aspect of this disclosure provides a driving method for a shift register circuit as described above, comprising: In the first stage, the input sub-circuit transmits the valid level of the input terminal to the first node based on the valid level of the signal connected to the first clock signal terminal, and the input control sub-circuit transmits the potential of the first power supply signal terminal to the second node based on the potential of the first node. In the second stage, the output sub-circuit transmits the valid level signal connected to the second clock signal terminal to the output terminal based on the valid level of the first node's potential. In the third stage, the protection sub-circuit transmits the signal from the first power signal terminal to the first node based on the signal of the protection control terminal being at an effective level, and the input control terminal disconnects the first power signal terminal from the second node based on the potential of the first node being at an invalid level of the first power signal terminal.

[0018] The beneficial effects of this disclosure are as follows: This disclosure addresses existing problems by providing a shift register circuit and its driving method, gate driving circuit, and display device. By providing a protection sub-circuit and configuring it to electrically connect the first power signal terminal to the first node based on the signal from the protection control terminal, it can avoid short circuit leakage between the first power signal terminal and the second power signal terminal, improve the output stability of the shift register circuit, reduce the overall power consumption, and thus improve the battery life of the display product, which has broad application prospects. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 The circuit schematic of a shift register circuit in the related technology is shown; Figure 2 The timing diagrams of each port of the shift register circuit in the related technology are shown; Figure 3 This is a schematic block diagram of a shift register circuit according to an embodiment of the present disclosure; Figure 4 This is a schematic circuit diagram of a shift register circuit according to an embodiment of the present disclosure; Figure 5 This is a schematic circuit diagram of a shift register circuit according to another embodiment of the present disclosure; Figure 6 Show Figure 4 The schematic timing diagram of each port of the shift register circuit shown; Figure 7 Simulation diagram of power supply current for shift register circuits in related technologies and embodiments of this disclosure; Figure 8 This is a schematic block diagram of a gate drive circuit according to an embodiment of the present disclosure; Figure 9 This is a schematic block diagram of a gate drive circuit according to another embodiment of the present disclosure. Detailed Implementation

[0021] To more clearly illustrate this disclosure, the preferred embodiments and accompanying drawings will be used for further description. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of this disclosure.

[0022] It should be noted that, unless otherwise defined, the technical or scientific terms used in this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an," "a," or "the," etc., do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising," "including," etc., mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms "connected," "linked," etc., are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Furthermore, in this disclosure, an electrical connection can be a direct connection or a connection of transistors separated by a certain conducting element.

[0023] All transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of this disclosure, the gate of the transistor is called the control electrode, and one of the source and drain is called the first electrode, and the other is called the second electrode. In the embodiments of this disclosure, the first electrode of the transistor is called the source, and the second electrode is called the drain, as an example. In addition, the shift register circuit of the embodiments of this disclosure uses a P-type transistor. Therefore, the conduction condition of the transistor is that the control electrode is connected to a low-level signal, and the low level is called the effective level, while the high level is called the ineffective level, which will not be elaborated further below. It is conceivable that when an N-type transistor is used, the conduction condition of the transistor is reversed. When a high level is input to the gate, the source and drain are turned on. Therefore, the implementation of the N-type transistor should also be within the protection scope of the embodiments of this disclosure.

[0024] Figure 1 The circuit diagram of a shift register circuit in the related technology is shown. Figure 2 The timing diagram for each node and signal port is shown below. OUT1 represents the output signal of the current stage, and OUT2 represents the output signal of the next stage. The corresponding signal port is port OUT(n+1) in the circuit schematic. I_vgl and I_vgh represent the currents flowing through power supply terminals VGL and VGH, respectively. Power supply terminal VGL is typically low, and power supply terminal VGH is high. As can be seen from the diagram, within the time period defined by the two dashed lines, the potential of the first node N1 is low, and the output signal OUT2 of the next stage is low. This causes transistor M2 and transistor M10 to conduct simultaneously, resulting in a short circuit between power supply terminals VGH and VGL. This leads to a large-amplitude leakage current between the signal terminals that persists throughout the entire time period, increasing the product's power consumption. Furthermore, due to this short circuit, refer to... Figure 2 As shown, the potential of the second node N2 is pulled low, which will cause transistor M4 to be falsely turned on, resulting in poor output stability and increasing the risk of output abnormality.

[0025] To address at least one of the above technical problems, embodiments of this disclosure provide a shift register circuit, comprising: An input sub-circuit is electrically connected to the input terminal, the first node, and the first clock signal terminal, and is configured to electrically connect the input terminal and the first node based on the signal from the first clock signal terminal. The input control sub-circuit is electrically connected to the first node, the second node, and the first power signal terminal, and is configured to electrically connect the first power signal terminal to the second node based on the potential of the first node. An output sub-circuit, electrically connected to a first node, a second node, a first power supply signal terminal, a second clock signal terminal, and an output terminal, is configured to control the on / off state of the output terminal and the first power supply signal terminal, and the on / off state of the output terminal and the second clock signal terminal, based on the potentials of the second node and the first node; and The protection sub-circuit is electrically connected to the first node, the protection control terminal, and the first power signal terminal, and is configured to electrically connect the first power signal terminal to the first node based on the signal from the protection control terminal.

[0026] In this embodiment, by providing a protection sub-circuit and configuring it to electrically connect the first power signal terminal to the first node based on the signal from the protection control terminal, short-circuit leakage between the first power signal terminal and the second power signal terminal can be avoided, thereby improving the output stability of the shift register circuit, reducing the overall power consumption, and thus improving the battery life of the display product.

[0027] The following is combined with Figure 3 , Figure 4 and Figure 5The specific structure and function of the shift register circuit of the present disclosure are described with reference to specific embodiments.

[0028] Reference Figure 3 As shown, this disclosure provides a shift register circuit, including: an input sub-circuit 10, an input control sub-circuit 20, an output sub-circuit 30, and a protection sub-circuit 40.

[0029] The input sub-circuit 10 is electrically connected to the input terminal STV, the first node N1 and the first clock signal terminal CLK1, and is configured to electrically connect the input terminal STV and the first node N1 based on the signal of the first clock signal terminal CLK1.

[0030] The input control sub-circuit 20 is electrically connected to the first node N1, the second node N2 and the first power signal terminal VGH, and is configured to electrically connect the first power signal terminal VGH to the second node N2 based on the potential of the first node N1.

[0031] The output sub-circuit 30 is electrically connected to the first node N1, the second node N2, the first power supply signal terminal VGH, the second clock signal terminal CLK2, and the output terminal OUT(n). It is configured to control the on / off state of the output terminal OUT(n) and the first power supply signal terminal VGH, as well as the on / off state of the output terminal OUT(n) and the second clock signal terminal CLK2, based on the potential of the second node N2 and the first node N1.

[0032] It should be noted that "OUT(n)" here refers to the nth stage shift register circuit, where n is an integer greater than or equal to 1.

[0033] The protection sub-circuit 40 is electrically connected to the first node N1, the protection control terminal CLK3, and the first power signal terminal VGH, and is configured to electrically connect the first power signal terminal VGH to the first node N1 based on the signal of the protection control terminal CLK3.

[0034] It should be noted that, in Figure 3 and Figure 4 The designation "CLK3" indicates the protection control terminal. This designation signifies that the signal input to the protection control terminal is a clock signal distinct from the first clock signal terminal CLK1 and the second clock signal terminal CLK2. In another example, refer to... Figure 5 In this circuit, the protection control terminal can use the same signal as the output terminal of the next-stage shift register circuit. For example, the protection control terminal can be electrically connected to the output terminal of the next-stage shift register circuit, thus... Figure 5 In the example, to illustrate the difference between this signal and connection relationship, "OUT(n+1)" indicates that the protection control terminal is electrically connected. The specific implementation will be described in further detail in the corresponding example, and will not be repeated here.

[0035] Specifically, refer to Figure 4As shown, the protection sub-circuit 40 includes a first transistor T1. The first electrode of the first transistor T1 is electrically connected to the first power supply signal terminal VGH, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the protection control terminal CLK3. The protection control terminal CLK3 is connected to a third clock signal. When the third clock signal connected to the protection control terminal CLK3 is at a valid level, the first transistor T1 is turned on, electrically connecting the first node N1 to the first power supply signal terminal VGH. In this example, the first power supply signal terminal VGH is at a high level, thereby writing a high level to the first node N1.

[0036] Continue to refer to Figure 4 As shown, the input sub-circuit 10 includes a second transistor T2. The first electrode of the second transistor T2 is electrically connected to the input terminal STV, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal terminal CLK1. When the signal connected to the first clock signal terminal CLK1 is at an active level, the second transistor T2 is turned on, electrically connecting the input terminal STV to the first node N1.

[0037] The input control sub-circuit 20 includes a third transistor T3. The first electrode of the third transistor T3 is electrically connected to the first power supply signal terminal VGH, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1. When the potential of the first node N1 is at an effective level, the third transistor T3 is turned on, electrically connecting the first power supply signal terminal VGH to the second node N2.

[0038] As can be seen, when the first transistor T1 in the protection sub-circuit 40 is turned on, the first node N1 is connected to a high level, that is, the potential of the first node N1 is an invalid level for the third transistor T3, so the third transistor T3 is turned off, thereby disconnecting the first power supply signal terminal VGH from the second node N2.

[0039] Continue to refer to Figure 4 As shown, the output sub-circuit 30 includes a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. Specifically, the first electrode of the fourth transistor T4 is electrically connected to the first power supply signal terminal VGH, the second electrode is electrically connected to the output terminal OUT(n), and the control electrode is electrically connected to the second node N2; the first electrode of the fifth transistor T5 is electrically connected to the second clock signal terminal CLK2, the second electrode is electrically connected to the output terminal OUT(n), and the control electrode is electrically connected to the first node N1; the first electrode of the first capacitor C1 is electrically connected to the second node N2, and the second electrode is electrically connected to the first power supply signal terminal VGH; the first electrode of the second capacitor C2 is electrically connected to the first node N1, and the second electrode is electrically connected to the output terminal OUT(n).

[0040] When the potential of the second node N2 is active, the fourth transistor T4 is turned on, electrically connecting the first power supply signal terminal VGH to the output terminal OUT(n). When the first node N1 is active, the fifth transistor T5 is turned on, transmitting the signal from the second clock signal terminal CLK2 to the output terminal OUT(n). The first capacitor C1 is used to store the potential of the second node N2, and the second capacitor C2 is used to store the potential of the first node N1.

[0041] Optionally, refer to Figure 4 As shown, the shift register circuit may further include a first voltage regulator circuit 50. The first voltage regulator circuit 50 is electrically connected to a first node N1, a second node N2, a third node N3, a first power supply signal terminal VGH, and a second clock signal terminal CLK2, and is configured to electrically connect the first power supply signal terminal VGH to the third node N3 based on the potential of the first node N1, and to electrically connect the second clock signal terminal CLK2 to the second node N2 based on the potential of the third node N3.

[0042] Specifically, the first voltage regulator circuit 50 includes a sixth transistor T6, a seventh transistor T7, and a third capacitor C3. The first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CLK2, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the third node N3. The first electrode of the seventh transistor T7 is electrically connected to the first power supply signal terminal VGH, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the first node N1. The first electrode of the third capacitor C3 is electrically connected to the second clock signal terminal CLK2, and the second electrode is electrically connected to the third node N3. The third node N3 is the common connection point of the control electrode of the sixth transistor T6, the first electrode of the seventh transistor T7, and the second electrode of the third capacitor C3.

[0043] When the first node N1 is at an active level, the seventh transistor T7 is turned on, transmitting the high level of the first power supply signal terminal VGH to the third node N3. At this time, the sixth transistor T6 is turned off. However, if the second clock signal terminal CLK2 is activated, it charges the third capacitor C3 with an active level, making the third node N3 active. In this case, the sixth transistor T6 is turned on, transmitting the signal from the second clock signal terminal CLK2 to the second node N2. The first voltage regulator circuit 50 is used to charge the second node N2 and stabilize its potential with the cooperation of the three devices. The specific implementation process will be described in detail in the driving process section of the shift register circuit below, and will not be repeated here.

[0044] Optionally, the shift register circuit may further include a second voltage regulator circuit 60. The second voltage regulator circuit 60 is electrically connected to the first node N1, the second node N2, the fourth node N4, the second clock signal terminal CLK2, and the first power supply signal terminal VGH, and is configured to electrically connect the first power supply signal terminal VGH to the fourth node N4 based on the potential of the second node N2, and to electrically connect the first node N1 to the fourth node N4 based on the signal of the second clock signal terminal CLK2.

[0045] Specifically, refer to Figure 4 As shown, the second voltage regulator circuit 60 includes an eighth transistor T8 and a ninth transistor T9. The first electrode of the eighth transistor T7 is electrically connected to the first power supply signal terminal VGH, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the second node N2. The first electrode of the ninth transistor T9 is electrically connected to the fourth node N4, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the second clock signal terminal. The common connection point of the eighth transistor T8 and the ninth transistor T9 is the fourth node N4.

[0046] Continue to refer to Figure 4 As shown, the shift register circuit may further include a third voltage regulator sub-circuit 70. The third voltage regulator sub-circuit 70 is electrically connected to the second node N2, the second power supply signal terminal VGL, and the third voltage regulation control terminal, configuring the second power supply signal terminal to be electrically connected to the second node based on the signal from the third voltage regulation control terminal. In this example, the third voltage regulation control terminal is electrically connected to the output terminal of the next-stage shift register circuit; therefore, the third voltage regulation control terminal is identified by the output terminal OUT(n+1) of the next-stage shift register circuit.

[0047] Specifically, the first electrode of the tenth transistor T10 is electrically connected to the second node N2, the second electrode is electrically connected to the second power supply signal terminal VGL, and the control electrode is electrically connected to the third voltage regulation control terminal, which can be electrically connected to the output terminal OUT(n+1) of the next stage shift register circuit. When a valid voltage regulation control signal is applied to the third voltage regulation control terminal, the tenth transistor T10 is turned on, transmitting the potential of the second power supply signal terminal VGL to the second node N2. In this example, the signal applied to the second power supply signal terminal VGL is low.

[0048] Optionally, refer to Figure 4As shown, the output sub-circuit 30 is electrically connected to the first node N1 through the fourth voltage regulator sub-circuit 80. The fourth voltage regulator sub-circuit 80 includes an eleventh transistor T11. The first electrode of the eleventh transistor T11 is electrically connected to the first node N1, and the second electrode is electrically connected to the fifth node N5 corresponding to the control electrode of the fifth transistor T5. The control electrode is electrically connected to the second power supply signal terminal VGL. Because the potential of the second power supply signal terminal VGL is low, the eleventh transistor T11 will be in the conducting state as long as the voltage difference between the fifth node N5 and the second power supply signal terminal VGL meets the conduction requirement of the eleventh transistor T11. It is used to prevent current backflow and leakage due to voltage changes at the fifth node N5. That is, when the potential of the fifth node N5 does not meet the conduction condition of the eleventh transistor T11, the eleventh transistor T11 is turned off to avoid leakage.

[0049] In another alternative embodiment, refer to Figure 5 As shown, it is similar to Figure 4 The example shown shows that the protection sub-circuit 40 includes: a first transistor T1, the first electrode of which is electrically connected to the first power supply signal terminal VGH, the second electrode of which is electrically connected to the first node N1, and the control electrode is electrically connected to the protection control terminal, which is connected to the output terminal OUT(n+1) of the next-stage shift register circuit. Specifically, when the signal at the output terminal OUT(n+1) of the next-stage shift register circuit is at an active level, the first transistor T1 is turned on, transmitting the potential of the first power supply signal terminal VGH to the first node N1.

[0050] Figure 5 In the circuit schematic shown, the other circuit structures are similar to those described above, and will not be repeated here.

[0051] To further understand the structural relationships and functions of the shift register circuits in the embodiments of this disclosure, the following will be used as an example. Figure 4 Taking the circuit schematic as an example, combined with Figure 6 The timing diagram shown describes the driving process of the shift register circuit in detail.

[0052] It should be noted that in the timing diagram, "OUT1" represents the signal at the output terminal OUT(n) of the current stage shift register circuit, "OUT2" represents the signal at the output terminal OUT(n+1) of the next stage shift register circuit cascaded with the current stage, "I_vgh" represents the current signal at the first power supply terminal VGH, "I_vgl" represents the current signal at the second power supply terminal VGL, and "CLK3" represents the signal at the protection control terminal CLK3 connected to the clock signal. Furthermore, although the potentials of the first voltage terminal VGH and the second voltage terminal VGL are not shown in the timing diagram, it should be understood that in this document, the first power supply terminal VGH is a power supply terminal with a constant high potential, and the second power supply terminal VGL is a power supply terminal with a constant low potential. Additionally, since the transistors shown in this example are all P-type transistors, with low level being the active level and high level being the inactive level, for ease of correspondence with the potentials in the timing diagram, low level will be used to refer to the active level and high level to refer to the inactive level below.

[0053] The driving process of the shift register circuit in this embodiment includes: a first stage, a second stage, a third stage, and a fourth stage.

[0054] In the first stage, i.e. time period t1, the first clock signal terminal CLK1 is at a low level, the second clock signal terminal CLK2 is at a high level, the protection control terminal CLK3 is at a high level, and the signal connected to the input terminal STV is at a low level.

[0055] At this time, the second transistor T2 is turned on, transmitting the low-level signal of the input terminal STV to the first node N1. Because the eleventh transistor T11 is normally open, the signal of the input terminal STV charges the second capacitor C2, pulling the potential of the first node N1 low. After the first node N1 becomes low, the third transistor T3 is turned on, electrically connecting the first power supply signal terminal VGH to the second node N2, writing a high level to the second node N2. At the same time, because the first node N1 is low, the seventh transistor T7 is turned on, electrically connecting the first power supply signal terminal VGH to the third node N3, thus turning off the sixth transistor T6. At this time, the signal of the protection control terminal CLK3 is high, and the first transistor T1 is turned off, ensuring that the first node N1 is not electrically connected to the first power supply signal terminal VGH. When the second node N2 is high, the fourth transistor T4 is turned off. When the first node N1 is high, the fifth transistor is turned on, transmitting the high-level signal of the second clock signal terminal CLK2 to the output terminal OUT(n), outputting a high-level signal.

[0056] In addition, since the second node N2 is at a high level, the eighth transistor T8 is turned off, the second clock signal terminal CLK2 is at a high level, the ninth transistor T9 is turned off, and therefore the high level of the first power supply signal terminal VGH will not be transmitted to the first node N1.

[0057] In the second stage, i.e. time period t2, the first clock signal terminal CLK1 is at a high level, the second clock signal terminal CLK2 becomes low level, the protection control terminal CLK3 is at a high level, and the signal connected to the input terminal STV is at a high level.

[0058] At this time, the second transistor T2 is turned off, and the first transistor T1 is also turned off. The eleventh transistor T11 remains on, and under the bootstrap effect of the second capacitor C2, it further charges, pulling the potentials of the first node N1 and the fifth node N5 low; the third transistor T3 remains on, and the high level of the first power supply signal terminal VGH continues to be written to the second node N2; at the same time, the seventh transistor T7 is on, and the third node N3 also continues to be written with the high level of the first power supply signal terminal VGH; the sixth transistor T6 is turned off, and the second clock signal terminal CLK2 is not connected to the second node N2. The second node N2 is at a high level, the fourth transistor T4 is turned off, the first node N1 and the fifth node N5 are at a low level, the fifth transistor T5 is on, and transmits the low-level signal of the second clock signal terminal CLK2 to the output terminal OUT(n), outputting a low-level signal.

[0059] In addition, when the second clock signal terminal CLK2 is low, the ninth transistor T9 is turned off, but because the second node N2 is high, the eighth transistor T8 is turned off, and the high level of the first power supply signal terminal VGH will not be transmitted to the first node N1.

[0060] In the third stage, i.e. time period t3, the first clock signal terminal CLK1 is at a high level, the second clock signal terminal CLK2 is at a high level, the protection control terminal CLK3 is at a low level, and the signal connected to the input terminal STV is at a high level.

[0061] At this time, the first transistor T1 is directly turned on by the protection control terminal CLK3, electrically connecting the first power signal terminal VGH to the first node N1, pulling the first node high, thereby turning off the third transistor T3. Because the signal connected to the control electrode of the tenth transistor T10 is the output signal of the next stage shift register circuit, the tenth transistor T10 is turned on, and the second power signal terminal VGL is electrically connected to the second node N2. It can be seen that in the embodiment of this disclosure, because of the presence of the first transistor T1, the first node N1 is directly pulled high during time period t3, thus disconnecting the path between the first power signal terminal VGH and the second power signal terminal VGL, avoiding a short circuit between the first power signal terminal VGH and the second power signal terminal VGL.

[0062] Because the second node N2 is low, the fourth transistor T4 is turned on, transmitting the potential of the first power supply signal terminal VGH to the output terminal OUT(n). The output terminal OUT(n) outputs a high level. Because the first node N1 is high, the corresponding fifth node N5 is also high, and the fifth transistor T5 is turned off. Additionally, because the second node N2 is low, the eighth transistor T8 is turned on, electrically connecting the first power supply signal terminal VGH to the fourth node N4. However, the second clock signal terminal CLK2 is high, and the ninth transistor T9 is turned off. Furthermore, because the first node N1 is high, the seventh transistor T7 is turned off. Due to the effect of the third capacitor C3, the third node N3 remains high, and the sixth transistor T6 is turned off. Therefore, the high level of the second clock signal terminal CLK2 is not transmitted to the second node N2.

[0063] In the fourth stage, i.e. time period t4, the first clock signal terminal CLK1 is at a low level, the second clock signal terminal CLK2 is at a high level, the protection control terminal CLK3 is at a high level, and the signal connected to the input terminal STV is at a high level.

[0064] At this point, even if the first clock signal terminal CLK1 goes low and the second transistor T2 turns on, the first node N1 remains high because the input terminal STV is always an invalid high level, thus the fifth transistor T5 remains off. Since the first node N1 is high, the third transistor T3 and the seventh transistor T7 remain off, and the high level of the first power supply signal terminal VGH is not transmitted to the second node N2. Meanwhile, the second clock signal terminal CLK2 keeps the third node N3 high through the third capacitor C3, the sixth transistor T6 turns off, and the second node N2 remains low. The fourth transistor T4 turns on, electrically connecting the first power supply signal terminal VGH to the output terminal OUT(n).

[0065] It should be noted that, as Figure 6 As shown, during the period after time period t4, when the input terminal STV no longer receives a valid level, the output terminal OUT(n) is kept high by maintaining a high level through the first node N1 and the second node N2 maintaining a low level. In order to ensure that the second node N2 remains low, the function of the first voltage regulator circuit 50 is to periodically charge the second node N2 with a low level using the second clock signal terminal CLK2, while the second voltage regulator circuit 60 can periodically charge the first node N1 with a high level.

[0066] Specifically, during the period after time t4 and while the input STV signal is high, when the second clock signal terminal CLK2 is low, the third node N3 is low, and the sixth transistor T6 is turned on, charging the second clock signal terminal CLK2 to the second node N2 with a low potential, which helps to maintain the low potential of the second node N2. On the other hand, when the second clock signal terminal CLK2 is low, and the second node N2 is also low, the ninth transistor T9 and the eighth transistor T8 are both turned on, using the high level of the first power supply signal terminal VGH to charge the first node N1 with a high level to keep the fifth transistor T5 off.

[0067] It should also be noted that, although the above driving process is based on Figure 4 The circuit schematic shown is used for explanation, but according to... Figure 6 As can be understood from the timing diagram, during the t3 period, the signal at the output terminal OUT(n+1) of the next-stage shift register circuit is also at a low level. When this signal is used as the signal connected to the protection control terminal, the technical effect described above can also be achieved. Through this setting, one signal line providing the clock signal can be reduced, thereby simplifying the size of the outer frame.

[0068] Figure 7 The diagram shows a simulation comparison of the power supply current of a shift register circuit according to an embodiment of this disclosure and a shift register circuit of related technologies. In the diagram, the upper waveform represents the current at the second power supply signal terminal VGL, and the lower waveform represents the current at the first power supply signal terminal VGH. Figure 7 The dashed waveform corresponds to the relevant technology shift register circuit without the protection sub-circuit 40, while the solid waveform corresponds to the shift register circuit of the present disclosure embodiment.

[0069] Combination Figure 1 and Figure 7 As can be seen, in the related technology, a short circuit between the first power signal terminal VGH and the second power signal terminal VGL causes leakage currents with high amplitude and long duration to occur at both terminals. In contrast, combined with Figure 6 and Figure 7 As shown, by providing a protection sub-circuit, short circuits at the first power signal terminal VGH and the second power signal terminal VGL are avoided, and the leakage current is significantly improved.

[0070] Based on the same inventive concept, other embodiments of this disclosure also provide another gate drive circuit, including multiple cascaded shift register circuits.

[0071] Optionally, the first output of the nth stage shift register circuit is electrically connected to the input of another stage shift register circuit, where n is a positive integer greater than or equal to 1, and the input of the first stage shift register is electrically connected to the initial signal line.

[0072] The structure and function of the shift register circuit used for cascading have been described in detail in the above embodiments with reference to the circuit structure and timing diagram, and will not be repeated here.

[0073] Optionally, in embodiments of this disclosure, each stage of the shift register circuit in a gate driving circuit can output an effective level output signal row by row or every other row. When outputting an effective level output signal row by row, the output terminal of the nth stage shift register circuit is electrically connected to the input terminal of the (n+1)th stage shift register circuit. When outputting an effective level output signal every other row, for example, every other row, the output terminal of the nth stage shift register circuit is electrically connected to the input terminal of the (n+2)th stage shift register circuit. Any gate driving circuit that can be cascaded with the shift register circuits of the above embodiments to output a shifted effective level signal is within the scope of protection of this disclosure.

[0074] Alternatively, when a clock signal is connected to the protection control terminal, for example, in a shift register circuit... Figure 4 In the circuit structure shown, the gate drive circuit formed by the cascaded shift register circuit can be driven by clock signals through, for example, 3 or 4 clock signal lines. For ease of understanding, the protection control terminal CLK3 is used as the third clock signal terminal to connect to the third clock signal.

[0075] Optionally, the first clock signal terminal of the (3n-2)th stage shift register circuit is electrically connected to the first clock signal line, the second clock signal terminal is electrically connected to the second clock signal line, and the third clock signal terminal is electrically connected to the third clock signal line. The first clock signal terminal of the (3n-1)th stage shift register circuit is electrically connected to the second clock signal line, the second clock signal terminal is electrically connected to the third clock signal line, and the third clock signal terminal is electrically connected to the first clock signal line. The first clock signal terminal of the (3n)th stage shift register circuit is electrically connected to the third clock signal line, the second clock signal terminal is electrically connected to the first clock signal line, and the third clock signal terminal is electrically connected to the second clock signal line, where n is an integer greater than or equal to 1.

[0076] by Figure 8The example shown is a cascaded gate drive circuit of four shift register circuits G1-G4. In the first-stage shift register circuit G1, the first clock signal terminal CLK1 is electrically connected to the first clock signal line clk1, the second clock signal terminal CLK2 is electrically connected to the second clock signal line clk2, and the third clock signal terminal CLK3 is electrically connected to the third clock signal line clk3. Similarly, in the second-stage shift register circuit G2, the first clock signal terminal CLK1 is electrically connected to the second clock signal line clk2, the second clock signal terminal CLK2 is electrically connected to the third clock signal line clk3, and the third clock signal terminal CLK3 is electrically connected to the first clock signal line clk1. In the third-stage shift register circuit G3, the first clock signal terminal CLK1 is electrically connected to the third clock signal line clk3, the second clock signal terminal CLK2 is electrically connected to the first clock signal line clk1, and the third clock signal terminal CLK3 is electrically connected to the second clock signal line clk2. This pattern continues, with each cycle consisting of three cascaded shift register circuits, cyclically connected to the three clock signal lines. Figure 6 The timing of the clock signal in the timing diagram shown, with the third time period t1 to t4 forming a cycle, satisfies the following: Figure 8 The diagram shows the connection method for the three clock signal lines. Note that, for ease of illustration, the connection relationship between the third voltage regulator control terminal and the next stage output terminal is not shown.

[0077] Optionally, the first clock signal terminal of the (4n-3)th stage shift register circuit is electrically connected to the first clock signal line, the second clock signal terminal is electrically connected to the second clock signal line, and the third clock signal terminal is electrically connected to the third clock signal line; the first clock signal terminal of the (4n-2)th stage shift register circuit is electrically connected to the fourth clock signal line, the second clock signal terminal is electrically connected to the first clock signal line, and the third clock signal terminal is electrically connected to the second clock signal line; the first clock signal terminal of the (4n-1)th stage shift register circuit is electrically connected to the third clock signal line, the second clock signal terminal is electrically connected to the fourth clock signal line, and the third clock signal terminal is electrically connected to the first clock signal line; the first clock signal terminal of the (4n-1)th stage shift register circuit is electrically connected to the third clock signal line, the second clock signal terminal is electrically connected to the fourth clock signal line, and the third clock signal terminal is electrically connected to the first clock signal line; and the first clock signal terminal of the (4n)th stage shift register circuit is electrically connected to the second clock signal line, the second clock signal terminal is electrically connected to the third clock signal line, and the third clock signal terminal is electrically connected to the fourth clock signal line, where n is an integer greater than or equal to 1.

[0078] For example, with Figure 9The example shown is a cascaded gate drive circuit of a 4-stage shift register circuit G1-G4. In the first-stage shift register circuit G1, the first clock signal terminal CLK1 is electrically connected to the first clock signal line clk1, the second clock signal terminal CLK2 is electrically connected to the second clock signal line clk2, and the third clock signal terminal CLK3 is electrically connected to the third clock signal line clk3. In the second-stage shift register circuit G2, the first clock signal terminal CLK1 is electrically connected to the fourth clock signal line clk4, the second clock signal terminal CLK2 is electrically connected to the first clock signal line clk1, and the third clock signal terminal CLK3 is electrically connected to the second clock signal line clk2. The third-stage shift register... The first clock signal terminal CLK1 of register circuit G3 is electrically connected to the third clock signal line clk3, the second clock signal terminal CLK2 is electrically connected to the fourth clock signal line clk4, and the third clock signal terminal CLK3 is electrically connected to the first clock signal line clk1. Similarly, the first clock signal terminal CLK1 of the fourth-stage shift register circuit G4 is electrically connected to the second clock signal line clk2, the second clock signal terminal CLK2 is electrically connected to the third clock signal line clk3, and the third clock signal terminal CLK3 is electrically connected to the fourth clock signal line clk4. Here, n is an integer greater than or equal to 1. This process continues, with every four cascaded shift register circuits forming one cycle, cyclically connected to the three clock signal lines. Note that, for ease of illustration, the connection between the third voltage regulator control terminal and the next stage output terminal is not shown in the diagram.

[0079] It should be understood that, although Figure 8 and Figure 9 The diagram illustrates the structure of shift register circuits with 3 clock signal lines and 4 signal lines, but this disclosure is not limited to this. Where space permits, it can be implemented with an even greater number of clock signal lines. Figure 4 In this structure, three clock signal lines represent the minimum required configuration. Additionally, for... Figure 5 In terms of structure, the number of clock signal lines can be reduced to two, that is, the first clock signal terminal and the second clock signal terminal require a total of two clock signal lines, and the protection control terminal is replaced by the output terminal of the next stage.

[0080] By providing the gate drive circuit including the shift register circuit described above, short circuits and leakage can be avoided at the first power supply signal terminal and the second power supply signal terminal, thereby improving output stability and reducing power loss.

[0081] Based on the same inventive concept, embodiments of this disclosure also provide a display device, including the gate driving circuit described in the above embodiments.

[0082] By implementing the above settings, the display device can improve output stability, reduce power loss, and enhance the user experience.

[0083] It should be noted that in this embodiment, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, vehicle display, digital photo frame or navigator. By using the above gate drive circuit, a more stable display driving effect can be provided with less power loss, which has broad application prospects.

[0084] Based on the same inventive concept, embodiments of this disclosure also provide a driving method applied to the shift register circuit described above, comprising: In the first stage, the input sub-circuit transmits the valid level of the input terminal to the first node based on the valid level of the signal connected to the first clock signal terminal, and the input control sub-circuit transmits the potential of the first power supply signal terminal to the second node based on the potential of the first node. In the second stage, the output sub-circuit transmits the effective level signal connected to the second clock signal terminal to the output terminal based on the effective potential level of the first node; In the third stage, the protection sub-circuit transmits the signal from the first power signal terminal to the first node based on the signal of the protection control terminal being at an effective level, and the input control terminal disconnects the first power signal terminal from the second node based on the potential of the first node being at an invalid level of the first power signal terminal.

[0085] Those skilled in the art should understand that the specific process of the above method has been explained in detail with reference to the timing diagrams when describing the specific circuit principle of the shift register circuit above, and will not be repeated here.

[0086] The above driving methods can avoid short circuits and leakage at the high and low power signal terminals, improve output stability, reduce power loss, and extend the battery life of display products, thus having broad application prospects.

[0087] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. A shift register circuit, characterized in that, include: An input sub-circuit is electrically connected to an input terminal, a first node, and a first clock signal terminal, and is configured to electrically connect the input terminal to the first node based on the signal from the first clock signal terminal. An input control sub-circuit is electrically connected to the first node, the second node, and the first power signal terminal, and is configured to electrically connect the first power signal terminal to the second node based on the potential of the first node. An output sub-circuit is electrically connected to the first node, the second node, the first power signal terminal, the second clock signal terminal, and the output terminal, and is configured to control the on / off state of the output terminal and the first power signal terminal and the on / off state of the output terminal and the second clock signal terminal based on the potential of the second node and the first node. as well as A protection sub-circuit is electrically connected to the first node, the protection control terminal, and the first power signal terminal, and is configured to electrically connect the first power signal terminal to the first node based on the signal from the protection control terminal.

2. The shift register circuit according to claim 1, characterized in that, The protection sub-circuit includes: a first transistor, The first electrode of the first transistor is electrically connected to the first power supply signal terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the protection control terminal. The protection control terminal is connected to the third clock signal or the output signal of the next-stage shift register circuit.

3. The shift register circuit according to claim 1, characterized in that, Also includes: First voltage regulator circuit, The first voltage regulator circuit is electrically connected to the first node, the second node, the third node, the first power signal terminal, and the second clock signal terminal, and is configured to electrically connect the first power signal terminal to the third node based on the potential of the first node and to electrically connect the second clock signal terminal to the second node based on the potential of the third node.

4. The shift register circuit according to claim 1, characterized in that, Also includes: Second voltage regulator circuit, The second voltage regulator circuit is electrically connected to the first node, the second node, the fourth node, the second clock signal terminal, and the first power signal terminal, and is configured to electrically connect the first power signal terminal to the fourth node based on the potential of the second node and to electrically connect the first node to the fourth node based on the signal of the second clock signal terminal.

5. The shift register circuit according to claim 1, characterized in that, Also includes: The third voltage regulator circuit, The third voltage regulator sub-circuit is electrically connected to the second node, the second power signal terminal, and the third voltage regulation control terminal, and is configured to electrically connect the second power signal terminal to the second node based on the signal of the third voltage regulation control terminal.

6. The shift register circuit according to claim 1, characterized in that, The input sub-circuit includes a second transistor, the first electrode of the second transistor is electrically connected to the input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal terminal. The input control sub-circuit includes a third transistor, the first electrode of which is electrically connected to the first power signal terminal, the second electrode of which is electrically connected to the second node, and the control electrode of which is electrically connected to the first node. The output sub-circuit includes a fourth transistor, a fifth transistor, a first capacitor, and a second capacitor. The first electrode of the fourth transistor is electrically connected to the first power signal terminal, the second electrode is electrically connected to the output terminal, and the control electrode is electrically connected to the second node. The first electrode of the fifth transistor is electrically connected to the second clock signal terminal, the second electrode is electrically connected to the output terminal, and the control electrode is electrically connected to the first node. The first electrode of the first capacitor is electrically connected to the second node, and the second electrode is electrically connected to the first power signal terminal. The first electrode of the second capacitor is electrically connected to the first node, and the second electrode is electrically connected to the output terminal.

7. The shift register circuit according to claim 3, characterized in that, The first voltage regulator circuit includes a sixth transistor, a seventh transistor, and a third capacitor. The first electrode of the sixth transistor is electrically connected to the second clock signal terminal, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the third node. The first electrode of the seventh transistor is connected to the first power signal terminal, the second electrode is connected to the third node, and the control electrode is connected to the first node. The first electrode of the third capacitor is electrically connected to the second clock signal terminal, and the second electrode is electrically connected to the third node.

8. The shift register circuit according to claim 4, characterized in that, The second voltage regulator circuit includes: an eighth transistor and a ninth transistor. The first electrode of the eighth transistor is electrically connected to the first power signal terminal, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the second node. The first electrode of the ninth transistor is electrically connected to the fourth node, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the second clock signal terminal.

9. The shift register circuit according to claim 5, characterized in that, The third voltage regulator circuit includes a tenth transistor. The first electrode of the tenth transistor is electrically connected to the second node, the second electrode is electrically connected to the second power supply signal terminal, the control electrode is electrically connected to the third voltage regulation control terminal, and the third voltage regulation control terminal is electrically connected to the output terminal of the next stage shift register circuit.

10. The shift register circuit according to claim 6, characterized in that, The output sub-circuit is electrically connected to the first node through the fourth voltage regulator sub-circuit. The fourth voltage regulator circuit includes an eleventh transistor, the first electrode of which is electrically connected to the first node, the second electrode of which is electrically connected to the control electrode of the fifth transistor, and the control electrode is electrically connected to the second power signal terminal.

11. A gate driving circuit, characterized in that, include: A series of cascaded shift register circuits as described in any one of claims 1-10.

12. The gate driving circuit according to claim 11, characterized in that, The protection control terminal serves as the third clock signal terminal to receive the third clock signal. The first clock signal terminal of the 3n-2 stage shift register circuit is electrically connected to the first clock signal line, the second clock signal terminal is electrically connected to the second clock signal line, and the third clock signal terminal is electrically connected to the third clock signal line. The first clock signal terminal of the 3n-1 stage shift register circuit is electrically connected to the second clock signal line, the second clock signal terminal is electrically connected to the third clock signal line, and the third clock signal terminal is electrically connected to the first clock signal line. The first clock signal terminal of the 3n stage shift register circuit is electrically connected to the third clock signal line, the second clock signal terminal is electrically connected to the first clock signal line, and the third clock signal terminal is electrically connected to the second clock signal line. or The first clock signal terminal of the 4n-3 stage shift register circuit is electrically connected to the first clock signal line, the second clock signal terminal is electrically connected to the second clock signal line, and the third clock signal terminal is electrically connected to the third clock signal line. The first clock signal terminal of the 4n-2 stage shift register circuit is electrically connected to the fourth clock signal line, the second clock signal terminal is electrically connected to the first clock signal line, and the third clock signal terminal is electrically connected to the second clock signal line. The first clock signal terminal of the 4n-1 stage shift register circuit is electrically connected to the third clock signal line, the second clock signal terminal is electrically connected to the fourth clock signal line, and the third clock signal terminal is electrically connected to the first clock signal line. The first clock signal terminal of the 4n stage shift register circuit is electrically connected to the second clock signal line, the second clock signal terminal is electrically connected to the third clock signal line, and the third clock signal terminal is electrically connected to the fourth clock signal line. Where n is an integer greater than or equal to 1.

13. A display device, characterized in that, Includes the gate drive circuit as described in claim 11 or 12.

14. A driving method for a shift register circuit as described in any one of claims 1-10, characterized in that, include: In the first stage, the input sub-circuit transmits the valid level of the input terminal to the first node based on the valid level of the signal connected to the first clock signal terminal, and the input control sub-circuit transmits the potential of the first power signal terminal to the second node based on the potential of the first node; In the second stage, the output sub-circuit transmits the effective level signal connected to the second clock signal terminal to the output terminal based on the effective potential level of the first node; In the third stage, the protection sub-circuit transmits the signal of the first power signal terminal to the first node based on the signal of the protection control terminal being at an effective level, and the input control terminal disconnects the first power signal terminal from the second node based on the potential of the first node being at an invalid level of the first power signal terminal.

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