Variable resistance memory and control method of variable resistance memory

Abstract

The application provides a variable resistance memory and a control method of the variable resistance memory. The variable resistance memory comprises a memory cell array, a controller, a write circuit and a read circuit. The write circuit is used for providing a bias voltage to the memory cell array under the control of the controller. The controller is used for controlling the write circuit to provide a first group of bias voltages to the memory cell array in a first-step read process and controlling the write circuit to provide a second group of bias voltages to the memory cell array in a second-step read process. The read circuit is used for, for each target memory cell, performing a subtraction operation on a first read signal of the target memory cell in the first-step read process and a second read signal of the target memory cell in the second-step read process, so as to obtain a resistance value of the target memory cell. In this way, the leakage current interference of unselected memory cells can be effectively offset, and the resistance value of the target memory cell can be accurately extracted.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a variable resistance memory and a control method for the variable resistance memory. Background Technology

[0002] With the rapid development of storage technology, variable resistance memory (VRAM) has become a core candidate technology for next-generation storage technologies due to its advantages such as high storage density, low power consumption, and long lifespan. However, in practical applications, the read accuracy and reliability of memory largely depend on the accurate determination of the resistance value of the memory cells. Because memory cells themselves have resistance differences between high and low resistance states and are highly susceptible to external noise and interference, traditional read methods generally face problems such as signal interference, insufficient accuracy, and poor stability. Especially in high-density storage scenarios, how to quickly and accurately determine the resistance value of each memory cell has become a key bottleneck restricting the development of storage technology. Therefore, how to achieve accurate identification and efficient reading of memory cells while ensuring the overall performance of the memory cell array remains a major challenge for current technology. Summary of the Invention

[0003] In view of this, this application provides a variable resistance memory and a control method for the variable resistance memory, so as to accurately identify the resistance value of the target memory cell.

[0004] Specifically, this application is implemented through the following technical solution:

[0005] The first aspect of this application provides a variable resistance memory, which includes a memory cell array, a controller, a write circuit, and a read circuit;

[0006] The write circuit is used to provide a bias voltage to the memory cell array under the control of the controller;

[0007] The controller is configured to control the write circuit to provide a first set of bias voltages to the memory cell array during the first reading process, and to control the write circuit to provide a second set of bias voltages to the memory cell array during the second reading process. In each reading process, the bit line bias voltage provided to the selected target memory cell is a first specified value, and the word line bias voltage is a second specified value; the bit line bias voltage provided to other unselected memory cells is a third specified value, and the word line bias voltage is a fourth specified value. The first specified value and the second specified value are different, and the first specified value and the third specified value are located on the same side of the second specified value. The values ​​of the first specified value, the third specified value, and the fourth specified value remain unchanged during the first reading process and the second reading process, while the value of the second specified value differs during the first reading process and the second reading process.

[0008] The read circuit is used to perform a subtraction operation on each target memory cell based on the first read signal of the target memory cell in the first step of the read process and the second read signal of the target memory cell in the second step of the read process to obtain the resistance value of the target memory cell.

[0009] A second aspect of this application provides a control method for a variable resistor memory, the method comprising:

[0010] In the first reading step, the control write circuit provides a first set of bias voltages to the memory cell array, and in the second reading step, the control write circuit provides a second set of bias voltages to the memory cell array. In each reading step, the bit line bias voltage provided to the selected target memory cell is a first specified value, and the word line bias voltage is a second specified value; the bit line bias voltage provided to other unselected memory cells is a third specified value, and the word line bias voltage is a fourth specified value. The first specified value and the second specified value are different, and the first specified value and the third specified value are located on the same side of the second specified value. The values ​​of the first specified value, the third specified value, and the fourth specified value remain unchanged in the first reading step and the second reading step, while the value of the second specified value differs in the first reading step and the second reading step.

[0011] For each target memory cell, the resistance value of the target memory cell is obtained by subtracting the first read signal of the target memory cell in the first step of the read process and the second read signal of the target memory cell in the second step of the read process.

[0012] The variable resistance memory and its control method provided in this application apply different word line bias voltages to the target memory cell during two-step read operations, while keeping the bias voltages of the bit lines and unselected cells constant. This ensures that the leakage current of the unselected cells remains consistent throughout the two reads. The read circuit can effectively cancel out the influence of leakage current by subtracting the two read signals, retaining only the true response signal of the target memory cell. This significantly improves the accuracy and stability of resistance reading, reduces interference caused by leakage current accumulation in large-scale arrays, improves the signal-to-noise ratio, avoids misjudgments, and simplifies the overall design and reduces power consumption without introducing additional complex isolation circuit structures. Attached Figure Description

[0013] Figure 1 A schematic diagram of a first embodiment of the variable resistance memory provided in this application;

[0014] Figure 2 This is a schematic diagram of a memory cell array shown in an exemplary embodiment of this application;

[0015] Figure 3 A schematic diagram illustrating the implementation principle of a two-read process as shown in an exemplary embodiment of this application;

[0016] Figure 4 for Figure 3 A schematic diagram of the bias voltage during the two reading processes is shown.

[0017] Figure 5 A schematic diagram illustrating the implementation principle of a readout circuit as shown in an exemplary embodiment of this application;

[0018] Figure 6 A schematic diagram illustrating the implementation principle of a readout circuit for another exemplary embodiment of this application;

[0019] Figure 7 A partial schematic diagram of a variable memory cell shown in another exemplary embodiment of this application;

[0020] Figure 8 A flowchart of an embodiment of the control method for the variable resistor memory provided in this application. Detailed Implementation

[0021] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0022] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used herein are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0023] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0024] The following specific embodiments are given to illustrate the technical solution of this application in detail.

[0025] Figure 1 This is a schematic diagram of a first embodiment of the variable resistance memory provided in this application. Figure 2 This is a schematic diagram illustrating a memory cell array as shown in an exemplary embodiment of this application. Please also refer to... Figure 1 and Figure 2 The variable resistance memory provided in this embodiment includes a memory cell array, a controller, a write circuit, and a read circuit;

[0026] The write circuit is used to provide a bias voltage to the memory cell array under the control of the controller;

[0027] The controller is configured to control the write circuit to provide a first set of bias voltages to the memory cell array during the first reading process, and to control the write circuit to provide a second set of bias voltages to the memory cell array during the second reading process. In each reading process, the bit line bias voltage provided to the selected target memory cell is a first specified value, and the word line bias voltage is a second specified value; the bit line bias voltage provided to other unselected memory cells is a third specified value, and the word line bias voltage is a fourth specified value. The first specified value and the second specified value are different, and the first specified value and the third specified value are located on the same side of the second specified value. The values ​​of the first specified value, the third specified value, and the fourth specified value remain unchanged during the first reading process and the second reading process, while the value of the second specified value differs during the first reading process and the second reading process.

[0028] The read circuit is used to perform a subtraction operation on each target memory cell based on the first read signal of the target memory cell in the first step of the read process and the second read signal of the target memory cell in the second step of the read process to obtain the resistance value of the target memory cell.

[0029] For details, please refer to Figure 2 A memory cell array is a cross-array structure composed of a large number of memory cells. Each memory cell consists of a resistor, or each memory cell consists of a selector and a resistor connected in series. It should be noted that in... Figure 2 In the example shown, each memory cell consists of a selector and a resistor connected in series.

[0030] In this context, the selector is an electronic component within the memory cell that acts as a switch to control whether current flows through the circuit. The selector can be a diode, an Oversinski threshold switch, a tunneling diode, a Zener diode, etc.; however, this embodiment does not limit its application.

[0031] As can be understood from the preceding description, the variable resistance memory provided in this embodiment can be composed of only resistors for each memory cell without a selector, and the variable resistance memory can work without relying on a selector.

[0032] In practical implementation, the write circuit, upon receiving commands from the controller, provides bit-line bias voltage and word-line bias voltage to the memory cell array. Its core function is to output the required voltage signals according to the controller's instructions. The controller, in turn, controls the write circuit by sending control commands during the read process, instructing the write circuit to provide word-line bias voltage and bit-line bias voltage to the memory cell array.

[0033] Understandably, bias voltages are provided by the write circuitry to the word line bias voltage and bit line bias voltage of the memory cell array during read operations. The word line bias voltage, applied to the word lines, determines whether the selected memory cell is activated. The bit line bias voltage, applied to the bit lines, controls the current flow within the memory cell.

[0034] In this embodiment, a two-step read process is involved. Specifically, in the first read process, the controller provides a first set of bias voltages to the memory cell array through the write circuit; in the second read process, the controller provides a second set of bias voltages to the memory cell array through the write circuit.

[0035] For further details, please refer to [link / reference]. Figure 2To facilitate differentiation, in each step, the bit line bias voltage provided to the selected target memory cell is denoted as the first specified value VRHSEL, and the word line bias voltage provided to the selected target memory cell is denoted as the second specified value VRLSEL; similarly, the bit line bias voltage provided to other unselected memory cells is denoted as the third specified value VRHUSEL, and the word line bias voltage provided to other unselected memory cells is denoted as the fourth specified value VRLUSEL.

[0036] It should be noted that during each reading step, the first specified value and the second specified value are different. The first specified value and the third specified value are on the same side of the second specified value, that is, the first specified value and the third specified value are both greater than the second specified value, or the first specified value and the third specified value are both less than the third specified value.

[0037] Furthermore, during the two reading processes, the values ​​of the first, third, and fourth specified values ​​remain unchanged in the first and second reading processes, while the value of the second specified value differs in the first and second reading processes.

[0038] During each reading step, the values ​​of the first, second, third, and fourth specified values ​​are set according to actual needs. In this implementation, they are not limited, as long as the above requirements are met.

[0039] Figure 3 A schematic diagram illustrating the implementation principle of a two-step reading process is shown for an exemplary embodiment of this application, wherein, Figure 3 Figure (A) shows the first reading process. Figure 3 Figure (B) shows the second reading process. Figure 4 for Figure 3 The diagram shows the bias voltage during the two reading processes. Please also refer to... Figure 3 and Figure 4 ,For example, Figure 3 and Figure 4 In the example shown, during the first read operation, the bit line bias voltage VRHSEL provided to the selected target memory cell is VDD, and the word line bias voltage VRLSEL is 0. The voltage difference between the two is used to activate the target memory cell. Furthermore, the bit line bias voltage VRHUSEL provided to the unselected memory cells is VDD / 2, and the word line bias voltage VRLUSEL is VDD / 2, to suppress leakage current in the unselected memory cells. Finally, the read circuit reads the first read signal of the memory cell array, which is IBL, denoted as lbl_phase0.

[0040] It should be noted that in this embodiment, VDD is the read voltage. In different circuits, the specific voltage value corresponding to VDD may be different. For example, VDD can be 1.8 V, 3.3 V, 5 V, etc.

[0041] Furthermore, the second reading process is based on the first reading process. The controller controls the writing circuit to provide a second set of bias voltages to the memory cell array. The second set of bias voltages is a set of voltages that are different from the first set of bias voltages.

[0042] See Figure 3 Figure (B) in the middle, and Figure 4 For example, in the example above, during the second read step, the bit line bias voltage VRHSEL provided to the selected target memory cell remains VDD, while the word line bias voltage VRLSEL is changed to 2VDD. The two form a voltage difference used to acquire the current of the target memory cell at a higher word line voltage level. Similarly, the bit line bias voltage VRHUSEL provided to other unselected memory cells remains VDD / 2, and the word line bias voltage VRLUSEL remains VDD / 2, used to suppress leakage current in the unselected memory cells. At this time, the second read step is performed, and the second read signal obtained is IBL, denoted as lbl_phase1.

[0043] It should be noted that, as described above, the bias voltage provided during each reading step must meet the following conditions:

[0044] (1) The first specified value VRHSEL and the third specified value VRHUSEL are located on the same side of the second specified value VRLSEL; that is, VRHSEL > VRLSEL and VRHUSEL > VRLSEL, or VRHSEL < VRLSEL and VRHUSEL < VRLSEL.

[0045] (2) The first specified value and the third specified value are greater than the maximum value among the fourth specified values ​​or less than the minimum value among the fourth specified values. In other words, the first specified value is greater than the maximum value among the fourth specified values ​​and the third specified value is greater than the maximum value among the fourth specified values; or, the first specified value is less than the minimum value among the fourth specified values ​​and the third specified value is less than the minimum value among the fourth specified values, that is, VRHSEL > max{VRLUSEL} and VRHUSEL > max{VRLUSEL}, or VRHSEL < min{VRLUSEL} and VRHUSEL < min{VRLUSEL}.

[0046] Furthermore, the following conditions must be met between the two read steps:

[0047] (1) Between the two reading steps, the first specified value, the third specified value and the fourth specified value remain unchanged, while the second specified value changes, that is, VRHSEL, VRHUSEL and VRLUSEL remain unchanged, while VRLSEL changes.

[0048] (2) Between the two readings, the second specified value VRLSEL remains unchanged.

[0049] It should be noted that the specific values ​​of the first, second, third, and fourth specified values ​​are set according to actual needs, and are not limited in this embodiment. In specific implementation, by setting the specific values ​​of the first, second, third, and fourth specified values, the direction of the total current is kept consistent between the two read steps. That is, the leakage current of each row of unselected memory cells is IL, the current of the selected memory cells in the first read step is IR, and the current in the second read step is -IR. It is necessary to ensure that IL+IR and IL-IR are in the same direction.

[0050] It should be noted that when each memory cell is composed of a selector and a resistor connected in series, the voltage difference between the first specified value and the second specified value is greater than the selector's turn-on voltage. That is, the values ​​of VRHSEL - VRLSEL are greater than the selector's turn-on voltage.

[0051] In addition, the values ​​of VRHUSEL-VRLSEL, VRHUSEL-VRLUSEL, and VRHSEL-VRLUSEL are made less than the selector's turn-on voltage to ensure that other unselected memory cells are not accessed.

[0052] Understandably, by controlling the bias voltage of each memory cell during each read step, current leakage and crosstalk can be effectively prevented, ensuring the accuracy of the read process. During the first and second read steps, by providing different word line and bit line bias voltages, the controller can selectively access target memory cells while maintaining a stable voltage for unselected memory cells, thus avoiding signal interference.

[0053] Furthermore, after two reads, for each target memory cell, the read circuit performs a subtraction operation based on the first read signal of the target memory cell in the first read process and the second read signal of the target memory cell in the second read process to obtain the resistance value of the target memory cell.

[0054] Specifically, by using subtraction, the noise and errors that are the same in the first and second reading processes can be canceled out, the influence of other leakage paths in the memory array can be eliminated, and the resistance value of the target memory cell can be accurately obtained.

[0055] In practical implementation, for example, referring to the example above, the first read signal IBL in the first reading process is Ibl_phase0, and the second read signal IBL in the second reading process is Ibl_phase1. The difference between Ibl_phase0 and Ibl_phase1 is the final read signal, which is equal to (device current under VDD bias) - (device current under -VDD bias) - (device current under VDD bias). In this way, the current from other leakage paths is eliminated.

[0056] As described above, it is understood that subtraction effectively cancels out the same noise and error in the two read processes, ensuring accurate measurement of the resistance of the target memory cell and improving reliability and measurement accuracy.

[0057] It should be noted that the difference between Ibl_phase0 and Ibl_phase1 is a current value, which can be converted into a binary resistance value through transformation. The specific implementation principle and process of this conversion can be found in relevant technical descriptions, and will not be elaborated upon here.

[0058] The variable resistance memory provided in this embodiment applies different word line bias voltages to the target memory cell during two-step read processes, while keeping the bias voltages of the bit lines and unselected cells constant. This ensures that the leakage current of the unselected cells remains consistent in both reads. The read circuit can effectively cancel out the influence of leakage current by subtracting the two read signals, retaining only the true response signal of the target memory cell. Therefore, it not only significantly improves the accuracy and stability of resistance reading, but also reduces interference caused by leakage current accumulation in large-scale arrays, improves the signal-to-noise ratio, avoids misjudgments, and simplifies the overall design and reduces power consumption by eliminating the need for additional complex isolation circuit structures.

[0059] It should be noted that the variable resistance memory provided in this application may be RRAM, PCRAM, MRAM, FRAM, etc., and is not limited to this embodiment.

[0060] The specific form of the read circuit in the variable resistor memory provided in this application is described below.

[0061] Optionally, in one possible implementation, Figure 5 A schematic diagram illustrating the implementation principle of a readout circuit as shown in an exemplary embodiment of this application; wherein, Figure 5 Figure (A) is a schematic diagram of a read circuit shown in an exemplary embodiment. Figure 5 Figure (B) in the diagram is the signal timing diagram for the readout circuit. Please refer to it. Figure 5 The reading circuit includes a first clamping circuit and a first current memory circuit;

[0062] The first clamping circuit includes a first MOS transistor M1, the gate of the first MOS transistor M1 is connected to a clamping voltage source, the source of the first MOS transistor M1 is connected to the word line where the target memory cell is located, and the drain of the first MOS transistor M1 is connected to the input terminal of the first current memory circuit.

[0063] The first current memory circuit includes a second MOSFET M2, a first capacitor C1, and a first switch Q1; the source of the second MOSFET M2 constitutes the input terminal of the current memory circuit, the drain of the second MOSFET M2 is connected to a preset first voltage source, and the gate of the second MOSFET M2 is connected to the first transistor of the first switch Q1.

[0064] The first terminal of the first capacitor C1 is connected to a preset second voltage source, the second terminal of the first capacitor C1 is connected to the first terminal of the first switch Q1, and the second terminal of the first switch Q1 is connected to the source of the second MOS transistor M2 to form the output terminal of the reading circuit.

[0065] In the first step of the reading process, the first switch Q1 is in the off state, and the first reading signal is stored in the first capacitor C1; in the second step of the reading process, the first switch C1 is in the on state, and the voltage value output by the output terminal changes according to the first reading signal stored in the first capacitor C1 and the currently input second reading signal.

[0066] For details, please refer to Figure 5 During the first read operation, the word line current IBL output by the memory array is limited by the first MOSFET M1 and then applied to the source of the second MOSFET M2. The first capacitor C1 stores the gate voltage of the second MOSFET M2, which records the current Ibl_phase0 of the first read signal. At this time, since the first switch Q1 is off, the output V... OUT The voltage does not change directly with IBL for the time being, but remains unchanged. Furthermore, during the second read process, the first switch Q1 is turned on, the gate voltage of the second MOSFET M2 is maintained at Ibl_phase0, the second read signal Ibl_phase1 during the second read process flows through MI, Ibl_phase0 and Ibl_phase1 are subtracted at the output terminal, and the difference between the two is output at the output terminal.

[0067] Referring to the preceding description, it can be understood that this read circuit, by introducing a first clamping circuit at the word line end, can stabilize the word line potential within a preset clamping voltage range, thereby avoiding read errors caused by voltage fluctuations. Simultaneously, the included first current memory circuit samples and holds the read current of the memory cell during the first read step, and in the second read step, it works together with the current input signal at the output end to achieve the holding and superposition of the read signal. Therefore, this circuit not only improves the stability and anti-interference capability of the read process but also reduces the power consumption caused by continuous driving.

[0068] Furthermore, in another possible implementation, Figure 6 The schematic diagram illustrates the implementation principle of a read circuit for another exemplary embodiment of this application. Figure 6 Figure (A) is a schematic diagram of a read circuit shown in an exemplary embodiment. Figure 6 Figure (B) in the diagram is the signal timing diagram of the reading circuit.

[0069] The read circuit includes a second clamping circuit, a current mirror circuit, and a second current memory circuit.

[0070] The second clamping circuit includes a third MOS transistor M3, the gate of which is connected to a clamping voltage source, the source of which is connected to the word line of the target memory cell, and the drain of which is connected to the input terminal of the current mirror circuit.

[0071] The input terminal of the current mirror circuit is connected to the input terminal of the second current memory circuit;

[0072] The second current memory circuit includes a fourth MOSFET M4, a second capacitor C2, and a second switch Q2; the first terminal of the second switch Q2 is connected to the drain of the fourth MOSFET M4 to form the input terminal of the second current memory circuit.

[0073] The second terminal of the second switch Q2 is connected to the first terminal of the second capacitor C2 and the gate of the fourth MOS transistor M4, respectively, and the second terminal of the second capacitor C2 is grounded.

[0074] The source of the fourth MOS transistor M4 is grounded, and the drain of the fourth MOS transistor M4 constitutes the output terminal of the read circuit.

[0075] In the first reading process, the second switch Q2 is in the off state, and the first reading signal is stored in the second capacitor; in the second reading process, the second switch Q2 is in the on state, and the current value output by the output terminal changes according to the first reading signal stored in the second capacitor C2 and the currently input second reading signal.

[0076] Specifically, in the first reading step, the word line current enters the current mirror circuit through M3, resulting in a mirrored current. This mirrored current is stored in capacitor C2, and the output is temporarily held at this time. Further, in the second reading step, the charge in capacitor C2 drives M4, causing M4 to convert the stored signal into a current output. At this point, the output is simultaneously affected by the stored signal in the capacitor and the current current mirrored current, resulting in the output being the result of subtracting the historical signal from the current signal.

[0077] Referring to the preceding description, it can be understood that this read circuit achieves step-by-step reading of the target memory cell and retention of the current signal through the coordinated action of the second clamping circuit, the current mirror circuit, and the second current memory circuit. Specifically, the third MOSFET in the second clamping circuit, under the control of the clamping voltage, introduces the current on the word line of the target memory cell into the current mirror circuit, ensuring the stability of the current signal amplitude. The current mirror circuit copies and transmits the input current and synchronously sends it to the second current memory circuit. The second current memory circuit utilizes the structure of the second capacitor and the fourth MOSFET. In the first reading process, the second switch is turned off, and the voltage corresponding to the read current signal is stored in the capacitor, thereby maintaining the first read signal. In the second reading process, the second switch is turned on, and the voltage stored in the capacitor, together with the newly input second read signal, controls the fourth MOSFET to output the corresponding current, thereby superimposing or comparing the two read signals for output. Through this design, the circuit can achieve stable reading of the memory cell and retain previous current information in step-by-step operations.

[0078] Optional, Figure 7 A partial schematic diagram of a variable memory cell shown in another exemplary embodiment of this application is provided below. Figure 7 In one possible implementation, the selected target memory cell includes a plurality of memory cells, the plurality of memory cells include a reference memory cell, and the variable resistor memory further includes a comparator;

[0079] The comparator is used to compare the resistance value of the target memory (excluding the reference memory cell) with the resistance value of the reference memory cell, and output the resistance state information of the target memory according to the comparison result; the resistance state information is a binary signal used to indicate whether the target memory cell is in a high resistance state or a low resistance state.

[0080] It should be noted that the selected memory cells are usually located on different bit lines during selection. Optionally, a comparator is used to compare the resistance value of the target memory cell (excluding the reference memory cell) with the resistance value of the reference memory cell, and outputs the resistance state information of the target memory cell based on the comparison result. This resistance state information is a binary signal used to indicate whether the target memory cell is in a high-resistance state or a low-resistance state.

[0081] In this embodiment, the resistance value of the target memory cell is compared with the reference resistance value of the reference memory cell to output clear binary resistance state information. Specifically, during the reading process, the resistance value of each target memory cell is obtained through two steps of reading and subtraction. Simultaneously, a reference memory cell is pre-selected, and its resistance value is a preset value used as a threshold for determining high and low resistance states. The comparator compares the resistance value of the target memory cell with the resistance value of the reference memory cell. If the resistance value of the target memory cell is greater than the resistance value of the reference memory cell, the comparator outputs 1, indicating that the target memory is in a high resistance state; if the resistance value of the target memory cell is less than or equal to the resistance value of the reference memory cell, the comparator outputs 0, indicating that the target memory is in a low resistance state.

[0082] In this way, continuous resistance information is standardized and delimited through a reference memory cell, transforming it into binary resistance information. This mechanism effectively shields the impact of noise interference and process deviations on absolute resistance determination during the reading process, improving the stability and accuracy of the reading.

[0083] Optionally, in one possible implementation, the controller is further configured to determine the resistance level of the target memory cell based on the resistance value of the target memory cell and a preset comparison relationship between the reference resistance range and the resistance level.

[0084] Specifically, the preset correspondence between the reference resistance range and the resistance level is set according to actual needs, and is not limited in this embodiment. For example, in one possible implementation, Table 1 shows the preset correspondence between the reference resistance range and the resistance level as illustrated in an exemplary embodiment of this application:

[0085] Table 1. Correspondence between preset reference resistance range and resistance level

[0086] Reference resistance range Binary representation Resistance level 1kΩ 00 low resistance state [1kΩ 3kΩ] 01 medium resistance state [3kΩ 5kΩ] 10 Medium to high resistance state Greater than 5k ohms 11 High resistance state

[0087] In specific implementation, referring to Table 1, when the resistance value corresponding to the target memory cell is obtained based on the subtraction operation, the resistance value is represented by the current value. Further, the current value is converted into a binary representation. Further, the correspondence between the resistance value of the target memory cell and the correspondence between the preset reference resistance value range and the resistance state level is searched, that is, the correspondence containing the binary representation is searched, and then the resistance state level recorded in the correspondence is determined as the resistance state level of the target memory cell.

[0088] The method provided in this embodiment effectively avoids misjudgment problems caused by inherent resistance fluctuations and noise interference when making a single threshold judgment by pre-setting the reference resistance range corresponding to each resistance level. In this way, even if there is a small deviation in the resistance value of the target memory cell, as long as it is within the corresponding range, its resistance level can be accurately identified.

[0089] In addition to providing a variable resistance memory, this application also provides a control method for the variable resistance memory. The control method for the variable resistance memory provided in this application is described below.

[0090] Figure 8 This is a flowchart of an embodiment of the control method for the variable resistor memory provided in this application. Please refer to... Figure 8 The control method for the variable resistance memory provided in this embodiment includes:

[0091] S801. During the first step of reading, the control write circuit provides a first set of bias voltages to the memory cell array, and during the second step of reading, the control write circuit provides a second set of bias voltages to the memory cell array.

[0092] In each reading step, the bit line bias voltage provided to the selected target memory cell is a first specified value, and the word line bias voltage is a second specified value; the bit line bias voltage provided to other unselected memory cells is a third specified value, and the word line bias voltage is a fourth specified value; the first specified value and the second specified value are different, and the first specified value and the third specified value are located on the same side of the second specified value; the first specified value, the third specified value, and the fourth specified value remain unchanged in the first reading step and the second reading step, while the second specified value is different in the first reading step and the second reading step.

[0093] For details on the specific implementation principles and processes of the reading process, please refer to the above description; they will not be repeated here.

[0094] S802. For each target memory cell, the resistance value of the target memory cell is obtained by subtracting the first read signal of the target memory cell in the first step of the read process and the second read signal of the target memory cell in the second step of the read process.

[0095] For details on the specific implementation principles and processes of this step, please refer to the descriptions in relevant technologies; they will not be repeated here.

[0096] Optionally, the selected target memory cell includes multiple memory cells, the multiple memory cells including a reference memory cell; the method further includes:

[0097] The resistance value of the target memory (excluding the reference memory cell) is compared with the resistance value of the reference memory cell, and the resistance state information of the target memory is output according to the comparison result; the resistance state information is a binary signal used to indicate whether the target memory cell is in a high resistance state or a low resistance state.

[0098] Optionally, based on the comparison result, the resistive state information of the target memory can be output, including:

[0099] The comparison result indicates that the resistance value of the target memory is greater than the resistance value of the reference memory cell. If the resistance state information of the target memory is 1, the resistance state information of the target memory is output as 0.

[0100] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A variable resistance memory, characterized in that, The variable resistance memory includes a memory cell array, a controller, a write circuit, and a read circuit; The write circuit is used to provide a bias voltage to the memory cell array under the control of the controller; The controller is configured to control the write circuit to provide a first set of bias voltages to the memory cell array during the first reading process, and to control the write circuit to provide a second set of bias voltages to the memory cell array during the second reading process. In each reading process, the bit line bias voltage provided to the selected target memory cell is a first specified value, and the word line bias voltage is a second specified value; the bit line bias voltage provided to other unselected memory cells is a third specified value, and the word line bias voltage is a fourth specified value. The first specified value and the second specified value are different, and the first specified value and the third specified value are located on the same side of the second specified value. The values ​​of the first specified value, the third specified value, and the fourth specified value remain unchanged during the first reading process and the second reading process, while the value of the second specified value differs during the first reading process and the second reading process. The read circuit is used to perform a subtraction operation on each target memory cell, based on the first read signal of the target memory cell in the first step of the read process and the second read signal of the target memory cell in the second step of the read process, to obtain the resistance value of the target memory cell. The read circuit includes a first clamping circuit and a first current memory circuit. The first clamping circuit includes a first MOSFET, the gate of the first MOSFET is connected to a clamping voltage source, the source of the first MOSFET is connected to the word line where the target memory cell is located, and the drain of the first MOSFET is connected to the input terminal of the first current memory circuit. The first current memory circuit includes a second MOSFET, a first capacitor, and a first switching transistor. The source of the second MOSFET constitutes the input terminal of the current memory circuit, the drain of the second MOSFET is connected to a preset first voltage source, and the gate of the second MOSFET is connected to the first terminal of the first switching transistor. The first terminal of the first capacitor is connected to a preset second voltage source, the second terminal of the first capacitor is connected to the first terminal of the first switching transistor, and the second terminal of the first switching transistor is connected to the source of the second MOSFET to form the output terminal of the read circuit. The read circuit includes a second clamping circuit, a current mirror circuit, and a second current memory circuit. The second clamping circuit includes a third MOSFET, the gate of which is connected to a clamping voltage source, the source of which is connected to the word line of the target memory cell, and the drain of which is connected to the input of the current mirror circuit. The input of the current mirror circuit is connected to the input of the second current memory circuit. The second current memory circuit includes a fourth MOSFET, a second capacitor, and a second switch. The first terminal of the second switch and the drain of the fourth MOSFET are connected to form the input of the second current memory circuit. The second terminal of the second switch is connected to the first terminal of the second capacitor and the gate of the fourth MOSFET, respectively. The second terminal of the second capacitor is grounded. The source of the fourth MOSFET is grounded, and the drain of the fourth MOSFET forms the output of the read circuit.

2. The variable resistance memory according to claim 1, characterized in that, The selected target memory cell includes multiple memory cells, including a reference memory cell; the variable resistor memory also includes a comparator. The comparator is used to compare the resistance value of the target memory cell (excluding the reference memory cell) with the resistance value of the reference memory cell, and output the resistance state information of the target memory cell according to the comparison result; the resistance state information is a binary signal used to indicate whether the target memory cell is in a high resistance state or a low resistance state.

3. The variable resistance memory according to claim 1, characterized in that, The first switch is in the off state during the first reading process, and the first reading signal is stored in the first capacitor; The first switch is in the on state during the second reading process, and the voltage value output by the output terminal changes according to the first reading signal stored in the first capacitor and the currently input second reading signal.

4. The variable resistance memory according to claim 1, characterized in that, The second switch is in the off state during the first reading process, and the first reading signal is stored in the second capacitor; The second switch is in the on state during the second reading process, and the current value output by the output terminal changes according to the first reading signal stored in the second capacitor and the currently input second reading signal.

5. The variable resistance memory according to claim 1, characterized in that, Each memory cell in the memory cell array is composed of a resistor; or, Each memory cell in the memory cell array consists of a selector and a resistor connected in series.

6. The variable resistance memory according to claim 5, characterized in that, When each memory cell is composed of a selector and a resistor connected in series, the voltage difference between the first specified value and the second specified value is greater than the turn-on voltage of the selector.

7. The variable resistance memory according to claim 1, characterized in that, The controller is further configured to determine the resistance level of each target memory cell based on the resistance value of the target memory cell and a comparison relationship between a preset reference resistance range and resistance level.

8. A control method for a variable resistance memory, characterized in that, The method includes: In the first reading step, the control write circuit provides a first set of bias voltages to the memory cell array, and in the second reading step, the control write circuit provides a second set of bias voltages to the memory cell array. In each reading step, the bit line bias voltage provided to the selected target memory cell is a first specified value, and the word line bias voltage is a second specified value; the bit line bias voltage provided to other unselected memory cells is a third specified value, and the word line bias voltage is a fourth specified value. The first specified value and the second specified value are different, and the first specified value and the third specified value are located on the same side of the second specified value. The values ​​of the first specified value, the third specified value, and the fourth specified value remain unchanged in the first reading step and the second reading step, while the value of the second specified value differs in the first reading step and the second reading step. For each target memory cell, the read circuit performs a subtraction operation based on the first read signal of the target memory cell in the first step of the read process and the second read signal of the target memory cell in the second step of the read process to obtain the resistance value of the target memory cell; The read circuit includes a first clamping circuit and a first current memory circuit. The first clamping circuit includes a first MOSFET, the gate of which is connected to a clamping voltage source, the source of which is connected to the word line where the target memory cell is located, and the drain of which is connected to the input terminal of the first current memory circuit. The first current memory circuit includes a second MOSFET, a first capacitor, and a first switch. The source of the second MOSFET forms the input terminal of the current memory circuit, the drain of which is connected to a preset first voltage source, and the gate of which is connected to the first terminal of the first switch. The first terminal of the first capacitor is connected to a preset second voltage source, the second terminal of which is connected to the first terminal of the first switch, and the second terminal of the first switch is connected to the source of the second MOSFET to form the output terminal of the read circuit. The read circuit includes a second clamping circuit, a current mirror circuit, and a second current memory circuit. The second clamping circuit includes a third MOSFET, the gate of which is connected to a clamping voltage source, the source of which is connected to the word line of the target memory cell, and the drain of which is connected to the input of the current mirror circuit. The input of the current mirror circuit is connected to the input of the second current memory circuit. The second current memory circuit includes a fourth MOSFET, a second capacitor, and a second switch. The first terminal of the second switch and the drain of the fourth MOSFET are connected to form the input of the second current memory circuit. The second terminal of the second switch is connected to the first terminal of the second capacitor and the gate of the fourth MOSFET, respectively. The second terminal of the second capacitor is grounded. The source of the fourth MOSFET is grounded, and the drain of the fourth MOSFET forms the output of the read circuit.

9. The method according to claim 8, characterized in that, The selected target memory cell includes multiple memory cells, the multiple memory cells including a reference memory cell; the method further includes: The resistance value of the target memory cell (excluding the reference memory cell) is compared with the resistance value of the reference memory cell, and the resistance state information of the target memory cell is output according to the comparison result; the resistance state information is a binary signal used to indicate whether the target memory cell is in a high resistance state or a low resistance state.

10. The method according to claim 9, characterized in that, Based on the comparison results, the resistive state information of the target memory cell is output, including: If the comparison result indicates that the resistance value of the target memory cell is greater than the resistance value of the reference memory cell, the resistance state information of the target memory cell is output as 1; otherwise, the resistance state information of the target memory cell is input as 0.

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