Capacitors for microelectronic devices with increased density and related methods

Abstract

The invention relates to capacitors for microelectronic devices with increased density and related methods. A capacitor for a microelectronic device includes a first electrode and a second electrode. The first electrode includes: a first base portion at a first level; a second substrate portion at a second level; a first substrate contact extending from the first substrate portion to the second substrate portion; a first plate extending from the first base portion; a second plate extending from the second base portion; and a capacitor plate contact extending from the first plate to the second plate. The second electrode includes: a first base portion formed at the first level; a second substrate portion formed at the second level; a second substrate contact extending from the first substrate portion to the second substrate portion; a first plate extending from the first base portion; a second plate extending from the second base portion; and a capacitor plate contact extending from the first plate to the second plate. Additional capacitors and related methods are also disclosed.

Description

[0001] Cross-reference of related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 654,755, filed May 31, 2024, entitled “Capacitors for a Microelectronic Device HAVING INCREASED DENSITY AND RELATED METHODS,” filed pursuant to 35 U.S. SC § 119(e), and also claims the benefit of the filing date of U.S. Patent Application No. 19 / 195,257, filed April 30, 2025, entitled “Capacitors for a Microelectronic Device HAVING INCREASED DENSITY AND RELATED METHODS.” Technical Field

[0003] The embodiments disclosed herein relate to electronic devices and the manufacture of electronic devices. More specifically, embodiments of this disclosure relate to electronic devices, such as microelectronic devices having increased capacitor density. Background Technology

[0004] A capacitor is an electrical device that stores energy through electrical conductors (e.g., plates) separated by a dielectric (insulating) material. One conductor can accept a positive charge and the other can accept a negative charge, thereby maintaining the charge in the capacitor. Many types of capacitors exist for a wide variety of applications. These applications include memory, noise filtering, circuit system protection, and the like.

[0005] An example of a capacitor is a MIM capacitor. MIM capacitors operate as parallel-plate capacitors, where metal plates (electrodes) are separated by a dielectric (insulating) material. MIM capacitors are known to provide stable capacitance and high capacitance per unit area. Electronic devices contain arrays of memory cells, each memory cell containing a storage node (e.g., a capacitor) and access means (e.g., a transistor). Peripheral circuitry (e.g., driver circuitry, decoders, sense amplifiers, etc.) is used to access and read / or write data associated with the memory cells. Summary of the Invention

[0006] In some embodiments, a capacitor for a microelectronic device includes a first electrode and a second electrode. The first electrode includes: a first substrate portion at a first layer; a second substrate portion at a second layer; a first substrate contact extending from the first substrate portion to the second substrate portion; one or more first plates extending from the first substrate portion; one or more second plates extending from the second substrate portion; and a capacitor plate contact extending from the one or more first plates to the one or more second plates. The second electrode includes: a first substrate portion formed at the first layer; a second substrate portion formed at the second layer; a second substrate contact extending from the first substrate portion to the second substrate portion; one or more first plates extending from the first substrate portion; one or more second plates extending from the second substrate portion; and a capacitor plate contact extending from the one or more first plates to the one or more second plates.

[0007] In some embodiments, a method of manufacturing a capacitor for a microelectronic device includes: forming a first electrode plate with a first capacitor electrode at a first layer; forming a first capacitor plate contact connected to and extending from the first electrode plate; forming a second electrode plate with a second capacitor electrode at the first layer; and forming a second capacitor plate contact connected to and extending from the second electrode plate. The method further includes a third electrode plate with the first capacitor electrode formed at a second layer and aligned with the first electrode plate, the third electrode plate being formed adjacent to the first capacitor plate contact, and the first capacitor plate contact electrically coupling the first electrode plate and the third electrode plate. The method further includes a fourth electrode plate with the second capacitor electrode formed at a second layer and aligned with the second electrode plate, the fourth electrode plate being formed adjacent to the second capacitor plate contact, and the second capacitor plate contact electrically coupling the second electrode plate and the fourth electrode plate.

[0008] In some embodiments, an electronic system includes: an input device; an output device; a processor device operatively connected to the input device and the output device; and a memory device operatively connected to the processor device. The memory device includes a capacitor for a microelectronic device, the capacitor including: a first electrode plate disposed at a first level; and a second electrode plate disposed at the first level, the second electrode plate being interdigitated with the first electrode plate. The capacitor further includes: a third electrode plate disposed at a second level and aligned with the first electrode plate; and a fourth electrode plate disposed at the second level and aligned with the second electrode plate, the fourth electrode plate being interdigitated with the third electrode plate. The capacitor further includes: a first capacitor plate contact extending from the first electrode plate to the third electrode plate and electrically coupling the first electrode plate and the third electrode plate; and a second capacitor plate contact extending from the second electrode plate to the fourth electrode plate and electrically coupling the second electrode plate and the fourth electrode plate. Attached Figure Description

[0009] For a detailed understanding of this disclosure, reference should be made to the following detailed description in conjunction with the accompanying drawings, wherein similar elements are generally designated by similar numerals, and wherein:

[0010] Figure 1 A schematic top view showing a conventional capacitor used in microelectronic devices;

[0011] Figure 2 A schematic top view showing a capacitor for a microelectronic device according to an exemplary embodiment of the present disclosure;

[0012] Figure 3 This is a partial schematic top view of a capacitor used in microelectronic devices, which can be shown as a section taken along the framed area D. Figure 1 The conventional capacitor or the one cut along the frame region D according to Figure 2 The capacitor of an exemplary embodiment of the disclosed content;

[0013] Figure 4 Display along from Figure 3 A schematic isometric view of a conventional capacitor, taken from the framed area A.

[0014] Figure 5 Demonstrating exemplary embodiments according to this disclosure along from Figure 3 A schematic isometric view of the capacitor cut off in the framed area A;

[0015] Figure 6A A schematic isometric view of a conventional capacitor is shown, and Figure 6B Showing the cut along line BB Figure 6A A schematic isometric cross-sectional view of a conventional capacitor;

[0016] Figure 7A A schematic isometric view of a capacitor according to an exemplary embodiment of the present disclosure is shown, and Figure 7B Showing the cut along line CC Figure 7A A schematic isometric cross-sectional view of a capacitor;

[0017] Figure 8A , Figure 8B and Figure 8C An exemplary contact width of a capacitor contact according to an exemplary embodiment of the present disclosure is shown;

[0018] Figure 9A , Figure 9B and Figure 9C An exemplary contact length of a capacitor contact according to an exemplary embodiment of the present disclosure is shown;

[0019] Figure 10 A side view of a capacitor according to an exemplary embodiment of the present disclosure is shown;

[0020] Figure 11A , Figure 11B and Figure 11C An exemplary process flow for manufacturing contacts for a capacitor according to an exemplary embodiment of the present disclosure is shown;

[0021] Figure 12A , Figure 12B and Figure 12C An exemplary process flow for manufacturing contacts for a capacitor according to exemplary embodiments of the present disclosure is shown; and

[0022] Figure 13 A schematic block diagram illustrating an exemplary electronic system according to an exemplary embodiment of the present disclosure is shown. Detailed Implementation

[0023] The descriptions given herein are not actual views of any capacitor or any component thereof for use in a microelectronic device, but are merely idealized representations used to describe embodiments of this disclosure.

[0024] The following description provides specific details (e.g., material type, material thickness, and process conditions) to provide a detailed description of the embodiments described herein. However, those skilled in the art will understand that the embodiments disclosed herein can be practiced without these specific details. In fact, the embodiments can be combined with conventional manufacturing techniques used in the semiconductor industry. Furthermore, the description provided herein does not constitute a complete description of an electronic device or a complete process flow for manufacturing an electronic device, and the structures described below do not constitute a complete electronic device. Only those process actions and structures necessary for understanding the embodiments described herein are described in detail below. Additional actions to form a complete electronic device can be performed using conventional techniques.

[0025] Unless otherwise indicated, the materials described herein can be formed using conventional techniques, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD) (including sputtering, evaporation, ionization PVD, and / or plasma-enhanced CVD), or epitaxial growth. Alternatively, the material can be grown in situ. Depending on the specific material to be formed, the technique used for depositing or growing the material can be selected by a person skilled in the art. Material removal can be accomplished using any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, planarization (e.g., chemical-mechanical planarization), or other known methods, unless the context otherwise indicates.

[0026] The accompanying drawings presented herein are for illustrative purposes only and do not represent actual views of any particular material, component, structure, electronic device, or electronic system. Variations in the shapes depicted in the drawings are expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas illustrated, but rather include, for example, shape deviations caused by manufacturing processes. For example, areas illustrated or described as box-shaped may have rough and / or non-linear characteristics, while areas illustrated or described as circular may contain some rough and / or linear characteristics. Furthermore, illustrated acute angles may be rounded, and vice versa. Therefore, the areas illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the areas and do not limit the scope of the claims. The drawings are not necessarily drawn to scale. Additionally, common elements between figures may retain the same numerical designations.

[0027] As used herein, the singular forms following “a”, “an” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0028] As used in this document, “and / or” includes any and all combinations of one or more of the associated listed items.

[0029] As used herein, the term “may” in relation to materials, structures, features, or methodological actions indicates that they are considered for implementation of embodiments of this disclosure, and this term is used preferentially over the more restrictive term “yes” in order to avoid any implication that other compatible materials, structures, features, and methods may be used in conjunction with them.

[0030] As used herein, for ease of description, spatial relative terms (e.g., "below," "under," "bottom," "above," "top," "front," "back," "left," "right," and the like) may be used to describe the relationship of one element or feature to another(s) illustrated in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of material other than those depicted in the figures. For example, if the material in the figures were inverted, an element described as "below" or "below" or "on the bottom of" other elements or features would be oriented as "above" or "on top" other elements or features. Thus, the term "below" may cover both "above" and "below" orientations depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped) and the spatial relative descriptors used herein may be interpreted accordingly.

[0031] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes the degree to which a given parameter, property, or condition is satisfied with small variations (e.g., within acceptable tolerances), as would be understood by one of ordinary skill in the art. For example, depending on the particular parameter, property, or condition that is substantially satisfied, it may be satisfied by at least 90.0%, at least 95.0%, at least 99.0%, or even at least 99.9%.

[0032] As used herein, the term “about” for a particular parameter includes the value and has a meaning defined by the context (e.g., it includes the degree of error associated with the measurement of the given parameter, as well as variations caused by manufacturing tolerances, etc.).

[0033] As used herein, the term "conductive material" means and includes electrically conductive materials. Conductive materials may include, but are not limited to, one or more of doped polysilicon, undoped polysilicon, metals, alloys, conductive metal oxides, conductive metal nitrides, conductive metal silicides, and conductive doped semiconductor materials. For example only, conductive materials may be tungsten (W) or tungsten nitride (WN). y Nickel (Ni), Tantalum (Ta), Tantalum nitride (TaN) y ), Tantalum silicide (TaSi) x Platinum (Pt), Copper (Cu), Silver (Ag), Gold (Au), Aluminum (Al), Molybdenum (Mo), Titanium (Ti), Titanium Nitride (TiN) y Titanium silicide (TiSi) x Titanium silicon nitride (TiSi) x N y ), Titanium aluminum nitride (TiAl) x N y ), molybdenum nitride (MoN) x ), iridium (Ir), iridium oxide (IrO) z ), Ruthenium (Ru), Ruthenium oxide (RuO) z One or more of the following: n-doped polycrystalline silicon, p-doped polycrystalline silicon, undoped polycrystalline silicon, and conductive doped silicon.

[0034] As used herein, the term “configured” means the size, shape, material composition, and arrangement of one or more of at least one structure and at least one device that facilitates the operation of one or more of the structure and the device in a predetermined manner.

[0035] As used herein, the phrase “coupled to” refers to structures that are operatively connected to each other, such as by direct ohmic connection or by indirect connection (e.g., via another structure) electrical connection.

[0036] As used herein, the term "dielectric material" means and includes electrically insulating materials. Dielectric materials may include, but are not limited to, one or more of insulating oxide materials or insulating nitride materials. Dielectric oxides may be oxide materials, metal oxide materials, or combinations thereof. Dielectric oxides may include, but are not limited to, silicon oxide (SiO₂). x Silicon dioxide (SiO2), phosphosilicate glass, borosilicate glass, borosilicate-phosphosilicate glass, fluorosilicate glass, alumina (AlO2) x ), gadolinium oxide (GdO) x ), Hafnium oxide (HfO) x ), magnesium oxide (MgO) x ), niobium oxide (NbO) x), tantalum oxide (TaO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x Hafnium silicate, dielectric oxide nitride materials (e.g., SiO2), x N y ), dielectric carbon nitride materials (e.g., SiO2) x C z N y ( ), or combinations thereof, or combinations of one or more of the listed materials with silicon oxide. Dielectric nitride materials may include, but are not limited to, silicon nitride.

[0037] As used herein, the term "electronic device" includes, but is not limited to, memory devices, and semiconductor devices, such as logic devices, processor devices, or radio frequency (RF) devices, which may or may not incorporate memory. Furthermore, electronic devices may incorporate memory, among other functions, for example, a so-called "system-on-a-chip" (SoC) that includes both a processor and memory, or an electronic device that includes both logic and memory. Electronic devices may, for example, be 3D electronic devices, such as 3D NAND flash memory devices.

[0038] Figure 1 , 4 Examples of conventional capacitors 10 for electronic devices (e.g., microelectronic devices) are shown in 6A and 6B. The capacitor 10 may include a first electrode 102 and a second electrode 104. The first electrode 102 may include a plurality of plates 106 extending from a substrate portion 103. The capacitor 10 may include a plurality of substrate portions 103 and a plurality of plates 106 at different levels (e.g., at a first level 107a, a second level 107b, and a third level 107c), such as... Figure 4 and 6A As shown in the diagram. The second electrode 104 may also include a plurality of plates 108 extending from the base portion 105. The base portion 105 and the plurality of plates 108 may be located at layers corresponding to those base portions and plates in the first electrode 102, for example at layers 107a, 107b, 107c, as shown in the diagram. Figure 4 and 6A As shown in the figure. The plate 106 of the first electrode 102 and the plate 108 of the second electrode 104 may be interdigitated (e.g., as shown in the figure). Figure 1 , 4 (As shown in 6A and 6B), such that the first and second electrodes 102 and 104 respectively define the first and second terminals of the capacitor 10. In some embodiments, dielectric material 109 may be disposed between the first and second electrodes 102 and 104.

[0039] The base portion 103 of the first electrode 102 may include a base contact 110 extending between a first layer 107a and a second layer 107b and between the second layer 107b and a third layer 107c. Similarly, the base portion 105 of the second electrode 104 may include a base contact 112 extending between a first layer 107a and a second layer 107b and between the second layer 107b and a third layer 107c. The base contacts 110 and 112 are configured to electrically couple the first, second, and third layers 107a, 107b, and 107c of the base portions 103 and 105 of the first and second electrodes 102 and 104, respectively.

[0040] While not intended to be limiting, exemplary capacitors may be configured to have a length 114 that is relatively longer than the width 116 of the base portion 103 or base portion 105. In some examples, the length 114 may be about 300 times or about 400 times the width 116 of the base portion 103 or base portion 105. The plate 106 of the first electrode 102 and the plate 108 of the second electrode 104 may be configured to have a width 118 that is substantially similar to or smaller than the width 116 of the base portions 103, 105. For example, the width 118 of the plates 106, 108 may be about half to about equal to the width 116 of the base portions 103, 105. The width 120 of the distance between plates 106 and 108 (e.g., the width 120 of the dielectric material 109 between plates 106 and 108) may be similar to the width 118 of plates 106 and 108. The base contact 110 on the base portion 103 of the first electrode 102 and the base contact 112 on the base portion 105 of the second electrode 104 may be configured to have a square cross-section 124 similar in width to the width 118 of plates 106 and 108. The base contact 110 on the base portion 103 of the first electrode 102 and the base contact 112 on the base portion 105 of the second electrode 104 may have a distance 122 therebetween approximately equal to the width 116 of the base portions 103 and 105. The distal ends of each of plates 106 and 108 may be spaced apart by a distance 126 approximately equal to the width 116 of the base portions 103 and 105.

[0041] For example, although not intended to be limiting, an exemplary capacitor may be configured to have a length 114 of approximately 1000 dμm (where 1 dμm = 50 nm). The base portion 103 of the first electrode 102 and the base portion 105 of the second electrode 104 may be configured to have a width 116 of approximately 3 dμm. The plate 106 of the first electrode 102 and the plate 108 of the second electrode 104 may be configured to have a width 118 of approximately 2 dμm. The width 120 of the distance between the plates 106 and 108 (the width 120 of the dielectric material 109 between the plates 106 and 108) may be approximately 2 dμm. The base contact 110 on the base portion 103 of the first electrode 102 and the base contact 112 on the base portion 105 of the second electrode 104 may be configured to have a square cross-section 124 of 2 dμm × 2 dμm (the base portion 105 may not be perfectly square, as the square pattern may be rounded during subsequent processing and manufacturing). The base contact 110 on the base portion 103 of the first electrode 102 and the base contact 112 on the base portion 105 of the second electrode 104 may have a distance 122 of about 3 d μm between them. The distal end of each of the plates 106 and 108 may be spaced apart from the corresponding one of the base portions 103 and 105 by a distance 126 of about 3 d μm.

[0042] Figure 2 , 5 Images 7A and 7B illustrate examples of capacitors 20 having increased capacitor density compared to conventional capacitors 10 according to embodiments of the present disclosure. Capacitor 20 may be a capacitor for a microelectronic device and may include MIM capacitors, MOM capacitors, MOS capacitors, or the like. In some embodiments, capacitor 20 is a MIM capacitor. Capacitor 20 may include a first electrode 202 and a second electrode 204. The first electrode 202 may include a plurality of plates 206 (e.g., fingers, combs) extending vertically from a substrate portion 203. The substrate portion 203 and the plurality of plates 206 may be formed at various levels, such as at a first level 207a, a second level 207b, and a third level 207c, as shown below. Figure 5 and 7A As shown in the diagram. Therefore, the base portion 203 at the first layer 207a can be referred to as the first base portion, the base portion 203 at the second layer 207b can be referred to as the second base portion, and the base portion at the third layer can be referred to as the third base portion. Similarly, the plate 206 formed at the first layer can be referred to as the first plate, the plate 206 formed at the second layer can be referred to as the second plate, and the plate 206 formed at the third layer can be referred to as the third plate.

[0043] The distances between vertically adjacent layers 207a and 207b, and between vertically adjacent layers 207b and 207c, can be uniform, or the vertically adjacent layers 207a, 207b, and 207c can be spaced at different distances. For example, the distance between the first layer 207a, the second layer 207b, and the third layer 207c can range from approximately 200 nm to approximately 800 nm, for example, from approximately 300 nm to approximately 600 nm.

[0044] The second electrode 204 may also include a plurality of plates 208 extending from the base portion 205. The base portion 205 and the plurality of plates 208 may be formed at layers corresponding to those base portions and plates in the first electrode 202, for example at layers 207a, 207b, and 207c. Figure 5 and 7A As shown in the diagram. Therefore, the base portion 205 at the first layer 207a can be referred to as the first base portion, the base portion 205 at the second layer 207b can be referred to as the second base portion, and the base portion at the third layer can be referred to as the third base portion. Similarly, the plate 208 formed at the first layer can be referred to as the first plate, the plate 208 formed at the second layer can be referred to as the second plate, and the plate 208 formed at the third layer can be referred to as the third plate.

[0045] Although Figure 5 and 7A The diagram shows three layers 207a, 207b, and 207c, but only two layers or more may exist. For example, the layers of capacitor 20 may include other contact structures, wiring structures, gate, source, drain regions, or complementary metal-oxide-semiconductor (CMOS) circuit systems. The plate 206 of the first electrode 202 and the plate 208 of the second electrode 204 may be interdigitated (e.g., as shown in the diagram). Figure 2 , 5 (As shown in 7A and 7B), such that the first and second electrodes 202 and 204 respectively form the first and second terminals of the capacitor 20. In some embodiments, dielectric material 209 may be disposed between the first and second electrodes 202 and 204.

[0046] The base portion 203 of the first electrode 202 may include a first base contact 210 extending between a first layer 207a and a second layer 207b and between a second layer 207b and a third layer 207c. Similarly, the base portion 205 of the second electrode 204 may include a second base contact 212 extending between a first layer 207a and a second layer 207b and between a second layer 207b and a third layer 207c. The first and second base contacts 210 and 212 are configured to electrically couple the first, second, and third layers 207a, 207b, and 207c of the base portions 203 and 205 of the first and second electrodes 202 and 204, respectively. In other words, the first base contact 210 is configured to electrically couple the first, second, and third base portions of the first base portion 203 of the first electrode 202, and the second base contact 212 is configured to electrically couple the first, second, and third base portions of the second base portion 205 of the second electrode 204.

[0047] While not intended to be limiting, the exemplary capacitor 20 may be configured to have a length 214 that is relatively longer than the width 216 of the base portion 203 or base portion 205. In some examples, the length 214 may be approximately 300 or 400 times the width 216 of the base portion 203 or base portion 205. The plate 206 of the first electrode 202 and the plate 208 of the second electrode 204 may be configured to have a width 218 that is substantially similar to or smaller than the width 216 of the base portions 203, 205. For example, the width 218 of the plates 206, 208 may be approximately half to approximately equal to the width 216 of the base portions 203, 205. The width 220 of the distance between plates 206 and 208 (e.g., the width 220 of the dielectric material 209 between plates 206 and 208) may be similar to the width 218 of plates 206 and 208. The first base contact 210 on the base portion 203 of the first electrode 202 and the second base contact 212 on the base portion 205 of the second electrode 204 may be configured to have a square cross-section 224 similar in width to the width 218 of plates 206 and 208. The first base contact 210 on the base portion 203 of the first electrode 202 and the second base contact 212 on the base portion 205 of the second electrode 204 may have a distance 222 therebetween approximately equal to the width 216 of the base portions 203 and 205. The distal ends of each of plates 206 and 208 may be spaced apart by a distance 229 approximately equal to the width 216 of the base portions 203 and 205.

[0048] For example, although not intended to be limiting, the exemplary capacitor 20 may be configured to have a length 214 of approximately 1000 dμm. The base portion 203 of the first electrode 202 and the base portion 205 of the second electrode 204 may be configured to have a width 216 of approximately 3 dμm. The plate 206 of the first electrode 202 and the plate 208 of the second electrode 204 may be configured to have a width 218 of approximately 2 dμm. The width 220 of the distance between the plates 206 and 208 (e.g., the width 220 of the dielectric material 209 between the plates 206 and 208) may be approximately 2 dμm. The first base contact 210 on the base portion 203 of the first electrode 202 and the second base contact 212 on the base portion 205 of the second electrode 204 may be configured to have a square cross-section 224 of 2 dμm × 2 dμm. The first base contact 210 on the base portion 203 of the first electrode 202 and the second base contact 212 on the base portion 205 of the second electrode 204 may have a distance 222 of about 3 d μm therebetween. The distal end of each of the plates 206 and 208 may be spaced apart from the corresponding one of the base portions 203 and 205 by a distance 229 of about 3 d μm.

[0049] To increase the capacitor density of capacitor 20 compared to conventional capacitor 10 without changing the integration scheme, capacitor 20 may further include multiple capacitor plate contacts 226. For example... Figure 2 , 5 As shown in 7A and 7B, a plurality of capacitor plate contacts 226 exist along the length of the plate 206 of the first electrode 202 and the plate 208 of the second electrode 204. Figure 5 and 7A As shown, capacitor plate contact 226 extends from a first layer 207a of plate 206 of first electrode 202 to a second layer 207b of plate 206 of first electrode 202, and from the second layer 207b of plate 206 of first electrode 202 to a third layer 207c of plate 206 of first electrode 202. Similarly, capacitor plate contact 226 extends from a first layer 207a of plate 208 of second electrode 204 to a second layer 207b of plate 208 of second electrode 204, and from the second layer 207b of plate 208 of second electrode 204 to a third layer 207c of plate 208 of second electrode 204. In other words, capacitor plate contact 226 can electrically couple the first, second, and third plates of plate 206 of first electrode 202, and capacitor plate contact 226 can electrically couple the first, second, and third plates of plate 208 of second electrode 204.

[0050] Capacitor plate contact 226 in Figure 2 , 5Examples 7A and 7B are shown with a uniform pitch. For example, the pitch of the capacitor plate contact 226 can range from about 60 nm to about 110 nm, such as from about 60 nm to about 80 nm or from about 80 nm to about 100 nm. The pitch of the capacitor plate contact 226 can be customized depending on the desired spacing between the first electrode 202 and the second electrode 204. Although Figure 2 , 5 Examples 7A and 7B show capacitor plate contacts 226 evenly spaced on the first and second electrodes 202 and 204 of capacitor 20, but the spacing between adjacent capacitor plate contacts 226 can vary. Additionally, although... Figure 5 and 7A The capacitor plate contacts 226 between layers 207a, 207b, and 207c are vertically aligned with each other, but the capacitor plate contacts 226 between layers 207a and 207b and between layers 207b and 207c can be vertically offset from each other.

[0051] By adding capacitor plate contacts 226 along the plates 206, 208 (e.g., fingers, combs) of the first electrode 202 and the second electrode 204, the density and performance of the capacitor 20 can be increased by at least about 25% to about 30% compared to a conventional capacitor 10 which only includes base contacts 110, 112 on the base portions 103, 105. The capacitor plate contacts 226 achieve increased capacitance between the electrodes 202, 204 by increasing the total surface area of ​​each of the electrodes 202, 204 (e.g., terminals) of the capacitor 20. Without being bound by any theory, it is believed that the capacitor plate contacts 226 on the first electrode 202 and the second electrode 204 provide an edge field effect, which increases the capacitance of the capacitor 20. The edge field effect is achieved although the capacitor plate contacts 226 do not form a continuous plate. Increased density and performance can be achieved without increasing cost. Furthermore, the capacitor 20 can be formed using a process similar to that of the conventional capacitor 10. Therefore, the capacitor 20 can be formed without substantially changing the process. By utilizing capacitor plate contact 226, capacitor plate contact 226 can be used as a parallel plate capacitor between layers 207a, 207b and 207c of capacitor 20.

[0052] Although Figure 2 , 5 Examples of capacitor plate contacts 226 on the first and second electrodes 202, 204 of capacitor 20 are shown in 7A and 7B, but different configurations of capacitor plate contacts 226 are possible, such as... Figures 8A to 9C As shown in the image. Figures 8A to 9C Different configurations of capacitor plate contacts 226 on any of the plates 206 and 208 of capacitor electrodes 202 and 204 are shown. The capacitor plate contacts 226 may be configured with a width 228 (e.g., ...). Figures 8A to 8C (as shown in the image), and separated by a distance of 230 between adjacent capacitor plate contacts 226 (e.g. Figures 9A to 9C (As shown in the image). Figures 8A to 8C As shown in the configuration, the width 228 of the capacitor plate contact 226 may differ from the width 218 of the plates 206, 208 (e.g., smaller). Figure 8A and 8B (as shown in the image) or the same as (e.g.) Figure 8C (As shown in the image). For example, in Figure 8A In this configuration, the width 228a of the capacitor plate contact 226 can be configured to be approximately half the width 218 of the plates 206 and 208. In one example, the width 218 of the plates 206 and 208 can be approximately 2 dμm and the width 228a of the capacitor plate contact 226 can be approximately 1 dμm.

[0053] exist Figure 8B In another example shown, the width 228b of the capacitor plate contact 226 can be configured to be approximately three-quarters of the width 218 of the plates 206, 208. In one example, the width 218 of the plates 206, 208 can be approximately 2 dμm and the width 228b of the capacitor plate contact 226 can be approximately 1.5 dμm.

[0054] exist Figure 8C In another example shown, the width 228c of the capacitor plate contact 226 may be configured to be approximately the same as the width 218 of the plates 206, 208. In one example, the width 218 of the plates 206, 208 may be approximately 2 dμm and the width 228c of the capacitor plate contact 226 may be approximately 2 dμm.

[0055] As the width 228 of the capacitor plate contact 226 increases, the capacitance of the capacitor 20 increases. However, as the width 228 of the capacitor plate contact 226 increases, the likelihood that the capacitor plate contact 226 may detach from one of the layers 207a, 207b, 207c of the plates 206, 208 during processing (e.g., due to improper alignment) increases. This may increase the likelihood of a short circuit between the plates 206, 208. In some instances, a significant increase in capacitance can be achieved using the capacitor plate contact 226, which exhibits a width 228a that is substantially equal to half the width 218 of the plates 206, 208 (e.g., ...). Figure 8A (As shown in the figure), while also minimizing the possibility of misalignment between capacitor plate contact 226 and one of layers 207a, 207b, 207c.

[0056] like Figures 9A to 9C As shown, the distance 230 between adjacent capacitor plate contacts 226 can be configured to different lengths relative to the width 218 of either plate 206 or 208. For example, in Figure 9A In this embodiment, the distance 230a between adjacent capacitor plate contacts 226 can be approximately equal to the width 218 of plates 206 and 208. In one example, the width 218 of plates 206 and 208 can be approximately 2 dμm and the distance 230a between capacitor plate contacts 226 can be approximately 2 dμm.

[0057] exist Figure 9B In another example shown, the distance 230b between the capacitor plate contacts 226 may be approximately half the width 218 of the plates 206, 208. In one example, the width 218 of the plates 206, 208 may be approximately 2 d μm and the distance 230a between the capacitor plate contacts 226 may be approximately 1 d μm.

[0058] exist Figure 9C In another example shown, there may be no distance between adjacent capacitor plate contacts 226. In other words, capacitor plate contacts 226 may form a substantially continuous plate extending from a first layer 207a of plates 206, 208 to a second layer 207b or from a second layer 207b to a third layer 207c.

[0059] When the distance 230 between the capacitor plate contacts 226 decreases, the capacitance of capacitor 20 increases. However, it has been found that decreasing the distance 230 between the capacitor plate contacts 226 has a smaller effect on the capacitance of capacitor 20 compared to increasing the width 228 of the capacitor plate contacts 226 relative to the width 218 of the plates 206, 208. In some instances, decreasing the distance 230 between the capacitor plate contacts 226 can introduce increased complexity into the manufacture of capacitor 20. In some instances, a significant increase in capacitance can be achieved by having a length approximately equal to the width 218 of the plates 206, 208 (e.g., ...). Figure 9A The distance 230a between the capacitor plate contacts 226 (as shown in the figure) is achieved without introducing substantial changes to the process of forming the capacitor 20. Therefore, the capacitor 20 can be formed without different or complex processes.

[0060] In such Figure 2 In some examples shown, the capacitor plate contact 226 on the plate 206 of the first electrode 202 may be offset in the x-direction from the capacitor plate contact 226 on the plate 208 of the second electrode 204. In other examples, the capacitor plate contact 226 on the plate 206 of the first electrode 202 may be substantially aligned in the x-direction with the capacitor plate contact 226 on the plate 208 of the second electrode 204. In some examples, such as Figure 10As shown, capacitor plate contact 226 may exhibit sloping sidewalls (e.g., tapered) from top to bottom to facilitate manufacturing and ensure that capacitor plate contact 226 rests on one of the layers 207b, 207c of plates 206, 208 of capacitor 20. Therefore, the critical dimension (CD) of the upper portion of capacitor plate contact 226 may be relatively larger than the CD of the lower portion of capacitor plate contact 226. In some instances, the slope of capacitor plate contact 226 from the third layer 207c of plates 206, 208 to the second layer 207b of plates 206, 208 may be parallel to the plane parallel to layers 207a, 207b, 207c (e.g., ...). Figure 10 The angle between approximately 80 and 90 degrees is between the x-direction and the x-direction. In some instances, the slope of the capacitor plate contact 226 from the third layer 207c of plates 206, 208 to the second layer 207b of plates 206, 208 can be parallel to the plane parallel to layers 207a, 207b, 207c (e.g., Figure 10 The angle between the capacitor plate contact 226 and the second layer 207b of plates 206, 208 and the first layer 207a of plates 206, 208 is approximately 88 degrees. In some instances, the slope of the capacitor plate contact 226 from the second layer 207b of plates 206, 208 to the first layer 207a of plates 206, 208 may be parallel to the plane parallel to layers 207a, 207b, 207c (e.g., Figure 10 The angle between approximately 80 and 90 degrees is between the x-direction and the x-direction of the plates 206 and 208. In some examples, the slope of the capacitor plate contact 226 from the second layer 207b of the plates 206 and 208 to the first layer 207a of the plates 206 and 208 can be parallel to the plane parallel to the layers 207a, 207b, and 207c (e.g., Figure 10 The x-direction in the middle is about 89 degrees.

[0061] As mentioned above, the capacitor plate contacts 226 of capacitor 20 can be formed without altering the integration scheme of capacitor 20. The method of forming capacitor plate contacts 226, 326, and 426 can be robust against insufficient etching because the capacitor plate contacts 226, 326, and 426 can form a shield due to the proximity of the electric field lines. Capacitor plate contacts 226 can be formed using any suitable method. Figures 11A to 11C An example of forming a capacitor plate contact 326 according to an embodiment of the present disclosure is shown. The capacitor plate contact 326 can be coupled with... Figure 2 , 5 The capacitor plate contact 226 shown in 7A and 7B is similar to that described above. The capacitor plate contact 326 electrically connects a plate 306 at one layer to a plate 306 at another layer (e.g., an upper overlay layer, a lower overlay layer). The plate 306 or wire may be similar to the plate 206 of the first electrode 202. Although Figures 11A to 11CNot shown, but a plate or line similar to plate 208 of the second electrode 204 may exist laterally adjacent to plate 306.

[0062] exist Figure 11A In this embodiment, the capacitor plate contact 326 may be formed of a conductive material (such as those described above). The capacitor plate contact 326 may be surrounded by a first dielectric material 332 (such as those described above). By way of example only, an opening (not shown) may be formed in the first dielectric material 332 using conventional photolithography techniques. The opening may substantially correspond in size and shape to the size and shape of the capacitor plate contact 326 to be formed therein. A pad 333 may be formed in the opening prior to the formation of the conductive material of the capacitor plate contact 326. The capacitor plate contact 326 and the first dielectric material 332 may be formed using any suitable microfabrication process (such as CVD, ALD, PVD, or the like). The capacitor plate contact 326 and the first dielectric material 332 may be formed over a substrate structure (not shown). The substrate structure may be a substrate material or construction on which additional features (e.g., materials, structures, devices) of the microelectronic device are formed. The substrate structure may contain one or more materials, structures, and / or regions formed therein and / or on it. The substrate structure may include a semiconductor structure (e.g., a semiconductor wafer), or a substrate semiconductor material on a support structure. For example, the substrate structure may include a conventional silicon substrate (e.g., a conventional silicon wafer), or another bulk substrate comprising semiconductor material. Alternatively, the substrate structure may include a conductive structure. In some embodiments, the substrate structure includes one or more conductive features, structures, and / or regions formed therein and / or on it. A second dielectric material 334 may be formed over the capacitor plate contact 326 and the first dielectric material 332, such as... Figure 11A As shown in the figure. The second dielectric material 334 may be formed of the same material as the first dielectric material 332 or may be formed of a separate dielectric material.

[0063] like Figure 11B As shown, a trench 336 can be formed in the second dielectric material 334 adjacent to (e.g., directly adjacent to) the capacitor plate contact 326. The trench 336 can be formed using any suitable microfabrication process (e.g., by patterning the second dielectric material 334 using photolithography and etching). The trench 336 can substantially correspond in size and shape to the size and shape of the plate 306 or line to be formed therein. A pad 335 can be formed in the trench 336 prior to forming the plate 306. Figure 11C As shown, a plate 306 or line is formed of conductive material adjacent to the capacitor plate contact 326 and in the trench 336. The plate 306 can make electrical contact with the capacitor plate contact 326. Subsequently, additional semiconductor features corresponding to the overlay layers 207a, 207b, 207c of the microelectronic device can be formed over the plate 306 and the second dielectric material 334.

[0064] Therefore, in some embodiments, a capacitor for a microelectronic device includes a first electrode and a second electrode. The first electrode includes: a first substrate portion at a first layer; a second substrate portion at a second layer; a first substrate contact extending from the first substrate portion to the second substrate portion; one or more first plates extending from the first substrate portion; one or more second plates extending from the second substrate portion; and a capacitor plate contact extending from the one or more first plates to the one or more second plates. The second electrode includes: a first substrate portion formed at the first layer; a second substrate portion formed at the second layer; a second substrate contact extending from the first substrate portion to the second substrate portion; one or more first plates extending from the first substrate portion; one or more second plates extending from the second substrate portion; and a capacitor plate contact extending from the one or more first plates to the one or more second plates.

[0065] Figures 12A to 12C Another example of manufacturing capacitor plate contact 426 is shown. Capacitor plate contact 426 can be used with... Figure 2 , 5 The capacitor plate contact 226 shown in 7A and 7B is similar to that described above. In other words, the capacitor plate contact 326 can electrically connect a plate 306 at one layer to a plate 306 at another layer (e.g., an upper layer, a lower layer). The plate 406 or wire may be similar to the plate 206 of the first electrode 202. Although Figures 12A to 12C Not shown, but a plate or line similar to plate 208 of the second electrode 204 may exist laterally adjacent to plate 406.

[0066] exist Figure 12AIn this configuration, plate 406 or a line may be formed of a conductive material. Plate 406 may be surrounded by a first dielectric material 432. Plate 406 may be surrounded by a first dielectric material 432 (e.g., a dielectric material as described above). By way of example only, an opening (not shown) may be formed in the first dielectric material 432 using conventional photolithography techniques. The opening may substantially correspond in size and shape to the size and shape of the plate 406 formed therein. A pad 433 may be formed in the opening prior to the conductive material forming plate 406. Plate 406 and the first dielectric material 432 may be formed using any suitable microfabrication process (e.g., CVD, ALD, PVD, or similar). Plate 406 and the first dielectric material 432 may be formed over a substrate structure (not shown). The substrate structure may be a substrate material or construction on which additional features (e.g., materials, structures, devices) of a microelectronic device are formed. The substrate structure may contain one or more materials, structures, and / or regions formed therein and / or on it. The substrate structure may include a semiconductor structure (e.g., a semiconductor wafer), or a substrate semiconductor material on a support structure. For example, the substrate structure may include a conventional silicon substrate (e.g., a conventional silicon wafer), or another bulk substrate comprising semiconductor material. Alternatively, the substrate structure may include a conductive structure. In some embodiments, the substrate structure includes one or more conductive features, structures, and / or regions formed therein and / or on it. A second dielectric material 434 may be formed over the plate 406 and the first dielectric material 432, such as... Figure 12A As shown in the figure. The second dielectric material 434 may be formed of the same material as the first dielectric material 432 or may be formed of a separate dielectric material.

[0067] like Figure 12B As shown, a trench 438 can be formed in the second dielectric material 434 adjacent to (e.g., directly adjacent to) the plate 406. The trench 438 can be formed using any suitable microfabrication process (e.g., by patterning the second dielectric material 434 using photolithography and etching). The trench 438 can substantially correspond in size and shape to the size and shape of the capacitor plate contact 426 to be formed therein. A pad 435 can be formed in the trench 438 prior to forming the capacitor plate contact 426. Figure 12C As shown, capacitor plate contacts 426 are formed of conductive material adjacent to plate 406 and in trench 438. Capacitor plate contacts 426 can make electrical contact with plate 406. Subsequently, additional semiconductor features corresponding to the overlay layers 207a, 207b, 207c of the microelectronic device can be formed over capacitor plate contacts 426 and the second dielectric material 434.

[0068] Figure 11C and 12CThe capacitor plate contacts 326 and 426 shown can be used to electrically connect plates 306 and 406 at one layer to plates 306 and 406 at another layer (e.g., an upper layer, a lower layer). In other words, plates 306 and 406 at the layer corresponding to layer 207a can be electrically connected to the layer corresponding to layer 207b via capacitor plate contacts 326 and 426. Similarly, plates 306 and 406 at the layer corresponding to layer 207b can be electrically connected to the layer corresponding to layer 207c via capacitor plate contacts 326 and 426.

[0069] Therefore, in some embodiments, a method of manufacturing a capacitor for a microelectronic device includes: forming a first electrode plate with a first capacitor electrode at a first layer; forming a first capacitor plate contact connected to and extending from the first electrode plate; forming a second electrode plate with a second capacitor electrode at the first layer; and forming a second capacitor plate contact connected to and extending from the second electrode plate. The method further includes a third electrode plate with the first capacitor electrode formed at a second layer and aligned with the first electrode plate, the third electrode plate being formed adjacent to the first capacitor plate contact, and the first capacitor plate contact electrically coupling the first electrode plate and the third electrode plate. The method further includes a fourth electrode plate with the second capacitor electrode formed at a second layer and aligned with the second electrode plate, the fourth electrode plate being formed adjacent to the second capacitor plate contact, and the second capacitor plate contact electrically coupling the second electrode plate and the fourth electrode plate.

[0070] According to embodiments of the present disclosure, capacitors (e.g., capacitor 20) Figure 2 , 3 5, 7A, and 7B) can be used in embodiments of the electronic systems disclosed herein. For example, Figure 13 This is a schematic block diagram of an illustrative electronic system 500 according to embodiments of the present disclosure. The electronic system 500 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a tablet computer with Wi-Fi or cellular capabilities (e.g., for example...). or Tablet computers, e-books, navigation devices, etc. Electronic system 500 includes at least one memory device 502. Memory device 502 may include one or more capacitors, such as those previously described herein (e.g., capacitor 20 (…)). Figure 2 , 3Electronic system 500 may further include at least one electronic signal processor device 504 (generally referred to as a “microprocessor”). Electronic signal processor device 504 may optionally include capacitors previously described herein (e.g., capacitor 20 (…)). Figure 2 , 3 5, 7A and 7B). Although the memory device 502 and the electronic signal processor device 504 are in Figure 13 The system is depicted as two (2) separate devices, but in additional embodiments, a single (e.g., only one) memory / processor device having the functionality of both memory device 502 and electronic signal processor device 504 is included in the electronic system 500. In such embodiments, the memory / processor device may include capacitors (e.g., capacitor 20) previously described herein. Figure 2 , 3 (5, 7A, and 7B). Electronic system 500 may further include one or more input devices 506 for users to input information into electronic system 500, such as, for example, a mouse or other pointing device, keyboard, touchpad, button, or control panel. Electronic system 500 may further include one or more output devices 508 for outputting information to users (e.g., visual or audio output), such as, for example, a monitor, display, printer, audio output jack, and / or speaker. In some embodiments, input device 506 and output device 508 include a single touchscreen device that can be used to both input information into electronic system 500 and output visual information to users. Input device 506 and output device 508 may be electrically communicated with one or more of memory device 502 and electronic signal processor device 504.

[0071] Therefore, in some embodiments, an electronic system includes: an input device; an output device; a processor device operatively connected to the input device and the output device; and a memory device operatively connected to the processor device. The memory device includes a capacitor for a microelectronic device, the capacitor including: a first electrode plate disposed at a first level; and a second electrode plate disposed at the first level, the second electrode plate being interdigitated with the first electrode plate. The capacitor further includes: a third electrode plate disposed at a second level and aligned with the first electrode plate; and a fourth electrode plate disposed at the second level and aligned with the second electrode plate, the fourth electrode plate being interdigitated with the third electrode plate. The capacitor further includes: a first capacitor plate contact extending from the first electrode plate to the third electrode plate and electrically coupling the first electrode plate and the third electrode plate; and a second capacitor plate contact extending from the second electrode plate to the fourth electrode plate and electrically coupling the second electrode plate and the fourth electrode plate.

[0072] Therefore, capacitor 20 can provide increased capacitor density without increasing cost or changing the capacitor integration scheme. In some instances, the minimum gain of the capacitor can be approximately 35% to 30%. Depending on the application, capacitor 20 can be scaled to different sizes. Capacitor 20 also provides flexible design and offers the aforementioned advantages even if random etching deficiencies occur during manufacturing of one or more capacitor plate contacts.

[0073] The embodiments of this disclosure described above and illustrated in the accompanying drawings do not limit the scope of this disclosure, which is covered by the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of this disclosure. In fact, various modifications to this disclosure (e.g., alternative useful combinations of described elements) will become apparent to those skilled in the art from this description, in addition to those shown and described herein. Such modifications and embodiments also fall within the scope of the appended claims and their equivalents.

[0074] Additional non-limiting example embodiments of this disclosure are described below.

[0075] Example 1: A capacitor for a microelectronic device, comprising: a first electrode including: a first substrate portion at a first layer; a second substrate portion at a second layer; a first substrate contact extending from the first substrate portion to the second substrate portion; one or more first plates extending from the first substrate portion; one or more second plates extending from the second substrate portion; and a capacitor plate contact extending from the one or more first plates to the one or more second plates; and a second electrode including: a first substrate portion formed at the first layer; a second substrate portion formed at the second layer; a second substrate contact extending from the first substrate portion to the second substrate portion; one or more first plates extending from the first substrate portion; one or more second plates extending from the second substrate portion; and a capacitor plate contact extending from the one or more first plates to the one or more second plates.

[0076] Example 2: According to the capacitor of Example 1, wherein the capacitor plate contact of the first electrode has a width of about 1 / 2 the width of the one or more first plates and the one or more second plates of the first electrode, and wherein the capacitor plate contact of the second electrode has a width of about 1 / 2 the width of the one or more first plates and the one or more second plates of the second electrode.

[0077] Example 3: According to the capacitor of Example 1, wherein the capacitor plate contact of the first electrode exhibits a width of approximately 3 / 4 of the width of the one or more first plates and the one or more second plates of the first electrode, and wherein the capacitor plate contact of the second electrode exhibits a width of approximately 3 / 4 of the width of the one or more first plates and the one or more second plates of the second electrode.

[0078] Example 4: According to the capacitor of Example 1, wherein the capacitor plate contact of the first electrode has a width approximately equal to the width of the one or more first plates and the one or more second plates of the first electrode, and wherein the capacitor plate contact of the second electrode has a width approximately equal to the width of the one or more first plates and the one or more second plates of the second electrode.

[0079] Example 5: A capacitor according to any one of Examples 1 to 4, wherein the distance between adjacent capacitor plate contacts of the first electrode is approximately equal to the width of the one or more first plates and the one or more second plates of the first electrode, and wherein the distance between the capacitor plate contacts of the second electrode is approximately equal to the width of the one or more first plates and the one or more second plates of the second electrode.

[0080] Example 6: A capacitor according to any one of Examples 1 to 4, wherein the distance between the capacitor plate contacts of the first electrode is approximately half the width of the one or more first plates and the one or more second plates of the first electrode, and wherein the distance between the capacitor plate contacts of the second electrode is approximately half the width of the one or more first plates and the one or more second plates of the second electrode.

[0081] Example 7: A capacitor according to any one of Examples 1 to 6, wherein the capacitor plate contact of the first electrode exhibits a tapered cross-sectional profile, and wherein the capacitor plate contact of the second electrode exhibits a tapered cross-sectional profile.

[0082] Example 8: The capacitor according to Example 7, wherein the taper is about 88 degrees or about 89 degrees.

[0083] Example 9: A capacitor according to any one of Examples 1 to 8, wherein the capacitor plate contact of the first electrode is offset from the capacitor plate contact of the second electrode.

[0084] Example 10: An electronic system comprising: an input device; an output device; a processor device operatively connected to the input device and the output device; and a memory device operatively connected to the processor device and comprising: a capacitor including: a first electrode plate disposed at a first level; a second electrode plate disposed at the first level, the second electrode plate being interdigitated with the first electrode plate; a third electrode plate disposed at a second level and aligned with the first electrode plate; a fourth electrode plate disposed at the second level and aligned with the second electrode plate, the fourth electrode plate being interdigitated with the third electrode plate; a first capacitor plate contact extending from the first electrode plate to the third electrode plate and electrically coupling the first electrode plate and the third electrode plate; and a second capacitor plate contact extending from the second electrode plate to the fourth electrode plate and electrically coupling the second electrode plate and the fourth electrode plate.

[0085] Example 11: According to the electronic system of Example 10, the capacitor further includes: a first base portion disposed at the first layer, the first electrode plate extending from the first base portion; a second base portion disposed at the first layer, the second electrode plate extending from the second base portion; a third base portion disposed at the second layer, the third electrode plate extending from the third base portion; and a fourth base portion disposed at the second layer, the fourth electrode plate extending from the fourth base portion, wherein the first base portion, the first electrode plate, the third base portion, the third electrode plate, and the first capacitor plate contact define a first electrode of the capacitor, and the second base portion, the second electrode plate, the fourth base portion, the fourth electrode plate, and the second capacitor plate contact define a second electrode of the capacitor.

[0086] Example 12: The electronic system according to Example 11, wherein the capacitor further includes: a first base contact extending from the first base portion to the third base portion and electrically coupling the first base portion to the third base portion; and a second base contact extending from the second base portion to the fourth base portion and electrically coupling the second base portion to the fourth base portion.

[0087] Example 13: The electronic system according to Example 12, wherein the capacitor further includes: a fifth electrode plate disposed at a third level and aligned with the first electrode plate; and a third capacitor plate contact extending from the third electrode plate to the fifth electrode plate and electrically coupling the third electrode plate and the fifth electrode plate.

[0088] Example 14: The electronic system according to Example 13, wherein the capacitor further comprises: a sixth electrode plate disposed at the third level and aligned with the second electrode plate, the sixth electrode plate being interdigitated with the fifth electrode plate; and a fourth capacitor plate contact extending from the fourth electrode plate to the sixth electrode plate and electrically coupling the fourth electrode plate and the sixth electrode plate.

[0089] Example 15: The electronic system according to Example 14, wherein the capacitor further comprises: a fifth base portion disposed at the third layer, wherein the fifth electrode plate extends from the fifth base portion; and a sixth base portion disposed at the third layer, wherein the sixth electrode plate extends from the sixth base portion.

[0090] Example 16: The electronic system according to Example 15, wherein: the fifth base portion, the fifth electrode plate and the third capacitor plate contact define a portion of the first electrode of the capacitor; and the sixth base portion, the sixth electrode plate and the fourth capacitor plate contact define a portion of the second electrode of the capacitor.

[0091] Example 17: The electronic system according to Example 16, wherein the capacitor further includes: a third base contact extending from the third base portion to the fifth base portion and electrically coupling the third base portion to the fifth base portion; and a fourth base contact extending from the fourth base portion to the sixth base portion and electrically coupling the fourth base portion to the sixth base portion.

[0092] Example 18: An electronic system according to any of Examples 14 to 17, wherein the first capacitor plate contact and the second capacitor plate contact present inclined sidewalls at a first angle, and wherein the third capacitor plate contact and the fourth capacitor plate contact present inclined sidewalls at a second angle different from the first angle.

[0093] Example 19: An electronic system according to any one of Examples 10 to 18, wherein the first capacitor plate contact is offset from the second capacitor plate contact in a direction parallel to the first electrode plate.

[0094] Example 20: A method of manufacturing a capacitor for an electronic device, the method comprising: forming a first electrode plate with a first capacitor electrode at a first layer; forming a first capacitor plate contact connected to and extending from the first electrode plate; forming a second electrode plate with a second capacitor electrode at the first layer; forming a second capacitor plate contact connected to and extending from the second electrode plate; forming a third electrode plate with the first capacitor electrode at a second layer and aligned with the first electrode plate, the third electrode plate being formed adjacent to the first capacitor plate contact, and the first capacitor plate contact electrically coupling the first electrode plate and the third electrode plate; and forming a fourth electrode plate with the second capacitor electrode at the second layer and aligned with the second electrode plate, the fourth electrode plate being formed adjacent to the second capacitor plate contact, and the second capacitor plate contact electrically coupling the second electrode plate and the fourth electrode plate.

Claims

1. A capacitor for a microelectronic device, comprising: The first electrode includes: The first basal portion, located at the first level. The second basal portion, located at the second level. A first base contact extends from the first base portion to the second base portion. One or more first plates extending from the first base portion, One or more second plates, extending from the second base portion, and A capacitor plate contact extending from the one or more first plates to the one or more second plates; and The second electrode includes: The first base portion is formed at the first layer. The second base portion is formed at the second layer. A second base contact extends from the first base portion to the second base portion. One or more first plates extending from the first base portion, One or more second plates, extending from the second base portion, and A capacitor plate contact extending from one or more first plates to one or more second plates.

2. The capacitor of claim 1, wherein the capacitor plate contact of the first electrode has a width of about 1 / 2 the width of the one or more first plates and the one or more second plates of the first electrode, and wherein the capacitor plate contact of the second electrode has a width of about 1 / 2 the width of the one or more first plates and the one or more second plates of the second electrode.

3. The capacitor of claim 1, wherein the capacitor plate contact of the first electrode has a width of approximately 3 / 4 of the width of the one or more first plates and the one or more second plates of the first electrode, and wherein the capacitor plate contact of the second electrode has a width of approximately 3 / 4 of the width of the one or more first plates and the one or more second plates of the second electrode.

4. The capacitor of claim 1, wherein the capacitor plate contact of the first electrode has a width approximately equal to the width of the one or more first plates and the one or more second plates of the first electrode, and wherein the capacitor plate contact of the second electrode has a width approximately equal to the width of the one or more first plates and the one or more second plates of the second electrode.

5. The capacitor according to any one of claims 1 to 4, wherein the distance between adjacent capacitor plate contacts of the first electrode is approximately equal to the width of the one or more first plates and the one or more second plates of the first electrode, and wherein the distance between the capacitor plate contacts of the second electrode is approximately equal to the width of the one or more first plates and the one or more second plates of the second electrode.

6. The capacitor according to any one of claims 1 to 4, wherein the distance between the capacitor plate contacts of the first electrode is approximately half the width of the one or more first plates and the one or more second plates of the first electrode, and wherein the distance between the capacitor plate contacts of the second electrode is approximately half the width of the one or more first plates and the one or more second plates of the second electrode.

7. The capacitor of claim 1, wherein the capacitor plate contact of the first electrode exhibits a tapered cross-sectional profile, and wherein the capacitor plate contact of the second electrode exhibits a tapered cross-sectional profile.

8. The capacitor of claim 7, wherein the taper is about 88 degrees or about 89 degrees.

9. The capacitor according to any one of claims 1 to 4, 7 or 8, wherein the capacitor plate contact of the first electrode is offset from the capacitor plate contact of the second electrode.

10. An electronic system comprising: Input device; Output device; A processor device operatively connected to the input device and the output device; and A memory device operatively connected to the processor device and comprising: Capacitors, including: The first electrode plate is placed at the first level; The second electrode plate is disposed at the first layer, and the second electrode plate and the first electrode plate are interdigitated. The third electrode plate is positioned at the second level and aligned with the first electrode plate. A fourth electrode plate is disposed at the second level and aligned with the second electrode plate, and the fourth electrode plate is interdigitated with the third electrode plate. A first capacitor plate contact extends from the first electrode plate to the third electrode plate and electrically couples the first electrode plate and the third electrode plate; and A second capacitor plate contact extends from the second electrode plate to the fourth electrode plate and electrically couples the second electrode plate and the fourth electrode plate.

11. The electronic system of claim 10, wherein the capacitor further comprises: A first base portion is disposed at the first layer, and the first electrode plate extends from the first base portion; A second base portion is disposed at the first layer, and a second electrode plate extends from the second base portion; A third base portion is disposed at the second layer, and the third electrode plate extends from the third base portion; and A fourth base portion, which is disposed at the second layer, wherein the fourth electrode plate extends from the fourth base portion, wherein The first base portion, the first electrode plate, the third base portion, the third electrode plate, and the first capacitor plate contact define the first electrode of the capacitor, and The second base portion, the second electrode plate, the fourth base portion, the fourth electrode plate, and the second capacitor plate contact define the second electrode of the capacitor.

12. The electronic system of claim 11, wherein the capacitor further comprises: A first base contact extends from the first base portion to the third base portion and electrically couples the first base portion to the third base portion; and A second base contact extends from the second base portion to the fourth base portion and electrically couples the second base portion to the fourth base portion.

13. The electronic system of claim 12, wherein the capacitor further comprises: The fifth electrode plate is positioned at the third level and aligned with the first electrode plate. and A third capacitor plate contact extends from the third electrode plate to the fifth electrode plate and electrically couples the third electrode plate and the fifth electrode plate.

14. The electronic system of claim 13, wherein the capacitor further comprises: A sixth electrode plate is disposed at the third level and aligned with the second electrode plate, and the sixth electrode plate and the fifth electrode plate are interdigitated. and A fourth capacitor plate contact extends from the fourth electrode plate to the sixth electrode plate and electrically couples the fourth electrode plate and the sixth electrode plate.

15. The electronic system of claim 14, wherein the capacitor further comprises: A fifth base portion is disposed at the third level, and the fifth electrode plate extends from the fifth base portion; and A sixth base portion is disposed at the third level, and the sixth electrode plate extends from the sixth base portion.

16. The electronic system according to claim 15, wherein: The fifth base portion, the fifth electrode plate, and the third capacitor plate contact define a portion of the first electrode of the capacitor; and The sixth base portion, the sixth electrode plate, and the fourth capacitor plate contact define a portion of the second electrode of the capacitor.

17. The electronic system of claim 16, wherein the capacitor further comprises: A third base contact extends from the third base portion to the fifth base portion and electrically couples the third base portion to the fifth base portion; and A fourth base contact extends from the fourth base portion to the sixth base portion and electrically couples the fourth base portion to the sixth base portion.

18. The electronic system according to any one of claims 14 to 17, wherein the first capacitor plate contact and the second capacitor plate contact present inclined sidewalls at a first angle, and wherein the third capacitor plate contact and the fourth capacitor plate contact present inclined sidewalls at a second angle different from the first angle.

19. The electronic system according to any one of claims 14 to 17, wherein the first capacitor plate contact is offset from the second capacitor plate contact in a direction parallel to the first electrode plate.

20. A method of manufacturing a capacitor for an electronic device, the method comprising: A first electrode plate that forms the first capacitor electrode at the first level; A first capacitor plate contact is formed that is connected to and extends from the first electrode plate; A second electrode plate is formed at the first level to create the second capacitor electrode; A second capacitor plate contact is formed that is connected to and extends from the second electrode plate; A third electrode plate is formed at the second level and aligned with the first electrode plate to form the first capacitor electrode. The third electrode plate is formed adjacent to the first capacitor plate contact and the first capacitor plate contact is electrically coupled to the first electrode plate and the third electrode plate. and A fourth electrode plate is formed at the second level and aligned with the second electrode plate to form the second capacitor electrode. The fourth electrode plate is formed adjacent to the second capacitor plate contact and the second capacitor plate contact is electrically coupled to the second electrode plate and the fourth electrode plate.

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