Chip batteries and their fabrication methods

Abstract

This application provides a chip battery and its fabrication method, belonging to the field of semiconductor technology. It includes a substrate, n capacitor structures, and n-1 normally open switching transistors, where n ≥ 2. The capacitor structures are located on the substrate, and at least a portion of the normally open switching transistors is located on the substrate. The first capacitor structure is connected in parallel to a load. The i-th capacitor structure is connected in series with the (i-1)-th normally open switching transistor and then in parallel to the load. The node between the first capacitor structure and the load is connected to the gate of the first normally open switching transistor, and the node between the i-th capacitor structure and the (i-1)-th normally open switching transistor is connected to the gate of the i-th normally open switching transistor, where 2 ≤ i ≤ n. The chip battery in this application does not have the problem of explosion or combustion, has a fast charging speed, does not have the problem of low-temperature degradation, and can avoid the problem of voltage drop after discharge. Furthermore, the series connection of the capacitor structures with the normally open switching transistors enables self-control of the chip battery's charging and discharging.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a chip battery and its fabrication method. Background Technology

[0002] Currently, lithium-ion batteries are among the most commonly used rechargeable batteries. Although lithium-ion batteries are inexpensive and have high energy density, they also have a series of drawbacks. For example, lithium-ion batteries are prone to explosion and combustion, posing safety issues; they charge slowly, and the charging speed affects their lifespan; they degrade faster at low temperatures, exhibiting poor low-temperature performance; and their voltage decreases as the battery capacity diminishes.

[0003] Therefore, there is an urgent need for a rechargeable battery to address the shortcomings of existing lithium-ion batteries. Summary of the Invention

[0004] In view of this, the embodiments of this application aim to provide a chip battery and a method for manufacturing the same, so as to overcome the shortcomings of existing lithium-ion batteries.

[0005] This application provides a chip battery for powering a load, comprising a substrate, n capacitor structures and n-1 normally open switching transistors, where n≥2, wherein the capacitor structures are located on the substrate and at least a portion of the normally open switching transistors are located on the substrate;

[0006] In this configuration, the first capacitor structure is connected in parallel to the load, the i-th capacitor structure is connected in series with the (i-1)-th normally open switch and then connected in parallel to the load, the node between the first capacitor structure and the load is connected to the gate of the first normally open switch, and the node between the i-th capacitor structure and the (i-1)-th normally open switch is connected to the gate of the i-th normally open switch, where 2≤i≤n.

[0007] In some embodiments, the substrate has a capacitor region and a switching region, the capacitor structures are all located within the capacitor region, and the normally open switching transistors are all located within the switching region.

[0008] In some embodiments, the substrate further comprises a metal wiring layer, which electrically connects and leads out the first terminals of the n capacitor structures to serve as the first electrode of the chip battery. The metal wiring layer also electrically connects the second terminal of the i-th capacitor structure to the source and gate of the (i-1)-th normally open switch, and the metal wiring layer also connects and leads out the drains of the n-1 normally open switches to the second terminal of the first capacitor structure and the gate of the first normally open switch to serve as the second electrode of the chip battery.

[0009] In some embodiments, the chip battery further includes:

[0010] A dielectric layer is located on the normally open switching transistor; and,

[0011] A hybrid bonding structure is located on the dielectric layer, and the capacitor structure is located on the hybrid bonding structure.

[0012] The hybrid bonding structure includes metal bonding members that connect the drains of n-1 normally open switching transistors to the second terminal of the first capacitor structure. The metal bonding members also electrically connect the second terminal of the i-th capacitor structure to the source and gate of the (i-1)-th normally open switching transistor.

[0013] The chip battery also includes a metal wiring layer located on the capacitor structure. The metal wiring layer electrically connects the first ends of n capacitor structures as the first electrode of the chip battery. The metal wiring layer also leads out the second end of the first capacitor structure as the second electrode of the chip battery.

[0014] In some embodiments, the capacitor structure includes a first electrode layer, a dielectric layer, and a second electrode layer. The first electrode layer includes a columnar main body and at least one disc-shaped extension. The extensions are sequentially spaced outside the main body along the vertical direction. The dielectric layer conformally wraps around the outer wall of the first electrode layer, and the second electrode layer wraps around the outer wall of the dielectric layer.

[0015] In some embodiments, adjacent capacitor structures are isolated by isolation pillars; or, the second electrode layer of all capacitor structures is a single integral structure.

[0016] In some embodiments, the normally open switch is a normally open PMOS transistor.

[0017] One embodiment of this application also provides a method for fabricating a chip battery, the chip battery being used to power a load, comprising:

[0018] Provide substrate;

[0019] n capacitor structures and n-1 normally open switching transistors are formed on the substrate, where n≥2, the capacitor structures are located on the substrate, and at least a portion of the normally open switching transistors are located on the substrate;

[0020] In this configuration, the first capacitor structure is connected in parallel to the load, the i-th capacitor structure is connected in series with the (i-1)-th normally open switch and then connected in parallel to the load, the node between the first capacitor structure and the load is connected to the gate of the first normally open switch, and the node between the i-th capacitor structure and the (i-1)-th normally open switch is connected to the gate of the i-th normally open switch, where 2≤i≤n.

[0021] In some embodiments, the substrate has a capacitor region and a switching region, and the step of forming the capacitor structure and the normally open switching transistor on the substrate includes:

[0022] The normally open switching transistor is formed within the switching region of the substrate;

[0023] The capacitor structure is formed within the capacitor region of the substrate; and,

[0024] A metal wiring layer is formed on the capacitor structure and the normally open switch. The metal wiring layer electrically connects the first terminals of the n capacitor structures and leads them out to serve as the first electrode of the chip battery. The metal wiring layer also electrically connects the second terminal of the i-th capacitor structure to the source and gate of the (i-1)-th normally open switch. The metal wiring layer also connects the drains of the n-1 normally open switches to the second terminal of the first capacitor structure and the gate of the first normally open switch and leads them out to serve as the second electrode of the chip battery.

[0025] In some embodiments, the step of forming the capacitor structure and the normally open switching transistor on the substrate includes:

[0026] A temporary substrate is provided, on which the capacitor structure and a first hybrid bonding layer are sequentially formed, wherein the first hybrid bonding layer is located on the capacitor structure;

[0027] The normally open switch and the second hybrid bonding layer are sequentially formed on the substrate, with the second hybrid bonding layer located on the normally open switch;

[0028] The first hybrid bonding layer and the second hybrid bonding layer are bonded together, forming a hybrid bonding structure. The hybrid bonding structure includes metal bonding elements that connect the drains of n-1 normally open switching transistors to the second terminal of the first capacitor structure. The hybrid bonding structure also electrically connects the second terminal of the i-th capacitor structure to the source and gate of the (i-1)-th normally open switching transistor.

[0029] The temporary substrate is removed, and a metal wiring layer is formed on the capacitor structure. The metal wiring layer electrically connects the first ends of the n capacitor structures as the first electrode of the chip battery. The metal wiring layer also leads out the second end of the first capacitor structure as the second electrode of the chip battery.

[0030] In some embodiments, the step of forming the capacitor structure includes:

[0031] A stacked structure is formed, the stacked structure including at least one first sacrificial layer and at least one second sacrificial layer, the first sacrificial layer and the second sacrificial layer being stacked alternately in sequence;

[0032] The stacked structure is etched to form n trenches penetrating the stacked structure;

[0033] The first sacrificial layer or the second sacrificial layer is etched laterally along the trench so that the sidewalls of the trench protrude laterally outward;

[0034] A dielectric layer is formed on the inner wall of the trench;

[0035] A first electrode layer is formed within the trench, and the first electrode layer fills the trench; and...

[0036] The stacked structure is removed, and a second electrode layer is formed at the original position of the stacked structure. The first electrode layer, the dielectric layer, and the second electrode layer constitute the capacitor structure.

[0037] In some embodiments, before etching the stacked structure to form the trench, the fabrication method further includes:

[0038] The stacked structure is etched to form an isolation trench that extends through the stacked structure;

[0039] The isolation groove is filled with isolation material to form an isolation column, which isolates n sub-regions; and,

[0040] When n trenches are formed, one trench is located within one of the sub-regions.

[0041] This application provides a chip battery and a method for fabricating the same, comprising a substrate, n capacitor structures and n-1 normally open switching transistors, where n≥2. The capacitor structures are located on the substrate, and at least a portion of the normally open switching transistors are located on the substrate. The first capacitor structure is connected in parallel to a load, the i-th capacitor structure is connected in series with the (i-1)-th normally open switching transistor and then in parallel to the load, the node between the first capacitor structure and the load is connected to the gate of the first normally open switching transistor, and the node between the i-th capacitor structure and the (i-1)-th normally open switching transistor is connected to the gate of the i-th normally open switching transistor, where 2≤i≤n. The unexpected benefits of this application are: It utilizes chip manufacturing processes to form capacitor structures on a substrate, supplying power to the load through the charging and discharging of these capacitor structures. The chip battery exhibits no risk of explosion or combustion, boasts rapid charging, and avoids low-temperature degradation. Since each capacitor structure supplies power to the load individually, it maintains a consistent supply voltage, preventing voltage drop after discharge. Furthermore, the overall capacity of the chip battery can be increased by enhancing the capacitance of individual capacitor structures or increasing the number of capacitor structures. Each chip battery is also very thin (down to <50μm), allowing for stacking with computing and memory chips to form an independent microcomputer system. It is also resistant to extreme environments and can be applied in fields such as exploration and medicine. In addition, by connecting the capacitor structure in series with the normally open switching transistor, self-control of the chip battery's charging and discharging can be achieved. Attached Figure Description

[0042] Figure 1 A flowchart illustrating a method for fabricating a chip battery according to an embodiment of this application.

[0043] Figure 2 This is a schematic diagram of a normally open switch transistor formed in the switching region of a substrate, according to an embodiment of this application.

[0044] Figure 3 This is a schematic diagram of a stacked structure formed on a substrate according to an embodiment of this application.

[0045] Figure 4 This is a schematic diagram of an etched stacked structure forming a trench according to an embodiment of this application.

[0046] Figure 5 for Figure 4 A top view of the semiconductor structure.

[0047] Figure 6 This is a schematic diagram of the structure of the second sacrificial layer being etched according to an embodiment of this application.

[0048] Figure 7 for Figure 6 A top view of the semiconductor structure.

[0049] Figure 8 This is a schematic diagram of a structure in which a dielectric layer is formed on the inner wall of a trench, according to an embodiment of this application.

[0050] Figure 9 for Figure 8 A top view of the semiconductor structure.

[0051] Figure 10 This is a schematic diagram of a structure in which a first electrode layer is formed in a trench, according to an embodiment of this application.

[0052] Figure 11 for Figure 10 A top view of the semiconductor structure.

[0053] Figure 12 This is a schematic diagram of an etched stack structure forming a release hole according to an embodiment of this application.

[0054] Figure 13 for Figure 12 A top view of the semiconductor structure.

[0055] Figure 14 This is a schematic diagram of a structure for removing the stacking structure according to an embodiment of this application.

[0056] Figure 15 This is a schematic diagram of a structure in which a second electrode layer is formed at the original position of the stacked structure, according to an embodiment of this application.

[0057] Figure 16 for Figure 15 A top view of the semiconductor structure.

[0058] Figure 17 This is a schematic diagram of an etched stacking structure to form an isolation trench structure according to an embodiment of this application.

[0059] Figure 18 for Figure 17 A top view of the semiconductor structure.

[0060] Figure 19 This is a schematic diagram of an isolation column structure formed by filling an isolation groove with isolation material, according to an embodiment of this application.

[0061] Figure 20 for Figure 19 A top view of the semiconductor structure.

[0062] Figure 21 This is a schematic diagram of a structure for forming a release hole by etching the stacked structure in each sub-region, according to an embodiment of this application.

[0063] Figure 22 for Figure 21 A top view of the semiconductor structure.

[0064] Figure 23 This is another structural schematic diagram of a second electrode layer formed at the original position of the stacked structure, provided as an embodiment of this application.

[0065] Figure 24 for Figure 23 A top view of the semiconductor structure.

[0066] Figure 25 This is a schematic diagram of the structure of a chip battery provided in one embodiment of this application.

[0067] Figure 26 This is an equivalent schematic diagram of a chip battery provided in one embodiment of this application.

[0068] Figure 27 This is a schematic diagram of the structure of another chip battery provided in an embodiment of this application.

[0069] Figure 28 This is a schematic diagram of a normally open switch transistor formed on a substrate, according to an embodiment of this application.

[0070] Figure 29 This is a schematic diagram of a capacitor structure formed on a temporary substrate according to an embodiment of this application.

[0071] Figure 30 This is a schematic diagram of a structure for bonding a first hybrid bonding layer and a second hybrid bonding layer according to an embodiment of this application.

[0072] Figure 31 This is a schematic diagram of the structure of another chip battery provided in an embodiment of this application.

[0073] The attached figures are labeled as follows:

[0074] 100 - Substrate; 100A - Switching region; 100B - Capacitor region; 110 - Temporary substrate; 101 - Oxide layer; 200 - Stacked structure; 200a - Trench; 200b - Release hole; 200c - Isolation trench; 201 - First sacrificial layer; 202 - Second sacrificial layer; 300 - Mask layer; 410 - Normally open switch; 400 - Capacitor structure; 401 - Dielectric layer; 402 - First electrode layer; 403 - Second electrode layer; 500 - Isolation pillar; 600 - Dielectric layer; 700 - Metal wiring layer; 701 - Plug structure; 800 - First hybrid bonding layer; 801 - First metal bond; 900 - Second hybrid bonding layer; 901 - Second metal bond; 890 - Hybrid bonding structure; 891 - Metal bond; R - Load; S - Source; D - Drain; G - Gate; C1 - First capacitor; C2 - Second capacitor; Cn-1 - (n-1)th capacitor; Cn - nth capacitor; MOS1 - First switch; MOS2 - Second switch; MOSn-1 - (n-1)th switch; P1 - First electrode; P2 - Second electrode. Detailed Implementation

[0075] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0076] Figure 25 This is a schematic diagram of the structure of a chip battery provided in one embodiment of this application. Figure 26 This is an equivalent schematic diagram of a chip battery provided in one embodiment of this application. Figure 25 and Figure 26 As shown, the chip battery includes a substrate 100, n capacitor structures 400 and n-1 normally open switching transistors 410, wherein n≥2, the capacitor structures 400 are located on the substrate 100, and at least a portion of the normally open switching transistors 410 are located on the substrate 100. Figure 25 The diagram schematically shows two capacitor structures 400 and two normally open switching transistors 410. However, it should be understood that the number of capacitor structures 400 and normally open switching transistors 410 should not be limited to the diagram. The chip battery has at least two capacitor structures 400 and one normally open switching transistor 410, and the number of capacitor structures 400 is one more than the number of normally open switching transistors 410.

[0077] Furthermore, the first capacitor structure 400 is connected in parallel to the load R, and the i-th capacitor structure 400 is connected in series with the (i-1)-th normally open switch 410 and then in parallel to the load R. The node between the first capacitor structure 400 and the load R is connected to the gate G of the first normally open switch 410, and the node between the i-th capacitor structure 400 and the (i-1)-th normally open switch 410 is connected to the gate G of the i-th normally open switch 410, where 2 ≤ i ≤ n. For ease of description, let's use... Figure 26 For example, the first capacitor structure 400, the second capacitor structure 400... the (n-1)th capacitor structure 400 and the nth capacitor structure 400 are respectively equivalent to the first capacitor C1, the second capacitor C2... the (n-1)th capacitor Cn-1 and the nth capacitor Cn. Similarly, the first normally open switch 410, the second normally open switch 410... the (n-1)th normally open switch 410 are respectively equivalent to the first switch MOS1, the second switch MOS2... the (n-1)th switch MOSn-1. From... Figure 26 As can be seen, the first capacitor C1 is connected in parallel with the load R, the second capacitor C2 is connected in series with the first switching transistor MOS1 and then in parallel with the load R, and the third capacitor ( Figure 26 (Not shown in the image) is connected in series with the second switch MOS2 and then in parallel with the load R... The nth capacitor Cn is connected in series with the (n-1)th switch MOSn-1 and then in parallel with the load R; the node between the first capacitor C1 and the load R is connected to the gate G of the first switch MOS1, the node between the second capacitor C2 and the first switch MOS1 is connected to the gate G of the second switch MOS2... The (n-1)th capacitor Cn-1 and the (n-2)th switch ( Figure 26 The node between (not shown) is connected to the gate G of the (n-1)th switch MOSn-1.

[0078] When the chip battery discharges, the first capacitor structure 400 begins to discharge, thus supplying power to the load R. At this time, all n-1 normally open switching transistors 410 are turned on, and the other capacitor structures 400 are disconnected and cannot supply power to the load R. After the first capacitor structure 400 has finished discharging, the voltage across it decreases, and the first normally open switching transistor 410 closes. At this time, the second capacitor structure 400 is connected and begins to discharge, supplying power to the load R. The other capacitor structures 400 remain disconnected and cannot supply power to the load R. When the (n-1)th capacitor structure 400 has finished discharging, the voltage across it decreases, causing the (n-1)th normally open switching transistor 410 to close. At this time, the nth capacitor structure 400 is connected and begins to discharge, supplying power to the load R. The other capacitor structures 400 can no longer supply power to the load R. When the chip battery is charging, the load R is replaced by the power source, which begins charging all capacitor structures 400. This causes the voltage across each capacitor structure 400 to rise, pulling up the gate voltage G of all normally open switching transistors 410 until all normally open switching transistors 410 are turned on. Therefore, this application can achieve self-control of chip battery charging and discharging by connecting capacitor structures 400 in series with normally open switching transistors 410. Furthermore, this application utilizes chip technology to form capacitor structures 400 on the substrate 100, and the charging and discharging of capacitor structures 400 supplies power to the load R. The chip battery does not have the problem of explosion or combustion, has a fast charging speed, and does not suffer from low-temperature degradation. The capacitor structures 400 supply power to the load R one by one, which can maintain the supply voltage at all times and avoid the problem of voltage drop after discharge. The capacity of the entire chip battery can also be increased by increasing the capacity of a single capacitor structure 400 or the number of capacitor structures 400. Moreover, the thickness of a single chip battery is very thin (it can be as thin as <50μm), and it can be stacked with computing chips and memory chips to form an independent microcomputer system. It is also resistant to extreme environments and can be applied in fields such as exploration and medicine.

[0079] Please continue reading. Figure 25In some embodiments, the substrate 100 may have a capacitor region 100B and a switching region 100A. The capacitor structure 400 may be entirely located within the capacitor region 100B, while the normally open switch transistor 410 may be entirely located within the switching region 100A. The substrate 100 also has a dielectric layer 600, which may be located only within the switching region 100A to cover the normally open switch transistor 410 and fill the height difference between the switching region 100A and the capacitor region 100B. Alternatively, the dielectric layer 600 may be located in both the capacitor region 100B and the switching region 100A to cover both the normally open switch transistor 410 and the capacitor structure 400. The substrate 100 also has a metal wiring layer 700, which may be located on the dielectric layer 600. The metal wiring layer 700 is used to interconnect the capacitor structure 400 and the normally open switch transistor 410. Specifically, the metal wiring layer 700 electrically connects and leads out the first terminals of n capacitor structures 400 to serve as the first electrode P1 of the chip battery. The metal wiring layer 700 also electrically connects the second terminal of the i-th capacitor structure 400 to the source S and gate G of the (i-1)-th normally open switch 410. Furthermore, the metal wiring layer 700 connects and leads out the drains D of the n-1 normally open switch 410 to the second terminal of the first capacitor structure 400 and the gate G of the first normally open switch 410, serving as the second electrode P2 of the chip battery. By connecting the two ends of the load R to the first electrode P1 and the second electrode P2 of the chip battery, the first to nth capacitor structures 400 automatically supply power to the load R sequentially.

[0080] In some embodiments, the normally open switch 410 can be a normally open PMOS transistor (depletion-mode PMOS transistor). For example, the normally open switch 410 may include a gate G, a source S, and a drain D, wherein the source S and drain D are located inside the substrate 100, and the gate G is located on the substrate 100. The gate G is also located between the corresponding source S and drain D. Therefore, a part of the normally open switch 410 (gate G) is located on the substrate 100, and another part (source S and drain D) is located inside the substrate 100.

[0081] In some embodiments, each capacitor structure 400 may include a first electrode layer 402, a dielectric layer 401, and a second electrode layer 403. The first electrode layer 402 includes a columnar main body and at least one disc-shaped extension. The extensions are sequentially spaced apart from the main body along the vertical direction. The main body and the extensions are integrally formed. The dielectric layer 401 conformally wraps around the outer wall of the first electrode layer 402, and the second electrode layer 403 wraps around the outer wall of the dielectric layer 401. In some embodiments, the extensions may be disc-shaped or square-shaped, but are not limited thereto. The extensions may increase the facing area of ​​the first electrode layer 402 and the second electrode layer 403, thereby increasing the capacitance of each capacitor structure 400.

[0082] Furthermore, in Figure 25 In this context, the second electrode layer 403 of all capacitor structures 400 is an integral structure, but this should not be a limitation. Figure 27 This is another schematic diagram of the structure of a chip battery provided in one embodiment of this application, as shown below. Figure 27 As shown, the substrate 100 may also have an isolation pillar 500. The isolation pillar 500 is located within the capacitor region 100B. Adjacent capacitor structures 400 can be isolated by the isolation pillar 500. In this case, the second electrode layer 403 of the adjacent capacitor structure 400 is also isolated by the isolation pillar 500.

[0083] It should be noted that the first electrode layer 402 and the second electrode layer 403 serve as the two electrodes of the capacitor structure 400. One of the first electrode layer 402 and the second electrode layer 403 can serve as the first end of the capacitor structure 400, and the other can serve as the second end of the capacitor structure 400. Figure 25 and Figure 27 In this case, the second electrode layer 403 is used as the first end of the capacitor structure 400, and the first electrode layer 402 is used as the second end of the capacitor structure 400. If the second electrode layer 403 of all capacitor structures 400 is an integral structure, using the second electrode layer 403 as the first end of the capacitor structure 400 can simplify the wiring.

[0084] Figure 31 This is a schematic diagram of the structure of another chip power supply provided in an embodiment of this application. For example... Figure 31As shown, in some embodiments, the capacitor structure 400 and the normally open switch 410 can be formed on different substrates and then bonded together by a bonding process. Specifically, at least a portion of the normally open switch 410 is located on the substrate 100, and another portion can be located within the substrate 100. The chip battery may also include a dielectric layer 600 and a hybrid bonding structure 890, wherein the dielectric layer 600 is located on and covers the normally open switch 410, the hybrid bonding structure 890 is located on and covers the dielectric layer 600, and the capacitor structure 400 is located on the hybrid bonding structure 890.

[0085] Combination Figure 31 and Figure 26 As shown, the hybrid bonding structure 890 includes metal bonding members 891. The metal bonding members 891 connect the drains D of n-1 normally open switching transistors 410 to the second terminal of the first capacitor structure 400. The metal bonding members 891 also electrically connect the second terminal of the i-th capacitor structure 400 to the source S and gate G of the (i-1)-th normally open switching transistor 410. In other words, the hybrid bonding structure 890 enables the interconnection between the normally open switching transistors 410 and the capacitor structure 400.

[0086] Furthermore, the chip battery also includes a metal wiring layer 700, which is located on the capacitor structure 400. The metal wiring layer 700 electrically connects the first ends of the n capacitor structures 400 as the first electrode P1 of the chip battery. The metal wiring layer 700 also leads out the second end of the first capacitor structure 400 as the second electrode P2 of the chip battery. Similarly, by connecting the two ends of the load R to the first electrode P1 and the second electrode P2 of the chip battery, the first capacitor structure 400 to the nth capacitor structure 400 can automatically supply power to the load R sequentially.

[0087] Based on this, one embodiment of this application also provides a method for preparing a chip battery. Figure 1 This is a schematic diagram of the structure corresponding to the steps of the chip battery fabrication method provided in an embodiment of this application, as shown below. Figure 1 As shown, the method for fabricating a chip battery includes:

[0088] Step S100: Provide substrate 100;

[0089] Step S200: Form n capacitor structures 400 and n-1 normally open switching transistors 410 on the substrate 100, where n≥2. The capacitor structures 400 are located on the substrate 100, and at least a portion of the normally open switching transistors 410 are located on the substrate 100.

[0090] In this configuration, the first capacitor structure 400 is connected in parallel to the load R, the i-th capacitor structure 400 is connected in series with the (i-1)-th normally open switch 410 and then connected in parallel to the load R, the node between the first capacitor structure 400 and the load R is connected to the gate G of the first normally open switch 410, and the node between the i-th capacitor structure 400 and the (i-1)-th normally open switch 410 is connected to the gate G of the i-th normally open switch 410, where 2≤i≤n.

[0091] Figures 2-31 This is a schematic diagram of the structure corresponding to the corresponding steps of the chip battery fabrication method provided in an embodiment of this application. Next, we will combine... Figures 2-31 The method for preparing a chip battery according to an embodiment of this application will be described in detail.

[0092] like Figure 2 As shown, in step S100, a substrate 100 is provided. The material of the substrate 100 can be silicon, germanium, silicon-germanium, silicon-on-insulator, germanium-on-insulator, gallium arsenide, silicon carbide, etc. The substrate 100 has a capacitor region 100B and a switching region 100A.

[0093] Please continue reading. Figure 2 In step S200, n-1 normally open switching transistors 410 are formed in the switching region 100A of the substrate 100. Figure 2 Two normally open switching transistors 410 are shown as an example. In some embodiments, the normally open switching transistors 410 may be normally open PMOS transistors, but this is not a limitation.

[0094] Specifically, the steps for forming a normally open switch 410 within the switching region 100A of the substrate 100 can be as follows: forming a trench isolation structure within the substrate 100, wherein the trench isolation structure defines a single active region within the substrate 100; performing ion implantation on the substrate 100 to form a source S and a drain D within each active region; and then forming a gate G on the substrate 100, wherein the gate G is located between the source S and the drain D of each active region. Each gate G and its two sides, the source S and the drain D, constitute a normally open switch 410. Since the gate G, the source S, and the drain D are all located within the switching region 100A, the normally open switch 410 is also located within the switching region 100A. Furthermore, a portion of the normally open switch 410 (the gate G) is located on the substrate 100, and another portion (the source S and the drain D) is located within the substrate 100.

[0095] like Figures 3-24 As shown, a capacitor structure 400 is formed within the capacitor region 100B. Figures 3-24 Several capacitor structures 400 are illustrated in the example, and, Figures 3-24 Only the capacitor region 100B of the substrate 100 is shown.

[0096] Specifically, such as Figure 3 As shown, an oxide layer 101 and a stacked structure 200 are sequentially formed on a substrate 100. The oxide layer 101 covers the top surface of the substrate 100, and the stacked structure 200 covers the top surface of the oxide layer 101. The stacked structure 200 includes at least one first sacrificial layer 201 and at least one second sacrificial layer 202, which are sequentially stacked on the substrate 100 at intervals. The first sacrificial layer 201 and the second sacrificial layer 202 are made of different materials, preferably materials with a large etching selectivity. For example, one of the first sacrificial layer 201 and the second sacrificial layer 202 can be made of silicon, and the other can be made of germanium-silicon, but this is not a limitation.

[0097] Please continue reading. Figure 3 After forming the stacked structure 200, a mask layer 300 can be formed on the stacked structure 200, covering the top surface of the stacked structure 200. The mask layer 300 and the oxide layer 101 can be made of the same material, for example, both can be silicon oxide.

[0098] like Figure 4 and Figure 5 As shown, the mask layer 300 and the stacked structure 200 are etched to form n trenches 200a. The trenches 200a penetrate the mask layer 300 and the stacked structure 200 and expose the top surface of the oxide layer 101. Figure 4 Two trenches 200a are shown as an example. Figure 5 Four grooves 200a are shown as an example.

[0099] like Figure 6 and Figure 7 As shown, the first sacrificial layer 201 or the second sacrificial layer 202 is etched laterally along the trench 200a so that at least one height position of the sidewall of the trench 200a protrudes laterally outward. It should be noted that during the lateral etching of the first sacrificial layer 201 or the second sacrificial layer 202, each layer is not completely removed, but only a portion is removed. Furthermore, after etching, adjacent trenches 200a are not connected. After etching, the trench 200a is laterally widened, thereby increasing the area of ​​each capacitor structure 400 and consequently increasing the capacitance of each capacitor structure 400.

[0100] like Figure 8 and Figure 9 As shown, a dielectric layer 401 is formed on the inner wall of the trench 200a, and the dielectric layer 401 conformally covers the inner wall of the trench 200a. The material of the dielectric layer 401 can be a high-k material, such as silicon oxide, hafnium-based oxides (such as HfO2, HfSiO, HfSiON, etc.), aluminum-based oxides (such as Al2O3), zirconium-based oxides (such as ZrO2), etc.

[0101] like Figure 10 and Figure 11 As shown, a first electrode layer 402 is formed within the trench 200a, and the first electrode layer 402 fills the trench 200a. The material of the first electrode layer 402 can be a metallic material, such as gold, silver, copper, tungsten, platinum, aluminum, etc., or other possible conductive materials.

[0102] like Figure 12 and Figure 13 As shown, the dielectric layer 401, the mask layer 300 and the stacked structure 200 are etched sequentially until the oxide layer 101 is exposed, forming a plurality of release holes 200b. The release holes 200b penetrate the dielectric layer 401, the mask layer 300 and the stacked structure 200 until the oxide layer 101 is exposed.

[0103] like Figure 14 As shown, an etchant is introduced through the release hole 200b to completely remove the stacked structure 200. The etchant can be a hydrofluoric acid solution. After entering through the release hole 200b, the hydrofluoric acid solution contacts the first sacrificial layer 201 and the second sacrificial layer 202, thereby removing the first sacrificial layer 201 and the second sacrificial layer 202.

[0104] like Figure 15 and Figure 16 As shown, a second electrode layer 403 is formed at the original position of the stacked structure 200. At this time, the dielectric layer 401 conformally wraps the outer wall of the first electrode layer 402, and the second electrode layer 403 wraps the outer wall of the dielectric layer 401. The first electrode layer 402, the dielectric layer 401, and the second electrode layer 403 constitute the capacitor structure 400. Figure 15 As shown, after the capacitor structure 400 is formed, the second electrode layer 403 of each capacitor structure 400 is an integral structure. Therefore, the second electrode layer 403 of each capacitor structure 400 is electrically connected to each other, which can simplify subsequent wiring.

[0105] In some embodiments, such as Figure 17 and Figure 18 As shown, before etching the mask layer 300 and the stacked structure 200 to form n trenches 200a, the mask layer 300 and the stacked structure 200 can be etched first to form a number of isolation trenches 200c. The isolation trenches 200c penetrate the mask layer 300 and the stacked structure 200 and expose the top surface of the oxide layer 101.

[0106] like Figure 19 and Figure 20 As shown, the isolation groove 200c is filled with isolation material to form an isolation pillar 500. The isolation pillar 500 can divide the capacitor region 100B into n independent sub-regions. Each sub-region is used to form a capacitor structure 400. The isolation pillar 500 can isolate adjacent capacitor structures 400.

[0107] like Figure 21 and Figure 22 As shown, when forming a plurality of release holes 200b by etching the dielectric layer 401, the mask layer 300 and the stacked structure 200, since each sub-region is isolated from each other, it is necessary to form at least one release hole 200b in each sub-region, and then remove the stacked structure 200 in each sub-region by means of the release hole 200b in each sub-region.

[0108] like Figure 23 and Figure 24 As shown, after removing the stacked structure 200, a second electrode layer 403 is formed at the original position of the stacked structure 200. At this time, the dielectric layer 401 conformally wraps around the outer wall of the first electrode layer 402, and the second electrode layer 403 wraps around the outer wall of the dielectric layer 401. The first electrode layer 402, the dielectric layer 401, and the second electrode layer 403 constitute the capacitor structure 400. Furthermore, from... Figure 23 and Figure 24 As can be seen, the second electrode layer 403 of each capacitor structure 400 is not a single piece, and adjacent capacitor structures 400 are separated by isolation pillars 500.

[0109] It should be noted that, Figures 3-24 When demonstrating the steps of forming the capacitor structure 400 in the capacitor region 100B, only the case of the capacitor region 100B is shown. In fact, when each film layer is formed in the capacitor region 100B, a corresponding film layer is also formed in the switching region 100A. However, the corresponding film layer in the switching region 100A will eventually be removed, and the final result is that the capacitor structure 400 is formed in the capacitor region 100B. This will not be elaborated here.

[0110] like Figure 25 As shown, after forming the capacitor structure 400 in the capacitor region 100B, a dielectric layer 600 can be formed on the substrate 100 and planarized. The dielectric layer 600 can cover only the switching region 100A, thereby filling the height difference between the switching region 100A and the capacitor region 100B. Of course, the dielectric layer 600 can also cover both the capacitor region 100B and the switching region 100A at the same time.

[0111] Next, a plurality of plug structures 701 are formed in the dielectric layer 600, and the source S, drain D, and gate G of each normally open switch 410 can be electrically connected to a plug structure 701. Then, a metal wiring layer 700 is formed on the dielectric layer 600 and the capacitor structure 400. The metal wiring layer 700 can electrically connect the first plate layer 402 and the second plate layer 403 that are electrically connected to each capacitor structure 400, and can also electrically connect the source S, drain D, and gate G of each normally open switch 410 via the plug structures 701. Afterwards, the capacitor structure 400 and the normally open switch can be connected via the metal wiring layer 700 in the following manner: Figure 26 The connections are made in the manner shown. Specifically, the metal wiring layer 700 electrically connects the first ends of n capacitor structures 400 and leads them out to serve as the first electrode P1 of the chip battery. The metal wiring layer 700 also electrically connects the second end of the i-th capacitor structure 400 to the source S and gate G of the (i-1)-th normally open switch transistor 410. The metal wiring layer 700 also connects the drain D of n-1 normally open switch transistors 410 to the second end of the first capacitor structure 400 and the gate G of the first normally open switch transistor 410 and leads them out to serve as the second electrode P2 of the chip battery.

[0112] In some embodiments, the capacitor structure 400 and the normally open switch 410 can be formed on different substrates, and then the capacitor structure 400 and the normally open switch 410 can be bonded together by bonding.

[0113] Specifically, such as Figure 28 As shown, firstly, n-1 normally open switching transistors 410 are formed on the substrate 100. Figure 28 Two normally open switching transistors 410 are shown as an example. The specific steps for forming normally open switching transistors 410 have been described above and will not be repeated here.

[0114] Please continue reading. Figure 28 After forming the normally open switch 410, a dielectric layer 600 can be formed on the substrate 100, covering the exposed areas of the normally open switch 410 and the substrate 100. Then, a plurality of plug structures 701 are formed within the dielectric layer 600, and the source S, drain D, and gate G of each normally open switch 410 can be electrically connected to a plug structure 701.

[0115] Next, a first hybrid bonding layer 800 is formed on the dielectric layer 600, covering the dielectric layer 600. The first hybrid bonding layer 800 has a plurality of first metal bonding members 801, which can be electrically connected to corresponding plug structures 701, thereby electrically connecting the source S, drain D and gate G of each normally open switching transistor 410.

[0116] like Figure 29 As shown, a temporary substrate 110 is provided, and n capacitor structures 400 are formed on the temporary substrate 110. Figure 29 Two capacitor structures 400 are illustrated in the example. The steps for forming the capacitor structure 400 on the temporary substrate 110 can be referred to the steps for forming the capacitor structure 400 on the substrate 100, and will not be repeated here.

[0117] Please continue reading. Figure 29 After forming the capacitor structure 400, a second hybrid bonding layer 900 can be formed on the capacitor structure 400, covering the capacitor structure 400. The second hybrid bonding layer 900 has a plurality of second metal bonding members 901, which can be electrically connected to the first electrode layer 402 and the second electrode layer 403 of each capacitor structure 400.

[0118] like Figure 30 As shown, the first hybrid bonding layer 800 and the second hybrid bonding layer 900 are bonded together using a hybrid bonding process. Correspondingly, the first metal bond 801 and the second metal bond 901 are bonded to each other and electrically connected. The first hybrid bonding layer 800 and the second hybrid bonding layer 900 constitute a hybrid bonding structure 890. The first metal bond 801 and the second metal bond 901 constitute the metal bond 891 in the hybrid bonding structure 890. Through the metal bond 891, the capacitor structure 400 and the normally open switching transistor 410 can be connected as shown in the diagram. Figure 26 The connections shown are made in a specific manner. Specifically, the metal bonding member 891 connects the drains D of n-1 normally open switching transistors 410 to the second terminal of the first capacitor structure 400. The metal bonding member 891 also electrically connects the second terminal of the i-th capacitor structure 400 to the source S and gate G of the (i-1)-th normally open switching transistor 410. In other words, the interconnection between the normally open switching transistors 410 and the capacitor structure 400 can be achieved through the hybrid bonding structure 890.

[0119] like Figure 30 As shown, the temporary substrate 110 is removed, and a metal wiring layer 700 is formed on the oxide layer 101. The metal wiring layer 700 can electrically connect the first ends of n capacitor structures 400 as the first electrode P1 of the chip battery. The metal wiring layer 700 can also lead out the second end of the first capacitor structure 400 as the second electrode P2 of the chip battery.

[0120] Furthermore, the chip battery in this application can increase the capacity of the capacitor structure 400 by increasing the number of film layers in the stacked structure 200, thereby increasing the capacity of the chip battery. According to calculations, when the dielectric layer 401 is selected as aluminum oxide with a thickness of 2nm (relative permittivity 9.8), and the number of layers of the second sacrificial layer 202 is 1000, a chip battery of size 1cm*1cm with an 80% electrode area ratio has a capacitor structure 400 capacity of 0.007F. Based on a charging voltage of 36V and a charging current of 1A, the charging time is 0.25s, and the capacity of a single chip battery is 0.07mAh. One 12-inch wafer can produce 700 1cm*1cm chip batteries, and the total capacity of the chip batteries that can be produced is 49mAh.

[0121] In summary, this embodiment provides a chip battery and its fabrication method, including a substrate 100, n capacitor structures 400 and n-1 normally open switching transistors 410, where n ≥ 2. The capacitor structures 400 are located on the substrate 100, and at least a portion of the normally open switching transistors 410 are located on the substrate 100. Specifically, the first capacitor structure 400 is connected in parallel to a load R, the i-th capacitor structure 400 is connected in series with the (i-1)-th normally open switching transistor 410 and then connected in parallel to the load R, the node between the first capacitor structure 400 and the load R is connected to the gate G of the first normally open switching transistor 410, and the node between the i-th capacitor structure 400 and the (i-1)-th normally open switching transistor 410 is connected to the gate G of the i-th normally open switching transistor 410, where 2 ≤ i ≤ n. An unexpected benefit of this application is that it utilizes chip manufacturing processes to form capacitor structures 400 on substrate 100. The load R is powered by the charging and discharging of these capacitor structures 400. The chip battery exhibits no risk of explosion, fast charging speed, and no low-temperature degradation. Since each capacitor structure 400 powers the load R individually, the supply voltage is consistently maintained, preventing voltage drop after discharge. Furthermore, the overall capacity of the chip battery can be increased by increasing the capacitance of individual capacitor structures 400 or by increasing the number of capacitor structures 400. Each chip battery is also very thin (down to <50μm), allowing it to be stacked with computing chips and memory chips to form an independent microcomputer system. It is also resistant to extreme environments and can be applied in fields such as exploration and medicine. In addition, by connecting the capacitor structure 400 in series with a normally open switch 410, self-control of the chip battery's charging and discharging can be achieved.

[0122] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0123] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0124] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0125] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. A chip battery for powering a load, characterized by, The chip battery comprises a substrate, n capacitor structures and n-1 normally-on switch tubes, n≥2, the capacitor structures are located on the substrate, and at least part of the normally-on switch tubes are located on the substrate. The first capacitor structure is connected in parallel to the load, the ith capacitor structure is connected in parallel to the load after being connected in series with the (i-1)th normally-on switch tube, the node between the first capacitor structure and the load is connected to the gate of the first normally-on switch tube, and the node between the ith capacitor structure and the (i-1)th normally-on switch tube is connected to the gate of the ith normally-on switch tube, 2≤i≤n.

2. The chip battery according to claim 1, characterized by The substrate has a capacitor region and a switch region, the capacitor structures are located in the capacitor region, and the normally-on switch tubes are located in the switch region.

3. The chip battery according to claim 2, characterized by The substrate further has a metal wiring layer, the metal wiring layer electrically connects the first ends of the n capacitor structures and leads out, so as to serve as the first electrode of the chip battery, the metal wiring layer further electrically connects the second end of the ith capacitor structure with the source of the (i-1)th normally-on switch tube and the gate of the ith normally-on switch tube, and the metal wiring layer further connects the drains of the n-1 normally-on switch tubes with the second end of the first capacitor structure and the gate of the first normally-on switch tube and leads out, so as to serve as the second electrode of the chip battery.

4. The chip battery according to claim 1, wherein The chip battery further comprises: a dielectric layer located on the normally-on switch tubes; and a hybrid bonding structure located on the dielectric layer, and the capacitor structures are located on the hybrid bonding structure.

5. The chip battery according to claim 4, characterized by The hybrid bonding structure has a metal bonding member, the metal bonding member connects the drains of the n-1 normally-on switch tubes with the second end of the first capacitor structure, and the metal bonding member further electrically connects the second end of the ith capacitor structure with the source of the (i-1)th normally-on switch tube and the gate of the ith normally-on switch tube; and The chip battery further comprises a metal wiring layer, the metal wiring layer is located on the capacitor structures, the metal wiring layer electrically connects the first ends of the n capacitor structures, so as to serve as the first electrode of the chip battery, and the metal wiring layer leads out the second end of the first capacitor structure, so as to serve as the second electrode of the chip battery.

6. The chip battery according to any one of claims 1 to 5, characterized by The capacitor structure comprises a first electrode plate layer, a dielectric layer and a second electrode plate layer, the first electrode plate layer comprises a columnar main body part and at least one disc-shaped extension part, the extension part is sequentially and spacedly sleeved outside the main body part in the vertical direction, the dielectric layer wraps the outer wall of the first electrode plate layer, and the second electrode plate layer wraps the outer wall of the dielectric layer.

7. The chip battery according to claim 6, characterized by The capacitor structures are isolated by isolation columns; or the second electrode plate layers of all the capacitor structures are integrated structures.

8. The chip battery according to any one of claims 1 to 5, characterized by The normally-on switch tube is a normally-on PMOS tube.

9. A method for manufacturing a chip battery, the chip battery being used to power a load, characterized in that, The chip battery comprises: a substrate is provided; n capacitor structures and n-1 normally-on switch tubes are formed on the substrate, n≥2, the capacitor structures are located on the substrate, and at least part of the normally-on switch tubes are located on the substrate; The first capacitor structure is connected in parallel to the load, the i-th capacitor structure is connected in parallel to the load after being connected in series to the (i-1)-th normally-on switch tube, the node between the first capacitor structure and the load is connected to the gate of the first normally-on switch tube, the node between the i-th capacitor structure and the (i-1)-th normally-on switch tube is connected to the gate of the i-th normally-on switch tube, and 2≤i≤n.

10. The method of claim 9, wherein the chip battery is prepared by the steps of: The substrate has a capacitor region and a switch region, and the step of forming the capacitor structure and the normally-on switch tube on the substrate comprises: ​ forming the normally-on switch tube in the switch region of the substrate; forming the capacitor structure in the capacitor region of the substrate; and forming a metal wiring layer on the capacitor structure and the normally-on switch tube, the metal wiring layer electrically connecting the first ends of the n capacitor structures and leading out as the first electrode of the chip battery, the metal wiring layer also electrically connecting the second end of the first capacitor structure and the source of the (i-1)-th normally-on switch tube and the gate of the i-th normally-on switch tube, and the metal wiring layer also electrically connecting the drain of the (i-1)-th normally-on switch tube and the second end of the first capacitor structure and the gate of the first normally-on switch tube and leading out as the second electrode of the chip battery.

11. The method of claim 9, wherein the chip battery is prepared by the steps of: The step of forming the capacitor structure and the normally-on switch tube on the substrate comprises: ​ providing a temporary substrate, sequentially forming the capacitor structure and a first hybrid bonding layer on the temporary substrate, and the first hybrid bonding layer being located on the capacitor structure; sequentially forming the normally-on switch tube and a second hybrid bonding layer on the substrate, and the second hybrid bonding layer being located on the normally-on switch tube; bonding the first hybrid bonding layer and the second hybrid bonding layer together, the first hybrid bonding layer and the second hybrid bonding layer forming a hybrid bonding structure, the hybrid bonding structure having a metal bonding member, the metal bonding member connecting the drain of the (i-1)-th normally-on switch tube and the second end of the first capacitor structure, and the metal bonding member also electrically connecting the second end of the i-th capacitor structure and the source of the (i-1)-th normally-on switch tube and the gate of the i-th normally-on switch tube; and removing the temporary substrate and forming a metal wiring layer on the capacitor structure, the metal wiring layer electrically connecting the first ends of the n capacitor structures and leading out as the first electrode of the chip battery, and the metal wiring layer also leading out the second end of the first capacitor structure as the second electrode of the chip battery.

12. The method for preparing a chip battery according to any one of claims 9 to 11, characterized in that, The step of forming the capacitor structure comprises: forming a stack structure, the stack structure comprising at least one first sacrificial layer and at least one second sacrificial layer, the first sacrificial layer and the second sacrificial layer being stacked in sequence with a spacing therebetween; etching the stack structure to form n grooves penetrating through the stack structure; laterally etching the first sacrificial layer or the second sacrificial layer along the grooves so that the sidewalls of the grooves protrude laterally outward; forming a dielectric layer on the inner walls of the grooves; and forming a metal wiring layer on the dielectric layer, the metal wiring layer electrically connecting the first ends of the n capacitor structures and leading out as the first electrode of the chip battery, and the metal wiring layer also electrically connecting the second end of the first capacitor structure and leading out as the second electrode of the chip battery. forming a first plate layer in the trench, the first plate layer filling the trench; and removing the stack structure and forming a second plate layer at the original position of the stack structure, the first plate layer, the dielectric layer and the second plate layer constituting the capacitor structure.

13. The method of claim 12, wherein the chip battery is prepared by the steps of: Before etching the stack structure to form the trench, the preparation method further comprises: ​ etching the stack structure to form an isolation groove penetrating through the stack structure; filling an isolation material in the isolation groove to form an isolation column, the isolation column isolating n sub-regions; and when forming n trenches, one of the trenches is located in one of the sub-regions.

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