Display device

Abstract

There is provided a display device including a first display area including pixel circuits and scan lines configured to provide scan signals to the pixel circuits of the first display area. The display device includes a second display area located at one side of the first display area and including pixel circuits and scan lines configured to provide scan signals to the pixel circuits of the second display area. The display device includes a first scan driver located at a first side edge of a first display area, a second scan driver located at a second side edge of the first display area, a third scan driver located at a first side edge of the second display area and a fourth scan driver located at a second side edge of the second display area.

Description

Technical Field

[0001] Embodiments of this disclosure relate to display devices. Background Technology

[0002] With the development of an information-oriented society, the demand for display devices is constantly increasing. For example, display devices are used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs. Display devices in which each pixel of the display panel includes a light-emitting element capable of emitting light itself can display images without a backlight unit that provides light to the display panel.

[0003] In some cases, a display device may include multiple pixels, data lines and gate lines connected to the multiple pixels, a data driver that provides data voltage to the data lines, and a scan driver that provides scan signals to the gate lines. The data driver and scan driver may drive the multiple pixels at a predetermined frequency. Summary of the Invention

[0004] Embodiments supported by this disclosure provide a display device that can reduce the load for outputting scan signals and reduce the size of the non-display area.

[0005] An embodiment supported by aspects of this disclosure provides a display device comprising: a first display area including pixel circuitry and scan lines for providing scan signals to the pixel circuitry; a second display area located on one side of the first display area, including pixel circuitry and scan lines for providing scan signals to the pixel circuitry; a first scan driver located at a first side edge of the first display area, overlapping with the pixel circuitry and electrically connected to a first side of the scan lines of the first display area; a second scan driver located at a second side edge of the first display area opposite to the first side edge, overlapping with the pixel circuitry and electrically connected to a second side of the scan lines of the first display area opposite to the first side edge; a third scan driver located at a first side edge of the second display area, overlapping with the pixel circuitry and electrically connected to a first side of the scan lines of the second display area; and a fourth scan driver located at a second side edge of the second display area opposite to the first side edge, overlapping with the pixel circuitry and electrically connected to a second side of the scan lines of the second display area opposite to the first side edge.

[0006] In an embodiment, the display device may further include: a first connecting line electrically connecting a first scan driver and a first side of a scan line in a first display area; a second connecting line electrically connecting a second scan driver and a second side of a scan line in the first display area; a third connecting line electrically connecting a third scan driver and a first side of a scan line in the second display area; and a fourth connecting line electrically connecting a fourth scan driver and a second side of a scan line in the second display area.

[0007] The second and third connecting lines can be disposed between the pixel circuits of the first and second display areas. The second and third connecting lines do not overlap with the pixel circuits of the first and second display areas.

[0008] The first connecting line may be closer to the first side edge of the first display area than the first scan driver, the second connecting line may be closer to the second side edge of the first display area than the second scan driver, the third connecting line may be closer to the first side edge of the second display area than the third scan driver, and the fourth connecting line may be closer to the second side edge of the second display area than the fourth scan driver.

[0009] The display device may further include a dividing line disposed between a first display area and a second display area to separate the first display area and the second display area from each other. The pixel circuits of the first display area and the pixel circuits of the second display area may be spaced apart from each other, with the dividing line between them.

[0010] The second connecting line can be disposed between the dividing line and the pixel circuit of the first display area, and can be disposed without overlapping with the pixel circuit of the first display area. The third connecting line can be disposed between the dividing line and the pixel circuit of the second display area, and can be disposed without overlapping with the pixel circuit of the second display area.

[0011] Each of the first to fourth scan drivers may include a scan transistor disposed in a first active layer comprising a first material, and the pixel circuit may include a transistor disposed in a second active layer comprising a second material different from the first material.

[0012] The display device may further include: a first active layer including a semiconductor region of a scanning transistor; a first gate layer disposed on the first active layer and including a gate electrode of a scanning transistor; a second gate layer disposed on the first gate layer; a second active layer disposed on the second gate layer and including a semiconductor region of a transistor; and a third gate layer disposed on the second active layer and including a gate electrode of a transistor and a scan line.

[0013] The display device may further include a first source metal layer disposed on the third gate layer. The first source metal layer may include connection electrodes that electrically connect the scan transistor to the scan line.

[0014] The display device may further include: a first active layer including a semiconductor region of a transistor of a pixel circuit; a first gate layer disposed on the first active layer and including a gate electrode of a transistor and a scan line; a second gate layer disposed on the first gate layer; a second active layer disposed on the second gate layer and including a semiconductor region of a scan transistor of each of a first scan driver to a fourth scan driver; and a third gate layer disposed on the second active layer and including a gate electrode of a scan transistor.

[0015] The display device may further include a first source metal layer disposed on the third gate layer. The first source metal layer may include connection electrodes that electrically connect the scan transistor to the scan line.

[0016] The pixel circuit may include: a first transistor configured to provide a drive current to a light-emitting element; a second transistor configured to provide a data voltage to the gate electrode of the first transistor; a third transistor configured to provide a reference voltage to the gate electrode of the first transistor; a fourth transistor configured to provide an initialization voltage to the first electrode of the light-emitting element; a fifth transistor configured to provide a drive voltage to the first electrode of the first transistor; and a sixth transistor configured to electrically connect a second electrode of the first transistor and a first electrode of the light-emitting element.

[0017] The pixel circuit may include: a first transistor configured to provide a drive current to a light-emitting element; a second transistor configured to provide a data voltage to a first electrode of the first transistor; a third transistor configured to electrically connect a second electrode of the first transistor and a gate electrode of the first transistor; a fourth transistor configured to provide a first initialization voltage to the gate electrode of the first transistor; a fifth transistor configured to provide a drive voltage to the first electrode of the first transistor; a sixth transistor configured to electrically connect a second electrode of the first transistor and a first electrode of the light-emitting element; and a seventh transistor configured to provide a second initialization voltage to the first electrode of the light-emitting element.

[0018] An embodiment supported by aspects of this disclosure provides a display device comprising: a display area including pixel circuitry, scan lines extending in a first direction to provide scan signals to the pixel circuitry, and a boundary line extending in a second direction intersecting the first direction and passing through the center of the display area; a first display area located on a first side of the boundary line within the display area; a second display area located on a second side of the display area opposite to the first side of the boundary line; a first scan driver located at the first edge of the display area and electrically connected to a first side of the scan lines in the first display area; a second scan driver located on the first side of the boundary line and electrically connected to a second side opposite to the first side of the scan lines in the first display area; a third scan driver located on the second side opposite to the first side of the boundary line and electrically connected to a first side of the scan lines in the second display area; and a fourth scan driver located at the second edge opposite to the first edge of the display area and electrically connected to a second side opposite to the first side of the scan lines in the second display area.

[0019] The first and second scan drivers may overlap with the pixel circuitry of the first display area. The third and fourth scan drivers may overlap with the pixel circuitry of the second display area.

[0020] The display device may further include: a first connecting line electrically connecting a first scan driver and a first side of a scan line of a first display area; a second connecting line electrically connecting a second scan driver and a second side of a scan line of the first display area; a third connecting line electrically connecting a third scan driver and a first side of a scan line of the second display area; and a fourth connecting line electrically connecting a fourth scan driver and a second side of a scan line of the second display area.

[0021] The second and third connecting lines can be disposed between the pixel circuits of the first and second display areas. The second and third connecting lines do not need to overlap with the pixel circuits of the first and second display areas.

[0022] The first connecting line can be closer to the first side edge of the display area than the first scan driver. The second connecting line can be closer to the dividing line than the second scan driver. The third connecting line can be closer to the dividing line than the third scan driver. The fourth connecting line can be closer to the second side edge of the display area than the fourth scan driver.

[0023] The first through fourth scan drivers may include scan transistors disposed in a first active layer comprising a silicon-based material. Pixel circuitry may include transistors disposed in a second active layer comprising an oxide-based material.

[0024] The pixel circuit may include transistors disposed in a first active layer comprising a silicon-based material. Each of the first to fourth scan drivers may include a scan transistor disposed in a second active layer comprising an oxide-based material.

[0025] In an embodiment according to aspects of the present disclosure, in a display device, a first scan driver and a second scan driver are arranged on two edges of a first display area to provide scan signals, and a third scan driver and a fourth scan driver are arranged on two edges of a second display area to provide scan signals, thereby reducing the load for outputting scan signals and the size of the non-display area. Attached Figure Description

[0026] These and / or other features supported by aspects of this disclosure will become apparent and more readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 This is a perspective view showing a display device according to an embodiment of the present disclosure;

[0028] Figure 2 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0029] Figure 3 This is a plan view showing a display device according to an embodiment of the present disclosure;

[0030] Figure 4 This is a view showing the emission area and pixel circuitry in a display device according to an embodiment;

[0031] Figure 5 This is a view showing the emission area, pixel circuitry, scan driver, and connecting lines in a display device according to an embodiment;

[0032] Figure 6 This is a block diagram illustrating a scan driver for a display device according to an embodiment of the present disclosure;

[0033] Figure 7 This is a circuit diagram illustrating an example of pixels in a display device according to an embodiment of the present disclosure;

[0034] Figure 8 This is a circuit diagram illustrating another example of pixels in a display device according to an embodiment of the present disclosure;

[0035] Figure 9 This is a cross-sectional view showing a display device according to an embodiment of the present disclosure; and

[0036] Figure 10 This is a cross-sectional view showing a display device according to another embodiment of the present disclosure. Detailed Implementation

[0037] Embodiments of this disclosure will now be described more fully below with reference to the accompanying drawings, in which various embodiments of this disclosure are illustrated. However, aspects supported by this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary aspects of this disclosure to those skilled in the art. Throughout the specification, the same reference numerals denote the same components. In the drawings, the thickness of layers and regions is exaggerated for clarity.

[0038] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings herein, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0039] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or there may be an intervening layer. Conversely, when an element is referred to as being "directly" on another element, there is no intervening element.

[0040] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms containing “at least one,” unless the context clearly indicates otherwise. Thus, reference to “the” element following “an” in a claim includes one element and multiple elements. For example, “one element” has the same meaning as “at least one element,” unless the context clearly indicates otherwise. “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” “At least one of A and B” or “selected from at least one of A and B” means “A and / or B.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprises” and / or “comprising” or “includes” and / or “including” specify the presence of the stated features, regions, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, regions, integrals, steps, operations, elements, components and / or groups thereof.

[0041] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to encompass different orientations of the devices. For example, if a device in one of the drawings is flipped, an element described as being “down” to the other elements will be oriented “up” to the other elements. Thus, the term “down” can encompass both “down” and “up” orientations depending on the specific orientation of the drawing. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” the other elements will be oriented “above” the other elements. Thus, the term “below” or “under” can encompass both “up” and “down” orientations.

[0042] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms “about” or “approximately” as used herein include the values ​​and mean within an acceptable deviation range for a particular value as determined by one of ordinary skill in the art.

[0043] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having meanings consistent with their meanings in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0044] Embodiments are described herein with reference to cross-sectional views as schematic representations of idealized embodiments. Therefore, variations in the shape of the figures should be expected, for example, due to manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but should include, for example, deviations in shape due to manufacturing processes. For instance, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to represent the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0045] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0046] Figure 1 This is a perspective view showing a display device according to an embodiment of the present disclosure.

[0047] refer to Figure 1 The display device 10 is used to display moving or still images. The display device 10 can be used as a display screen for portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs), as well as for various products such as televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices.

[0048] The display device 10 may include a display panel 100, a data driver 200, a timing controller 300, a power supply unit 400, a data circuit board 500, and a control circuit board 600.

[0049] When viewed from above, the display panel 100 may have a rectangular shape, having a longer side in the X-axis direction and a shorter side in the Y-axis direction intersecting the X-axis direction. The angle where the longer side in the X-axis direction and the shorter side in the Y-axis direction meet each other may be rounded with a predetermined curvature or may be formed at a right angle. When viewed from above, the shape of the display panel 100 is not limited to a quadrilateral shape, but may be formed into various polygonal shapes, circular shapes, or elliptical shapes. The display panel 100 may be formed flat, but embodiments of the present disclosure are not limited thereto. For example, the display panel 100 may be formed at the left and right ends and may include curved portions with constant or varying curvature. The display panel 100 may be formed flexible, such that the display panel 100 may be curved, bent, folded, or rolled up.

[0050] Display panel 100 may include a display area DA for displaying images and a non-display area NDA disposed around the display area DA. The display area DA may occupy most of the area of ​​display panel 100. The display area DA may be located in the center of display panel 100. The display area DA may include multiple pixels for displaying images and a scan driver.

[0051] Each of the plurality of pixels may include a light-emitting element that emits light. The light-emitting element may include, but is not limited to, at least one of the following: an organic light-emitting diode including an organic emitting layer, a quantum dot light-emitting diode including a quantum dot emitting layer, an inorganic light-emitting diode including an inorganic semiconductor, and a micro light-emitting diode (microLED).

[0052] The scan driver can provide scan signals to the gate lines of the display area DA. The scan driver can be located at the center of the non-display area NDA, or on the left and right sides of the non-display area NDA, but the embodiments of this disclosure are not limited thereto.

[0053] The non-display area NDA can be set adjacent to the display area DA. The non-display area NDA can be located outside the display area DA. The non-display area NDA can surround the display area DA. The non-display area NDA can be defined as the boundary of the display panel 100.

[0054] The non-display area NDA may include fan-out lines and pads. The fan-out lines can electrically connect the data driver 200 to data lines in the display area DA. The pads can be electrically connected to the data circuit board 500. The pads may be located on the underside of the display panel 100, but embodiments of this disclosure are not limited thereto.

[0055] The data driver 200 can output signals and voltages for driving the display panel 100. The data driver 200 can provide data voltage to the data lines. The data driver 200 can provide power voltage to the power supply lines and can provide scan control signals to the scan driver. The data driver 200 can be implemented as an integrated circuit (IC) and mounted on the data circuit board 500 using chip-on-film (COF) technology. Alternatively, the data driver 200 can be mounted in the non-display area NDA of the display panel 100 using chip-on-glass (COG) technology, chip-on-plastic (COP) technology, or ultrasonic bonding.

[0056] The timing controller 300 can be mounted on the control circuit board 600 and can receive digital video data and timing synchronization signals from the display driving system or graphics device via a user connector provided on the control circuit board 600. The timing controller 300 can appropriately coordinate the digital video data for the pixel arrangement structure in response to the timing synchronization signal and can provide the coordinated digital video data to the data driver 200. The timing controller 300 can generate data control signals and scan control signals based on the timing synchronization signal. The timing controller 300 can control the timing of applying data voltage from the data driver 200 based on the data control signal and can control the timing of providing scan signals from the scan driver based on the scan control signal.

[0057] The power supply unit 400 can be mounted on the control circuit board 600 to apply power supply voltage to the display panel 100 and the data driver 200. For example, the power supply unit 400 can generate a drive voltage, a common voltage, an initialization voltage, a bias voltage, a gate high voltage, a gate low voltage, or a reference voltage. The power supply unit 400 can provide power supply voltage to drive multiple pixels and the data driver 200.

[0058] Data circuit board 500 can be disposed on pads located at one edge of display panel 100. Data circuit board 500 can be attached to the pads using conductive adhesive members such as, for example, anisotropic conductive film. Data circuit board 500 can be electrically connected to signal lines of display panel 100 via the anisotropic conductive film. Display panel 100 can receive data voltage and power supply voltage through data circuit board 500. For example, data circuit board 500 can be a flexible printed circuit board (FPCB), a rigid printed circuit board (PCB), or a flexible film such as, for example, chip on film (COF).

[0059] The control circuit board 600 can be attached to the data circuit board 500 using a low-resistance, high-reliability material such as, for example, anisotropic conductive film or self-assembling anisotropic conductive paste (SAP). The control circuit board 600 can be electrically connected to the data circuit board 500. The control circuit board 600 can be a flexible printed circuit board or a printed circuit board.

[0060] Figure 2 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0061] refer to Figure 2 The display panel 100 may include a display area DA and a non-display area NDA. The display area DA may include pixels SP, gate lines GL, emission control lines EML, data lines DL, voltage lines VL, and a scan driver 800.

[0062] Each of the multiple pixels SP can be connected to a gate line GL, a data line DL, an emitter control line EML, and a voltage line VL. Each of the multiple pixels SP may include at least one transistor, a light-emitting element, and a capacitor.

[0063] Gate lines GL can extend in the X-axis direction and can be spaced apart from each other in the Y-axis direction, which intersects the X-axis direction. Gate lines GL can sequentially provide gate signals to multiple pixels SP.

[0064] The emission control lines EML can extend in the X-axis direction and can be spaced apart from each other in the Y-axis direction. The emission control lines EML can sequentially provide emission signals to pixels SP.

[0065] The data lines DL can extend in the Y-axis direction and can be spaced apart from each other in the X-axis direction. The data lines DL can provide data voltage received from the data driver 200 to the pixels SP. The data voltage can determine the brightness of each of the multiple pixels SP.

[0066] Voltage lines VL can extend in the Y-axis direction and can be spaced apart from each other in the X-axis direction. Voltage lines VL can provide power supply voltages to multiple pixels SP. The power supply voltage can include at least one of the following: driving voltage, common voltage, initialization voltage, bias voltage, gate high voltage, gate low voltage, and reference voltage. For example, the driving voltage can be a high-level voltage used to drive the light-emitting elements of the pixels SP, and the common voltage can be a low-level voltage used to drive the light-emitting elements of the pixels SP.

[0067] Scan driver 800 may include gate driver 810 and emit control driver 820. Gate driver 810 may include multiple transistors for generating a gate signal based on a gate control signal GCS. Emitter control driver 820 may include multiple transistors for generating an emit signal based on an emit control signal ECS. For example, gate driver 810 and emit control driver 820 may include transistors disposed in a first active layer comprising a first material, and pixel SP may include transistors disposed in a second active layer comprising a second material different from the first material. Gate driver 810 may provide a gate signal to gate line GL, and emit control driver 820 may provide an emit signal to emit control line EML.

[0068] Data driver 200 can convert digital video data DATA into analog data voltage and provide it to data line DL. The gate signal of gate driver 810 can be used to select the pixel SP to which the data voltage is applied, and the selected pixel SP can receive the data voltage through data line DL.

[0069] The timing controller 300 can receive digital video data DATA and timing signals from the graphics device 700. For example, the graphics device 700 may be, but is not limited to, the graphics card of the display device 10. The timing controller 300 can generate a data control signal DCS based on the timing signals and provide the digital video data DATA and the data control signal DCS to the data driver 200, thereby controlling the operating timing of the data driver 200. The timing controller 300 can control the operating timing of the gate driver 810 by generating a gate control signal GCS based on the timing signals and providing the gate control signal GCS to the gate driver 810. The timing controller 300 can control the operating timing of the transmission control driver 820 by generating a transmission control signal ECS based on the timing signals and providing the transmission control signal ECS to the transmission control driver 820. The timing controller 300 can change the driving frequency of the display panel 100 based on the input frequency of the digital video data DATA from the graphics device 700.

[0070] The power supply unit 400 can be disposed on the data circuit board 500 and provides power voltage to the data driver 200 and the display panel 100. The power supply unit 400 can generate a driving voltage and provide it to the driving voltage line, and it can also generate a common voltage and provide it to a common electrode shared by the light-emitting elements of the pixels SP. The power supply unit 400 can generate an initialization voltage and provide it to the initialization voltage line, and it can also generate a bias voltage and provide it to the bias voltage line. The power supply unit 400 can generate a gate high voltage and provide it to the gate high voltage line, generate a gate low voltage and provide it to the gate low voltage line, and it can also generate a reference voltage and provide it to the reference voltage line.

[0071] Figure 3 This is a plan view showing a display device according to an embodiment of the present disclosure.

[0072] refer to Figure 3 The display area DA may include a first display area DA1 and a second display area DA2. The first display area DA1 may be the left portion of the display area DA, and the second display area DA2 may be the right portion of the display area DA. However, it should be understood that the position and size of the first display area DA1 and the second display area DA2 are not limited thereto. A dividing line BNL may be located between the first display area DA1 and the second display area DA2, and distinguish between the two display areas. The dividing line BNL may extend in the Y-axis direction and pass through the center of the display area DA.

[0073] Scan driver 800 may include a first scan driver 801, a second scan driver 802, a third scan driver 803, and a fourth scan driver 804. For example, each of the first scan driver 801, second scan driver 802, third scan driver 803, and fourth scan driver 804 may include a gate driver 810 and an emitter control driver 820. In another example, each of the first scan driver 801, second scan driver 802, third scan driver 803, and fourth scan driver 804 may include one of a gate driver 810 and an emitter control driver 820. Scan driver 800 can be electrically connected to scan line SL via a connection line CNL. Scan line SL may correspond to... Figure 2 The gate line GL or emitter control line EML. The connection line CNL may include a first connection line CNL1, a second connection line CNL2, a third connection line CNL3, and a fourth connection line CNL4.

[0074] The first scan driver 801 can be located at the left edge of the first display area DA1. The left edge of the first display area DA1 can be the left edge of the entire display area DA. The first connection line CNL1 can be closer to the left edge of the first display area DA1 than the first scan driver 801. The first connection line CNL1 can be electrically connected to the left end of the scan line SL of the first display area DA1. Therefore, the first scan driver 801 can provide a scan signal to the scan line SL of the first display area DA1 through the first connection line CNL1.

[0075] The second scan driver 802 can be located at the right edge of the first display area DA1. The second connection line CNL2 can be closer to the right edge of the first display area DA1 than the second scan driver 802. The right edge of the first display area DA1 can correspond to the boundary line BNL. The second connection line CNL2 can be electrically connected to the right end of the scan line SL of the first display area DA1. Therefore, the second scan driver 802 can provide a scan signal to the scan line SL of the first display area DA1 through the second connection line CNL2.

[0076] The third scan driver 803 can be located at the left edge of the second display area DA2. The third connecting line CNL3 can be closer to the left edge of the second display area DA2 than the third scan driver 803. The left edge of the second display area DA2 can correspond to the dividing line BNL. The dividing line BNL can be set between the second connecting line CNL2 and the third connecting line CNL3. The third connecting line CNL3 can be electrically connected to the left end of the scan line SL of the second display area DA2. Therefore, the third scan driver 803 can provide a scan signal to the scan line SL of the second display area DA2 through the third connecting line CNL3.

[0077] The fourth scan driver 804 can be located at the right edge of the second display area DA2. The right edge of the second display area DA2 can be the right edge of the entire display area DA. The fourth connection line CNL4 can be closer to the right edge of the second display area DA2 than the fourth scan driver 804. The fourth connection line CNL4 can be electrically connected to the right end of the scan line SL of the second display area DA2. Therefore, the fourth scan driver 804 can provide a scan signal to the scan line SL of the second display area DA2 through the fourth connection line CNL4.

[0078] Therefore, the display device 10 includes a first scan driver 801 and a second scan driver 802 located at the two edges of the first display area DA1 to provide scan signals, and a third scan driver 803 and a fourth scan driver 804 located at the two edges of the second display area DA2 to provide scan signals, such that the load for outputting scan signals by the display device 10 can be reduced compared to a display device in which the scan drivers are disposed at the two edges of the entire display area. In some aspects, the scan drivers 800 are disposed in the first display area DA1 and the second display area DA2, thereby reducing the area of ​​the non-display area NDA.

[0079] Figure 4 This is a view showing the emission area and pixel circuitry in a display device according to an embodiment. Figure 4 Multiple rows and columns are schematically shown. It should be noted that the display device 10 may include more than […]. Figure 4 The rows and columns shown are more rows and columns.

[0080] refer to Figure 4 Each of the first display area DA1 and the second display area DA2 may include an emission area EA and a pixel circuit PC. Multiple pixel circuit PCs may be arranged along the first row ROW1, second row ROW2, third row ROW3, ​​and fourth row ROW4 in the X-axis direction. The pixel circuit PCs of the first display area DA1 may be arranged along the 11th column COL11, 12th column COL12, 13th column COL13, 14th column COL14, 15th column COL15, and 16th column COL16 in the Y-axis direction. The pixel circuit PCs of the second display area DA2 may be arranged along the 21st column COL21, 22nd column COL22, 23rd column COL23, 24th column COL24, 25th column COL25, and 26th column COL26 in the Y-axis direction. The 11th column COL11 of the first display area DA1 and the 21st column COL21 of the second display area DA2 may be closest to the boundary line BNL.

[0081] The emission region EA may include a first emission region EA1, a second emission region EA2, and a third emission region EA3. Pixel circuits PC may be associated with each emission region EA. A single unit pixel may include the first emission region EA1, the second emission region EA2, and the third emission region EA3 to represent a black and white image or a grayscale image. However, it should be understood that the configuration of unit pixels is not limited to this.

[0082] For example, the first emission area EA1 and the second emission area EA2 of the first display area DA1 can overlap with the pixel circuits PC arranged in columns 11 (COL11) and 14 (COL14). The third emission area EA3 of the first display area DA1 can overlap with the pixel circuits PC arranged in columns 12 (COL12), 13 (COL13), 15 (COL15), and 16 (COL16). The first emission area EA1 and the second emission area EA2 of the second display area DA2 can overlap with the pixel circuits PC arranged in columns 22 (COL22), 23 (COL23), 25 (COL25), and 26 (COL26). The third emission area EA3 of the second display area DA2 can overlap with the pixel circuits PC arranged in columns 21 (COL21) and 24 (COL24). The pixel circuits PC and the emission areas EA can be arranged in a symmetrical manner. Figure 4 Other methods besides those shown overlap with each other.

[0083] Figure 5 This is a view showing the emission area, pixel circuitry, scan driver, and connecting lines in a display device according to an embodiment. Figure 5 yes Figure 3 Superimposed on Figure 4 The view above. Components that are the same as those described in this document will be briefly described or omitted.

[0084] refer to Figure 5 The first scan driver 801 and the second scan driver 802 of the first display area DA1 can overlap with the pixel circuit PC of the first display area DA1 in the Z-axis direction or the thickness direction. The first scan driver 801 and the second scan driver 802 can also overlap with the emission area EA of the first display area DA1. For example, the first connecting line CNL1 can overlap with the pixel circuit PC disposed at the left edge of the first display area DA1. In another example, the first connecting line CNL1 can be disposed between the left boundary of the first display area DA1 and the pixel circuit PC, such that the first connecting line CNL1 does not overlap with the pixel circuit PC. The second connecting line CNL2 can be disposed between the boundary line BNL and the pixel circuit PC in the 11th column COL11, such that the second connecting line CNL2 does not overlap with the pixel circuit PC. The second connecting line CNL2 may not overlap with the emission area EA of the first display area DA1.

[0085] The third scan driver 803 and the fourth scan driver 804 of the second display area DA2 can overlap with the pixel circuit PC of the second display area DA2 in the Z-axis direction or the thickness direction. The third scan driver 803 and the fourth scan driver 804 can overlap with the emission area EA of the second display area DA2. The third connecting line CNL3 can be disposed between the boundary line BNL and the pixel circuit PC in the 21st column COL21, such that the third connecting line CNL3 does not overlap with the pixel circuit PC. The third connecting line CNL3 may not overlap with the emission area EA of the second display area DA2. For example, the fourth connecting line CNL4 can overlap with the pixel circuit PC disposed at the right edge of the second display area DA2. In another example, the fourth connecting line CNL4 can be disposed between the right boundary of the second display area DA2 and the pixel circuit PC, such that the fourth connecting line CNL4 does not overlap with the pixel circuit PC.

[0086] Therefore, the display device 10 includes a first scan driver 801 and a second scan driver 802 located at the two edges of the first display area DA1 to provide scan signals, and a third scan driver 803 and a fourth scan driver 804 located at the two edges of the second display area DA2 to provide scan signals, such that the load for outputting scan signals by the display device 10 can be reduced compared to a display device in which the scan drivers are disposed at the two edges of the entire display area. In some aspects, the scan drivers 800 are disposed in the first display area DA1 and the second display area DA2, thereby reducing the area of ​​the non-display area NDA.

[0087] Figure 6 This is a block diagram illustrating a scan driver for a display device according to an embodiment of the present disclosure.

[0088] refer to Figure 6 The scan driver 800 may include multiple stage STGs. A clock line CKL provides a clock signal CK to the stage STG. A gate high voltage line VGHL provides a gate high voltage VGH to the stage STG, and a gate low voltage line VGLL provides a gate low voltage VGL to the stage STG. Each stage STG generates a scan signal and provides it to the scan line SL. The stage STG may include a first stage STG1, a second stage STG2, a third stage STG3, and a fourth stage STG4.

[0089] The first-stage STG1 can be connected to the start line STL and can receive the start signal FLM. The first-stage STG1 can receive the clock signal CK, the gate high voltage VGH, and the gate low voltage VGL, and provide the first scan signal to the first scan line SL1.

[0090] The second-stage STG2 can receive the carry signal CR from the first-stage STG1. The second-stage STG2 can receive the clock signal CK, the gate high voltage VGH, and the gate low voltage VGL, and provide the second scan signal to the second scan line SL2.

[0091] The third-stage STG3 can receive the carry signal CR from the second-stage STG2. The third-stage STG3 can receive the clock signal CK, the gate high voltage VGH, and the gate low voltage VGL, and provide the third scan signal to the third scan line SL3.

[0092] The fourth stage STG4 can receive the carry signal CR from the third stage STG3. The fourth stage STG4 can receive the clock signal CK, the gate high voltage VGH, and the gate low voltage VGL, and provide the fourth scan signal to the fourth scan line SL4.

[0093] Figure 7 This is a circuit diagram illustrating an example of pixels in a display device according to an embodiment of the present disclosure.

[0094] refer to Figure 7 The first display area DA1 and the second display area DA2 may include a plurality of pixels SP. Each of the plurality of pixels SP may be connected to a first gate line GWL, a second gate line GRL, a third gate line GIL, a first transmit control line EML1, a second transmit control line EML2, a data line DL, a reference voltage line VRL, a power supply voltage line VDL, an initialization voltage line VIL, and a low-level voltage line VSL.

[0095] A pixel SP may include a pixel circuit PC and a light-emitting element ED. The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, as well as a first capacitor C1 and a second capacitor C2.

[0096] The first transistor T1 may include a gate electrode, a drain electrode, and a source electrode. The first transistor T1 can control the drain-source current (Ids) (or drive current) based on the data voltage applied to the gate electrode. The drive current (Ids) flowing through the channel of the first transistor T1 is proportional to the square of the difference between the threshold voltage (Vth) of the first transistor T1 and the voltage between the gate and source electrodes (Vgs) (Ids = k' × (Vgs - Vth)). 2), where k represents a scaling factor determined by the structure and physical properties of the first transistor T1, Vgs represents the gate-source voltage of the first transistor T1, and Vth represents the threshold voltage of the first transistor T1. The gate electrode of the first transistor T1 can be connected to the first node N1, the drain electrode of the first transistor T1 can be connected to the source electrode of the fifth transistor T5, and the source electrode of the first transistor T1 can be connected to the second node N2. The first transistor T1 may also include a bias electrode electrically connected to the second node N2.

[0097] An LED can receive a driving current (Ids) to emit light. The amount or brightness of light emitted from an LED can be proportional to the magnitude of the driving current (Ids).

[0098] The light-emitting element (ED) can be an organic light-emitting diode (OLED) comprising a first electrode, a second electrode, and an organic light-emitting layer disposed between the first and second electrodes. Optionally, the ED can be an inorganic light-emitting element comprising a first electrode, a second electrode, and an inorganic semiconductor disposed between the first and second electrodes. Optionally, the ED can be a quantum dot light-emitting element comprising a first electrode, a second electrode, and a quantum dot emitting layer disposed between the first and second electrodes. As another example, the ED can be a micro light-emitting diode (microLED).

[0099] The first electrode of the light-emitting element ED can be electrically connected to the third node N3. The first electrode of the light-emitting element ED can be electrically connected to the drain electrode of the fourth transistor T4 and the source electrode of the sixth transistor T6 through the third node N3. The second electrode of the light-emitting element ED can be electrically connected to the low-level voltage line VSL and can receive a low-level voltage from the low-level voltage line VSL.

[0100] The second transistor T2 can be turned on by a first gate signal on the first gate line GWL to electrically connect the data line DL to the first node N1, which is the gate electrode of the first transistor T1. The second transistor T2 can be turned on in response to the first gate signal to apply a data voltage to the first node N1. The gate electrode of the second transistor T2 can be connected to the first gate line GWL, the drain electrode of the second transistor T2 can be connected to the data line DL, and the source electrode of the second transistor T2 can be connected to the first node N1.

[0101] The third transistor T3 can be turned on by a second gate signal on the second gate line GRL to electrically connect the reference voltage line VRL to the first node N1, which is the gate electrode of the first transistor T1. The third transistor T3 can be turned on in response to the second gate signal to apply a reference voltage to the first node N1. The gate electrode of the third transistor T3 can be connected to the second gate line GRL, the drain electrode of the third transistor T3 can be connected to the reference voltage line VRL, and the source electrode of the third transistor T3 can be connected to the first node N1.

[0102] The fourth transistor T4 can be turned on by the third gate signal of the third gate line GIL to electrically connect the third node N3, which serves as the first electrode of the light-emitting element ED, to the initialization voltage line VIL. When the fourth transistor T4 is turned on based on the third gate signal, the first electrode of the light-emitting element ED can discharge to the initialization voltage. The gate electrode of the fourth transistor T4 can be connected to the third gate line GIL, the drain electrode of the fourth transistor T4 can be connected to the third node N3, and the source electrode of the fourth transistor T4 can be connected to the initialization voltage line VIL.

[0103] The fifth transistor T5 can be turned on by the first transmit signal of the first transmit control line EML1, and can electrically connect the power supply voltage line VDL to the drain electrode of the first transistor T1. The gate electrode of the fifth transistor T5 can be connected to the first transmit control line EML1, the drain electrode of the fifth transistor T5 can be connected to the power supply voltage line VDL, and the second electrode of the fifth transistor T5 can be connected to the drain electrode of the first transistor T1.

[0104] The sixth transistor T6 can be turned on by the second emission signal of the second emission control line EML2, so as to electrically connect the second node N2, which is the source electrode of the first transistor T1, to the third node N3, which is the first electrode of the light-emitting element ED. The second emission signal can be the inverted signal of the first emission signal, but the embodiments of this disclosure are not limited thereto. The gate electrode of the sixth transistor T6 can be connected to the second emission control line EML2, the drain electrode of the sixth transistor T6 can be connected to the second node N2, and the source electrode of the sixth transistor T6 can be connected to the third node N3.

[0105] Each of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6 may include an oxide-based active layer. The first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6 may have a coplanar structure in which the gate electrode is located at the top. The first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6 may be n-type transistors and may output current introduced into the drain electrode via the source electrode based on a high gate voltage applied to the gate electrode. The oxide-based active layer may have a relatively small S-factor, which can increase the constant current drive area in the low grayscale region and improve the low grayscale representation.

[0106] In another example, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may include an active layer formed of low-temperature polycrystalline silicon (LTPS). The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be p-type transistors and may output current introduced into the source electrode via the drain electrode based on a low gate voltage applied to the gate electrode.

[0107] A first capacitor C1 can be electrically connected between a first node N1, which serves as the gate electrode of the first transistor T1, and a second node N2, which serves as the source electrode of the first transistor T1. For example, the first electrode of the first capacitor C1 can be electrically connected to the first node N1, and the second electrode of the first capacitor C1 can be electrically connected to the second node N2, so that the potential difference between the gate electrode and the source electrode of the first transistor T1 can be maintained.

[0108] The second capacitor C2 can be electrically connected between the power supply voltage line VDL and the second node N2, which serves as the source electrode of the first transistor T1. For example, the first electrode of the second capacitor C2 can be electrically connected to the power supply voltage line VDL, and the second electrode of the second capacitor C2 can be electrically connected to the second node N2, so that the potential difference between the power supply voltage line VDL and the source electrode of the first transistor T1 can be maintained.

[0109] Figure 8 This is a circuit diagram illustrating another example of pixels in a display device according to an embodiment of the present disclosure.

[0110] refer to Figure 8The first display area DA1 and the second display area DA2 may include a plurality of pixels SP. Each of the plurality of pixels SP may be connected to a first gate line GWL, a second gate line GCL, a third gate line GIL, a fourth gate line GBL, an emit control line EML, a data line DL, a power supply voltage line VDL, a first initialization voltage line VIL1, a second initialization voltage line VIL2, a bias voltage line VBL, and a low-level voltage line VSL.

[0111] A pixel SP may include a pixel circuit PC and a light-emitting element ED. The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8, as well as a capacitor C1.

[0112] The first transistor T1 can control the drive current supplied to the light-emitting element ED. The first transistor T1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 can be connected to a third node N3, the first electrode of the first transistor T1 can be connected to a first node N1, and the second electrode of the first transistor T1 can be connected to a second node N2. For example, the first electrode of the first transistor T1 can be a drain electrode, and the second electrode can be a source electrode. However, it should be understood that embodiments of this disclosure are not limited thereto.

[0113] The first transistor T1 can control the drain-source current (Ids) (hereinafter referred to as the "drive current") based on the data voltage applied to the gate electrode. The drive current (Ids) flowing through the channel of the first transistor T1 is proportional to the square of the difference between the threshold voltage (Vth) of the first transistor T1 and the voltage between the gate and source electrodes (Vgs) (Ids = k' × (Vgs - Vth)). 2 ), where k represents a scaling factor determined by the structure and physical properties of the first transistor T1, Vgs represents the gate-source voltage of the first transistor T1, and Vth represents the threshold voltage of the first transistor T1.

[0114] A light-emitting element (ED) can receive a driving current (Ids) to emit light. The amount or brightness of the light emitted from the ED can be proportional to the magnitude of the driving current (Ids). The ED may include a first electrode, a second electrode, and an emitting layer disposed between the first and second electrodes. The first electrode of the ED can be connected to a fourth node N4. The first electrode of the ED can be electrically connected to the second electrode of a sixth transistor T6 and the first electrode of a seventh transistor T7 via the fourth node N4. The second electrode of the ED can be electrically connected to a low-level voltage line VSL and can receive a low-level voltage from the low-level voltage line VSL. For example, the first electrode of the ED can be an anode electrode or a pixel electrode, while the second electrode of the ED can be a cathode electrode or a common electrode. However, it should be understood that the embodiments of this disclosure are not limited thereto.

[0115] The second transistor T2 can be turned on by a first gate signal on the first gate line GWL to electrically connect the data line DL to the first node N1, which is the first electrode of the first transistor T1. The first gate line GWL can be a scan write line. The second transistor T2 can be turned on in response to the first gate signal to apply a data voltage to the first node N1. The gate electrode of the second transistor T2 can be connected to the first gate line GWL, the first electrode of the second transistor T2 can be connected to the data line DL, and the second electrode of the second transistor T2 can be connected to the first node N1.

[0116] The third transistor T3 can be turned on by the second gate signal of the second gate line GCL, and the second node N2, which is the second electrode of the first transistor T1, can be electrically connected to the third node N3, which is the gate electrode of the first transistor T1. The gate electrode of the third transistor T3 can be connected to the second gate line GCL, the first electrode of the third transistor T3 can be connected to the second node N2, and the second electrode of the third transistor T3 can be connected to the third node N3.

[0117] The fourth transistor T4 can be turned on by the third gate signal of the third gate line GIL to electrically connect the third node N3, which serves as the gate electrode of the first transistor T1, to the first initialization voltage line VIL1. When the fourth transistor T4 is turned on based on the third gate signal, the gate electrode of the first transistor T1 can be initialized to the first initialization voltage. The gate electrode of the fourth transistor T4 can be connected to the third gate line GIL, the first electrode of the fourth transistor T4 can be connected to the third node N3, and the second electrode of the fourth transistor T4 can be connected to the first initialization voltage line VIL1.

[0118] The fifth transistor T5 can be turned on by the transmit signal of the transmit control line EML, and can electrically connect the power supply voltage line VDL to the first node N1, which is the first electrode of the first transistor T1. The gate electrode of the fifth transistor T5 can be connected to the transmit control line EML, the first electrode of the fifth transistor T5 can be connected to the power supply voltage line VDL, and the second electrode of the fifth transistor T5 can be connected to the first node N1.

[0119] The sixth transistor T6 can be turned on by the emission signal of the emission control line EML to electrically connect the second node N2, which is the second electrode of the first transistor T1, to the fourth node N4, which is the first electrode of the light-emitting element ED. The gate electrode of the sixth transistor T6 can be connected to the emission control line EML, the first electrode of the sixth transistor T6 can be connected to the second node N2, and the second electrode of the sixth transistor T6 can be connected to the fourth node N4.

[0120] The seventh transistor T7 can be turned on by the fourth gate signal of the fourth gate line GBL to electrically connect the second initialization voltage line VIL2 to the fourth node N4, which serves as the first electrode of the light-emitting element ED. When the seventh transistor T7 is turned on based on the fourth gate signal, the first electrode of the light-emitting element ED can be initialized to the second initialization voltage. The second initialization voltage of the second initialization voltage line VIL2 can be different from the first initialization voltage of the first initialization voltage line VIL1. In another example, the second initialization voltage can be equal to the first initialization voltage. The gate electrode of the seventh transistor T7 can be connected to the fourth gate line GBL, the first electrode of the seventh transistor T7 can be connected to the fourth node N4, and the second electrode of the seventh transistor T7 can be connected to the second initialization voltage line VIL2.

[0121] The eighth transistor T8 can be turned on by the fourth gate signal of the fourth gate line GBL to electrically connect the bias voltage line VBL to the first node N1, which is the first electrode of the first transistor T1. The gate electrode of the eighth transistor T8 can be connected to the fourth gate line GBL, the first electrode of the eighth transistor T8 can be connected to the bias voltage line VBL, and the second electrode of the eighth transistor T8 can be connected to the first node N1.

[0122] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may include oxide-based semiconductor regions. For example, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may have a coplanar structure in which the gate electrode is disposed above the oxide-based semiconductor region. Transistors with such coplanar structures have excellent leakage current characteristics and support low-frequency driving, thereby reducing power consumption. Therefore, the display device 10 includes the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 with good leakage current characteristics, so that the display device 10 can prevent leakage current from flowing within the pixel and stably maintain the voltage within the pixel.

[0123] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be n-type transistors. For example, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can output the current flowing into the first electrode to the second electrode based on a high gate voltage applied to the gate electrode.

[0124] In another example, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may include a silicon-based semiconductor region. For example, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may include a semiconductor region formed of low-temperature polycrystalline silicon (LTPS). The semiconductor region formed of LTPS can have high electron mobility and excellent conduction characteristics. At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be a p-type transistor. A p-type transistor can output current flowing into the first electrode to the second electrode based on a low gate voltage applied to the gate electrode.

[0125] Capacitor C1 can be connected between the third node N3, which serves as the gate electrode of the first transistor T1, and the power supply voltage line VDL. For example, the first capacitor electrode of capacitor C1 is connected to the third node N3, and the second capacitor electrode of capacitor C1 is connected to the power supply voltage line VDL, so that the potential difference between the power supply voltage line VDL and the gate electrode of the first transistor T1 can be maintained.

[0126] In another example, display device 10 may include... Figure 7 and Figure 8 The pixel circuits shown in the circuit diagram are different pixel circuits.

[0127] Figure 9 This is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0128] refer to Figure 9 The display panel 100 may include a substrate SUB, a metal layer BML, a buffer layer BF, a first active layer ACTL1, a first gate insulator GI1, a first gate layer GTL1, a second gate insulator GI2, a second gate layer GTL2, a first interlayer dielectric layer ILD1, a second active layer ACTL2, a third gate insulator GI3, a third gate layer GTL3, a second interlayer dielectric layer ILD2, a first source metal layer SDL1, a first via layer VIA1, a second source metal layer SDL2, a second via layer VIA2, a pixel electrode AE, and a pixel defining layer PDL.

[0129] The substrate SUB can be a base substrate or a base component. The substrate SUB can be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB can include, but is not limited to, polymer resins, such as, for example, polyimide (PI). In another example, the substrate SUB can include glass or metallic materials.

[0130] The metal layer BML can be disposed on the substrate SUB. The metal layer BML may include a first connection electrode CNE1. The first connection electrode CNE1 can electrically connect the second electrode SDE of the scan transistor STR to the second connection electrode CNE2.

[0131] The buffer layer BF can be disposed on the metal layer BML. For example, the buffer layer BF may include an inorganic membrane capable of preventing the penetration of air or moisture. For example, the buffer layer BF may include multiple inorganic membranes stacked alternately on top of each other.

[0132] The first active layer ACTL1 may be disposed on the buffer layer BF. The first active layer ACTL1 may include a silicon-based material. For example, the first active layer ACTL1 may be formed of low-temperature polycrystalline silicon (LTPS). The first active layer ACTL1 may include the semiconductor region SACT of the scan transistor STR, the first electrode SSE, and the second electrode SDE.

[0133] Scan transistors STR can be disposed in the display area DA to form a scan driver 800. Therefore, each of the first scan driver 801, the second scan driver 802, the third scan driver 803, and the fourth scan driver 804 may include multiple scan transistors STR disposed in the first active layer ACTL1 and the first gate layer GTL1. The scan transistors STR of the scan driver 800 may overlap with the transistors TR of the pixel SP in the Z-axis direction or the thickness direction.

[0134] A first gate insulator GI1 can be disposed on the first active layer ACTL1. The first gate insulator GI1 can insulate the first active layer ACTL1 from the first gate layer GTL1.

[0135] The first gate layer GTL1 may be disposed on the first gate insulator GI1. The first gate layer GTL1 may include the gate electrode SGE of the scan transistor STR.

[0136] The second gate insulator GI2 can be disposed on the first gate layer GTL1. The second gate insulator GI2 can insulate the first gate layer GTL1 from the second gate layer GTL2.

[0137] A second gate layer GTL2 may be disposed on a second gate insulator GI2. The second gate layer GTL2 may include a capacitor electrode CPE. The capacitor electrode CPE may overlap with the gate electrode SGE of the scan transistor STR to form a capacitor.

[0138] The first interlayer dielectric layer ILD1 can be disposed on the second gate layer GTL2. The first interlayer dielectric layer ILD1 can insulate the second gate layer GTL2 from the second active layer ACTL2.

[0139] The second active layer ACTL2 may be disposed on the first interlayer dielectric layer ILD1. The second active layer ACTL2 may include an oxide-based material. The second active layer ACTL2 may include the semiconductor region ACT of the transistor TR, the first electrode DE, and the second electrode SE.

[0140] Transistor TR can be disposed in the first display area DA1 and the second display area DA2 to form pixel SP. Transistor TR can be... Figure 7The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6, and Figure 8 One of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. The transistor TR of the pixel SP and the scan transistor STR of the scan driver 800 can overlap each other in the Z-axis direction or the thickness direction.

[0141] The third gate insulator GI3 can be disposed on the second active layer ACTL2. The third gate insulator GI3 can insulate the second active layer ACTL2 from the third gate layer GTL3.

[0142] The third gate layer GTL3 can be disposed on the third gate insulator GI3. The third gate layer GTL3 may include the gate electrode GE of the transistor TR and the scan line SL. The scan line SL can provide the scan signal received from the scan driver 800 to the gate electrode GE of the transistor TR.

[0143] The second interlayer dielectric layer ILD2 can be disposed on the third gate layer GTL3. The second interlayer dielectric layer ILD2 can insulate the third gate layer GTL3 from the first source metal layer SDL1.

[0144] A first source metal layer SDL1 can be disposed on a second interlayer dielectric layer ILD2. The first source metal layer SDL1 may include a first anode connection electrode ANE1 and a second connection electrode CNE2. The first anode connection electrode ANE1 can electrically connect the transistor TR of pixel SP to the pixel electrode AE. The second connection electrode CNE2 can electrically connect the scan transistor STR of scan driver 800 to the scan line SL. The second connection electrode CNE2 can correspond to... Figure 3 and Figure 5 The first connecting line CNL1, the second connecting line CNL2, the third connecting line CNL3, and the fourth connecting line CNL4.

[0145] The first via layer VIA1 can be disposed on the first source metal layer SDL1. The first via layer VIA1 can insulate the first source metal layer SDL1 from the second source metal layer SDL2.

[0146] A second source metal layer SDL2 can be disposed on the first via layer VIA1. The second source metal layer SDL2 may include a second anode connection electrode ANE2. The first anode connection electrode ANE1 and the second anode connection electrode ANE2 can electrically connect the pixel electrode AE ​​to the transistor TR.

[0147] The second via layer VIA2 can be disposed on the second source metal layer SDL2. The second via layer VIA2 can insulate the second source metal layer SDL2 from the pixel electrode AE.

[0148] The pixel electrode AE ​​can be disposed on the second via layer VIA2. The pixel electrode AE ​​can be exposed through the emitter region EA. The pixel electrode AE ​​can be... Figure 7 or Figure 8 The first electrode of the light-emitting element ED.

[0149] A pixel-defining layer (PDL) can be disposed on the second via layer (VIA2). The PDL can define multiple emission regions (EA). The PDL can include an organic insulating material, such as, for example, polyimide (PI).

[0150] Figure 10 This is a cross-sectional view showing a display device according to another embodiment of the present disclosure.

[0151] refer to Figure 10 The display panel 100 may include a substrate SUB, a metal layer BML, a buffer layer BF, a first active layer ACTL1, a first gate insulator GI1, a first gate layer GTL1, a second gate insulator GI2, a second gate layer GTL2, a first interlayer dielectric layer ILD1, a second active layer ACTL2, a third gate insulator GI3, a third gate layer GTL3, a second interlayer dielectric layer ILD2, a first source metal layer SDL1, a first via layer VIA1, a second source metal layer SDL2, a second via layer VIA2, a pixel electrode AE, and a pixel defining layer PDL.

[0152] The substrate SUB can be a base substrate or a base component. The substrate SUB can be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB can include, but is not limited to, polymer resins, such as, for example, polyimide (PI). In another example, the substrate SUB can include glass or metallic materials.

[0153] The metal layer BML can be disposed on the substrate SUB. The metal layer BML may include a second connection electrode CNE2. The second connection electrode CNE2 can be connected to the first electrode DE of the transistor TR.

[0154] The buffer layer BF can be disposed on the metal layer BML. For example, the buffer layer BF may include an inorganic membrane capable of preventing the penetration of air or moisture. For example, the buffer layer BF may include multiple inorganic membranes stacked alternately on top of each other.

[0155] The first active layer ACTL1 can be disposed on the buffer layer BF. The first active layer ACTL1 can include a silicon-based material. For example, the first active layer ACTL1 can be formed of low-temperature polycrystalline silicon (LTPS). The first active layer ACTL1 can include the semiconductor region ACT of the transistor TR, the first electrode DE, and the second electrode SE.

[0156] Transistor TR can be disposed in the first display area DA1 and the second display area DA2 to form pixel SP. Transistor TR can be... Figure 7 The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6, and Figure 8 One of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. The transistor TR of the pixel SP and the scan transistor STR of the scan driver 800 can overlap each other in the Z-axis direction or the thickness direction.

[0157] A first gate insulator GI1 can be disposed on the first active layer ACTL1. The first gate insulator GI1 can insulate the first active layer ACTL1 from the first gate layer GTL1.

[0158] A first gate layer GTL1 may be disposed on a first gate insulator GI1. The first gate layer GTL1 may include the gate electrode GE of the transistor TR and a scan line SL. The scan line SL may provide a scan signal received from the scan driver 800 to the gate electrode GE of the transistor TR.

[0159] The second gate insulator GI2 can be disposed on the first gate layer GTL1. The second gate insulator GI2 can insulate the first gate layer GTL1 from the second gate layer GTL2.

[0160] A second gate layer GTL2 may be disposed on a second gate insulator GI2. The second gate layer GTL2 may include a capacitor electrode CPE. The capacitor electrode CPE may overlap with the gate electrode GE of the transistor TR to form a capacitor.

[0161] The first interlayer dielectric layer ILD1 can be disposed on the second gate layer GTL2. The first interlayer dielectric layer ILD1 can insulate the second gate layer GTL2 from the second active layer ACTL2.

[0162] The second active layer ACTL2 may be disposed on the first interlayer dielectric layer ILD1. The second active layer ACTL2 may include an oxide-based material. The second active layer ACTL2 may include the semiconductor region SACT of the scanning transistor STR, the first electrode SSE, and the second electrode SDE.

[0163] Scan transistors STR can be disposed in the display area DA to form a scan driver 800. Therefore, each of the first scan driver 801, the second scan driver 802, the third scan driver 803, and the fourth scan driver 804 may include multiple scan transistors STR disposed in the second active layer ACTL2 and the third gate layer GTL3. The scan transistors STR of the scan driver 800 may overlap with the transistors TR of the pixel SP in the Z-axis direction or the thickness direction.

[0164] The third gate insulator GI3 can be disposed on the second active layer ACTL2. The third gate insulator GI3 can insulate the second active layer ACTL2 from the third gate layer GTL3.

[0165] The third gate layer GTL3 can be disposed on the third gate insulator GI3. The third gate layer GTL3 may include the gate electrode SGE of the scan transistor STR.

[0166] The second interlayer dielectric layer ILD2 can be disposed on the third gate layer GTL3. The second interlayer dielectric layer ILD2 can insulate the third gate layer GTL3 from the first source metal layer SDL1.

[0167] A first source metal layer SDL1 can be disposed on a second interlayer dielectric layer ILD2. The first source metal layer SDL1 may include a first anode connection electrode ANE1 and a first connection electrode CNE1. The first anode connection electrode ANE1 can electrically connect the scan transistor STR of the scan driver 800 to the pixel electrode AE. The first connection electrode CNE1 can electrically connect the scan transistor STR of the scan driver 800 to the scan line SL. The first connection electrode CNE1 can correspond to... Figure 3 and Figure 5 The first connecting line CNL1, the second connecting line CNL2, the third connecting line CNL3, and the fourth connecting line CNL4.

[0168] The first via layer VIA1 can be disposed on the first source metal layer SDL1. The first via layer VIA1 can insulate the first source metal layer SDL1 from the second source metal layer SDL2.

[0169] A second source metal layer SDL2 can be disposed on the first via layer VIA1. The second source metal layer SDL2 may include a second anode connection electrode ANE2. The first anode connection electrode ANE1 and the second anode connection electrode ANE2 can electrically connect the pixel electrode AE ​​to the scanning transistor STR.

[0170] The second via layer VIA2 can be disposed on the second source metal layer SDL2. The second via layer VIA2 can insulate the second source metal layer SDL2 from the pixel electrode AE.

[0171] The pixel electrode AE ​​can be disposed on the second via layer VIA2. The pixel electrode AE ​​can be exposed through the emitter region EA. The pixel electrode AE ​​can be... Figure 7 or Figure 8 The first electrode of the light-emitting element ED.

[0172] A pixel-defining layer (PDL) can be disposed on the second via layer (VIA2). The PDL can define multiple emission regions (EA). The PDL can include an organic insulating material, such as, for example, polyimide (PI).

[0173] The display device according to embodiments of the present disclosure can be applied to various electronic devices. The electronic device according to embodiments of the present disclosure includes the aforementioned display device, and may further include modules or devices with additional functions in addition to the display device. The electronic device according to embodiments of the present disclosure may include a display module, a processor, a memory, and a power module.

[0174] The processor may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0175] The memory can store data required for the operation of the processor or display module. When the processor executes an application stored in the memory, image data signals and / or input control signals are transmitted to the display module, and the display module can process the received signals and output image information through the display screen.

[0176] Power modules may include power modules such as power adapters or batteries, as well as power conversion modules that convert the power supplied by the power modules to generate the power required for the operation of electronic devices.

[0177] At least one of the components of an electronic device according to embodiments of the present disclosure may be included in a display device 10 according to embodiments of the present disclosure. Furthermore, some modules that are functionally included in a single module may be included in the display device 10, and other modules may be provided separately from the display device 10. For example, the display device 10 may include a display module, and the processor, memory, and power module may be provided as other devices within the electronic device besides the display device 10.

[0178] The various electronic devices to which the display device 10 according to embodiments of the present disclosure is applied may include not only image display electronic devices such as smartphones, tablet PCs (personal computers), laptops, TVs and desktop monitors, but also wearable electronic devices including display modules such as smart glasses, head-mounted displays and smartwatches, as well as vehicle electronic devices including display modules such as CID (center information display) and interior mirror displays arranged on the dashboard, the central instrument panel of a car, and the dashboard.

[0179] The aspects of this disclosure should not be construed as limited to the embodiments set forth herein. Rather, exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art the concepts supported by the aspects of this disclosure.

[0180] While exemplary aspects of this disclosure have been specifically shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit or scope of the exemplary embodiments described herein as defined by the appended claims.

Claims

1. A display device, comprising: The first display area includes: Pixel circuits; and Scan lines are configured to provide scan signals to the pixel circuitry of the first display area; The second display area is located to one side of the first display area and includes: Pixel circuits; and Scan lines are configured to provide scan signals to the pixel circuitry of the second display area; A first scan driver is located at a first side edge of the first display area, wherein the first scan driver overlaps with the pixel circuit of the first display area and is electrically connected to the first side of the scan line of the first display area; The second scan driver is located at the second side edge of the first display area opposite to the first side edge of the first display area, wherein the second scan driver overlaps with the pixel circuit of the first display area and is electrically connected to the second side of the scan line of the first display area opposite to the first side of the scan line of the first display area; A third scan driver is located at the first side edge of the second display area, wherein the third scan driver overlaps with the pixel circuitry of the second display area and is electrically connected to the first side of the scan line of the second display area; and A fourth scan driver is located at the second side edge of the second display area opposite to the first side edge of the second display area, wherein the fourth scan driver overlaps with the pixel circuit of the second display area and is electrically connected to the second side of the scan line of the second display area opposite to the first side of the scan line of the second display area.

2. The display device according to claim 1, further comprising: A first connecting line electrically connects the first scan driver and the first side of the scan line of the first display area; The second connecting line electrically connects the second scan driver and the second side of the scan line of the first display area; The third connecting line electrically connects the third scan driver and the first side of the scan line of the second display area; as well as The fourth connection line electrically connects the fourth scan driver and the second side of the scan line of the second display area.

3. The display device according to claim 2, wherein: The second connecting line and the third connecting line are disposed between the pixel circuit of the first display area and the pixel circuit of the second display area, and The second connecting line and the third connecting line do not overlap with the pixel circuit of the first display area and the pixel circuit of the second display area.

4. The display device according to claim 2, wherein: The first connecting line is closer to the first side edge of the first display area than the first scan driver. The second connecting line is closer to the second side edge of the first display area than the second scan driver. The third connecting line is closer to the first side edge of the second display area than the third scan driver, and The fourth connecting line is closer to the second side edge of the second display area than the fourth scan driver.

5. The display device according to claim 2, further comprising: A dividing line is set between the first display area and the second display area, and separates the first display area and the second display area from each other. The pixel circuits in the first display area and the second display area are spaced apart from each other, and the dividing line is between the pixel circuits in the first display area and the pixel circuits in the second display area.

6. The display device according to claim 5, wherein: The second connecting line is disposed between the dividing line and the pixel circuit of the first display area and does not overlap with the pixel circuit of the first display area. The third connecting line is disposed between the dividing line and the pixel circuit of the second display area and does not overlap with the pixel circuit of the second display area.

7. The display device according to claim 1, wherein: Each of the first to fourth scan drivers includes a scan transistor disposed in a first active layer comprising a first material, and The pixel circuits of the first display area and the second display area each include transistors disposed in a second active layer comprising a second material different from the first material.

8. The display device according to claim 7, further comprising: The first active layer includes the semiconductor region of the scan transistor of at least one of the scan drivers from the first scan driver to the fourth scan driver; A first gate layer is disposed on the first active layer and includes the gate electrode of the scan transistor of at least one scan driver from the first scan driver to the fourth scan driver; A second gate layer is disposed on the first gate layer; The second active layer is disposed on the second gate layer and includes the semiconductor region of the transistor of at least one pixel circuit in the pixel circuit of the first display area and the pixel circuit of the second display area; as well as A third gate layer is disposed on the second active layer and includes: The gate electrode of the transistor in at least one pixel circuit of the pixel circuit in the first display area and the pixel circuit in the second display area; as well as The scan lines of the first display area and the scan lines of the second display area are configured to provide corresponding scan signals to the gate electrode.

9. The display device according to claim 8, further comprising: A first source metal layer is disposed on the third gate layer, wherein the first source metal layer includes a connection electrode that electrically connects the scan transistor of at least one of the scan drivers from the first scan driver to the fourth scan driver to the scan line included in the third gate layer.

10. The display device according to claim 1, further comprising: The first active layer includes the semiconductor region of the transistor of the pixel circuit of the first display area or the pixel circuit of the second display area; A first gate layer is disposed on the first active layer and includes: The gate electrode of the transistor; and The scan lines in the first display area or the scan lines in the second display area; A second gate layer is disposed on the first gate layer; A second active layer is disposed on the second gate layer and includes the semiconductor region of the scan transistor of each of the first scan driver to the fourth scan driver; and A third gate layer is disposed on the second active layer and includes the gate electrode of the scan transistor of each of the first scan driver to the fourth scan driver.

11. The display device according to claim 10, further comprising: A first source metal layer is disposed on the third gate layer, wherein the first source metal layer includes a connection electrode that electrically connects the scan transistor of each of the first scan driver to the fourth scan driver to the scan line of the first display area or the scan line of the second display area.

12. The display device according to claim 1, wherein, The pixel circuit of the first display area and the pixel circuit of the second display area each include: The first transistor is configured to provide drive current to the light-emitting element; The second transistor is configured to provide a data voltage to the gate electrode of the first transistor; A third transistor is configured to provide a reference voltage to the gate electrode of the first transistor; A fourth transistor is configured to provide an initialization voltage to the first electrode of the light-emitting element; A fifth transistor is configured to provide a drive voltage to the first electrode of the first transistor; and A sixth transistor is configured to electrically connect the second electrode of the first transistor to the first electrode of the light-emitting element.

13. The display device according to claim 1, wherein, The pixel circuit of the first display area and the pixel circuit of the second display area each include: The first transistor is configured to provide drive current to the light-emitting element; The second transistor is configured to provide a data voltage to the first electrode of the first transistor; The third transistor is configured to electrically connect the second electrode of the first transistor and the gate electrode of the first transistor; A fourth transistor is configured to provide a first initialization voltage to the gate electrode of the first transistor; A fifth transistor is configured to provide a drive voltage to the first electrode of the first transistor; A sixth transistor is configured to electrically connect the second electrode of the first transistor and the first electrode of the light-emitting element; and A seventh transistor is configured to provide a second initialization voltage to the first electrode of the light-emitting element.

14. A display device, comprising: The display area includes: Pixel circuit, A first scan line extends in a first direction and is configured to provide a scan signal to the pixel circuit. A second scan line extends in the first direction and is configured to provide the scan signal to the pixel circuit. The dividing line extends in a second direction intersecting the first direction and passes through the center of the display area; A first display area is located in the display area, on the first side of the dividing line, and includes the first scan line; A second display area is located in the display area on the second side of the dividing line opposite to the first side of the dividing line, and includes the second scan line; A first scan driver is located at a first side edge of the display area and is electrically connected to a first side of the first scan line in the first display area; The second scan driver is located on the first side of the dividing line and is electrically connected to the second side of the first scan line in the first display area, which is opposite to the first side of the first scan line in the first display area. A third scan driver is located on the second side of the dividing line opposite to the first side of the dividing line, and is electrically connected to the first side of the second scan line in the second display area; and A fourth scan driver is located at the second side edge of the display area opposite to the first side edge of the display area, and is electrically connected to the second side of the second scan line in the second display area opposite to the first side of the second scan line in the second display area.

15. The display device according to claim 14, wherein: The first scan driver and the second scan driver overlap with the pixel circuit of the first display area in the pixel circuit, and The third scan driver and the fourth scan driver overlap with the pixel circuit of the second display area in the pixel circuit.

16. The display device according to claim 14, further comprising: The first connecting line electrically connects the first scan driver and the first side of the first scan line of the first display area; The second connecting line electrically connects the second scan driver to the second side of the first scan line of the first display area; The third connecting line electrically connects the third scan driver and the first side of the second scan line of the second display area; as well as The fourth connection line electrically connects the fourth scan driver and the second side of the second scan line of the second display area.

17. The display device according to claim 16, wherein: The second connecting line and the third connecting line are disposed between the pixel circuit of the first display area and the pixel circuit of the second display area in the pixel circuit, and The second connecting line and the third connecting line do not overlap with the pixel circuit of the first display area and the pixel circuit of the second display area.

18. The display device according to claim 16, wherein: The first connecting line is closer to the first side edge of the display area than the first scan driver. The second connection line is closer to the boundary line than the second scan driver. The third connection line is closer to the dividing line than the third scan driver, and The fourth connection line is closer to the second side edge of the display area than the fourth scan driver.

19. The display device according to claim 14, wherein: Each of the first to fourth scan drivers includes a scan transistor disposed in a first active layer comprising a silicon-based material, and Each pixel circuit includes a transistor disposed in a second active layer comprising an oxide-based material.

20. An electronic device, comprising: The display module is configured to display images. as well as The processor is configured to transmit image data signals to the display module, and The display module includes: The first display area includes: Pixel circuits; and Scan lines are configured to provide scan signals to the pixel circuitry of the first display area; The second display area is located to one side of the first display area and includes: Pixel circuits; and Scan lines are configured to provide scan signals to the pixel circuitry of the second display area; A first scan driver is located at a first side edge of the first display area, wherein the first scan driver overlaps with the pixel circuit of the first display area and is electrically connected to the first side of the scan line of the first display area; The second scan driver is located at the second side edge of the first display area opposite to the first side edge of the first display area, wherein the second scan driver overlaps with the pixel circuit of the first display area and is electrically connected to the second side of the scan line of the first display area opposite to the first side of the scan line of the first display area; A third scan driver is located at the first side edge of the second display area, wherein the third scan driver overlaps with the pixel circuitry of the second display area and is electrically connected to the first side of the scan line of the second display area; and A fourth scan driver is located at the second side edge of the second display area opposite to the first side edge of the second display area, wherein the fourth scan driver overlaps with the pixel circuit of the second display area and is electrically connected to the second side of the scan line of the second display area opposite to the first side of the scan line of the second display area.

Images