Back contact battery and its preparation method, photovoltaic module

Abstract

This application relates to the field of solar cell technology, specifically to a back-contact cell and its fabrication method, and a photovoltaic module, which can simplify the fabrication process. The back-contact cell includes: a semiconductor substrate, including a first surface and a second surface, the first surface including a first region, a second region and a third region, a doped crystalline silicon region formed on the surface of the first region, the third region located between the first region and the second region, the conductivity type of the doped crystalline silicon region being opposite to the conductivity type of the semiconductor substrate; a first unit structure disposed in the first region, including a first passivation structure disposed on the doped crystalline silicon region, the first passivation structure also covering the third region; a second unit structure disposed in the second region, the second unit structure including an amorphous silicon layer, a doped amorphous silicon layer and a conductive film disposed sequentially, the conductivity type of the doped amorphous silicon layer being the same as the conductivity type of the semiconductor substrate; a first electrode in electrical contact with the doped crystalline silicon region; and a second electrode in electrical contact with the doped amorphous silicon layer.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and in particular to a back contact cell and its preparation method, and a photovoltaic module. Background Technology

[0002] Photovoltaic power generation is a system that directly converts sunlight into electrical energy using solar cells based on the photovoltaic effect. The basic structure of a solar cell is a large-area planar PN junction. When sunlight shines on the PN junction, the junction absorbs the light energy and excites electrons and holes, subsequently generating a voltage in the PN junction, thus achieving photoelectric conversion. Therefore, the core structure for converting sunlight into electrical energy in crystalline silicon cells is the PN junction.

[0003] In photovoltaic power generation, HBC (Hybrid Back Contact) is a photovoltaic cell technology that combines IBC (Integrated Circuit) and HJT (Heterojunction). In the back-side design, the N-region and P-region are arranged in an interdigitated pattern, with a gap between them. The design of the back-side passivation structure is related to the power generation of the photovoltaic cell. Summary of the Invention

[0004] The applicant discovered that existing HBC battery back panel designs typically use intrinsic amorphous silicon + boron-doped amorphous silicon for passivation in the P-region, intrinsic amorphous silicon + phosphorus-doped amorphous silicon for passivation in the N-region, and aluminum oxide + silicon nitride for passivation in the Gap region. Different passivation layers are used for the P-region, Gap, and N-region, resulting in a complex manufacturing process. Furthermore, the intrinsic amorphous silicon passivation structures in the P-region and N-region have weak UV resistance and are more susceptible to UV damage during daily use, thus reducing power generation.

[0005] Based on this, it is necessary to propose a back contact cell that facilitates a simple passivation process, a method for preparing the back contact cell, and a photovoltaic module.

[0006] A first aspect of this application provides a back-contact battery, comprising: a semiconductor substrate including a first surface and a second surface disposed opposite to each other, the first surface including a first region, a second region, and a third region, a doped crystalline silicon region formed on the surface of the first region, the third region being located between the first region and the second region, the conductivity type of the doped crystalline silicon region being opposite to the conductivity type of the semiconductor substrate; a first unit structure disposed in the first region along a direction away from the first surface, the first unit structure including a first passivation structure disposed on the doped crystalline silicon region, and the first passivation structure further covering the third region; a second unit structure disposed in the second region along a direction away from the first surface, the second unit structure including an amorphous silicon layer, a doped amorphous silicon layer, and a conductive film disposed sequentially, the conductivity type of the doped amorphous silicon layer being the same as the conductivity type of the semiconductor substrate; a first electrode electrically contacting the doped crystalline silicon region; and a second electrode electrically contacting the doped amorphous silicon layer.

[0007] In some embodiments, the first passivation structure located in the third region along a direction parallel to the first surface is divided into a first part and a second part, wherein the second part is covered by the second unit structure.

[0008] In some embodiments, the width of the second portion is 10-50 μm along a direction parallel to the first surface.

[0009] In some embodiments, the thickness of the amorphous silicon layer is 2-20 nm, the thickness of the doped amorphous silicon layer is 10-50 nm, and the thickness of the conductive film is 30-150 nm.

[0010] In some embodiments, the first passivation structure includes an aluminum oxide layer and a silicon-based thin film layer sequentially disposed in the doped crystalline silicon region.

[0011] In some embodiments, the second surface is provided with a second passivation structure.

[0012] In some embodiments, the second passivation structure includes an aluminum oxide layer and a silicon-based thin film layer sequentially disposed on the second surface.

[0013] In some embodiments, the silicon-based thin film layer is one or a combination of silicon nitride, silicon oxide, silicon oxynitride, etc.

[0014] In some embodiments, the thickness of the alumina layer is 1-20 nm.

[0015] In some embodiments, both the first and second surfaces are provided with a velvety texture.

[0016] A second aspect of this application provides a method for fabricating a back-contact battery, the method comprising: providing a semiconductor substrate, the semiconductor substrate including a first surface and a second surface disposed opposite to each other, the first surface including a first region, a second region, and a third region, the third region being located between the first region and the second region; forming a doped silicon region on the first surface, the conductivity type of the doped silicon region being opposite to that of the semiconductor substrate; removing the doped silicon regions from the second region and the third region; forming an aluminum oxide thin film on the first surface and the second surface respectively; and performing an alumina thin film on the first surface and the second surface. A silicon-based thin film layer is formed on an aluminum thin film; the aluminum oxide thin film and the silicon-based thin film layer in the second region are removed; an amorphous silicon layer, a doped amorphous silicon layer, and a conductive film are sequentially coated on the first surface, wherein the conductivity type of the doped amorphous silicon layer is the same as that of the semiconductor substrate; the conductive film, the amorphous silicon layer, and the doped amorphous silicon layer in the first region are removed, and the conductive film, the amorphous silicon layer, and the doped amorphous silicon layer in the first part of the third region are removed, leaving a second part of the conductive film, the amorphous silicon layer, and the doped amorphous silicon layer, wherein the first part is close to the first region; a first electrode in contact with the doped crystalline silicon region and a second electrode in contact with the doped amorphous silicon layer are formed.

[0017] In some embodiments, the first and second electrodes are formed using a screen printing process; and the first and / or second electrodes are assisted in sintering using laser-assisted sintering technology.

[0018] A third aspect of this application provides a photovoltaic module including the aforementioned back contact battery.

[0019] In this application, the first passivation structure simultaneously covers both the first and third regions. This allows the passivation films on the first and third regions to be formed simultaneously, thus simplifying the process. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of a back contact battery according to an embodiment of this application.

[0021] Figure 2 This is a schematic flowchart of a method for preparing a back contact battery according to an embodiment of this application.

[0022] Figure 3 This is a schematic diagram of the structure after preparation method S100 of this application.

[0023] Figure 4 This is a schematic diagram of the structure after preparation method S200 of this application.

[0024] Figure 5 This is a schematic diagram of the structure after preparation method S300 of this application.

[0025] Figure 6 A schematic diagram of the structure after preparation method S500 of this application.

[0026] Figure 7 This is a schematic diagram of the structure after preparation method S600 of this application.

[0027] Figure 8 This is a schematic diagram of the structure after preparation method S700 of this application.

[0028] Figure 9 This is a schematic diagram of the structure after preparation method S800 of this application.

[0029] Figure 10 This is a schematic diagram of the structure of the photovoltaic module of this application.

[0030] Figure label:

[0031] 100. Photovoltaic module; 1. Back contact cell; 10. Semiconductor substrate; 110. First surface; S1. First region; S2. Second region; S3. Third region; S31. First part; S32. Second part; 112. Doped crystalline silicon region; 114. Textured surface; 120. Second surface; 20. First passivation structure; 30. Second unit structure; 310. Amorphous silicon layer; 320. Doped amorphous silicon layer; 330. Conductive film; 40. First electrode; 50. Second electrode; 610. Alumina layer; 620. Silicon-based thin film layer; 70. Second passivation structure; 2. First encapsulant film; 3. Second encapsulant film; 4. Front panel; 5. Back panel. Detailed Implementation

[0032] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0034] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0035] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0036] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0037] In this application, when numerical intervals (i.e., numerical ranges) are involved, unless otherwise specified, the distribution of selectable numerical values ​​within the numerical interval is considered continuous, and includes the two endpoints of the numerical interval (i.e., the minimum and maximum values), as well as every numerical value between these two endpoints. Unless otherwise specified, when a numerical interval refers only to integers within that numerical interval, it includes the two endpoint integers of the numerical range, as well as every integer between the two endpoints, which is equivalent to directly listing every integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical ranges disclosed in this application should be understood to include any and all subranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, percentage, ratio, etc. The term "numerical interval" can be broadly included to include percentage intervals, ratio intervals, proportion intervals, etc.

[0038] Unless the context otherwise indicates, the materials described herein can be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique used for depositing or growing the material can be selected by one of ordinary skill in the art.

[0039] Additionally, unless the context otherwise indicates, the material removal described herein can be achieved by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, abrasive planarization (e.g., chemical mechanical planarization (CMP)) or other known methods.

[0040] As used herein, the term "semiconductor" can refer to, for example, a material layer, substrate, wafer, or substructure, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon sapphire (SOS) technology, silicon-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a substrate semiconductor structure, and other semiconductor structures well known to those skilled in the art.

[0041] Firstly, reference Figure 1 This application provides a back contact battery 1, which includes a semiconductor substrate 10, a first unit structure, a second unit structure 30, a first electrode 40, and a second electrode 50.

[0042] The semiconductor substrate 10 includes a first surface 110 and a second surface 120 disposed opposite to each other. The first surface 110 includes a first region S1, a second region S2, and a third region S3. A doped silicon region 112 is formed within the surface of the first region S1. The third region S3 is located between the first region S1 and the second region S2. The conductivity type of the doped silicon region 112 is opposite to that of the semiconductor substrate 10. A first unit structure is disposed in the first region S1. Along the direction away from the first surface 110, the first unit structure includes a first passivation structure 20 disposed on the doped silicon region 112, and the first passivation structure 20 also covers the third region S3. A second unit structure 30 is disposed in the second region S2. Along the direction away from the first surface 110, the second unit structure 30 includes an amorphous silicon layer 310, a doped amorphous silicon layer 320, and a conductive film 330 disposed sequentially. The conductivity type of the doped amorphous silicon layer 320 is the same as that of the semiconductor substrate 10. A first electrode 40 is in electrical contact with the doped silicon region 112. The second electrode 50 is in electrical contact with the doped amorphous silicon layer 320.

[0043] In this application, the direction away from the first surface 110 is the Z- direction, and the direction away from the second surface 120 is the Z+ direction. The directions parallel to the first surface 110 and parallel to the second surface 120 are both the X direction in the figure.

[0044] The semiconductor substrate 10 is used to receive incident light and generate photogenerated carriers. The semiconductor substrate 10 can be, for example, silicon, germanium, germanium-silicon, or silicon on an insulator, and various doped silicon materials, including, but not limited to, boron-doped, phosphorus-doped, gallium-doped, antimony-doped, or mixed-doped silicon. The first surface 110 is specifically the back side of the semiconductor substrate 10. The back side is the side of the back-contact battery 1 that faces away from the sun when it is operating.

[0045] The doped silicon region 112 is formed by adding a dopant to the semiconductor substrate 10, and it is formed in the first region S1 of the first surface 110. The conductivity type of the doped silicon region 112 is opposite to that of the semiconductor substrate 10. For example, the semiconductor substrate 10 is N-type, and the doped silicon region 112 is a P-type doped silicon region, with the doping element being a P-type dopant such as boron. The doped silicon region 112 forms a P-region in the first region S1. Accordingly, the semiconductor substrate 10 can be P-type.

[0046] The first unit structure includes a first passivation structure 20. In addition to covering the first region S1, the first passivation structure 20 also covers the third region S3. The first passivation structure 20 ensures that the surface of the semiconductor substrate 10 has a good passivation effect in the first region S1 and the third region S3. The first passivation structure 20 includes, for example, an aluminum oxide layer 610 and a silicon nitride layer.

[0047] The second unit structure 30 is located in the second region S2. In the second unit structure 30, the conductivity type of the doped amorphous silicon layer 320 is the same as that of the semiconductor substrate 10. For example, if the semiconductor substrate 10 is an N-type semiconductor, the doped amorphous silicon layer 320 is an N-type doped amorphous silicon layer 320. The second unit structure 30 forms an N+ region in the second region S2. Specifically, the doping material for the doped amorphous silicon layer 320 can be, for example, phosphorus, arsenic, antimony, bismuth, etc. The amorphous silicon layer 310 and the doped amorphous silicon layer 320 together form a passivation structure, ensuring that the surface of the semiconductor substrate 10 has a good passivation effect in the second region S2.

[0048] It should be noted that the amorphous silicon layer 310 in the second unit structure 30 is either an intrinsic amorphous silicon layer 310 or a lightly doped amorphous silicon layer 320. Specifically, when preparing the doped amorphous silicon layer 320, a lower concentration of the same dopant material as in the intrinsic amorphous silicon layer 320 may be incorporated into the intrinsic amorphous silicon layer 310. In this case, the intrinsic amorphous silicon layer 310 is not strictly intrinsic amorphous silicon, but rather a lightly doped amorphous silicon layer 320, which can also be called a near-intrinsic amorphous silicon layer 310. For example, the amorphous silicon layer 310 is hydrogenated intrinsic amorphous silicon. The doped amorphous silicon layer 320 is hydrogenated doped amorphous silicon.

[0049] The conductive film 330 can enhance carrier collection. The material of the conductive film 330 can refer to the corresponding types in the prior art. For example, the material of the conductive film 330 can be an indium oxide-based thin film doped with at least one of tin, zinc, tungsten, or titanium.

[0050] The third region S3 serves to isolate the first unit and the second unit structure 30. For example, in this embodiment, the doped crystalline silicon region 112 forms a P region in the first region S1, and the doped crystalline silicon region 112 forms a PN junction with the semiconductor substrate 10; the second unit structure 30 forms an N+ region in the second region S2, and the doped amorphous silicon layer 320 is an N+ layer; the third region S3 isolates the P region and the N+ region.

[0051] In this application, the first passivation structure 20 simultaneously covers both the first region S1 and the third region S3. This allows the passivation films on the first region S1 and the third region S3 to be formed simultaneously, thus simplifying the process.

[0052] In some embodiments, along a direction parallel to the first surface 110, the first passivation structure 20 located in the third region S3 is divided into a first part S31 and a second part S32, wherein the second part S32 is covered by the second unit structure 30.

[0053] As shown in the figure, the amorphous silicon layer 310, the doped amorphous silicon layer 320, and the conductive film 330 in the second unit structure 30 also extend to the second part S32 covering the first passivation structure 20.

[0054] Furthermore, along a direction parallel to the first surface 110, the width of the second portion S32 is 10-50 μm.

[0055] In this application, the second unit structure 30 also covers the second portion S32 of the first passivation structure 20. This reduces process requirements and avoids exposing the semiconductor substrate 10 during the fabrication of the second unit structure 30. Specifically, the second unit structure 30 covers the second portion S32 of the first passivation structure 20, meaning the first passivation structure 20 and the second unit structure 30 overlap. Therefore, during the fabrication of the first passivation structure 20 and the second unit structure 30, it is not necessary to strictly control the dimensions of the first passivation structure 20 and the second unit structure 30 in the X direction to ensure a perfect connection, thus reducing process requirements. Correspondingly, it also avoids gaps between the first passivation structure 20 and the second unit structure 30 due to insufficient process precision, thereby preventing the first surface 110 of the semiconductor substrate 10 from being exposed.

[0056] The width of the second part S32 is 10-50 μm, which ensures that the first passivation structure 20 and the second unit structure 30 can overlap while minimizing the occlusion of the first passivation structure 20. For example, the width of the second part S32 is 10-20 μm, 10-30 μm, or 15-50 μm. Optionally, the width of the second part S32 is 10 μm, 15 μm, 25 μm, 36 μm, 45 μm, or 50 μm.

[0057] In some embodiments, the thickness of the amorphous silicon layer 310 is 2-20 nm, the thickness of the doped amorphous silicon layer 320 is 10-50 nm, and the thickness of the conductive film 330 is 30-150 nm. For example, the thickness of the amorphous silicon layer 310 is 2-5 nm, 2-10 nm, 5-15 nm, or 8-20 nm. The thickness of the doped amorphous silicon layer 320 is 10-19 nm, 15-35 nm, 10-40 nm, or 25-50 nm. The thickness of the conductive film 330 is 30-500 nm, 30-80 nm, 50-120 nm, or 50-150 nm.

[0058] Optionally, the thickness of the amorphous silicon layer 310 is 2nm, 5nm, 10nm, 16nm, or 20nm. Optionally, the thickness of the doped amorphous silicon layer 320 is 10nm, 15nm, 30nm, 42nm, or 50nm. Optionally, the thickness of the conductive film 330 is 30nm, 70nm, 100nm, 120nm, or 150nm.

[0059] In some embodiments, the first passivation structure 20 includes an aluminum oxide layer 610 and a silicon-based thin film layer 620 sequentially disposed on the doped silicon region 112. The silicon-based thin film layer 620 may be one or a combination of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiONx), etc. For example, the silicon-based thin film layer 620 is a silicon nitride layer.

[0060] In this application, the first passivation structure 20 is a composite passivation method using an aluminum oxide layer 610 and a silicon-based thin film layer 620, which can improve its durability in strong UV irradiation scenarios and reduce performance degradation during use.

[0061] In addition, compared with traditional TBC cells, the passivation structure of the P region greatly reduces the parasitic absorption effect of light due to the absence of a doped polycrystalline silicon layer.

[0062] In some embodiments, reference is made to Figure 1 A second passivation structure 70 is provided on the second surface 120. The second passivation structure 70 enables the second surface 120 of the semiconductor substrate 10 to have a better passivation effect, which can reduce the recombination rate of the silicon cell surface, reduce the recombination loss of charge carriers on the surface, and thus improve the photoelectric conversion efficiency of the cell.

[0063] Optionally, the second passivation structure 70 includes an aluminum oxide layer 610 and a silicon-based thin film layer 620 sequentially disposed on the second surface 120. Similar to the first passivation structure 20, the silicon-based thin film layer 620 may be one or a combination of silicon nitride, silicon oxide, silicon oxynitride, etc. For example, the silicon-based thin film layer 620 is a silicon nitride layer. The second passivation structure 70 employs a composite passivation method of aluminum oxide layer 610 and silicon-based thin film layer 620, which can improve its durability in strong UV irradiation scenarios and reduce performance degradation during use.

[0064] In some embodiments, the thickness of the alumina layer 610 in the first passivation structure 20 and the second passivation structure 70 is 1-20 nm. For example, the thickness of the alumina layer 610 is 1-5 nm, 1-10 nm, 5-10 nm, 5-15 nm, or 8-20 nm. Specifically, the thickness of the alumina layer 610 can be 1 nm, 4 nm, 7 nm, 10 nm, 15 nm, or 20 nm. The thickness of the silicon-based thin film layer 620 can be the same as the thickness of the alumina layer 610.

[0065] In some embodiments, both the first surface 110 and the second surface 120 are provided with a velvet surface 114 structure.

[0066] This application employs a double-sided textured 114 structure, thus enabling the battery structure to achieve an extremely high bifaciality, thereby increasing the actual power generation in various scenarios. Compared to a polished surface, the textured 114 structure facilitates slurry contact.

[0067] Furthermore, in this application, based on the textured surface 114 structure on the back side, the first region S1 and the third region S3 are passivated using aluminum oxide + silicon nitride, and the second region S2 is passivated using hydrogenated intrinsic amorphous silicon + hydrogenated doped amorphous silicon, which can achieve a high bifaciality.

[0068] refer to Figure 1 and Figure 2 This application also proposes a method for preparing a back contact battery 1. The method for preparing the back contact battery 1 includes the following steps.

[0069] S100, a semiconductor substrate 10 is provided. The semiconductor substrate 10 includes a first surface 110 and a second surface 120 disposed opposite to each other. The first surface 110 includes a first region S1, a second region S2 and a third region S3. The third region S3 is located between the first region S1 and the second region S2.

[0070] refer to Figure 3 A semiconductor substrate 10 is provided. The first surface 110 and the second surface 120 of the semiconductor substrate 10 can be texturized to form a surface textured structure 114. For example, the semiconductor substrate 10 is an N-type semiconductor, and the first region S1, the second region S2 and the third region S3 correspond to the P-region, the N-region and the isolation region between the P-region and the N-region, respectively.

[0071] S200, a doped silicon region 112 is formed in the first surface 110, and the conductivity type of the doped silicon region 112 is opposite to that of the semiconductor substrate 10.

[0072] refer to Figure 1 , Figure 4 In this step, doped silicon regions 112 located on the semiconductor substrate 10 are formed in the first region S1, the second region S2, and the third region S3 of the first surface 110. For example, by boron diffusion, the entire first surface 110 can have doped silicon regions 112.

[0073] S300, remove the doped silicon region 112 in the second region S2 and the third region S3.

[0074] For example, refer to Figure 5 The doped silicon regions 112 in the second region S2 and the third region S3 are processed by picosecond laser according to a preset pattern to expose the semiconductor substrate 10.

[0075] S400, aluminum oxide thin films are formed on the first surface 110 and the second surface 120, respectively. For example... Figure 6 As shown.

[0076] S500, silicon-based thin film layers 620 are formed on the alumina thin films of the first surface 110 and the second surface 120, respectively. For example... Figure 6 As shown.

[0077] S600, remove the alumina film and silicon-based film layer 620 from the second region S2, as shown. Figure 7 As shown.

[0078] Through steps S400 to S600, a first passivation structure 20 is formed in the first region S1 and the third region S3 of the first surface 110, and a passivation structure 20 is formed on the second surface 120. Figure 1 The second passivation structure 70 in the middle.

[0079] S700, an amorphous silicon layer 310, a doped amorphous silicon layer 320, and a conductive film 330 are sequentially coated on the first surface 110, wherein the conductivity type of the doped amorphous silicon layer 320 is the same as that of the semiconductor substrate 10. Figure 8 As shown.

[0080] S800, remove the conductive film 330, amorphous silicon layer 310, and doped amorphous silicon layer 320 from the first region S1, and remove the conductive film 330, amorphous silicon layer 310, and doped amorphous silicon layer 320 from the first portion S31 of the third region S3, leaving the conductive film 330, amorphous silicon layer 310, and doped amorphous silicon layer 320 in the second portion S32, with the first portion S31 close to the first region S1. Figure 9 As shown.

[0081] In step S700, the layers of the second unit structure 30 are first formed over the entire area of ​​the first surface 110. In step S800, the second unit structure 30 in the first region S1 is removed, and the second unit structure 30 on the first portion S31 in the third region S3 is also removed. Thus, only the second unit structure 30 in the second region S2 and the second unit structure 30 covering the second portion S32 in the third region S3 are retained. (Refer to...) Figure 1 .

[0082] S900, a first electrode 40 is formed in contact with the doped crystalline silicon region 112, and a second electrode 50 is formed in contact with the doped amorphous silicon layer 320. This results in... Figure 1 The back contact battery 1 is shown.

[0083] In the method for fabricating the back contact battery 1 of this application, the first passivation structure 20 simultaneously covers both the first region S1 and the third region S3. This allows the passivation films on the first region S1 and the third region S3 to be formed simultaneously, thus simplifying the process flow. Furthermore, compared to conventional TBC batteries, the passivation structure in the P-region, due to the absence of a doped polycrystalline silicon layer, significantly reduces parasitic light absorption effects.

[0084] In some embodiments, S900 includes: forming a first electrode 40 and a second electrode 50 using a screen printing process; and performing laser-assisted sintering on the first electrode 40 and / or the second electrode 50.

[0085] Laser-assisted sintering (LECO) is used to form better ohmic contacts, thereby improving the contact and increasing the fill factor. Specifically, when printing the first electrode 40, laser is used to assist in the sintering of the first electrode 40. This can control the amorphous silicon in the second region S2 from crystallizing while creating good ohmic contacts in the first region S1, thereby increasing the fill factor and ultimately increasing the power generation in actual use.

[0086] The preparation process of the back contact battery 1 of this application is briefly described below.

[0087] 1. Provide N-type silicon wafers as semiconductor substrates. The back side (first surface 110) and front side (second surface 120) of the N-type silicon wafer are textured on both sides to remove silicon wafer impurities and form a textured surface 114 structure. The pyramid base size is 1-5um, the pyramid height is 1-3um, and the reflectivity is 8-10%.

[0088] 2. Boron diffusion: Diffusion is carried out at a temperature of 800-1200℃ for 2-5 hours to form a thick boron-doped region, which forms a PN junction with the N-type silicon wafer. The thickness of the formed BSG (borosilicate glass layer) is 50-150nm, and the diffusion sheet resistance is 100-600Ω / □.

[0089] 3. Using a picosecond laser with a wavelength of 300-1100nm, a specific area of ​​the BSG on the back is processed according to a specific pattern to form an N-region (second region S2) and a Gap region (third region S3). The spot energy density is 100-3000W / mm2, and the linewidth is 80-1500um.

[0090] 4. BSG removal: Chain-type HF removal of the front (second surface 120) and side borosilicate glass layers.

[0091] 5. Alkaline Etching: First, use a mixture of potassium hydroxide (KOH) and texturing additive to simultaneously etch the BSG in the laser-affected areas on both the front and back sides, removing the boron-doped layer in the N-regions of the front and laser-affected back sides. The remaining BSG layer protects the non-laser areas from etching (using 20-40L of alkali, 2-5L of additive, temperature 60-80°C, and process time 100-300s). Then, wash away the protective BSG layer with hydrofluoric acid (HF).

[0092] 6. ALD: AlOx thin films are grown simultaneously on the front and back sides using atomic layer deposition, with a thickness of 1-20 nm.

[0093] 7. One or more combined films of SiNx, SiONx, and SiOx are deposited on the front and back sides using PECVD.

[0094] 8. A picosecond laser with a wavelength of 300-1100 nm is used to pattern the SiNx layer in the N-region on the back side and the gap region near the N-region according to a specific pattern. The spot energy density is 100-3000 W / mm2, and the linewidth is 80-1500 μm. In this way, a first passivation structure 20 is formed in the first region S1 and the third region S3 on the back side, and a second passivation structure 70 is formed on the front side.

[0095] 9. Use HF acid solution to wash away the SiNx and AlOx in the laser-affected area, exposing the silicon substrate in the N-region. Then treat the textured surface 114 of the N-region with a mixed solution of KOH and texturing additive to remove 1-5nm of laser damage.

[0096] 10. Hydrogenated intrinsic amorphous silicon (ia-Si:H) is deposited on the back side using PECVD to form... Figure 1 The amorphous silicon layer 310 and the hydrogenated phosphorus-doped amorphous silicon (na-Si:H) are used. The ia-Si:H film is controlled between 2-20 nm, and the na-Si:H film is controlled between 10-50 nm.

[0097] 11. A conductive film 330 is formed by depositing a TCO (transparent conductive oxide) layer on the back side using magnetron sputtering (PVD). The film thickness is 30-150 nm.

[0098] 12. Remove the TCO from the P area (first region S1) and the part of the gap area near the P area using a printing etching ink paste.

[0099] 13. Clean the battery cells with an alkaline solution in a bath to remove residual ink paste and remove the intrinsic amorphous silicon and phosphorus-doped amorphous silicon in the P region.

[0100] 14. The screen-printed metal electrodes are sintered at low temperatures (less than 200°C) to prevent the amorphous silicon in the N region from crystallizing. Laser-assisted sintering is used to process the gate lines in the P region, which can form good ohmic contacts.

[0101] refer to Figure 10 This application also proposes a photovoltaic module 100, including the aforementioned back contact battery 1.

[0102] For example, the photovoltaic module 100 includes a back contact cell 1, a first encapsulating film 2 and a second encapsulating film 3, a front panel 4, and a back panel 5. The first encapsulating film 2 and the second encapsulating film 3 are located on opposite sides of the back contact cell 1. Specifically, the first encapsulating film 2 faces the first surface 110 of the back contact cell 1, and the second encapsulating film 3 faces the second surface 120 of the back contact cell 1. For example, both the first encapsulating film 2 and the second encapsulating film 3 are EPE encapsulating films. The front panel 4 is disposed on the side of the second encapsulating film 3 opposite to the back contact cell 1, and the back panel 5 is disposed on the side of the first encapsulating film 2 opposite to the back contact cell 1. In this way, the front panel 4 is bonded to the back contact cell 1 through the second encapsulating film 3, and the back panel 5 is bonded to the back contact cell 1 through the first encapsulating film 2, thereby forming the photovoltaic module 100. For example, both the front panel 4 and the back panel 5 are transparent glass plates.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A back contact cell, characterized in that, The back contact solar cell comprises: a semiconductor substrate comprising a first surface and a second surface arranged oppositely, the first surface comprising a first region, a second region and a third region, a doped crystalline silicon region being formed in the surface of the first region, the third region being located between the first region and the second region, the doped crystalline silicon region having a conductive type opposite to that of the semiconductor substrate; a first unit structure arranged in the first region and comprising a first passivation structure arranged on the doped crystalline silicon region, the first passivation structure also covering the third region; a second unit structure arranged in the second region and comprising an amorphous silicon layer, a doped amorphous silicon layer and a conductive film arranged in sequence, the doped amorphous silicon layer having the same conductive type as the semiconductor substrate; a first electrode in electrical contact with the doped crystalline silicon region; and a second electrode in electrical contact with the doped amorphous silicon layer. In a direction parallel to the first surface, the first passivation structure in the third region is divided into a first part and a second part, and the second part covers the second unit structure. In a direction parallel to the first surface, the width of the second part is 10-50 μm.

2. The back contact cell of claim 1, wherein, The thickness of the amorphous silicon layer is 2-20 nm, the thickness of the doped amorphous silicon layer is 10-50 nm, and the thickness of the conductive film is 30-150 nm.

3. The back contact cell of claim 1, wherein, The first passivation structure comprises an aluminum oxide layer and a silicon-based thin film layer arranged in sequence on the doped crystalline silicon region.

4. The back contact cell of claim 1, wherein, The second surface is provided with a second passivation structure.

5. The back contact cell of claim 1, wherein, The second passivation structure comprises an aluminum oxide layer and a silicon-based thin film layer arranged in sequence on the second surface.

6. The back contact cell of claim 5, wherein, The silicon-based thin film layer is one or a combination of silicon nitride, silicon oxide and silicon oxynitride.

7. The back contact cell according to claim 4 or 6, characterized in that, The thickness of the aluminum oxide layer is 1-20 nm.

8. The back contact cell of claim 4 or 6, wherein, The first surface and the second surface are both provided with a textured structure.

9. The back contact cell of claim 1, wherein, The preparation method of the back contact solar cell comprises:

10. A method of producing a back contact cell, characterized by, providing a semiconductor substrate comprising a first surface and a second surface arranged oppositely, the first surface comprising a first region, a second region and a third region, the third region being located between the first region and the second region; forming a doped crystalline silicon region in the first surface, the doped crystalline silicon region having a conductive type opposite to that of the semiconductor substrate; removing the doped crystalline silicon region in the second region and the third region; forming an aluminum oxide thin film on the first surface and the second surface respectively; forming a silicon-based thin film layer on the aluminum oxide thin film of the first surface and the second surface respectively; removing the aluminum oxide thin film and the silicon-based thin film layer in the second region; covering an amorphous silicon layer, a doped amorphous silicon layer and a conductive film in sequence on the first surface, the doped amorphous silicon layer having the same conductive type as the semiconductor substrate. ​ removing the conductive film, the amorphous silicon layer, the doped amorphous silicon layer in the first region, and removing the conductive film, the amorphous silicon layer, the doped amorphous silicon layer in the first part of the third region, leaving the conductive film, the amorphous silicon layer, the doped amorphous silicon layer in the second part of the third region, the first part being close to the first region; forming a first electrode in contact with the doped crystalline silicon region, and a second electrode in contact with the doped amorphous silicon layer.

11. The method of claim 10, wherein, the first electrode and the second electrode are formed by a screen printing process; the first electrode and / or the second electrode are assisted sintered by a laser-assisted sintering technique.

12. A photovoltaic module, characterized by, a back contact cell as claimed in any one of claims 1 to 9.

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