High-density chip test equipment and electronic equipment

Abstract

The invention discloses high-density chip testing equipment and electronic equipment, and relates to the field of chip testing. The limiting frame, the PCB and the supporting frame are arranged from top to bottom and are fixedly connected. The resistance-capacitance material is electrically connected with a bonding pad of the PCB; the limiting frame is provided with a plurality of grooves, each groove is configured to place a to-be-tested chip, and a pin of the to-be-tested chip is electrically connected with a bonding pad of the PCB; the cover plate and the base structure are fixedly connected during testing, and the cover plate compacts the to-be-tested chip in the groove during fixed connection. The chip aging test fixture is well applied to environments such as chip aging and aging tests, a traditional chip fixture is not used, the test density is high, and the cost required by the chip aging and aging tests is effectively reduced. As the demand quantity of the high-quality chips is increased year by year, the chip quality requirement is continuously improved, the aging and aging tests of the high-quality chips are well optimized, the test cost is reduced, and an effective way is provided for improving the product competitiveness of chip design manufacturers.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip testing, in particular to a high-density chip testing device and an electronic device. BACKGROUND

[0002] Currently, chips are developing rapidly, the types of chips are increasing year by year, and the performance is improving year by year. In addition to chip design and production links, the performance and quality of chip products are ensured through screening and testing, which becomes a common way for chip design manufacturers. Higher requirements are put forward for the chip screening and testing link in the later stage, and the importance of the later screening and testing is increasingly prominent. In order to test the stability and actual service life of the chip under long-term working conditions, it is necessary to extract samples from a batch of chips for aging test. Especially for products with high quality requirements (such as automotive-grade products), in addition to batch aging test, chip burn-in steps are also needed to be supplemented as needed, so as to discover chip failure early and remove failed products, and ensure the high quality and high reliability of products.

[0003] Currently, the traditional single chip aging and burn-in test scheme is to use an aging test seat and other chip clamps for operation. Since the aging test seat is installed on the aging board, it needs to be customized and designed by the relevant manufacturer, which has high cost, and the test seat has large volume, and the number of test seats carried on a single aging board is small, resulting in a small number of chips in a batch for aging, and the cost of single chip aging and burn-in test is high. If the aging station is increased to increase the number of chips for aging and burn-in test, high hardware cost will be spent, which will increase the production cost of chip design manufacturers. SUMMARY

[0004] In view of the above problems, the present application provides a high-density chip aging test device and an electronic device to overcome the shortcomings of the prior art.

[0005] The embodiment of the present application provides a high-density chip testing device, which comprises a base structure and a cover plate 5, wherein the base structure comprises a support frame 1, a PCB board 2, a limiting frame 3 and a resistance-capacitance material 4. The limiting frame 3, the PCB board 2 and the support frame 1 are arranged and fixedly connected from top to bottom. The resistance-capacitance material 4 is electrically connected with the solder pad of the PCB board 2. The limiting frame 3 is provided with a plurality of grooves, each of which is configured to place a chip to be tested, and the pin of the chip to be tested is electrically connected with the solder pad. The cover plate 5 is fixedly connected with the base structure during testing, and the cover plate 5 presses the chip to be tested in the groove when fixedly connected.

[0006] Optionally, the cover plate 5 comprises a plurality of gaskets 6. The plurality of gaskets 6 are respectively arranged on the side of the cover plate 5 facing the chip to be tested, and when the cover plate 5 is fixedly connected with the base structure, the position of each gasket 6 corresponds to the position of each groove.

[0007] Optionally, during non-testing, the cover plate 5 is not fixedly connected with the base structure or is not connected.

[0008] Optionally, the high-density chip testing device further comprises at least two first-layer bolts 7. The at least two first-layer bolts 7 are respectively arranged at first preset positions to fixedly connect the limiting frame 3, the PCB board 2 and the support frame 1 from top to bottom. The first preset positions refer to positions, except for target regions, at which the limiting frame 3, the PCB board 2 and the support frame 1 can be fixedly connected from top to bottom. The target regions are the plurality of grooves and regions formed on the PCB board 2 and the support frame 1 corresponding to positions of the plurality of grooves.

[0009] Optionally, the high-density chip testing device further comprises at least two second-layer bolts 8. The at least two second-layer bolts 8 are respectively arranged at second preset positions to fixedly connect the cover plate 5 and the base structure during testing. The second preset positions refer to positions, except for target regions, at which the cover plate 5 and the base structure can be fixedly connected. The target regions are the plurality of grooves and regions formed on the PCB board 2, the support frame 1 and the cover plate 5 corresponding to positions of the plurality of grooves.

[0010] Optionally, the plurality of grooves are arranged in an n x m array on the limiting frame 3. n and m are equal or not equal.

[0011] Optionally, the high-density chip testing device further comprises a power line terminal and a test display region. The power line terminal is respectively connected with an external power source, the PCB board 2 and the test display region, and is configured to transmit electric energy generated by the power source to the PCB board 2 and the test display region. The test display region is configured to display the working state of the chip to be tested during testing.

[0012] Optionally, the gasket 6 comprises a silica gel gasket, a rubber gasket, a sponge gasket, a foam gasket or a polyurethane gasket.

[0013] Optionally, the resistance-capacitance material 4 is arranged near the solder pad and is electrically connected to the solder pad by soldering.

[0014] The electronic device provided by the embodiment of the present application comprises: a power supply and the high-density chip testing device according to any one of the preceding embodiments; the power supply is configured to provide a testing power supply for the high-density chip testing device; and the high-density chip testing device is configured to test a chip to be tested.

[0015] The high-density chip testing device provided by the present application comprises: a base structure and a cover plate 5, wherein the base structure comprises: a support frame 1, a PCB board 2 and a limiting frame 3, and a resistance-capacitance material 4; the limiting frame 3, the PCB board 2 and the support frame 1 are arranged and fixedly connected from top to bottom.

[0016] The resistance-capacitance material 4 is electrically connected to the solder pad of the PCB board 2; the limiting frame 3 is provided with a plurality of grooves, each groove is configured to place a chip to be tested, and the pin of the chip to be tested is electrically connected to the solder pad of the PCB board 2; and the cover plate 5 is fixedly connected to the base structure during testing, and the cover plate 5 presses the chip to be tested in the groove when fixedly connected.

[0017] The present application creatively provides a new high-density chip testing device, which completely discards the traditional chip clamp (such as an aging test seat), and designs a base structure, which uses the support frame 1 and the limiting frame 3 to fix the PCB board 2 in the middle, opens a plurality of grooves on the limiting frame 3, and each groove can place a chip to be tested, thereby improving the number of chips to be tested in a batch and improving the testing density.

[0018] In order to realize the aging and aging test of the chip to be tested, the resistance-capacitance material 4 required by the chip is electrically connected to the solder pad of the PCB board 2, and the pin of the chip to be tested is also electrically connected to the solder pad of the PCB board 2 after being placed in the groove. Finally, the cover plate 5 presses the chip to be tested in the groove during testing, so as to realize the test of the chip to be tested.

[0019] The high-density chip testing device provided by the present application is well applied to the chip aging and aging test environment, the entire testing device does not use the traditional chip clamp, the testing density is high, and the cost required by the chip aging and aging test can be effectively reduced. With the increasing demand for high-quality chips year by year and the increasing requirement for chip quality, the chip aging and aging test of high-quality chips is well optimized, the testing cost is reduced, an effective way for improving the product competitiveness of chip design manufacturers is provided, and the high-density chip testing device has wide application prospect and high practicability. BRIEF DESCRIPTION OF DRAWINGS

[0020] Various other advantages and benefits will become apparent to those of ordinary skill in the art, upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of preferred embodiments, and are not intended to limit the scope of the present application. Furthermore, the drawings are not necessarily drawn to scale. In the drawings: Figure 1 is a structural cross-sectional view of a conventional chip burn-in test apparatus; Figure 2 is a modular schematic diagram of a high-density chip burn-in test apparatus according to an embodiment of the present application; Figure 3 is a structural cross-sectional view of a high-density chip test apparatus according to an embodiment of the present application; Figure 4 is a structural top view of a high-density chip test apparatus according to an embodiment of the present application; Figure 5 is a schematic diagram of a high-density chip test apparatus according to an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to make the above objectives, features and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to explain, and not to limit, the present application, which is only a part of the embodiments, and not all of the embodiments, and is not intended to limit the present application.

[0022] The inventor has found that the conventional single chip burn-in and burn-in test scheme uses a chip clamp such as a burn-in test socket for operation. Referring to the structural cross-sectional view of a chip burn-in test apparatus shown in Figure 1 , the test chip is placed in the positioning frame of the burn-in test socket and the test buckle is pressed tightly, and the spring contact pins in the burn-in test socket form an electrical connection with the test chip pins or BUMP balls.

[0023] Figure 1 The burn-in test socket is installed on the burn-in board and fixed using bolts, and the other end of the spring contact pins below the burn-in test socket contacts and forms an electrical connection with the pads on the burn-in board, at which time power is supplied to the burn-in board to start the burn-in test.

[0024] The inventor has further found that this technical scheme using a burn-in chip clamp such as a burn-in test socket needs to be custom designed by the relevant manufacturer, which has a high cost, and the test socket has a large volume, and the number of test sockets carried on a single burn-in board is small, resulting in a small number of chips in a batch for burn-in, and the cost of burn-in and burn-in test of a single chip is high.

[0025] If the aging station is increased to increase the number of aging and burn-in test chips, higher aging hardware costs will be spent, the production cost of chip designers will be increased, and the competitiveness of chip products will be hindered.

[0026] In view of the above problems, the inventors have creatively proposed a high-density chip test device and electronic equipment. The technical solutions of the present application are described and explained in detail below.

[0027] The high-density chip test device of the present application, referring to the modular schematic diagram shown in Figure 2 The high-density chip test device includes a base structure and a cover plate 5, wherein the base structure includes a support frame 1, a PCB board 2, a limiting frame 3, and a resistance-capacitance material 4.

[0028] The limiting frame 3, the PCB board 2, and the support frame 1 are arranged and fixedly connected from top to bottom; the resistance-capacitance material 4 is electrically connected with the solder pad of the PCB board 2; the limiting frame 3 is provided with a plurality of grooves A, each groove A is configured to place a to-be-tested chip (not shown in Figure 2 The pins of the to-be-tested chip are electrically connected with the solder pad of the PCB board 2; the cover plate 5 is fixedly connected with the base structure during testing, and the cover plate 5 presses the to-be-tested chip in the groove A when fixedly connected.

[0029] As shown in Figure 2 , it is the case when the cover plate 5 is fixedly connected with the base structure, and during the non-testing period, the cover plate 5 is not fixedly connected or connected with the base structure. The so-called non-fixed connection means that the cover plate 5 can be designed as a semi-connected structure, for example: one side of the cover plate 5 can be connected with the base structure through a hinge structure, a damping structure, etc., and the other side can be completely separated from the base structure. During the non-testing period, the cover plate 5 is opened from one side to expose the groove A to facilitate the placement of the to-be-tested chip. During the testing period, the cover plate 5 is closed and fixed to realize the fixed connection with the base structure.

[0030] The so-called non-connection means that the cover plate 5 can completely separate from the base structure during the non-testing period to expose the entire base structure, which is conducive to the cleaning and maintenance of the base structure.

[0031] In an embodiment of the present application, a more preferred structure of the cover plate 5 includes a plurality of gaskets 6. The plurality of gaskets 6 are respectively arranged on the side of the cover plate 5 facing the to-be-tested chip, and the position of each gasket 6 corresponds to the position of each groove when the cover plate 5 is fixedly connected with the base structure. That is, the gasket serves to better compact the to-be-tested chip during testing to ensure the testing accuracy of the to-be-tested chip. The preferred selection of the gasket 6 includes silica gel gasket, rubber gasket, sponge gasket, foam gasket, and polyurethane gasket. Materials that meet certain hardness and are convenient to make and cut can be selected as the gasket 6.

[0032] It can be understood that if the manufacturing process of the cover plate 5 and the base structure is accurate enough to ensure that the cover plate 5 can be fixedly connected with the base structure without the gasket 6, the gasket 6 can be omitted, thereby reducing the cost of the high-density chip testing device itself, and indirectly reducing the cost of the chip design manufacturer.

[0033] In an embodiment of the present application, the resistor-capacitor material 4 is preferably arranged near the pads of the PCB 2 and is electrically connected to the pads by welding. Of course, the arrangement position of the resistor-capacitor material 4 can be determined according to the actual situation, but no matter where it is arranged, it needs to be electrically connected to the pads of the PCB 2.

[0034] In an embodiment of the present application, for the fixed connection of the limiting frame 3, the PCB 2, and the support frame 1, and the fixed connection of the cover plate 5 and the base structure, there can be multiple connection methods, such as bonding, bolts, bayonet, etc., and one preferred connection method is the bolt connection method.

[0035] Referring to Figure 3 , a preferred structure sectional view of a high-density chip testing device is shown, and Figure 3 , an exemplary chip to be tested 9 is shown. The high-density chip testing device further comprises: at least two first-layer bolts 7; the at least two first-layer bolts 7 are arranged at first preset positions respectively, so as to fixedly connect the limiting frame 3, the PCB 2, and the support frame 1 from top to bottom.

[0036] Among them, the so-called first preset position refers to a position, except for the target area, at which the limiting frame 3, the PCB 2, and the support frame 1 can be fixedly connected from top to bottom. The target area is the area formed by the plurality of grooves and the positions on the PCB 2 and the support frame 1 corresponding to the plurality of grooves.

[0037] The high-density chip testing device further comprises: at least two second-layer bolts 8; the at least two second-layer bolts 8 are arranged at second preset positions respectively, so as to fixedly connect the cover plate 5 and the base structure during testing.

[0038] Among them, the so-called second preset position refers to a position, except for the target area, at which the cover plate 5 and the base structure can be fixedly connected. The target area is the area formed by the plurality of grooves and the positions on the PCB 2, the support frame 1, and the cover plate 5 corresponding to the plurality of grooves.

[0039] In order to better understand the meaning of the above two preset positions, refer to Figure 4 , a preferred structure top view of a high-density chip testing device is shown. Figure 4The support frame 1, the PCB board 2, the limiting frame 3 and the cover plate 4 are all rectangular in the example, and this does not mean that these structures can only be rectangular.

[0040] For the first layer bolt 7 and the second layer bolt 8, in combination with the rectangle, the preferred selection is to take the diagonal position as the first preset position and the second preset position, so that the support frame 1, the PCB board 2 and the limiting frame 3 can be fixed by using only two first layer bolts 7 and two second layer bolts 8. Of course, the optimal selection is to take the four corner positions of the rectangle as the first preset position and the second preset position.

[0041] Figure 4 Each virtual frame represents a groove A, and a plurality of grooves A form a groove array. The plurality of grooves A are arranged in an n*m array on the limiting frame 3, where n and m can be equal or not equal (n, m > 1). Figure 4 The example is shown as 10*10). In this way, as many test chips as possible can be placed under the same area. The groove array formed by the plurality of grooves A is the target area, Figure 4 which is represented by a virtual frame array. Of course, it can be understood that any position other than the target area can be used as the first preset position and the second preset position, as long as it can meet the fixation and connection requirements. For other shapes of structures, the number of bolts and the preset positions can be determined by the person skilled in the art in combination with the specific shape, and will not be described here.

[0042] From the above explanation and description, it can be known that the high-density chip test device provided by the application completely discards the traditional chip clamp (such as an aging test seat), and the design uses the support frame 1 and the limiting frame 3 to clamp the PCB board 2 in the middle to fix it. A plurality of grooves are arranged on the limiting frame 3, and each groove can place a test chip, thereby improving the number of test chips in a batch and increasing the test density.

[0043] In order to realize the aging and aging test of the test chip, the chip working required resistance and capacitance material 4 is also electrically connected with the solder pad of the PCB board 2, and the pin of the test chip is also electrically connected with the solder pad of the PCB board 2 after being placed in the groove. Finally, the cover plate 5 is used to press the test chip in the groove during the test, so as to realize the test of the test chip.

[0044] The high-density chip test device provided by the application can be well applied to the chip aging and aging test environment. The entire test device does not use the traditional chip clamp, has high test density, and can effectively reduce the cost required for chip aging and aging test.

[0045] In addition, the high-density chip test device further comprises a power line terminal and a test display area. The power line terminal is connected with an external power supply, the PCB board 2 and the test display area, respectively.Figure 5 Fig. 1 is a schematic diagram of a high-density chip testing device according to an embodiment of the present application, Figure 5 Fig. 2 is a schematic diagram of a high-density chip testing device according to an embodiment of the present application,

[0046] The external power supply provides power, which is transmitted to the power line terminal through the power line. The power line terminal is configured to transmit the power generated by the power supply to the PCB 2 and the test display area. The test display area is configured to display the working status of the chip to be tested during the test.

[0047] Preferably, the test display area can use LEDs to identify the working status of the chip to be tested. When the LED is on, it indicates that the chip to be tested is working normally. When the LED is off, it indicates that the chip to be tested is not working normally.

[0048] Since the grooves are used to place the chip to be tested, the grooves can be designed according to the specifications of the existing chips, and the grooves of different sizes can be formed to form a groove array. For example, the chip to be tested is a 3x3mm DFN10 packaged chip. The PCB area required for a single station (i.e., a single groove) is 1.5cm 2 when using the conventional aging test seat, the PCB area required for a single station is 31cm 2 , and the area utilization rate of the PCB is increased by about 20 times. As can be seen, for the same area overhead, the high-density chip aging test device according to the present application can simultaneously perform aging and burn-in tests on more chips, thereby naturally reducing the test cost and providing an effective way to improve the product competitiveness of chip design manufacturers.

[0049] Based on the above high-density chip testing device, the electronic device according to an embodiment of the present application comprises a power supply and a high-density chip testing device according to any one of the above. The power supply is configured to provide a test power supply for the high-density chip testing device. The high-density chip testing device is configured to test the chip to be tested.

[0050] As described above, the high-density chip testing device according to the present application comprises a base structure and a cover plate 5. The base structure comprises a support frame 1, a PCB 2, a limiting frame 3, and a resistance-capacitance material 4. The limiting frame 3, the PCB 2, and the support frame 1 are arranged and fixedly connected from top to bottom.

[0051] The resistance-capacitance material 4 is electrically connected to the pads of the PCB 2. The limiting frame 3 is provided with a plurality of grooves. Each groove is configured to place a chip to be tested, and the pins of the chip to be tested are electrically connected to the pads of the PCB 2. The cover plate 5 is fixedly connected to the base structure during the test, and the cover plate 5 presses the chip to be tested in the groove when fixedly connected.

[0052] The application creatively proposes a new high-density chip testing device, completely abandoning the traditional chip clamp (such as an aging test seat, etc.), and designing a basic structure which adopts a support frame 1 and a limiting frame 3 to clamp and fix the PCB board 2 in the middle, and a plurality of grooves are formed on the limiting frame 3, each groove can place a chip to be tested, and the number of a batch of chips to be tested is increased, and the testing density is high.

[0053] At the same time, in order to realize the aging and aging test of the chip to be tested, the chip working required resistance and capacitance materials 4 are electrically connected with the pads of the PCB board 2, and the pins of the chip to be tested are also electrically connected with the pads of the PCB board 2 after being placed in the groove. Finally, the cover plate 5 is used to press the chip to be tested in the groove during the test, and the test of the chip to be tested is realized.

[0054] The high-density chip testing device provided by the application is well applied to the chip aging and aging test environment, the whole testing device does not use the traditional chip clamp, the testing density is high, and the cost required by the chip aging and aging test can be effectively reduced. With the increasing demand for high-quality chips year by year, the quality requirements of the chips are continuously improved, the aging and aging test of the high-quality chips is well optimized, the test cost is reduced, an effective way is provided for improving the product competitiveness of chip design manufacturers, and the application has wide application prospect and high practicability.

[0055] Although the preferred embodiments of the embodiments of the application have been described, those skilled in the art can make other changes and modifications to the embodiments once they know the basic creative concept. Therefore, the appended claims are intended to include the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the application.

[0056] Finally, it should be noted that, in this document, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or terminal device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or terminal device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or terminal device including the element.

[0057] The embodiments of the present application are described above with reference to the accompanying drawings, but the present application is not limited to the specific embodiments described above, and the specific embodiments described above are merely illustrative, but not restrictive, and a person of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the purpose of the present application and the scope protected by the claims, and these all belong to the protection of the present application.

Claims

1. A high density chip testing apparatus, characterized by, The utility model relates to a high density chip test equipment, including: Infrastructure and cover plate (5), the infrastructure includes: support frame (1), PCB board (2), limiting frame (3), resistance and capacity material (4); The limiting frame (3), the PCB board (2), the support frame (1) are laid from top to bottom and fixedly connected; Resistance and capacity material (4) and the pad electric connection of PCB board (2); The limiting frame (3) is equipped with a plurality of recess, every recess is configured to place the chip to be tested, and the pin of the chip to be tested is electrically connected with the pad; The cover plate (5) is fixedly connected with the infrastructure during testing, and the cover plate (5) is pressed in the recess when fixedly connected.

2. The high-density chip testing apparatus according to claim 1, wherein The cover plate (5) includes: a plurality of gaskets (6); A plurality of gaskets (6) are respectively arranged on the side of the cover plate (5) facing the chip to be tested, and when the cover plate (5) is fixedly connected with the infrastructure, the position of each gasket (6) corresponds to the position of each recess.

3. The high-density chip testing apparatus according to claim 1, wherein During non-testing, the cover plate (5) is not fixedly connected or connected with the infrastructure.

4. The high-density chip testing apparatus according to claim 1, wherein The high-density chip test equipment further comprises at least two first-layer bolts (7). At least two first-layer bolts (7) are respectively arranged at a first predetermined position to fixedly connect the limiting frame (3), the PCB board (2) and the support frame (1) from top to bottom. The first predetermined position refers to a position, except for a target area, at which the limiting frame (3), the PCB board (2) and the support frame (1) can be fixedly connected from top to bottom. The target area is the plurality of recesses and the area formed on the PCB board (2) and the support frame (1) corresponding to the positions of the plurality of recesses.

5. The high-density chip testing apparatus according to claim 1, wherein The high-density chip test equipment further comprises at least two second-layer bolts (8). At least two second-layer bolts (8) are respectively arranged at a second predetermined position to fixedly connect the cover plate (5) and the infrastructure during testing. The second predetermined position refers to a position, except for a target area, at which the cover plate (5) and the infrastructure can be fixedly connected. The target area is the plurality of recesses and the area formed on the PCB board (2), the support frame (1) and the cover plate (5) corresponding to the positions of the plurality of recesses.

6. The high-density chip testing apparatus according to claim 1, wherein The plurality of recesses are arranged in an n×m array on the limiting frame (3). n and m are equal or not equal.

7. The high-density chip testing apparatus according to claim 1, wherein The high-density chip test equipment further comprises a power line terminal and a test display area. The power line terminal is connected with an external power source, the PCB board (2) and the test display area, and is configured to transmit electric energy generated by the power source to the PCB board (2) and the test display area. The test display area is configured to display the working state of the chip to be tested during testing.

8. The high-density chip testing apparatus according to claim 2, wherein The gasket (6) includes a silica gel gasket, a rubber gasket, a sponge gasket, a foam gasket and a polyurethane gasket.

9. The high-density chip testing apparatus according to claim 1, wherein The resistance-capacitance material (4) is arranged near the pad and is electrically connected to the pad by welding.

10. An electronic device, comprising: The electronic device comprises a power supply and the high-density chip testing device according to any one of claims 1-9. The power supply is configured to provide a testing power supply for the high-density chip testing device. The high-density chip testing device is configured to test a chip under test.

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