Wafer testing method and device for SoC chip

Abstract

The application discloses a wafer testing method and device of an SoC chip, and belongs to the field of electronic equipment. A testing machine assembles a write operation testing instruction or a read operation testing instruction according to user input data and sends the testing instruction to an SoC chip; when the SoC chip receives the write operation testing instruction, the data field content of the testing instruction is written into a register, testing is performed, and testing result data is returned to the testing machine; when the SoC chip receives the read operation testing instruction, data in the register is returned to the testing machine. Data interaction between the testing machine and the SoC chip is realized through a TCLK pin level signal and a TIO pin level signal, a two-wire wafer testing method is adopted, the method is suitable for small chips with few pins, a plurality of small chips can be simultaneously tested on the testing machine, testing cost is reduced, and the method is convenient to use.

Description

Technical Field

[0001] This invention relates to the field of electronic devices, and more particularly to a wafer testing method and apparatus for SoC chips. Background Technology

[0002] A SoC (System on Chip) is a dedicated integrated circuit that contains a complete system and all embedded software. SoCs include embedded processors (such as MPUs, MCUs, or DSPs), memory (such as SRAM, SDRAM, or FlashROM), dedicated function modules (such as ADCs, DACs, PLLs, and 2D / 3D graphics processing units), I / O interface modules (such as USB, UART, and Ethernet), and on-chip buses, among other functional modules.

[0003] As existing electronic products become increasingly feature-rich and smaller in size, the area requirements for individual chips are decreasing in order to integrate more chips and achieve more functions. As the chip area shrinks, the number of pins also decreases accordingly. How to perform efficient wafer testing on small chips is an urgent problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a wafer testing method and apparatus for SoC chips.

[0005] In a first aspect, embodiments of the present invention provide a wafer testing method for a SoC chip, comprising:

[0006] Step T1: The SoC chip receives the instruction header of the test command sent by the test machine through the TCLK pin and TIO pin, determines the test mode according to the instruction header, and determines whether the read / write selection bit in the instruction header is the first preset value. If yes, proceed to step T2; otherwise, proceed to step T4.

[0007] Step T2: The SoC chip continues to receive the data field of the test instruction through the TCLK pin and the TIO pin, and stores the data field in the register corresponding to the test mode. It determines whether to perform the test based on the value of the enable test bit in the register. If yes, it executes step T3; otherwise, the test ends.

[0008] Step T3: The SoC chip performs tests according to the test mode and the test parameters in the register, and returns the test result data to the test machine through the TIO pin;

[0009] Step T4: The SoC chip obtains the data in the corresponding register according to the test mode, and after waiting for one switching cycle, returns the obtained data to the test machine through the TCLK pin and the TIO pin.

[0010] Secondly, embodiments of the present invention provide a wafer testing apparatus for a SoC chip, including an instruction decoding module and registers;

[0011] The instruction decoding module includes:

[0012] The receiving and judging unit is used to receive the instruction header of the test instruction sent by the test machine through the TCLK pin and the TIO pin, determine the test mode according to the instruction header, and judge whether the read / write selection bit in the instruction header is a first preset value. If it is, the receiving and storing judging unit is triggered; otherwise, the obtaining and returning unit is triggered.

[0013] The receiving and storing judgment unit is used to continue receiving the data field of the test instruction through the TCLK pin and the TIO pin, and store the data field in the test register corresponding to the test mode. It determines whether to perform the test based on the value of the enable test bit in the register. If yes, the test unit is triggered; otherwise, the test ends.

[0014] The test unit is used to perform tests according to the test mode and the test parameters in the register;

[0015] The return unit is used to return the test result data of the test unit to the test machine through the TIO pin;

[0016] The acquisition and return unit is used to acquire data in the corresponding register according to the test mode, and after waiting for one switching cycle, return the acquired data to the test machine through the TCLK pin and the TIO pin.

[0017] Thirdly, embodiments of the present invention provide an electronic device, the electronic device including at least one processor, a memory and instructions stored in the memory and executable by the at least one processor, wherein the at least one processor executes the wafer testing method of the above-described SoC chip.

[0018] Fourthly, embodiments of the present invention provide a computer-readable storage medium comprising a computer program that, when executed on an electronic device, causes the electronic device to perform the wafer testing method for the aforementioned SoC chip.

[0019] Fifthly, embodiments of the present invention provide a chip system, including a chip coupled to a memory for executing a computer program stored in the memory to perform the wafer testing method of the above-mentioned SoC chip.

[0020] Compared with the prior art, the present invention has the following advantages: The present application adopts a two-wire wafer testing method, which is applicable to small chips with few pins, and at the same time realizes the simultaneous testing of multiple chips on the testing machine, reducing testing costs and making it convenient to use. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the wafer testing system used in an embodiment of the present invention;

[0022] Figure 2 A flowchart of a wafer testing method for a SoC chip provided in Embodiment 1 of the present invention;

[0023] Figure 3 This is a schematic diagram illustrating the working principle of a wafer testing method for a SoC chip provided in Embodiment 2 of the present invention;

[0024] Figure 4 This is a schematic diagram illustrating the format of the test read instruction and the test write instruction in Embodiment 2 of the present invention;

[0025] Figure 5 This is a flowchart illustrating the operation of the test machine in a wafer testing method for a SoC chip according to Embodiment 2 of the present invention.

[0026] Figure 6 This is a schematic diagram of the storage states of the voltage test register, temperature test register, and oscillator test register within the chip provided in Embodiment 2 of the present invention;

[0027] Figure 7 This is a schematic diagram illustrating the specific data format of the voltage test write instruction, voltage test read instruction, temperature test write instruction, temperature test read instruction, oscillator test write instruction, and oscillator test read instruction provided in Embodiment 2 of the present invention.

[0028] Figure 8 This is a schematic diagram illustrating the transmission timing of the voltage test write instruction, voltage test read instruction, temperature test write instruction, temperature test read instruction, oscillator test write instruction, and oscillator test read instruction provided in Embodiment 2 of the present invention.

[0029] Figure 9 This is a flowchart illustrating the operation of a SoC chip in a wafer testing method for a SoC chip according to Embodiment 2 of the present invention. Detailed Implementation

[0030] This application proposes a wafer testing method and apparatus for SoC chips. The specific embodiments of this application will be described in detail below with reference to the accompanying drawings. Examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0031] Those skilled in the art will understand that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0032] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0033] Wafer testing is a core part of semiconductor manufacturing. It is achieved through die-level testing, including voltage alarm, temperature alarm, and oscillator function tests. Wafer test data can accurately locate process defects, quickly screen out defective chips, reduce subsequent invalid packaging costs, and improve the yield of subsequent tests. This also prevents irreparable losses caused by certain problems during chip use.

[0034] like Figure 1 As shown, wafer testing utilizes a system of equipment including a tester, a test bench, and a test head. The test channels on the test head connect to the pins of each chip placed on the wafer on the test bench. The tester communicates with the chips on the wafer via probe cards through the test head. Factors limiting wafer testing efficiency primarily include the number of test channels controlled by the test head and the number of pins required to test each chip on the wafer. Example 1

[0035] Embodiment 1 of the present invention provides a wafer testing method for SoC chips, such as... Figure 2 As shown, it includes:

[0036] Step T1: The SoC chip receives the instruction header of the test command sent by the test machine through the TCLK pin and TIO pin, determines the test mode according to the instruction header, and determines whether the read / write selection bit in the instruction header is the first preset value. If yes, proceed to step T2; otherwise, proceed to step T4.

[0037] Specifically, in this embodiment, the instruction header is 5 bits long and includes: the start bit of the highest bit, the read / write selection bit of the second highest bit, and the test mode of the lowest 3 bits.

[0038] In this embodiment, step T1 includes: the SoC chip samples the TIO pin level at the rising edge of the TCLK pin level within 5 cycles, obtains the instruction header of the test instruction based on all sampling results, obtains the value of the test mode from the 3 bits of low-order data in the instruction header, determines the corresponding test mode based on the value of the test mode, and determines whether the value of the second highest bit in the test instruction is the first preset value. If yes, step T2 is executed; otherwise, step T4 is executed.

[0039] Step T2: The SoC chip continues to receive the data field of the test command through the TCLK and TIO pins, and stores the data field in the register corresponding to the test mode. It determines whether to perform the test based on the value of the enable test bit in the register. If yes, it executes step T3; otherwise, the test ends.

[0040] In this embodiment, step T2 includes: the SoC chip determines the length of the data field of the test instruction according to the test mode, samples the level of the TIO pin at the rising edge of the TCLK pin level, stores the sampling results sequentially into the register corresponding to the test mode, and the sampling ends when the number of sampling results reaches the length of the data field. It then determines whether the value of the least significant bit in the register is the second preset value. If yes, step T3 is executed; otherwise, the test ends.

[0041] Step T3: The SoC chip performs tests according to the test mode and test parameters in the registers, and returns the test result data to the test machine through the TIO pin;

[0042] Optionally, the SoC chip testing in this embodiment includes a comparative test based on receiving external conditions according to a test mode and a self-test based on a test mode. Accordingly, step T3 includes: the SoC chip continuously receives the values ​​of externally provided test items, determines the test standard value based on the data in the register, and controls the TIO pin level to change and outputs it to the test machine when the value of the test item reaches the test standard value; or the SoC chip transmits the control signal in the register to the corresponding test module according to the test mode, the test module performs the corresponding test according to the control signal and outputs the test item value, and the SoC chip outputs the test item value to the test machine through the TIO pin;

[0043] For example, comparative tests include high voltage tests, low voltage tests, high temperature tests, and low temperature tests; self-tests include oscillator tests.

[0044] Optionally, the SoC chip can also perform its own tests (i.e., acquire its own parameters). Specifically, when the SoC chip receives a write operation test instruction, it performs the corresponding test and stores the test result data in a register. When it receives a read operation test instruction, it returns the data in the register to the test machine. The specific implementation process includes the following steps before step T3:

[0045] Step Y1: The SoC chip determines whether it needs to obtain its own parameter values ​​based on the test parameters in the register. If yes, it executes step Y2; otherwise, it executes step T3.

[0046] Specifically, step Y1 includes: the SoC chip determines whether the value at a preset position in the register is 0; if yes, it executes step Y2; otherwise, it executes step T3.

[0047] Step Y2: The SoC chip obtains its own parameter values ​​according to the test mode, replaces the values ​​at the corresponding positions in the register with its own parameter values, sets the enable test bit in the register to the first preset value, and returns to step T1.

[0048] Step T4: The SoC chip obtains the data in the corresponding register according to the test mode, and after waiting for one switching cycle, returns the obtained data to the test machine through the TCLK pin and TIO pin.

[0049] In this embodiment, the acquired data is returned to the test machine via the TCLK and TIO pins. This includes: the SoC chip sequentially outputting a corresponding level to the test machine via the TIO pin according to the value of each bit of the acquired data. The level output by the TIO pin changes on the rising edge of the TCLK pin level. Specifically, if the bit value is 1, the SoC chip outputs a high level to the test machine via the TIO pin on the rising edge of the TCLK pin level; if the bit value is 0, the SoC chip outputs a low level to the test machine via the TIO pin on the rising edge of the TCLK pin level.

[0050] In this embodiment, after each test instruction is completed, the chip is powered off and then powered on again. After the chip is powered on, the TCLK pin is pulled down to a low level by default, and the TIO pin is pulled up to a high level by default. At the same time, the tester controls TCLK to toggle from low to high, and controls TIO to send the next test instruction bit by bit on the falling edge of the TCLK pin level.

[0051] The method in this embodiment also includes the operation of the testing machine, specifically including:

[0052] Step S1: The test machine receives the raw data to be tested input by the user and sets the corresponding test mode in the instruction header according to the mode data in the raw data to be tested;

[0053] Step S2: The test machine determines whether the register operation in the original data to be tested is a write to the register. If yes, proceed to step S3; otherwise, proceed to step S5.

[0054] Step S3: The test machine sets the read / write selection bit in the instruction header to the first preset value, determines the length of the data field according to the test mode, obtains the storage status of the registers in the SoC chip according to the test mode, configures the data field using the test parameters in the original data to be tested according to the storage status and the length of the data field, and assembles the test instruction according to the instruction header and the data field.

[0055] Step S4: The test machine sends test commands to the SoC chip through the TCLK and TIO pins, and receives the test result data returned by the SoC chip through the TIO pin;

[0056] Specifically, the tester sends test commands to the SoC chip through the TCLK and TIO pins, including: the tester sequentially outputs the corresponding level to the SoC chip through the TIO pin according to the value of each bit in the test command, and the level output by the TIO pin changes on the falling edge of the TCLK pin level;

[0057] Optionally, receiving the test result data returned by the SoC chip through the TIO pin in step S4 includes: the tester determining whether a change in the TIO pin level is detected within a preset time; if yes, the test result data is obtained as a successful test, otherwise the test result data is obtained as a failed test; or, the tester determining whether a change in the TIO pin level is detected within a preset time; if yes, the TIO pin level is detected to obtain the test item value, otherwise the test fails.

[0058] Step S5: The test machine sets the read / write selection bit in the instruction header to the second preset value and assembles the test instruction according to the instruction header;

[0059] Step S6: The test machine sends the test command to the SoC chip through the TCLK and TIO pins, and after waiting for one switching cycle, it receives the test result data returned by the SoC chip through the TCLK and TIO pins.

[0060] Specifically, the process of sending the test command in step S6 is the same as in step S4, and will not be repeated here;

[0061] In this embodiment, step S6, receiving the test result data returned by the SoC chip through the TCLK pin and TIO pin, includes: the test machine determines the length of the test item information according to the test mode, samples the level output by the TIO pin sequentially at each falling edge of the TCLK pin level, stores the sampling results sequentially from low bit to high bit, and the sampling ends when the number of sampling results reaches the length of the test item information, and obtains the test item information based on the stored data.

[0062] Optionally, in this embodiment, after the test machine sends the write operation test instruction, it waits for a first preset time before sending the read operation test instruction. When the chip receives the write operation test instruction sent by the test machine, it obtains its own parameter value according to the test mode and writes it into the register. When it receives the read instruction, it returns the data in the register to the test machine. That is, before step S4, the test machine also includes: determining whether the SoC chip needs to obtain its own parameter value according to the test parameters in the data field. If so, it sends the test instruction to the SoC chip through the TCLK pin and TIO pin, waits for a first preset time, and then returns to step S1; otherwise, it executes step S4.

[0063] The test machine determines whether the SoC chip needs to obtain its own parameter values ​​based on the test parameters in the data field. This includes: the test machine determining whether the value at a preset position in the data field is 0. If it is, the test machine determines that the SoC chip needs to obtain its own parameter values; otherwise, the test machine determines that the SoC chip does not need to obtain its own parameter values.

[0064] This application adopts a two-wire wafer testing method, which is suitable for small chips with few pins. It enables the simultaneous testing of multiple small chips on a testing machine, reducing testing costs and making it convenient to use. Example 2

[0065] Embodiment 2 of this invention provides a wafer testing method for a SoC chip. This application implements a two-wire wafer testing method. The test machine organizes test instructions according to the storage state of the SoC chip registers and sends the test instructions to the instruction decoding module of the SoC chip through the TCLK pin level and the TIO pin level. The instruction decoding module of the SoC chip receives and parses the test instructions. If it is a write instruction, the data field output by the TIO pin level is stored in the register, and the test is performed according to the test instruction. After the test is completed, the test result data is output to the test machine through the TIO pin level. If it is a read instruction, the data in the register is sent to the test machine bit by bit through the TCLK pin level and the TIO pin level. The specific working principle is as follows: Figure 3 As shown, the data transmission process of the test machine is as follows: at the falling edge of the TCLK pin level, a high level (1) or a low level (0) is output through the TIO pin. The data reception process is as follows: at the falling edge of the TCLK pin level, the level of the TIO pin is sampled. If it is high, 1 is received; if it is low, 0 is received. The data reception process of the SoC chip is as follows: at the rising edge of the TCLK pin level, the level of the TIO pin is sampled. If it is high, 1 is received; if it is low, 0 is received. The data transmission process is as follows: when the TCLK pin level is in the rising edge state, a high level (1) or a low level (0) is output through the TIO pin.

[0066] The formats for test read and test write commands are as follows: Figure 4As shown, in this embodiment, the test write instruction includes an instruction header and a data field, and the test read instruction includes an instruction header. The instruction header includes a start bit, a read / write selection bit, and a test mode. The start bit is fixed at 0 and has a length of 1 bit. The read / write selection bit has a length of 1 bit and is used to identify the operation type; 0 indicates a write operation (writing data to the chip), and 1 indicates a read operation (reading data from the chip). The test mode has a length of 3 bits and is used to identify the test item; 000 indicates a voltage test, 001 indicates a temperature test, and 010 indicates an oscillator test. The specific content of the data field can be set according to actual needs, and its length is ≤32 bits.

[0067] like Figure 5 As shown, the working method of the testing machine in this embodiment includes:

[0068] Step 101: The tester receives the raw data to be tested input by the user, and determines the type of mode data in the raw data to be tested. If it is voltage, proceed to step 102; if it is temperature, proceed to step 108; if it is an oscillator, proceed to step 114.

[0069] In this embodiment, the raw data to be tested includes pattern data, register operations (read / write operations), and test parameters;

[0070] Step 102: The test machine sets the highest bit in the instruction header to 0 and the test mode to 000. It then determines whether the register operation in the original data to be tested is a write register. If yes, it executes step 103; otherwise, it executes step 106.

[0071] Step 103: The tester sets the read / write selection bit in the instruction header to 0, determines the length of the data field to be 17 bits according to the voltage test mode, obtains the storage status of the voltage test register in the SoC chip according to the voltage test mode, configures the data field using the test parameters in the original data to be tested according to the storage status and the length of the data field, and generates a voltage test write instruction according to the instruction header and the data field.

[0072] In this embodiment, the storage states of the registers corresponding to different test modes are different, such as... Figure 6As shown, the voltage test register corresponding to the voltage test mode has a capacity of 17 bits. The stored data content from low to high bits is as follows: 1 bit of enable test TEN (1 indicates test has started, 0 indicates test has not started), 3 bits of voltage output selection VD_OUTSEL, used to identify the type of test signal (000 indicates the test signal is VDH), 2 bits of fine-tuning value TRIM, 4 bits of low control parameter VDLC, 4 bits of high control parameter VDHC, 1 bit of reset signal RESEN (1 indicates the voltage module is working normally, 0 indicates the voltage module is not working normally), and 2 bits of voltage IP enable VD_EN (01 indicates the voltage module is enabled, 00 indicates the voltage module is not enabled).

[0073] Correspondingly, such as Figure 7 As shown, the voltage test write instruction includes a 5-bit instruction header (00000) + a 17-bit data field, and the length of the voltage test write instruction is 22 bits.

[0074] Based on the storage state and the length of the data field, the test parameters in the raw data to be tested are used to configure the data field. For example, the voltage IP enable VD_EN is configured as 01, the reset signal RESEN is configured as 1, the high control parameter VDHC is configured as 0111, the low control parameter VDLC is configured as 0000, the fine-tuning value TRIM is configured as 01, the voltage output selection VD_OUTSEL is configured as 000, and the test enable TEN is configured as 1. That is, in this step, the voltage test write instruction generated according to the instruction header and the data field is: 0000001101110000010001, and the SoC chip performs high voltage testing.

[0075] Step 104: The tester sends a voltage test write command to the SoC chip via the TCLK and TIO pins and begins monitoring the changes in the TIO pin level.

[0076] In this embodiment, the tester sends a voltage test write command to the SoC chip via the TCLK and TIO pins. Specifically, the tester sequentially outputs a corresponding level to the SoC chip via the TIO pin based on the value of each bit of the voltage test write command. The level output by the TIO pin changes on the falling edge of the TCLK pin level. For example, if the bit value is 1, the TIO pin outputs a high level to the SoC chip on the falling edge of the TCLK pin output level; if the bit value is 0, the TIO pin outputs a low level to the SoC chip on the falling edge of the TCLK pin output level. The timing of the transmission process is as follows: Figure 8 As shown;

[0077] Step 105: The tester determines whether a low level is detected at the TIO pin within a preset time. If yes, the voltage test result data is obtained as a successful test; otherwise, the voltage test result data is obtained as a failed test.

[0078] For example, the preset time in this embodiment is 10ms; the TIO pin is high level by default, and the VDH signal is output through the TIO pin in step 105. If the VDH signal is low level, it means that the voltage test is successful.

[0079] Step 106: The tester sets the read / write selection bit in the instruction header to 1, generates a voltage test read instruction based on the instruction header, and sends the voltage test read instruction to the SoC chip through the TCLK pin and TIO pin;

[0080] In this embodiment, the voltage test read command is as follows: Figure 7 As shown, it includes: a 5-bit instruction header 01000. The transmission process of the voltage test read instruction is the same as step 104, and will not be repeated here. The timing of the transmission process is as follows: Figure 8 As shown;

[0081] Step 107: The tester waits for one switching cycle, determines the voltage information length to be 17 bits according to the voltage test mode, samples the level of the TIO pin sequentially on each falling edge of the TCLK pin level, stores the sampling results sequentially from low bit to high bit, until the number of sampling results reaches 17, and the sampling ends. The voltage information is obtained from the stored data.

[0082] In this embodiment, the tester sends a voltage test read command (including start bit, read / write selection bit, and test mode) through the TIO pin on the falling edge of the TCLK pin level. After waiting for one toggling cycle (the size of the toggling cycle can be set as needed), the tester receives and stores the data returned by the SoC chip through the TCLK pin level and the TIO pin level. For example, the tester starts sampling the TIO pin level on the 8th falling edge of the TCLK pin level and stores the sampling results sequentially from low bit to high bit. Specifically, if the sampling result is high, 1 is stored sequentially from low bit to high bit; if the sampling result is low, 0 is stored sequentially from low bit to high bit. When the number of sampling results reaches 17, the sampling ends, and the voltage information is obtained based on the stored data.

[0083] Step 108: The test machine sets the highest bit in the instruction header to 0 and the test mode to 001. It then determines whether the register operation in the original data to be tested is a write register. If yes, it executes step 109; otherwise, it executes step 112.

[0084] Step 109: The test machine sets the read / write selection bit in the instruction header to 0, determines the length of the data field to be 13 bits according to the temperature test mode, obtains the storage status of the temperature test register in the SoC chip according to the temperature test mode, configures the data field using the test parameters in the original data to be tested according to the storage status and the length of the data field, and generates a temperature test write instruction according to the instruction header and the data field.

[0085] In this embodiment, the storage states of the registers corresponding to different test modes are different, such as... Figure 6 As shown, the temperature test register corresponding to the temperature test mode has a capacity of 13 bits. The stored data content from low to high bits is as follows: 1 bit of enable test TEN (1 indicates test started, 0 indicates test not started), 3 bits of voltage output selection TD_OUTSEL, used to identify the type of test signal (000 indicates test signal is TDH), 3 bits of low control parameter TDLC, 4 bits of high control parameter TD_HC, and 2 bits of temperature IP enable TD_EN (01 indicates temperature module is on, 00 indicates temperature module is not on).

[0086] Correspondingly, such as Figure 7 As shown, the temperature test write instruction includes a 5-bit instruction header (00001) + a 13-bit data field, and the length of the temperature test write instruction is 18 bits.

[0087] In step 109, the data field is configured using the test parameters in the original data to be tested according to the storage status and the length of the data field. For example, the temperature IP enable TD_EN is configured to 01, the high control parameter TD_HC is configured to 1100, the low control parameter TDLC is configured to 000, the voltage output selection TD_OUTSEL is configured to 000, and the test enable TEN is configured to 1. That is, in this step, the temperature test write instruction generated according to the instruction header and the data field is: 000010111000000001, and the SoC chip performs high temperature testing.

[0088] Step 110: The test machine sends a temperature test write command to the SoC chip through the TCLK and TIO pins and begins to monitor the changes in the TIO pin level;

[0089] Specifically, the temperature test write command sending process in this step is the same as the voltage test write command sending process in step 104, and will not be repeated here. The specific timing of the sending process is as follows: Figure 8 As shown;

[0090] Step 111: The tester determines whether a low level is detected in the TIO pin output within a preset time. If yes, the temperature test result data is obtained as a successful test; otherwise, the temperature test result data is obtained as a failed test.

[0091] For example, the preset time in this embodiment is 10ms; the TIO pin is high by default, and the TDH signal is output through the TIO pin in step 111. If the TDH signal is low, it means that the temperature test is successful.

[0092] Step 112: The test machine sets the read / write selection bit in the instruction header to 1, generates a temperature test read instruction according to the instruction header, and sends the temperature test read instruction to the SoC chip through the TCLK pin and TIO pin;

[0093] In this embodiment, the temperature test read command is as follows: Figure 7 As shown, the 5-bit instruction header (01001) is included. The sending process of the temperature test read instruction is the same as the sending process of the voltage test write instruction in step 104, and will not be repeated here. The specific timing of the sending process is as follows: Figure 8 As shown;

[0094] Step 113: The tester waits for one switching cycle, determines the temperature information length to be 13 bits according to the temperature test mode, samples the level of the TIO pin on each falling edge of the TCLK pin, stores the sampling results sequentially from low bit to high bit, until the number of sampling results reaches 13, and the sampling ends. The temperature information is obtained from the stored data.

[0095] In this embodiment, the tester sends a temperature test read command (including start bit, read / write selection bit, and test mode) through the TIO pin on the falling edge of the TCLK pin level. After waiting for one toggling cycle (the size of the toggling cycle can be set as needed), the tester receives and stores the data returned by the SoC chip through the TCLK pin level and the TIO pin level. For example, the tester starts sampling the TIO pin level on the 8th falling edge of the TCLK pin level and stores the sampling results sequentially from low bit to high bit. Specifically, if the sampling result is high, 1 is stored sequentially from low bit to high bit; if the sampling result is low, 0 is stored sequentially from low bit to high bit. Sampling ends when the number of sampling results reaches 13, and the temperature information is obtained based on the stored data.

[0096] Step 114: The test machine sets the highest bit in the instruction header to 0 and the test mode to 010. It then determines whether the register operation in the original data to be tested is a write register. If yes, it executes step 115; otherwise, it executes step 118.

[0097] Step 115: The test machine sets the read / write selection bit in the instruction header to 0, determines the length of the data field to be 12 bits according to the oscillator test mode, determines the storage state of the oscillator test register in the SoC chip according to the oscillator test mode, configures the data field using the test parameters in the original data to be tested according to the storage state and the length of the data field, and generates the oscillator test write instruction according to the instruction header and the data field.

[0098] In this embodiment, the storage states of the registers corresponding to different test modes are different, such as... Figure 6 As shown, the oscillator test register corresponding to the oscillator test mode has a capacity of 12 bits. The stored data, from low to high, consists of: a 1-bit enable test TEN (e.g., 1 indicates test started, 0 indicates test not started), a 2-bit oscillator output selection OSC_OUTSEL, used to indicate the type of test signal (e.g., 00 indicates the output test signal is OSC_CLK, 11 indicates the oscillator frequency self-test function, without outputting a test feedback signal through TIO), and a 2-bit frequency division parameter OD (e.g., ...). 00 indicates that the clock output is not divided; 01 indicates that the clock output is divided. 1-bit oscillator enable EN (1 indicates oscillator enabled, 0 indicates oscillator not enabled), 1-bit reset signal RESET (0 indicates oscillator is working normally, 1 indicates oscillator is not working normally), 1-bit lock enable LC_EN (1 indicates oscillator LOCK signal can be output, 0 indicates oscillator LOCK signal cannot be output), 4-bit trimming value OSC_TRIM.

[0099] Correspondingly, such as Figure 7 As shown, the oscillator test write instruction includes a 5-bit instruction header (00010) + a 12-bit data field, and the length of the oscillator test write instruction is 17 bits.

[0100] In step 115, the data field is configured using the test parameters in the original data to be tested according to the storage state and the length of the data field. For example, the fine-tuning value OSC_TRIM is configured as 0111; the lock enable LC_EN is configured as 1; the reset signal RESET is configured as 0; the oscillator enable EN is configured as 1; the frequency division parameter OD is configured as 00; the oscillator output selection OSC_OUTSEL is configured as 00; and the test enable TEN is configured as 1. That is, in this step, the oscillator test write instruction generated according to the instruction header and the data field is: 00010011110100001. The SoC chip needs to output a frequency value that is 0111 greater than its own frequency.

[0101] Step 116: The test machine sends an oscillator test write command to the SoC chip through the TCLK and TIO pins and starts monitoring the changes in the TIO pin level;

[0102] Specifically, the oscillator test write command sending process in this step is the same as the voltage test write command sending process in step 104, and will not be repeated here. The timing sequence of the specific sending process is as follows: Figure 8 As shown;

[0103] Step 117: The tester determines whether a low level is detected on the TIO pin within a preset time. If so, the frequency of the TIO pin is detected, and the clock frequency of the TIO output is obtained based on the detected data. Otherwise, the oscillator test result data is obtained as a test failure.

[0104] The clock frequency in this step is the oscillator test result data. The test machine displays the clock frequency. If the tester determines that the clock frequency does not meet the error range, the relevant control signals in the test parameters of the original data to be tested are modified after the chip is restarted and input into the test machine. The test machine reorganizes the oscillator test write command and sends it to the SoC chip for retesting.

[0105] Step 118: The test machine sets the read / write selection bit in the instruction header to 1, generates an oscillator test read instruction according to the instruction header, and sends the oscillator test read instruction to the SoC chip through the TCLK pin and TIO pin;

[0106] In this embodiment, the oscillator test read command is as follows: Figure 7 As shown, the oscillator test read command sending process is the same as the voltage test write command sending process in step 104, including a 5-bit instruction header 01010. Therefore, it will not be repeated here. The specific timing of the sending process is as follows: Figure 8 As shown;

[0107] Step 119: The tester waits for one switching cycle, determines the oscillator information length to be 12 bits according to the oscillator test mode, samples the level of the TIO pin on each falling edge of the TCLK pin, stores the sampling results sequentially from low bit to high bit, until the number of sampling results reaches 12, and the sampling ends. The oscillator information is obtained from the stored data.

[0108] In this embodiment, the tester sends an oscillator test read command (including start bit, read / write selection bit, and test mode) through the TIO pin at the falling edge of the TCLK pin level. After waiting for one toggling cycle (the size of the toggling cycle can be set as needed), the tester receives and stores the data returned by the SoC chip through the TCLK pin level and the TIO pin level. For example, the tester starts sampling the TIO level at the 8th falling edge of the TCLK pin level and stores the sampling results sequentially from low bit to high bit. Specifically, if the sampling result is high, 1 is stored sequentially from low bit to high bit; if the sampling result is low, 0 is stored sequentially from low bit to high bit. When the number of sampling results reaches 12, the sampling ends, and the oscillator information is obtained based on the stored data.

[0109] like Figure 9 As shown, the operating method of the SoC chip in this embodiment includes:

[0110] Step 201: The SoC chip receives the instruction header of the test command sent by the test machine through the TCLK pin and TIO pin, parses the instruction header to obtain the test mode and read / write selection bit, and determines the type of test mode. If it is a voltage test, proceed to step 202; if it is a temperature test, proceed to step 206; if it is an oscillator test, proceed to step 210.

[0111] In this embodiment, the instruction header is 5 bits long and includes: the start bit of the highest bit, the read / write selection bit of the second highest bit, and the test mode of the lowest 3 bits.

[0112] Specifically, in this embodiment, step 201 includes: the SoC chip samples the TIO pin level at the rising edge of the TCLK pin level within 5 cycles, obtains the instruction header of the test instruction based on all sampling results, obtains the value of the test mode from the 3-bit low-order data in the instruction header, and determines the type of test mode based on the value of the test mode. For example, if the value of the test mode is 000, the test mode is voltage test, and step 202 is executed; if the value of the test mode is 001, the test type is temperature test, and step 206 is executed; if the value of the test mode is 010, the test type is oscillator test, and step 211 is executed.

[0113] Step 202: The SoC chip determines whether the read / write selection bit is 0. If yes, proceed to step 203; otherwise, proceed to step 205.

[0114] Specifically, in this embodiment, step 202 includes: the SoC chip determines whether the value of the second highest bit in the instruction header is 0; if yes, it executes step 203; otherwise, it executes step 205.

[0115] Step 203: The SoC chip continues to receive the data field of the voltage test command through the TCLK and TIO pins and stores it in the voltage test register. It determines whether the least significant bit in the voltage test register is 1. If yes, proceed to step 204; otherwise, the test ends.

[0116] Specifically, in this embodiment, step 203 includes: the SoC chip determines that the length of the data field of the voltage test instruction is 17 bits according to the voltage test, samples the level of the TIO pin at the rising edge of the TCLK pin, stores the sampling result in the voltage test register, and the sampling ends when the number of sampling results reaches 17. It then determines whether the value of the lowest bit in the voltage test register is 1. If yes, step 204 is executed; otherwise, the test ends.

[0117] Step 204: The SoC chip continuously receives external voltage, determines the voltage test standard based on the data in the voltage test register, and controls the TIO pin level to change and outputs it to the test machine when the external voltage reaches the voltage test standard.

[0118] For example, the data in the voltage test register is related to 3.5V, which means that the chip is required to alarm when the voltage is 3.5V. When the externally supplied voltage reaches 3.5V, the SoC chip outputs VDH low level through the TIO pin (the TIO pin level is high level by default, and low level is valid).

[0119] Step 205: The SoC chip obtains 17 bits of data from the voltage test register, waits for one switching cycle, and then returns the obtained data to the test machine through the TCLK pin and the TIO pin.

[0120] In this embodiment, if the tester does not receive test result data after sending the voltage test write command, it will send the voltage test read command again to confirm whether the SoC chip has successfully written the data field to the register after receiving the voltage test write command. If the data is successfully written to the register, the SoC chip will obtain the data from the voltage test register after receiving the voltage test read command.

[0121] Optionally, the size of the turning cycle in this embodiment can be set according to actual needs;

[0122] In this embodiment, the acquired 17-bit data is returned to the test machine via the TCLK pin and the TIO pin. This includes: the SoC chip sequentially outputs the corresponding level to the test machine via the TIO pin according to the value of each bit of the acquired 17-bit data. The level output by the TIO pin changes on the rising edge of the TCLK pin level. Specifically, if the value of the bit is 1, the SoC chip outputs a high level to the test machine via the TIO pin on the rising edge of the TCLK pin level; if the value of the bit is 0, the SoC chip outputs a low level to the test machine via the TIO pin on the rising edge of the TCLK pin level.

[0123] Step 206: The SoC chip determines whether the read / write selection bit is 0. If yes, proceed to step 207; otherwise, proceed to step 209.

[0124] In this embodiment, the implementation process of this step is the same as that of step 202, and will not be repeated here;

[0125] Step 207: The SoC chip continues to receive the data field of the temperature test write command through the TCLK pin and TIO pin and stores it in the temperature test register. It determines whether the least significant bit data in the temperature test register is 1. If yes, proceed to step 208; otherwise, the test ends.

[0126] Specifically, in this embodiment, step 207 includes: the SoC chip determines that the length of the data field of the temperature test instruction is 13 bits according to the temperature test, samples the TIO pin level at the rising edge of the TCLK pin level, stores the sampling result in the temperature test register, and the sampling ends when the number of sampling results reaches 13. It then determines whether the value of the least significant bit in the temperature test register is 1. If yes, step 208 is executed; otherwise, the test ends.

[0127] Step 208: The SoC chip continuously receives the external temperature, determines the temperature test standard based on the data in the temperature test register, and controls the TIO pin level to change and outputs it to the test machine when the external temperature reaches the temperature test standard.

[0128] For example, the temperature test result data output in this step is TDH, and the data in the temperature test register is the relevant parameters of 90℃. That is, the chip is required to alarm when the temperature reaches 90℃. When the external temperature reaches 90℃, the SoC chip outputs TDH as low level through the TIO pin (the TIO pin level is high level by default, and low level is valid).

[0129] Step 209: The SoC chip obtains 13 bits of data from the temperature test register, waits for one switching cycle, and then returns the obtained data to the test machine through the TCLK pin and the TIO pin.

[0130] In this embodiment, the implementation process of this step is the same as that of step 205, and will not be repeated here;

[0131] Step 210: The SoC chip determines whether the read / write selection bit is 0. If yes, proceed to step 211; otherwise, proceed to step 213.

[0132] In this embodiment, the implementation process of this step is the same as that of step 202, and will not be repeated here;

[0133] Step 211: The SoC chip continues to receive the data field of the oscillator test write instruction through the TCLK pin and TIO pin and stores it in the oscillator test register. It determines whether the least significant bit data in the oscillator test register is 1. If yes, it executes step 212; otherwise, the test ends.

[0134] Specifically, in this embodiment, step 211 includes: the SoC chip determines that the length of the data field of the oscillator test instruction is 12 bits according to the oscillator test, samples the TIO pin level at the rising edge of the TCLK pin level, stores the sampling result in the oscillator test register, and the sampling ends when the number of sampling results reaches 12. It then determines whether the value of the lowest bit in the oscillator test register is 1. If yes, step 212 is executed; otherwise, the test ends.

[0135] Step 212: The SoC chip transmits the control signal in the oscillator test register to the internal oscillator. The oscillator outputs the corresponding clock frequency to the SoC chip according to the control signal. The SoC chip outputs the corresponding level to the test machine through the TIO pin according to the clock frequency.

[0136] In this embodiment, the level output by the TIO pin is the clock signal OSC_CLK;

[0137] Step 213: The SoC chip obtains 12 bits of data from the oscillator test register, waits for one switching cycle, and then returns the obtained data to the test machine through the TCLK pin and the TIO pin;

[0138] In this embodiment, the implementation process of this step is the same as that of step 205, and will not be repeated here.

[0139] In this embodiment, after the voltage test write command, voltage test read command, temperature test write command, temperature test read command, oscillator test write command, or oscillator test read command are completed, the chip is powered off and then powered on again. After the chip is powered on, the TCLK pin is pulled down to a low level by default, and the TIO pin is pulled up to a high level by default. At the same time, the tester controls the TCLK pin to toggle from a low level to a high level, and sends the next test command bit by bit through the TIO pin level on the falling edge of the TCLK pin level.

[0140] Optionally, in this embodiment, the chip oscillator can also perform self-testing (i.e., acquire its own frequency). The specific implementation process is as follows: The test machine assembles an oscillator test write command (00010 011110100111, where the oscillator output selection OSC_OUTSEL is set to 11, indicating the oscillator frequency self-test function, without outputting a test feedback signal via TIO) and sends it to the SoC chip. The test machine waits for a preset duration (e.g., 10ms) before assembling an oscillator test read command (01010) and sending it to the chip. After receiving the oscillator test write command, the SoC chip writes the data field of the oscillator test write command into the oscillator register. The SoC chip obtains the oscillator's own clock frequency parameters and replaces them with the configuration fine-tuning value OSC_TRIM in the oscillator register, modifying the enable test TEN in the oscillator register to 0. Upon receiving the oscillator read test command, the chip obtains 12 bits of data from the oscillator test register and returns the obtained data to the test machine after one clock cycle. After the test, the SoC chip performs the next round of testing after power-down and power-on. Example 3

[0141] Embodiment 3 of the present invention provides a wafer testing device for a SoC chip, including an instruction decoding module and a register;

[0142] The instruction decoding module includes:

[0143] The receiving and judging unit is used to receive the instruction header of the test instruction sent by the test machine through the TCLK pin and TIO pin, determine the test mode according to the instruction header, and judge whether the read / write selection bit in the instruction header is the first preset value. If it is, the receiving and storing judging unit is triggered; otherwise, the obtaining and returning unit is triggered.

[0144] The receive storage judgment unit is used to continue receiving the data field of the test instruction through the TCLK pin and TIO pin, and store the data field into the register corresponding to the test mode. It determines whether to perform the test based on the value of the enable test bit in the register. If yes, the test unit is triggered; otherwise, the test ends.

[0145] The test unit is used to perform tests based on the test mode and the test parameters in the register;

[0146] The return unit is used to return the test result data of the test unit to the test machine via the TIO pin;

[0147] The return unit is used to retrieve data from the corresponding register according to the test mode, and after waiting for one switching cycle, the retrieved data is returned to the test machine through the TCLK and TIO pins.

[0148] The wafer testing apparatus in this embodiment further includes: a testing machine that interacts with the instruction decoding module, the testing machine specifically including:

[0149] The receiving organization unit is used to receive the raw data to be tested input by the user and set the corresponding test mode in the instruction header according to the pattern data in the raw data to be tested.

[0150] In this embodiment, the instruction header is 5 bits long and includes: the start bit of the highest bit, the read / write selection bit of the second highest bit, and the test mode of the lowest 3 bits.

[0151] The first judgment unit is used to determine whether the register operation in the original data to be tested is a write register. If it is, the first setting and assembly unit is triggered; otherwise, the second setting and assembly unit is triggered.

[0152] The first setup and assembly unit is used to set the read / write selection bit in the instruction header to a first preset value, determine the length of the data field according to the test mode, obtain the storage status of the registers in the SoC chip according to the test mode, configure the data field using the test parameters in the original data to be tested according to the storage status and the length of the data field, and compose a test instruction according to the instruction header and the data field.

[0153] The first transmitting and receiving unit is used to send test commands to the command decoding module through the TCLK pin and the TIO pin, and to receive test result data returned by the command decoding module through the TIO pin.

[0154] The second assembly unit is used to set the read / write selection bit in the instruction header to a second preset value and assemble test instructions according to the instruction header.

[0155] The second transmitting and receiving unit is used to send test commands to the command decoding module through the TCLK and TIO pins, and receive the test result data returned by the command decoding module through the TCLK and TIO pins after waiting for one switching cycle.

[0156] In this embodiment, the first or second transmitting / receiving unit sends the test command to the instruction decoding module via the TCLK and TIO pins. This includes: the first or second transmitting / receiving unit sequentially outputting the corresponding level to the instruction decoding module via the TIO pin according to the value of each bit in the test command. The TIO pin level changes on the falling edge of the TCLK pin level. Specifically, if the bit value is 1, a high level is output to the instruction decoding module via the TIO pin on the falling edge of the TCLK pin level; if the bit value is 0, a low level is output to the instruction decoding module via the TIO pin on the falling edge of the TCLK pin level.

[0157] Optionally, in this embodiment, the first transmitting and receiving unit receives the test result data returned by the SoC chip through the TIO pin. Specifically, the first transmitting and receiving unit determines whether a change in the TIO pin level is detected within a preset time. If so, the test result data is obtained as a successful test; otherwise, the test result data is obtained as a failed test.

[0158] Optionally, in this embodiment, the first transmitting and receiving unit receives the test result data returned by the SoC chip through the TIO pin. Specifically, the first transmitting and receiving unit determines whether a change in the TIO pin level is detected within a preset time. If so, the TIO pin level is detected to obtain the test item value; otherwise, the test fails.

[0159] In this embodiment, the second transmitting and receiving unit receives the test result data returned by the SoC chip through the TCLK pin and the TIO pin. Specifically, the second transmitting and receiving unit determines the length of the test item information according to the test mode, samples the level output by the TIO pin sequentially at each falling edge of the TCLK pin level, stores the sampling results sequentially from low bit to high bit, and ends sampling when the number of sampling results reaches the length of the test item information. The test item information is obtained based on the stored data.

[0160] In this embodiment, the receiving judgment unit is specifically used to sample the TIO pin level on the rising edge of the TCLK pin level within 5 cycles, obtain the instruction header of the test instruction based on all sampling results, obtain the value of the test mode from the 3 bits of low-order data in the instruction header, determine the corresponding test mode based on the value of the test mode, and determine whether the value of the second highest bit in the test instruction is the first preset value. If it is, the receiving storage judgment unit is triggered; otherwise, the acquisition return unit is triggered.

[0161] In this embodiment, the receiving and storage judgment unit is specifically used to determine the length of the data field of the test instruction according to the test mode, sample the TIO pin level on the rising edge of the TCLK pin level, and store the sampling results sequentially into the register corresponding to the test mode until the number of sampling results reaches the length of the data field and the sampling ends. It then determines whether the value of the lowest bit in the register is the second preset value. If it is, the test unit is triggered; otherwise, the test ends.

[0162] Optionally, the apparatus in this embodiment may further include a feedback processing module;

[0163] The test unit is specifically used to transmit control signals from the register to the feedback processing module;

[0164] The feedback processing module is used to receive control signals output by the test unit, perform corresponding tests according to the control signals, and output test result data to the return unit.

[0165] The return unit is also used to output test result data to the test machine via the TIO pin.

[0166] Optionally, the test unit is specifically used to continuously receive values ​​of externally provided test items and determine the test standard based on the data in the register;

[0167] The return unit is specifically used to control the TIO pin level to change and output to the test machine when the value of the test item reaches the test standard.

[0168] In this embodiment, the acquisition return unit returns the acquired data to the test machine through the TCLK pin and the TIO pin. Specifically, the acquisition return unit outputs the corresponding level to the test machine through the TIO pin according to the value of each bit of the acquired data. The TIO pin level changes on the rising edge of the TCLK pin level. Specifically, if the value of the bit is 1, a high level is output to the test machine through the TIO pin on the rising edge of the TCLK pin level; if the value of the bit is 0, a low level is output to the test machine through the TIO pin on the rising edge of the TCLK pin level.

[0169] In this embodiment, the instruction decoding module further includes: a first judgment unit, used to determine whether it is necessary to obtain its own parameter value based on the test parameters in the register; if so, the acquisition and replacement setting unit is triggered; otherwise, the test unit is triggered.

[0170] The replacement setting unit obtains its own parameter value according to the test mode, replaces the value at the corresponding position in the register with its own parameter value, sets the enable test bit in the register to the first preset value, and triggers the receiving judgment unit.

[0171] Correspondingly, the test machine also includes a judgment and transmission unit, which is used to determine whether the SoC chip needs to obtain its own parameter values ​​based on the test parameters in the data field. If so, the test command is sent to the instruction decoding module through the TCLK pin and TIO pin, and the receiving organization unit is triggered after waiting for a first preset time. Otherwise, the first transmission and reception unit is triggered.

[0172] This application implements wafer testing via two lines, making it suitable for chiplet testing. It increases the number of chips that can be tested simultaneously, improves wafer testing efficiency, and reduces the dependence of wafer testing on the number of chip pins. Using the chip design of this application reduces the number of test pins and chip area, lowers chip manufacturing costs, and meets the needs of electronic products for multifunctionality and size. Furthermore, in this application, users can set the data format in the test register as needed. Compared to the CPU's built-in debug interface protocol, the instruction format has fewer bits and a faster single-transmission rate, further improving wafer testing efficiency.

[0173] In this embodiment, the TCLK and TIO pins can be reused after the wafer is packaged into a chip and used as other functional pins. Furthermore, the technical solution of transmitting clock signals with the TCLK pin and transmitting data signals with the TIO pin in this embodiment is not limited to test application scenarios, but can also be applied to other data communication application scenarios.

[0174] Optionally, embodiments of this application also provide an electronic device, which includes at least one processor, a memory, and instructions stored in the memory and executable by the at least one processor. The at least one processor executes the instructions to implement the wafer testing method for the SoC chip in the above embodiments. When the electronic device is a chip system, it can be composed of chips or may include chips and other discrete devices; embodiments of this application do not specifically limit this. The chip is coupled to the memory and is used to execute the computer program stored in the memory to perform the wafer testing method for the SoC chip disclosed in the above embodiments.

[0175] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be entirely or partially in the form of a computer program product. This computer program product includes one or more computer programs. When the computer program is loaded and executed on an electronic device, all or part of the processes or functions described in the embodiments of this application are generated. The computer program can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one base station, electronic device, server, or data center to another via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to the electronic device or a data storage device including one or more servers, data centers, etc., that can be integrated using media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)). In the embodiments of this application, the electronic device may include the aforementioned apparatus.

[0176] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0177] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of this application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.

Claims

1. A wafer testing method for a SoC chip, characterized in that, The method includes: Step T1: The SoC chip receives the instruction header of the test command sent by the test machine through the TCLK pin and TIO pin, determines the test mode according to the instruction header, and determines whether the read / write selection bit in the instruction header is the first preset value. If yes, proceed to step T2; otherwise, proceed to step T4. Step T2: The SoC chip continues to receive the data field of the test instruction through the TCLK pin and the TIO pin, and stores the data field in the register corresponding to the test mode. It determines whether to perform the test based on the value of the enable test bit in the register. If yes, it executes step T3; otherwise, the test ends. Step T3: The SoC chip performs tests according to the test mode and the test parameters in the register, and returns the test result data to the test machine through the TIO pin; Step T4: The SoC chip obtains the data in the corresponding register according to the test mode, and after waiting for one switching cycle, returns the obtained data to the test machine through the TCLK pin and the TIO pin; Step T1 includes: the SoC chip samples the TIO pin level at the rising edge of the TCLK pin level within 5 cycles, obtains the instruction header of the test instruction based on all sampling results, obtains the value of the test mode from the 3 bits of low-order data in the instruction header, determines the corresponding test mode based on the value of the test mode, and determines whether the value of the second highest bit in the test instruction is the first preset value. If yes, step T2 is executed; otherwise, step T4 is executed.

2. The method as described in claim 1, characterized in that, The instruction header is 5 bits long and includes: a start bit (highest bit), a read / write select bit (second highest bit), and a test mode (lowest 3 bits).

3. The method as described in claim 1, characterized in that, Step T2 includes: the SoC chip determines the length of the data field of the test instruction according to the test mode, samples the level of the TIO pin at the rising edge of the TCLK pin level, stores the sampling results sequentially into the register corresponding to the test mode, and the sampling ends when the number of sampling results reaches the length of the data field. It then determines whether the least significant bit in the register is a second preset value. If yes, step T3 is executed; otherwise, the test ends.

4. The method as described in claim 1, characterized in that, Step T3 includes: the SoC chip transmits the control signal in the register to the corresponding test module according to the test mode; the test module performs corresponding tests according to the control signal and outputs the test item value; and the SoC chip outputs the corresponding level to the test machine through the TIO pin according to the test item value.

5. The method as described in claim 1, characterized in that, Step T3 includes: the SoC chip continuously receives the values ​​of externally provided test items, determines the test standard value based on the data in the register, and controls the TIO pin level to change and outputs it to the test machine when the value of the test item reaches the test standard value.

6. The method as described in claim 1, characterized in that, The step T4, in which the acquired data is returned to the test machine via the TCLK pin and the TIO pin, includes the following: the SoC chip sequentially outputs a corresponding level to the test machine via the TIO pin according to the value of each bit of the acquired data, and the level output by the TIO pin changes on the rising edge of the TCLK pin level.

7. The method as described in claim 1, characterized in that, The process preceding step T3 also includes: Step Y1: The SoC chip determines whether it needs to obtain its own parameter value based on the test parameters in the register. If yes, it executes step Y2; otherwise, it executes step T3. Step Y2: The SoC chip obtains its own parameter value according to the test mode, replaces the value at the corresponding position in the register with its own parameter value, sets the enable test bit in the register to the first preset value, and returns to step T1.

8. The method as described in claim 1, characterized in that, The method further includes: Step S1: The test machine receives the raw data to be tested input by the user, and sets the corresponding test mode in the instruction header according to the mode data in the raw data to be tested; Step S2: The test machine determines whether the register operation in the original data to be tested is a write register. If yes, it executes step S3; otherwise, it executes step S5. Step S3: The test machine sets the read / write selection bit in the instruction header to a first preset value, determines the length of the data field according to the test mode, obtains the storage status of the registers in the SoC chip according to the test mode, configures the data field using the test parameters in the original data to be tested according to the storage status and the length of the data field, and composes a test instruction according to the instruction header and the data field. Step S4: The test machine sends the test command to the SoC chip through the TCLK pin and the TIO pin, and receives the test result data returned by the SoC chip through the TIO pin; Step S5: The test machine sets the read / write selection bit in the instruction header to a second preset value and assembles test instructions according to the instruction header; Step S6: The test machine sends the test command to the SoC chip through the TCLK pin and the TIO pin, and after waiting for one switching cycle, receives the test result data returned by the SoC chip through the TCLK pin and the TIO pin.

9. The method as described in claim 8, characterized in that, The test machine sends the test command to the SoC chip through the TCLK pin and the TIO pin, including: the test machine sequentially outputs the corresponding level to the SoC chip through the TIO pin according to the value of each bit in the test command, and the level output by the TIO pin changes on the falling edge of the TCLK pin level.

10. The method as described in claim 8, characterized in that, The step S4, receiving the test result data returned by the SoC chip through the TIO pin, includes: the test machine determining whether a change in the TIO pin level is detected within a preset time; if yes, the test result data is obtained as a successful test; otherwise, the test result data is obtained as a failed test.

11. The method as described in claim 8, characterized in that, The step S4, receiving the test result data returned by the SoC chip through the TIO pin, includes: the test machine determining whether a change in the TIO pin level is detected within a preset time; if so, the TIO pin level is detected to obtain the test item value; otherwise, the test fails.

12. The method as described in claim 8, characterized in that, The step S6, which involves receiving the test result data returned by the SoC chip via the TCLK pin and the TIO pin, includes: the test machine determining the length of the test item information according to the test mode, sampling the level output by the TIO pin sequentially at each falling edge of the TCLK pin level, storing the sampling results sequentially from low bit to high bit, until the number of sampling results reaches the length of the test item information, and obtaining the test item information based on the stored data.

13. The method as described in claim 8, characterized in that, Before step S4, the test machine further includes: determining whether the SoC chip needs to obtain its own parameter values ​​based on the test parameters in the data field. If so, the test machine sends the test command to the SoC chip through the TCLK pin and the TIO pin, waits for a first preset time, and then returns to step S1; otherwise, it executes step S4.

14. A wafer testing apparatus for a SoC chip, characterized in that, Includes instruction decoding module and registers; The instruction decoding module includes: The receiving and judging unit is used to receive the instruction header of the test instruction sent by the test machine through the TCLK pin and TIO pin, determine the test mode according to the instruction header, and judge whether the read / write selection bit in the instruction header is a first preset value. If it is, the receiving and storing judging unit is triggered; otherwise, the obtaining and returning unit is triggered. The receiving and storing judgment unit is used to continue receiving the data field of the test instruction through the TCLK pin and the TIO pin, and store the data field in the register corresponding to the test mode. It determines whether to perform the test based on the value of the enable test bit in the register. If yes, the test unit is triggered; otherwise, the test ends. The test unit is used to perform tests according to the test mode and the test parameters in the register; The return unit is used to return the test result data of the test unit to the test machine through the TIO pin; The acquisition and return unit is used to acquire data in the corresponding register according to the test mode, and after waiting for one switching cycle, return the acquired data to the test machine through the TCLK pin and the TIO pin; The receiving judgment unit is specifically used to sample the TIO pin level on the rising edge of the TCLK pin level within 5 cycles, obtain the instruction header of the test instruction based on all sampling results, obtain the value of the test mode from the 3 bits of low-order data in the instruction header, determine the corresponding test mode based on the value of the test mode, and determine whether the value of the second highest bit in the test instruction is the first preset value. If it is, the receiving storage judgment unit is triggered; otherwise, the acquisition return unit is triggered.

15. An electronic device, characterized in that, The electronic device includes at least one processor, a memory, and instructions stored in the memory and executable by the at least one processor, wherein the at least one processor executes the instructions to implement the method according to any one of claims 1 to 13.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a computer program that, when run on an electronic device, causes the electronic device to perform the method as described in any one of claims 1 to 13.

17. A chip system, characterized in that, The device includes a chip coupled to a memory for executing a computer program stored in the memory to perform the method according to any one of claims 1-13.

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