Verilog HDL code model construction method and related device

Abstract

The invention discloses a construction method of a Verilog HDL (Hardware Description Language) code model and a related device. Firstly, a basic Butterworth filter and a VCode template are created in GCKontrol, and an IP core equivalent to an addition and subtraction operation unit in the filter is designed in Vivado based on service requirements. Then configuring a VCode template port to be consistent with the addition and subtraction operation unit to generate a VCode module, after the addition and subtraction operation unit is replaced, enabling a GCKontrol code generation directory to point to a Vivado path, and finally instantiating an IP core to the VCode module to complete model generation. According to the method, GCKontrol and IP core multiplexing are combined, automatic standardized code generation is achieved, manual work and skill dependence are reduced, efficiency and interface consistency are improved, and errors and development cost risks are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital integrated circuit design and digital signal processing, in particular to a construction method of a Verilog HDL code model and related devices. BACKGROUND

[0002] At present, in the field of digital integrated circuit design and FPGA development, the generation of Verilog HDL (Verilog Hardware Description Language) code still largely depends on the manual coding of technical personnel. This mode puts forward very high professional requirements for technical personnel, who not only need to deeply understand the logical design principles of digital circuits, but also must be proficient in the coding rules specific to Verilog HDL, including module definition, port declaration, syntax differences between sequential logic and combinational logic, correct use of signal types, and coding skills related to timing constraints and resource optimization in hardware implementation, etc.

[0003] However, the limitations of manual coding are also very prominent: on the one hand, for complex digital systems (such as modules containing filtering algorithms, protocol processing, etc.), the amount of code is often in the tens of thousands or even hundreds of thousands, and technical personnel need to write and debug line by line, resulting in a long development cycle, low efficiency, and difficulty in meeting the design requirements of rapid iteration; on the other hand, in the process of manual coding, errors are easily caused by negligence of syntax details (such as mismatch of port bit width, lack of sensitive signal list in sequential logic), omissions of logical design (such as incomplete state machine jump conditions), or deviations in understanding of hardware implementation characteristics (such as not considering the impact of signal delay on timing), which are not only difficult to troubleshoot, but also may not be exposed until the simulation or hardware testing stage, further increasing the design cost and risk. Therefore, the way of manual coding to generate Verilog HDL code has obvious shortcomings in efficiency and reliability. SUMMARY

[0004] Based on the above problems, the present application provides a construction method of a Verilog HDL code model and related devices, which can improve the efficiency of code generation in complex digital system design, reduce the error rate, and thus shorten the development cycle, reduce the design cost and risk.

[0005] The present application embodiment discloses the following technical solutions:

[0006] A construction method of a Verilog HDL code model, the method comprising:

[0007] create a basic Butterworth filter and a VCode template in GCKontrol, and create an intellectual property IP core equivalent to an addition and subtraction operation unit in the basic Butterworth filter based on a business requirement in a vivado project; the VCode template defines a basic input and output framework; the addition and subtraction operation unit is located at a signal aggregation node in the basic Butterworth filter, and is used for operation and output of output signals of a plurality of pre-processing modules; the business requirement is used to define operation logic and interface specifications of the IP core, so that the IP core meets adaptation requirements of Verilog HDL code generation;

[0008] configure a number of ports and bit widths of the VCode template to obtain a VCode module; the number of ports and the bit widths of the VCode module are consistent with the number of ports and the bit widths of the addition and subtraction operation unit;

[0009] replace the addition and subtraction operation unit in the basic Butterworth filter with the VCode module to obtain a replaced Butterworth filter, and set a generation code directory of the GCKontrol as a code storage path of the vivado project;

[0010] instance the IP core into the VCode module of the replaced Butterworth filter to obtain a Verilog HDL code model.

[0011] In a possible implementation manner, the method further includes:

[0012] determining a number of input ports, a number of output ports and bit widths of each port of the addition and subtraction operation unit;

[0013] configuring the number of input ports, the number of output ports and the bit widths of each port of the VCode template to be consistent with the addition and subtraction operation unit, and configuring a scaling value for each port to obtain the VCode module.

[0014] In a possible implementation manner, the method further includes:

[0015] obtaining a test signal;

[0016] generating first code and second code through simulation based on the test signal in the basic Butterworth filter and the Verilog HDL code model respectively;

[0017] checking whether the first code is consistent with the second code;

[0018] If the first code is consistent with the second code, it is determined that the Verilog HDL code model meets the design requirements; otherwise, the VCode module configuration and IP core instantiation process are returned to be adjusted and verified again.

[0019] In a possible implementation, the IP core has the same bit width and data type as the VCode module, and the control signal of the IP core is time-sequentially consistent with the corresponding signal of the VCode module.

[0020] In a possible implementation, the method further includes:

[0021] performing static timing analysis on the Verilog HDL code model to obtain an analysis result;

[0022] When the analysis result shows that the signal transmission delay between the modules does not exceed a preset maximum delay threshold, it is determined that the signal transmission delay between the modules in the Verilog HDL code model meets the timing performance requirement of hardware deployment.

[0023] When the analysis result shows that the setup time margin and the hold time margin between the modules are both greater than zero and not lower than a preset safety threshold, it is determined that the setup time and the hold time between the modules in the Verilog HDL code model meet the timing constraint condition.

[0024] A construction device of a Verilog HDL code model, the device includes:

[0025] A creating unit is configured to create a basic Butterworth filter and a VCode template in GCKontrol, and create an IP core equivalent to an addition and subtraction operation unit in the basic Butterworth filter in a vivado project based on a business requirement; the VCode template defines a basic input and output framework; the addition and subtraction operation unit is located at a signal aggregation node in the basic Butterworth filter, and is configured to operate and output the output signals of a plurality of pre-processing modules; and the business requirement is configured to define the operation logic and interface specification of the IP core, so that the IP core meets the adaptation requirement of Verilog HDL code generation.

[0026] A first configuring unit is configured to configure the number of ports and the bit width of the VCode template to obtain a VCode module; the number of ports and the bit width of the VCode module are consistent with the number of ports and the bit width of the addition and subtraction operation unit.

[0027] The replacement unit is configured to replace the add-subtract operation unit in the basic Butterworth filter with the VCode module to obtain a replaced Butterworth filter, and set a generation code directory of the GCKontrol as a code storage path of a vivado project;

[0028] The instantiation unit is configured to instantiate the IP core into the VCode module of the replaced Butterworth filter to obtain a Verilog HDL code model.

[0029] In a possible implementation, the first configuration unit specifically includes:

[0030] The determination unit is configured to determine the number of input ports, the number of output ports and the bit width of each port of the add-subtract operation unit.

[0031] The second configuration unit is configured to configure the number of input ports, the number of output ports and the bit width of each port of the VCode template to be consistent with the add-subtract operation unit, and configure a scaling value for each port to obtain the VCode module.

[0032] In a possible implementation, the apparatus further includes:

[0033] The signal acquisition unit is configured to acquire a test signal.

[0034] The simulation unit is configured to simulate, based on the test signal, a basic Butterworth filter and the Verilog HDL code model to generate a first code and a second code, respectively.

[0035] The verification unit is configured to verify whether the first code is consistent with the second code, and if the first code is consistent with the second code, determine that the Verilog HDL code model meets the design requirement, otherwise, return to check the VCode module configuration and the IP core instantiation process, and re-adjust and verify.

[0036] A device for constructing a Verilog HDL code model, including a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the device implements the method for constructing a Verilog HDL code model.

[0037] A computer readable storage medium, in which instructions are stored, and when the instructions are executed on a terminal device, the terminal device executes the method for constructing a Verilog HDL code model.

[0038] Compared with the prior art, the present application has the following beneficial effects:

[0039] The application provides a construction method of a Verilog HDL code model and related devices. Specifically, when the construction method of the Verilog HDL code model is executed, first, a basic Butterworth filter and a corresponding VCode template are created in GCKontrol, and based on specific business requirements, an Intellectual Property (IP) core equivalent to the addition and subtraction operation unit function in the basic Butterworth filter is designed in a Vivado project. The VCode template defines the basic input and output structure; the addition and subtraction operation unit is located at the signal aggregation node and is responsible for calculating the output signals of the multi-channel pre-processing module. Second, the number of ports and the bit width of the VCode template are configured to be consistent with the addition and subtraction operation unit, and a corresponding VCode module is generated. Then, the addition and subtraction operation unit in the basic Butterworth filter is replaced with the VCode module, and the code generation directory of GCKontrol is specified as the code storage path of the Vivado project. Finally, the designed IP core is instantiated in the replaced VCode module, thereby completing the generation of the Verilog HDL code model and realizing the effective adaptation of code generation and business logic requirements.

[0040] The application overcomes the short board of manual coding by combining GCKontrol and IP core reuse. On the one hand, through the GCKontrol application example, the VCode template framework is used when creating the Butterworth filter using GCKontrol, which demonstrates how to quickly fill the VCode template with IP cores to quickly generate complete Verilog HDL code for the Butterworth filter, reducing the workload of manually writing a large amount of repetitive code and reducing the over-reliance on mastering Verilog HDL coding rules. At the same time, by uniformly configuring the port parameters, the modularity of the module interface is ensured, greatly improving the code generation efficiency of complex systems (such as modules containing filtering algorithms) and shortening the development cycle. On the other hand, by defining the operation logic and interface specification of the IP core based on business requirements, the IP core has code generation adaptability, and by instantiating it in the VCode module, it avoids problems such as syntax detail negligence, logic design omission, and understanding bias of hardware implementation characteristics in manual coding. Through the collaborative mechanism of tool generation and IP core reuse, the error rate is reduced, and the cost and risk of subsequent error checking are reduced, thereby improving the code generation efficiency while ensuring reliability. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the accompanying drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without any creative effort.

[0042] Figure 1 A method flowchart of a Verilog HDL code model construction method provided by an embodiment of the present application;

[0043] Figure 2 A structural schematic diagram of a basic Butterworth filter provided by an embodiment of the present application;

[0044] Figure 3 A structural schematic diagram of a fixed-point discrete filter provided by an embodiment of the present application;

[0045] Figure 4 A method flowchart of a model simulation method provided by an embodiment of the present application;

[0046] Figure 5 A structural schematic diagram of a Verilog HDL code model construction device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to facilitate the understanding of the technical solutions provided by the embodiments of the present application, the background art related to the embodiments of the present application will be described first.

[0048] Currently, the generation of Verilog HDL code mainly depends on manual coding by technical personnel, which requires the technical personnel to be proficient in the coding rules of Verilog HDL. However, manual coding is not only inefficient but also prone to errors, which makes the entire design process time-consuming and unreliable.

[0049] To solve this problem, the embodiment of the present application provides a construction method of a Verilog HDL code model and a related device. A basic Butterworth filter and a VCode template are created in GCKontrol, and an equivalent IP core is created in a Vivado project according to business requirements. The VCode template defines a basic input and output framework, and the addition and subtraction operation unit is used to operate and output the output signals of the multi-path pre-processing module. By configuring the number of ports and the bit width of the VCode template, a VCode module can be obtained, which is replaced into the basic Butterworth filter to generate a replaced Butterworth filter. The IP core is instantiated in the VCode module, and finally a Verilog HDL code model is obtained. The present application effectively overcomes the short board of manual coding by combining GCKontrol and IP core reuse. On the one hand, by using GCKontrol application as an example, the VCode template framework is used when creating a Butterworth filter by using GCKontrol. It shows how to quickly fill the VCode template with IP cores to quickly generate a complete Verilog HDL code of the Butterworth filter, reduces the workload of manually writing a large amount of repetitive code, reduces the dependence on mastering the Verilog HDL coding rules, and ensures the standardization of the module interface through unified configuration of the port parameters, greatly improves the code generation efficiency of the complex system, and shortens the development cycle. On the other hand, by defining the operation logic and interface specification of the IP core based on business requirements, the IP core has code generation adaptability, and is instantiated in the VCode module, which avoids problems such as syntax details negligence, logic design omission and understanding deviation of hardware implementation characteristics in manual coding, thereby improving the code generation efficiency, ensuring the reliability and reducing the error rate and subsequent troubleshooting cost.

[0050] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of the present application.

[0051] Referring to Figure 1 , the figure is a method flowchart of a construction method of a Verilog HDL code model provided by the embodiment of the present application, as Figure 1 shown, the construction method of the Verilog HDL code model can include steps S101-S104:

[0052] S101: Create a basic Butterworth filter and VCode template in GCKontrol, and create an IP core equivalent to the addition and subtraction operation unit in the basic Butterworth filter in the vivado project based on business needs.

[0053] In the GCKontrol system design and simulation software, first create a basic Butterworth filter and VCode template. GCKontrol is an ISO 26262 certified (ASIL-D level) graphical modeling and simulation tool that can achieve system design and simulation, and has rich control system modeling elements. It not only supports the modeling and simulation of linear and nonlinear systems, but also automatically generates efficient and high-quality C code. In addition, GCKontrol is combined with ModTest software to support FMU export, real-time simulation, automated testing and verification, and other functions.

[0054] In GCKontrol, a basic Butterworth filter is defined, as shown in Figure 2 The signal processing flow of this filter is performed from left to right. First, the signal enters the module named "Function", which performs preliminary function operation processing on the input signal, and the processed result is marked as y0 output. Then, the y0 signal is transmitted to the "Conversion" module, where the signal data type is converted to int32 format, completing the data format adaptation conversion. The converted signal u enters the core processing module "Discrete Filter Fixed Point", which is a fixed-point discrete filter that performs filtering operations on the input u signal to obtain the final output signal y. Finally, the output signal y is transmitted to the "Out" module to realize the final output of the signal, and the entire flow clearly shows the signal processing path and the functions of each module of the basic Butterworth filter. A VCode template is also created. This VCode template is mainly used to define the basic input and output framework to ensure a clear structure when generating Verilog HDL code later.

[0055] Figure 3The structure diagram of the fixed-point discrete filter (Discrete Filter FixedPoint) in the basic Butterworth filter is shown, specifically, the signal is first input from the leftmost port, and then divided into multiple paths for processing. One path passes through UnitDelay_1, Gain_1, UnitDelay_2, Gain_2, etc. in turn, another path passes through Gain_4 module, and another path passes through Gain_3 module, etc. These modules perform different operations such as delay and gain on the signal, and finally collect at the right side of the Add_Sub_2 module (i.e. addition and subtraction operation unit), which is located at the signal collection node, responsible for calculating and outputting the output signals of the multiple front-end processing modules, and the signals after operation processing are output from the rightmost port.

[0056] Next, based on specific business requirements, an IP core equivalent to the addition and subtraction operation unit in the basic Butterworth filter can also be created in the Vivado project. Business requirements are used to define the operation logic and interface specification of the IP core in this process, to ensure that the generated IP core can meet the adaptation requirements of Verilog HDL code generation. In this way, complex business logic is converted into specific hardware description language (such as Verilog HDL), realizing seamless connection from system-level design to hardware implementation.

[0057] The whole process combines the powerful modeling capability of GCKontrol and the professional hardware implementation capability of Vivado, not only improves the design efficiency, but also guarantees the quality and consistency of the generated code.

[0058] S102: Configure the number of ports and bit width for the VCode template to obtain a VCode module.

[0059] In order to ensure that the generated Verilog HDL code model can correctly interface match with the addition and subtraction operation unit, first, the number of ports and bit width need to be configured for the VCode template. This process is one of the key steps in building the entire system, which directly affects whether the subsequently generated VCode module can be seamlessly connected with the addition and subtraction operation unit.

[0060] Specifically, first, the VCode template is configured in detail. This includes defining the number of ports required in the VCode template, ensuring that these ports can adapt to the input and output requirements of the addition and subtraction operation unit. At the same time, it is also necessary to set appropriate bit width for each port to ensure the accuracy and integrity of data transmission. In this way, it can be ensured that the VCode module is completely consistent with the addition and subtraction operation unit in terms of function and interface.

[0061] In the specific operation process, the port configuration of the add-subtract operation unit is checked one by one, including the number of its input and output ports and the bit width of each port. Then, these configuration parameters are applied to the VCode template to ensure that the port number and bit width of the VCode module completely correspond to the add-subtract operation unit. This step not only guarantees the consistency of data, but also ensures that the VCode module can be seamlessly inserted into the original signal processing flow when the add-subtract operation unit is replaced.

[0062] In summary, by configuring the number of ports and bit width for the VCode template, a VCode module compatible with the add-subtract operation unit is obtained, thereby laying a solid foundation for subsequent replacement and integration work.

[0063] S103: Replace the add-subtract operation unit in the base Butterworth filter with the VCode module to obtain a replaced Butterworth filter, and set the generation code directory of GCKontrol to the code storage path of the vivado project.

[0064] After completing the port configuration of the VCode template and generating the VCode module, the next operation is to replace the add-subtract operation unit in the base Butterworth filter with the newly created VCode module. This step is one of the core links in the entire construction process, aiming to ensure that the new VCode module can be seamlessly integrated into the existing filter design.

[0065] Specifically, first locate the add-subtract operation unit in the base Butterworth filter, which is the key component of this filter, responsible for calculating and summarizing the output signals of the multi-channel pre-processing module. Next, replace these add-subtract operation units with the previously configured VCode module. In order to ensure that the replaced system can still work normally, carefully check the interface consistency between the VCode module and the add-subtract operation unit, including the number of ports and bit width parameters, to ensure that the data flow will not be affected by the replacement.

[0066] After the replacement is completed, a new version of the Butterworth filter is obtained - the replaced Butterworth filter. This version not only retains the design logic of the original filter, but also improves the flexibility and scalability of the system by introducing the VCode module.

[0067] Then, the storage path of the code needs to be set in order to further develop and verify in the Vivado project. For this purpose, the generated code directory of GCKontrol is set as the code storage path of the Vivado project. Specifically, the code generated by GCKontrol is directly placed in the path specified by the Vivado project, so that the generated code file can be seamlessly integrated into the Vivado project, thereby facilitating subsequent synthesis, simulation and implementation work.

[0068] Through this series of operations, not only the add-subtract operation unit is successfully replaced by the VCode module, but also the generated code can be correctly imported into the Vivado project, laying a solid foundation for further hardware implementation.

[0069] S104: instantiate the IP core into the VCode module of the replaced Butterworth filter to obtain a Verilog HDL code model.

[0070] After completing the replacement of the add-subtract operation unit in the basic Butterworth filter to the VCode module and completing the association of GCKontrol and the Vivado project path, by instantiating the IP core (whose operation logic and interface specification have been adapted to the Verilog HDL code generation requirements) designed based on business requirements into the VCode module of the replaced Butterworth filter, a complete Verilog HDL code model is finally obtained. This instantiation process essentially embeds the IP core as a functional unit into the standardized framework of the VCode module: the VCode module has ensured interface compatibility with the original add-subtract operation unit through port configuration, while the IP core replaces the original add-subtract operation unit to implement operation processing on multiple signals with operation logic that meets business requirements, the combination of the two not only preserves the coherence of the overall signal processing flow of the filter, but also realizes the conversion from graphical modeling to hardware description language code through the reuse of the IP core and the standardized framework of the VCode module. The generated Verilog HDL code model at this time not only contains the overall structure of the basic Butterworth filter, but also integrates the specific operation logic of the IP core, which not only meets the requirements of signal processing functions of business requirements, but also ensures the standardization and realizability of the code through the cooperation of the tool chain, thereby completing the closed-loop construction from system design to hardware code model.

[0071] Based on the content of S101-S104, first, the basic Butterworth filter and the corresponding VCode template are created in GCKontrol, and the IP core equivalent to the addition and subtraction operation unit in the filter is designed in Vivado project based on business requirements. The VCode template defines the basic input and output structure, and the addition and subtraction operation unit is used for the signal aggregation node, which is responsible for the operation of the output signal of the multi-channel pre-processing module. Then, the number and bit width of the VCode template port are configured to be consistent with the addition and subtraction operation unit, and the corresponding VCode module is generated. Then, the addition and subtraction operation unit in the filter is replaced with the VCode module, and the GCKontrol code generation directory is set to the Vivado project code storage path. Finally, the IP core is instantiated to the replaced VCode module to realize the automatic generation of the Verilog HDL code model. By combining GCKontrol and IP core reuse, the application reduces the repetitive work of manual coding and the dependence on professional skills, improves the design efficiency and interface standardization of complex systems, avoids traditional coding errors, improves code reliability, and effectively reduces development cost and risk.

[0072] In a possible implementation, the VCode module is obtained by configuring the number and bit width of the ports of the VCode template, and includes:

[0073] First, by analyzing the signal interaction logic of the addition and subtraction operation unit in the basic Butterworth filter, the number of input ports, the number of output ports, and the bit width parameters of each port are determined - these parameters directly determine the parallel processing capability and data precision of the signal. For example, if the addition and subtraction operation unit needs to receive 3-way 16-bit wide input signals and output 1-way 32-bit wide results, the parameters need to be accurately extracted. Then, the number of input ports, the number of output ports, and the bit width configuration of the VCode template are configured to be completely consistent with the addition and subtraction operation unit, so as to ensure that the signal will not be lost or incorrect due to port mismatch during transmission. In addition, each port can also be configured with a scaling value: the scaling value is used to define the decimal point position of the data, which directly affects the operation precision and value range in hardware implementation. By reasonably setting the scaling value, the VCode module can maintain the same numerical analysis rules as the addition and subtraction operation unit when receiving and outputting signals, avoiding operation errors caused by differences in scaling methods. Finally, through the accurate configuration of the above port parameters, the generated VCode module can seamlessly interface with the original addition and subtraction operation unit, providing a standardized signal interaction framework for subsequent instantiation of the IP core.

[0074] In a possible implementation, the application also provides a verification method for a Verilog HDL code model, as shown in Figure 4 Figure 4 ​A method flowchart of a model simulation method provided for an embodiment of the present application can be implemented through steps S401-S404.

[0075] S401: Obtain a test signal.

[0076] To verify the functional consistency of the Verilog HDL code model and the basic Butterworth filter, a test signal with typical characteristics needs to be obtained, which should be able to fully stimulate the core processing logic of the filter. For example, a composite sine signal such as y0=sin(SIMTIME×250×π+sin(SIMTIME×20×π) can be used. Wherein, SIMTIME represents a simulation time variable, π is a constant of the ratio of a circle, and the signal is superimposed by two sine components of different frequencies - a high-frequency sine signal of 250 Hz (Hertz) and a low-frequency sine signal of 20 Hz. This design can effectively test the processing capability of the filter for signals of different frequency bands: the high-frequency component can be used to verify the cutoff frequency characteristics of the filter, and the low-frequency component can be used to verify the retention effect of the target frequency band signal. By selecting such a test signal containing multiple frequency components, both the signal characteristics that the basic Butterworth filter may encounter in actual application and the subsequent simulation results can be covered, and it can be accurately judged whether the Verilog HDL code model accurately reproduces the filtering logic of the original filter, providing comprehensive and distinguishable input basis for the test process.

[0077] S402: Based on the test signal, respectively simulate the basic Butterworth filter and the Verilog HDL code model to generate first code and second code.

[0078] After obtaining the test signal, the functional consistency of the basic Butterworth filter and the Verilog HDL code model needs to be verified through simulation: the same test signal (such as a composite sine signal containing a 250 Hz high-frequency component and a 20 Hz low-frequency component) is input into two systems for simulation running. Among them, the basic Butterworth filter as the benchmark model processes the test signal according to its internal preset signal processing logic (including the operation rules of each module, signal flow path, etc.) in the GCKontrol environment, and finally generates the first code reflecting its output characteristics. The code contains key information such as filtered signal waveform, data sequence and timing characteristics.

[0079] Meanwhile, the completed Verilog HDL code model runs the same test signal in the Vivado environment, based on the interface specification of the integrated IP core operation logic and the VCode module, to perform equivalent processing on the input signal and generate a corresponding second code, which also covers the processed signal parameters and timing data. This simulation process needs to ensure that the simulation conditions (such as sampling frequency, simulation duration, initial state, etc.) of the two systems are completely consistent to eliminate external factors that interfere with the results, so that the generated first code and second code have a direct basis for comparison, thereby accurately determining whether the Verilog HDL code model faithfully reproduces the function of the basic Butterworth filter through subsequent consistency testing.

[0080] S403: Check whether the first code and the second code are consistent.

[0081] The process of checking whether the first code and the second code are consistent is to verify the equivalence of the two simulation results through multi-dimensional and high-precision comparison. First, intuitive comparison is made from the signal waveform level to observe whether the first code output by the basic Butterworth filter and the second code output by the Verilog HDL code model are consistent in overall trend, peak, valley, and period characteristics, especially whether the retention and attenuation of high and low frequency components in the test signal are consistent after filtering, for example, whether the 20Hz low frequency signal is effectively retained and whether the 250Hz high frequency signal is attenuated as expected. Second, quantitative testing of data accuracy is performed, and output values at multiple time nodes are extracted to compare whether the absolute error and relative error of the two are within the preset threshold range (such as error less than a certain order of magnitude), to ensure that the deviation caused by hardware implementation details or numerical calculation method differences is within an acceptable range. At the same time, timing logic is checked to check whether the time delay and phase shift of signal output are consistent to avoid timing misplacement caused by IP core instantiation or port configuration problems. In addition, the performance in special scenarios needs to be verified, such as whether the response is synchronized when the input signal suddenly changes and whether the steady-state output is consistently consistent. Through such comprehensive testing covering waveform characteristics, data accuracy, timing relationship, and special working conditions, it can be accurately determined whether the first code and the second code are consistent in function and performance, providing a reliable basis for subsequent determination of whether the Verilog HDL code model meets the design requirements.

[0082] S404: If the first code and the second code are consistent, it is determined that the Verilog HDL code model meets the design requirements; otherwise, return to check the VCode module configuration and IP core instantiation process and re-adjust and verify.

[0083] When the first code is consistent with the second code through multi-dimensional verification, it indicates that the Verilog HDL code model is completely matched with the basic Butterworth filter in core indicators such as signal processing logic, data precision, and timing characteristics, and can accurately reproduce the function and performance of the original filter, so it can be determined that the code model meets the design requirements and has the basis for practical application. On the contrary, if there is inconsistency between the two, it indicates that there is deviation in the code model construction process - it may be that the port configuration (such as the number of ports, bit width, or scaling value setting) of the VCode module does not match the original add-subtract operation unit, resulting in errors in signal transmission or analysis, or it may be that the instantiation process of the IP core is omitted (such as interface connection error, operation logic does not meet business requirements), making the signal processing result deviate from the expectation. At this time, the corresponding construction link needs to be returned, and the parameter configuration of the VCode module is checked whether it accurately corresponds to the interface characteristics of the original operation unit, and the instantiation logic of the IP core is checked whether it strictly follows the operation rules and interface specifications defined by the business requirements. After adjusting the problems found, the process from model construction to simulation verification is executed again until the simulation results of the two times are completely consistent, so as to ensure that the finally generated Verilog HDL code model not only meets the original design intention, but also reliably adapts to the hardware implementation requirements.

[0084] In a possible implementation, to ensure that the IP core and the VCode module can work seamlessly, they need to meet strict adaptation conditions: on the one hand, the bit width of the IP core and the VCode module must be exactly the same, that is, the signal bit number of the input and output ports is one-to-one correspondence, avoiding errors such as signal truncation or padding due to bit width mismatch, and ensuring the integrity of data transmission. At the same time, the data types of the two need to be consistent (such as fixed-point numbers and the same scaling method), ensuring that the numerical analysis rules are uniform, and preventing operation deviation caused by data format difference. On the other hand, the control signals (such as enable signal, reset signal, clock signal, etc.) of the IP core need to be strictly synchronized with the corresponding signals of the VCode module in timing, that is, the transition time, active level duration, and phase relationship with the data signal of the control signal are completely matched, avoiding abnormal interaction between modules (such as data sampling error, operation trigger time deviation) due to timing misalignment. Such consistency of bit width and data type and timing synchronization of control signal are the basis for the IP core to function stably in the VCode module, and are also the key prerequisite for ensuring that the entire Verilog HDL code model is logically correct and reliable in performance.

[0085] In a possible implementation, the hardware implementation feasibility of the Verilog HDL code model is further verified through static timing analysis, and the specific process is as follows:

[0086] First, static timing analysis is performed on the completed VerilogHDL code model. This analysis calculates key timing parameters such as signal transmission delay, setup time margin, and hold time margin between modules based on the physical characteristics of the hardware platform (such as logic unit delay, routing delay, etc.), and generates detailed analysis results.

[0087] If the analysis results show that the signal transmission delay between each module does not exceed the preset maximum delay threshold, it indicates that the signal transmission speed on the path can meet the real-time requirements of hardware deployment, ensuring that the data arrives at the target module within the specified time and avoiding logical errors caused by excessive delay.

[0088] If the analysis results simultaneously indicate that the setup time margin (i.e., the remaining time from data stabilization to clock edge triggering) and hold time margin (i.e., the duration for which data remains stable after clock edge triggering) between each module are both greater than zero and not lower than the preset safety threshold, it means that the stability of the data before and after the clock edge meets the timing constraint standard, effectively preventing sampling errors caused by data metastableness. By verifying these two timing metrics, we can validate whether the code model is suitable for the hardware deployment environment from a timing performance perspective, providing a reliable guarantee for subsequent hardware implementation.

[0089] See Figure 5 , Figure 5 This is a schematic diagram of a device for constructing a Verilog HDL code model, provided in an embodiment of this application. Figure 5 As shown, the apparatus for building this VerilogHDL code model includes:

[0090] Creation unit 501 is used to create a basic Butterworth filter and VCode template in GCKontrol, and to create an IP core in the Vivado project that is equivalent to the addition and subtraction operation unit in the basic Butterworth filter based on business requirements; the VCode template defines the basic input and output framework; the addition and subtraction operation unit is located at the signal aggregation node in the basic Butterworth filter and is used to perform operations and output on the output signals of the multi-channel preprocessing module; the business requirements are used to define the operation logic and interface specifications of the IP core so that the IP core meets the adaptation requirements for VerilogHDL code generation;

[0091] The first configuration unit 502 is used to configure the number of ports and bit width for the VCode template to obtain a VCode module; the number of ports and bit width of the VCode module are consistent with the number of ports and bit width of the addition and subtraction operation unit;

[0092] The replacing unit 503 is configured to replace the addition and subtraction operation unit in the base Butterworth filter with the VCode module to obtain a replaced Butterworth filter, and set a generation code directory of the GCKontrol to a code storage path of a vivado project;

[0093] The instantiating unit 504 is configured to instantiate the IP core into the VCode module of the replaced Butterworth filter to obtain a Verilog HDL code model.

[0094] In a possible implementation, the first configuration unit 502 specifically includes:

[0095] The determining unit is configured to determine the number of input ports, the number of output ports and the bit width of each port of the addition and subtraction operation unit.

[0096] The second configuration unit is configured to configure the number of input ports, the number of output ports and the bit width of each port of the VCode template to be consistent with the addition and subtraction operation unit, and configure a scaling value for each port to obtain the VCode module.

[0097] In a possible implementation, the apparatus further includes:

[0098] The signal obtaining unit is configured to obtain a test signal.

[0099] The simulation unit is configured to perform simulation to generate a first code and a second code based on the test signal in the base Butterworth filter and the Verilog HDL code model respectively.

[0100] The checking unit is configured to check whether the first code is consistent with the second code, and if the first code is consistent with the second code, it is determined that the Verilog HDL code model meets the design requirement, otherwise, the VCode module configuration and the IP core instantiation process are returned to be adjusted and verified again.

[0101] In a possible implementation, the bit width and the data type of the IP core and the VCode module are the same, and the control signal of the IP core and the corresponding signal of the VCode module keep consistent in timing.

[0102] In a possible implementation, the apparatus further includes:

[0103] The static timing analysis unit is configured to perform static timing analysis on the Verilog HDL code model to obtain an analysis result.

[0104] The timing constraint verification unit is configured to determine that the signal transmission delay between the modules in the Verilog HDL code model meets the timing performance requirement of hardware deployment when the analysis result shows that the signal transmission delay between the modules does not exceed the preset maximum delay threshold; and determine that the setup time and the hold time between the modules in the Verilog HDL code model meet the timing constraint condition when the analysis result shows that the setup time margin and the hold time margin between the modules are both greater than zero and not lower than the preset safety threshold.

[0105] In addition, the embodiment of the present application further provides a construction device of a Verilog HDL code model, which comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the construction method of the Verilog HDL code model as described above when executing the computer program.

[0106] In addition, the embodiment of the present application further provides a computer readable storage medium, wherein instructions are stored in the computer readable storage medium, and the instructions enable a terminal device to perform the construction method of the Verilog HDL code model as described above when the instructions are executed on the terminal device.

[0107] The present application significantly solves the deficiencies of manual coding by combining the GCKontrol and IP core reuse technology. On the one hand, through the GCKontrol application example, the VCode template framework is used when creating the Butterworth filter using GCKontrol, which demonstrates how to quickly fill the VCode template with IP cores to quickly generate the complete Verilog HDL code of the Butterworth filter, reduces the workload of repeatedly writing code for technical personnel, reduces the dependence on Verilog HDL coding skills, and guarantees the modularity interface specification through unified port parameter configuration, thereby improving the code generation efficiency of complex systems (such as filter algorithm modules) and shortening the development cycle. On the other hand, the operation logic and interface specification of the IP core are accurately defined based on business requirements, which makes it have good code generation adaptability, and then the IP core is instantiated into the VCode module, effectively avoiding common syntax errors, logic defects and hardware implementation understanding bias in manual coding. With the collaborative mechanism of tools and IP core reuse, not only the error rate is reduced, but also the cost and risk of subsequent debugging are reduced, realizing the dual improvement of code generation efficiency and design reliability.

[0108] The construction method of the Verilog HDL code model and the related device provided by the present application are described in detail above. The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts can be referred to the method part. It should be pointed out that for ordinary skilled in the art, without departing from the principles of the present application, the present application can be improved and modified, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0109] It should be understood that in the present application, "at least one" means one or more, and "multiple" means two or more. "And / or" is used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, "A and / or B" can represent three cases of only A, only B and A and B existing at the same time, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the front and rear associated objects. "At least one of the following" or similar expressions means any combination of these items, including single item or any combination of multiple items. For example, at least one of a, b or c can represent a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b and c can be single or multiple.

[0110] It should also be noted that in this document, relationship terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a…" does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A method of constructing a Verilog HDL code model, characterized by, The method comprises: creating a basic Butterworth filter and a VCode template in GCKontrol, and creating an intellectual property IP core equivalent to an addition and subtraction operation unit in the basic Butterworth filter in a vivado project based on a service requirement; the VCode template defines a basic input and output framework; the addition and subtraction operation unit is located at a signal aggregation node in the basic Butterworth filter, and is used for operation and output on output signals of a plurality of pre-processing modules; and the service requirement is used for defining operation logic and interface specifications of the IP core, so that the IP core meets adaptation requirements of Verilog HDL code generation; configuring a port number and a bit width of the VCode template to obtain a VCode module; the port number and the bit width of the VCode module are consistent with a port number and a bit width of the addition and subtraction operation unit; replacing the addition and subtraction operation unit in the basic Butterworth filter with the VCode module to obtain a replaced Butterworth filter, and setting a generated code directory of the GCKontrol as a code storage path of the vivado project; instantiating the IP core into the VCode module of the replaced Butterworth filter to obtain a Verilog HDL code model.

2. The method of claim 1, wherein, The method further comprises: determining an input port number, an output port number and a bit width of each port of the addition and subtraction operation unit; configuring the input port number, the output port number and the bit width of each port of the VCode template to be consistent with the addition and subtraction operation unit, and configuring a scaling value for each port to obtain the VCode module.

3. The method of claim 1, wherein, The method further comprises: obtaining a test signal; generating first code and second code through simulation based on the test signal in the basic Butterworth filter and the Verilog HDL code model respectively; verifying whether the first code is consistent with the second code; if the first code is consistent with the second code, it is determined that the Verilog HDL code model meets design requirements; otherwise, the VCode module configuration and IP core instantiation process are returned to be checked, and adjustment and verification are performed again.

4. The method of claim 1, wherein, The bit width and data type of the IP core and the VCode module are the same, and control signals of the IP core and corresponding signals of the VCode module are consistent in timing.

5. The method of claim 1, wherein, The method further comprises: performing static timing analysis on the Verilog HDL code model to obtain an analysis result; when the analysis result shows that signal transmission delay between modules does not exceed a preset maximum delay threshold, it is determined that the signal transmission delay between modules in the Verilog HDL code model meets timing performance requirements of hardware deployment; when the analysis result shows that setup time margin and hold time margin between modules are both greater than zero and not less than a preset safety threshold, it is determined that the setup time and the hold time between modules in the Verilog HDL code model meet timing constraint conditions.

6. An apparatus for constructing a Verilog HDL code model, characterized by comprising: The device comprises: The creating unit is configured to create a basic Butterworth filter and a VCode template in the GCKontrol, and create an IP core equivalent to an addition and subtraction operation unit in the basic Butterworth filter in a vivado project based on a service requirement; the VCode template defines a basic input and output framework; the addition and subtraction operation unit is located at a signal aggregation node in the basic Butterworth filter, and is configured to operate and output output signals of a plurality of pre-processing modules; and the service requirement is configured to define operation logic and interface specifications of the IP core, so that the IP core meets adaptation requirements of Verilog HDL code generation. The first configuration unit is configured to configure a port number and a bit width for the VCode template to obtain a VCode module; and the port number and the bit width of the VCode module are consistent with a port number and a bit width of the addition and subtraction operation unit. The replacing unit is configured to replace the addition and subtraction operation unit in the basic Butterworth filter with the VCode module to obtain a replaced Butterworth filter, and set a generation code directory of the GCKontrol as a code storage path of the vivado project. The instantiating unit is configured to instantiate the IP core into the VCode module of the replaced Butterworth filter to obtain a Verilog HDL code model.

7. The apparatus of claim 6, wherein, The first configuration unit specifically includes: A determining unit is configured to determine an input port number, an output port number, and a bit width of each port of the addition and subtraction operation unit. A second configuration unit is configured to configure the input port number, the output port number, and the bit width of each port of the VCode template to be consistent with the addition and subtraction operation unit, and configure a scaling value for each port to obtain the VCode module.

8. The apparatus of claim 6, wherein, The apparatus further includes: A signal obtaining unit is configured to obtain a test signal. An emulation unit is configured to respectively emulate the basic Butterworth filter and the Verilog HDL code model based on the test signal to generate a first code and a second code. A checking unit is configured to check whether the first code is consistent with the second code; if the first code is consistent with the second code, it is determined that the Verilog HDL code model meets design requirements; otherwise, the VCode module configuration and the IP core instantiation process are checked and adjusted and verified again.

9. A device for constructing a Verilog HDL code model, characterized by The apparatus further includes: A memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the construction method of the Verilog HDL code model according to any one of claims 1-5 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores instructions, and when the instructions run on a terminal device, the terminal device executes the construction method of the Verilog HDL code model according to any one of claims 1-5.

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