Code compilation methods, devices, assemblers, and media based on the P4 assembler

Abstract

This invention provides a code compilation method, apparatus, assembler, and medium based on a P4 assembler, comprising: acquiring an assembly code file to be processed; splitting and compiling the assembly code file to obtain multiple code segment compilation results; classifying the code segment compilation results into code segment groups based on auxiliary information, using the Parser component, Mat component, and Deparser component contained in the Ingress unit and Egress unit as classification types; linking the P4 table entry data and machine instruction code contained in the code segment group, and assigning a global instruction identifier and code segment header information to the linking result to obtain code segment binary code; and generating a firmware file based on the code segment binary code. This invention can simplify the compilation process of network processors, thereby improving development efficiency.

Description

Technical Field

[0001] This invention relates to the field of assembler technology, and in particular to a code compilation method, apparatus, assembler, and medium based on the P4 assembler. Background Technology

[0002] Network processors are typically designed to use complex machine instructions to support the processing of network packets. These instructions are usually tightly coupled with the hardware architecture, making it extremely complex, inefficient, and difficult to maintain when using machine instructions directly on these hardware devices to develop network applications. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a code compilation method, apparatus, assembler and medium based on P4 assembler, which can simplify the compilation process of network processors and thus improve development efficiency.

[0004] In a first aspect, the present invention provides a code compilation method based on a P4 assembler. The method is applied to a P4 assembler, which includes an Ingress unit and an Egress unit. Both the Ingress unit and the Egress unit contain a Parser component, a Mat component, and a Deparser component. The method includes:

[0005] Obtain the assembly code file to be processed. The assembly code file is written according to the instruction format of the P4 assembler.

[0006] The assembly code file is split and compiled to obtain multiple code segment compilation results. The code segment compilation results include at least auxiliary information, P4 table entry data and machine instruction code.

[0007] Based on auxiliary information, the code segment compilation results are classified into code segment groups according to the classification types of the Parser component, Mat component and Deparser component contained in the Ingress unit and Egress unit;

[0008] The P4 table entries and machine instruction codes contained in the code segment group are linked, and the linking result is assigned a global instruction identifier and code segment header information to obtain the code segment binary code; wherein, the global instruction identifier is used to describe the target assembly instruction corresponding to the linking result, and the code segment header information is used to describe the classification type to which the linking result belongs;

[0009] Firmware files are generated based on code segment binary code.

[0010] In one implementation, the assembly code file is split and compiled to obtain multiple code segment compilation results, including:

[0011] Analyze the contextual relationships between instructions contained in the assembly code file, and then split the assembly code file into multiple code segments based on these contextual relationships;

[0012] The code segment is compiled to convert the pseudo-instructions contained in the code segment into auxiliary information and P4 table entry data, and other instructions contained in the code segment into machine instruction code, thus obtaining the code segment compilation result.

[0013] In one implementation, based on auxiliary information, the code segment compilation results are classified into code segment groups according to the classification types of the Ingress unit, the Parser component, Mat component, and Deparser component contained in the Egress unit, including:

[0014] Based on the type declaration described in the auxiliary information, determine the target component to which the code segment compilation result belongs from the Parser component, Mat component, and Deparser component contained in the Ingress unit and Egress unit;

[0015] Based on the target component to which the code segment compilation results belong, the code segment compilation results are classified to obtain the code segment group corresponding to each target component.

[0016] In one implementation, the P4 table entry data includes at least key attribute information, which includes the code segment base address, segment start address, and segment end address; linking the P4 table entry data and machine instruction code contained within the code segment group includes:

[0017] For the code segment groups corresponding to the Parser and Deparser components, perform the following operations: use the compilation order as the linking order, and use the segment start address and segment end address as boundaries to link the P4 table entries and machine instruction codes in the code segment compilation results contained in the code segment group;

[0018] The Mat component includes multiple processing sub-components. The following operations are performed on the code segment group corresponding to the Mat component: the compilation results of the code segments contained in the code segment group are classified according to the processing sub-component as the classification type to obtain multiple code segment sub-groups. The compilation order is used as the linking order, and the segment start address and segment end address are used as boundaries to link the P4 table entry data and machine instruction code in the compilation results of the code segments contained in the code segment sub-groups.

[0019] In one implementation, the linking result is assigned a global instruction identifier and code segment header information to obtain the code segment binary code, including:

[0020] Based on the code segment base address in the P4 table entry data, a global instruction identifier is assigned to the linking result, and based on the target component to which the code segment group belongs, code segment header information is assigned to the linking result, thus obtaining the code segment binary code.

[0021] In one implementation, the P4 assembler is configured with a key action programming model, which describes the matching relationship between keys and assembly instructions. A key matches at least one assembly instruction, or multiple keys match the same assembly instruction. Based on the code segment base address in the P4 table entry data, a global instruction identifier is assigned to the linking result, including:

[0022] Determine the offset of the instruction in the link result, determine the key corresponding to the link result based on the offset and the base address of the code segment, and determine the global instruction identifier corresponding to the link result based on the key-action programming model and the key corresponding to the link.

[0023] In one implementation, generating a firmware file based on code segment binary code includes:

[0024] The binary code segments are linked together, and firmware header information is added to the linking result to obtain the firmware file.

[0025] Secondly, the present invention also provides a code compilation device based on a P4 assembler. The device is applied to a P4 assembler, which includes an Ingress unit and an Egress unit. Both the Ingress unit and the Egress unit contain a Parser component, a Mat component, and a Deparser component. The device includes:

[0026] The file acquisition module is used to acquire the assembly code file to be processed. The assembly code file is written according to the instruction format of the P4 assembler.

[0027] The splitting and compiling module is used to split and compile assembly code files to obtain multiple code segment compilation results. The code segment compilation results include at least auxiliary information, P4 table entry data and machine instruction code.

[0028] The grouping module is used to classify the code segment compilation results into code segment groups based on auxiliary information, using the Parser component, Mat component and Deparser component contained in the Ingress unit and Egress unit as classification types.

[0029] The linking module is used to link the P4 table entries and machine instruction codes contained in the code segment group, and to assign a global instruction identifier and code segment header information to the linking result to obtain the code segment binary code; wherein, the global instruction identifier is used to describe the target assembly instruction corresponding to the linking result, and the code segment header information is used to describe the classification type to which the linking result belongs;

[0030] Firmware file generation module, used to generate firmware files based on code segment binary code.

[0031] Thirdly, the present invention also provides an assembler including a processor and a memory, the memory storing computer-executable instructions executable by the processor, the processor executing the computer-executable instructions to implement any of the methods provided in the first aspect.

[0032] Fourthly, the present invention also provides a computer-readable storage medium storing computer-executable instructions, which, when invoked and executed by a processor, cause the processor to implement any of the methods provided in the first aspect.

[0033] This invention provides a code compilation method, apparatus, assembler, and medium based on a P4 assembler. The P4 assembler includes an Ingress unit and an Egress unit, both of which contain a Parser component, a Mat component, and a Deparser component. First, the assembly code file to be processed is obtained, which is written according to the instruction format of the P4 assembler. Then, the assembly code file is split and compiled to obtain multiple code segment compilation results. Each code segment compilation result includes at least auxiliary information, P4 table entry data, and machine instruction code. Next, based on the auxiliary information, the code segment compilation results are classified into code segment groups according to the Parser component, Mat component, and Deparser component contained in the Ingress and Egress units. Then, the P4 table entry data and machine instruction code contained within the code segment groups are linked, and a global instruction identifier and code segment header information are assigned to the linking result to obtain code segment binary code. The global instruction identifier describes the target assembly instruction corresponding to the linking result, and the code segment header information describes the classification type to which the linking result belongs. Finally, a firmware file is generated based on the code segment binary code. The above method provides an assembly instruction adapted to the P4 assembler. After obtaining the assembly code file written according to the corresponding instruction format, it is split, compiled, grouped and linked to obtain the binary code of the code segment carrying global instruction identifiers and code segment header information. Based on this, the final firmware file is generated. The embodiments of the present invention can simplify the compilation process of network processors and support the programming of complex network protocols on the self-developed P4 assembler, thereby improving development efficiency.

[0034] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0036] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0037] Figure 1 A flowchart illustrating a code compilation method based on the P4 assembler provided in an embodiment of the present invention;

[0038] Figure 2 A technical framework diagram of a code compilation method based on the P4 assembler provided in this embodiment of the invention;

[0039] Figure 3 A schematic diagram of a key action programming model provided in an embodiment of the present invention;

[0040] Figure 4 A schematic diagram of a section binary code provided for an embodiment of the present invention;

[0041] Figure 5 A schematic diagram of a firmware file p4data.bin provided in an embodiment of the present invention;

[0042] Figure 6 A schematic diagram of the structure of a code compilation device based on a P4 assembler provided in an embodiment of the present invention;

[0043] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] Programming Protocol-Independent Packet Processors (P4) are a type of programmable network packet processor that has emerged in recent years. With their programmability, users can quickly implement, experiment with, and deploy new network protocols on P4-enabled network devices, thus completely overturning the traditional production method of network equipment manufacturers needing to develop new hardware to support new network protocols, and greatly shortening the development cycle of new network protocols.

[0046] Different P4 devices support P4 programming in different ways: (1) Network equipment manufacturers: Leading network equipment manufacturers design network devices that support P4 programming. They will design and use independent machine instructions to support the processing of network packets. These machine instructions are tightly coupled with the hardware architecture and involve their core trade secrets. Therefore, they generally do not disclose their machine instructions. The assembly instructions that are closely related to the machine instructions are often closed-source. Therefore, the more common practice is to develop their own P4 compilation backend based on the open-source P4 high-level language, so that users can program their own network devices based on the general P4 language. However, this does not mean that they do not have machine instructions and assembler instructions. Instead, they encapsulate the relevant implementations as libraries and include them in the P4 compiler backend or P4 Runtime to achieve their isolation and protection purposes. (2) Open source community: BMv2 is a software switch developed by the P4 community. It uses the P4C compiler to compile P4 programs into JSON configuration files. Therefore, it does not involve programming P4 hardware devices. P4-eBPF is a compiler backend that converts P4 programs into Linux eBPF programs. eBPF is a virtual machine in the Linux kernel that allows user-space programs to safely inject code into the kernel. This virtualization technology uses the host machine's instructions to achieve the corresponding functions, and therefore does not involve programming P4 hardware devices.

[0047] In general, each hardware manufacturer's P4 devices are designed with proprietary machine instructions and dedicated compilers, but for various reasons they choose not to disclose the relevant technical information. Furthermore, the relevant technologies between manufacturers are incompatible with each other, and it is impossible to directly use the machine instructions of other hardware manufacturers to program their self-developed P4 programmable logic devices.

[0048] Based on this, this embodiment of the invention provides a smart network card device that supports P4. For this smart network card device: (1) there is a lack of targeted programming tools. The general P4 high-level language cannot directly program the self-developed hardware. Self-developed assembly instructions and a corresponding assembler are required to program this network card device. (2) High-level languages ​​need to be based on assembly instructions and assemblers in order to gradually convert high-level languages ​​into machine instructions.

[0049] This invention provides a code compilation method, apparatus, assembler, and medium based on a P4 assembler, including a set of assembly instructions fully adapted to the P4 smart network card developed by Yihua Technology, a set of organization methods suitable for these assembly instructions, and a complete assembler for assembling assembly instructions into machine code. This simplifies the compilation process of network processors, supports the programming of complex network protocols on the self-developed P4 smart network card, and thus improves development efficiency.

[0050] To facilitate understanding of this embodiment, a code compilation method based on the P4 assembler disclosed in this embodiment will first be described in detail. This method is applied to the P4 assembler, which includes an Ingress unit and an Egress unit. Both the Ingress and Egress units contain a Parser component, a Mat component, and a Deparser component. See [link to documentation]. Figure 1 The diagram shows a code compilation method based on the P4 assembler. The method mainly includes the following steps S102 to S110:

[0051] Step S102: Obtain the assembly code file to be processed.

[0052] The assembly code file is written according to the instruction format of the P4 assembler. The instruction format is used to limit the requirements that users need to follow when writing assembly code files, such as defining the beginning of a code segment with section, defining P4 table entry data with key, defining instruction name with INSTRUCTION_NAME, etc.

[0053] Step S104: Split and compile the assembly code file to obtain multiple code segment compilation results.

[0054] The compiled code segment results include at least auxiliary information, P4 table entry data, and machine instruction code. The auxiliary information declares at least the input / output direction of the instruction and its associated component. The P4 table entry data includes at least key attribute information, which includes the code segment base address, segment start address, and segment end address. In one implementation, the assembly code file is first split into multiple code segments based on the context of the instructions. Then, compilation is performed on a per-section basis. Pseudo-instructions within a code segment are compiled into auxiliary information and P4 table entry data, while other instructions within the code segment are compiled into machine instruction code, resulting in the corresponding compiled code segment results.

[0055] Step S106: Based on the auxiliary information, the code segment compilation results are classified into code segment groups according to the classification types of the Parser component, Mat component and Deparser component contained in the Ingress unit and Egress unit.

[0056] A code segment group contains the compilation results of multiple code segments belonging to the same component within the same unit. In one implementation, the compilation results of code segments can be grouped according to type declarations in auxiliary information, such as the direction attribute (i.e., the inbound and outbound directions), to obtain a code segment group.

[0057] Step S108: Link the P4 table entries and machine instruction codes contained in the code segment group, and assign a global instruction identifier and code segment header information to the linking result to obtain the code segment binary code.

[0058] The global instruction identifier describes the target assembly instructions corresponding to the linking result, and the code segment header information describes the classification type to which the linking result belongs. In one implementation, for each code segment group, the compilation order is used as the linking order, and the segment start address and segment end address are used as boundaries to link the P4 table entries and machine instruction codes within the code segment compilation results contained in the code segment group; based on the code segment base address in the P4 table entry data, a global instruction identifier is assigned to the linking result, and based on the target component to which the code segment group belongs, code segment header information is assigned to the linking result to obtain the code segment binary code.

[0059] Step S110: Generate a firmware file based on the code segment binary code. In one implementation, the code segment binary code is linked, and firmware header information is added to the linking result to obtain the firmware file.

[0060] The code compilation method based on the P4 assembler provided in this embodiment of the invention can simplify the compilation process of network processors, support the programming of complex network protocols on the self-developed P4 assembler, and thus improve development efficiency.

[0061] In one implementation, see Figure 2The diagram illustrates a technical framework for a code compilation method based on the P4 assembler. The P4 assembler reads multiple assembly code files, such as Protocol_1.p4a, Protocol_2.p4a, ..., Protocol_x.p4a; it splits these assembly code files into multiple code sections; these sections are grouped to determine the target component to which the compiled code result belongs from the Parser, Mat, and Deparser components contained in the Ingress and Egress units; and multiple compiled code sections belonging to the same component within the same unit are grouped into the same code section group, which clearly defines the key, action ID (global instruction identifier), and action (assembly instruction); finally, all the code section binary codes are linked to obtain the final firmware file p4data.fw. Specifically, the Parser component is the key component in the P4 processor for extracting network packets; the Mat component is the Match-action execution unit, the core component in the P4 processor for modifying packets; and the Deparser component is the execution unit in the P4 processor for reassembling network packets.

[0062] To facilitate understanding, the assembly instructions adapted to the P4 assembler are explained below:

[0063] The assembler is designed based on the self-developed P4 processor and consists of three main components (Parser component, Mat component and Deparser component) for assembly instructions. Each component contains multiple network-specific assembly instructions and a segmented compilation mechanism is designed to support the storage of network programs in multiple files. Each file can contain multiple segments, and each segment has specific functions and compilation rules.

[0064] (1) Assembly instruction format design: all instructions adopt a unified instruction format:

[0065] INSTRUCTION_NAME{[START:LENGTH]} {parameter1, parameter2, ...}

[0066] Command format description:

[0067] - INSTRUCTION_NAME: Instruction name, such as MOV, SHFT, etc.;

[0068] - [START:LENGTH]: Instruction parameter used to specify the starting address and displacement;

[0069] - parameter1, parameter2, ... : Instruction parameters, used to specify the parameters of the instruction, such as the register name as the parameter of the MOV instruction.

[0070] (2) P4 Assembly Instruction Set Design:

[0071] (2.1) Hardware architecture-based phased instruction set design: The assembler has designed a dedicated instruction set for the three major modules: Parser, MAT, and Deparser. The instructions of each stage are directly mapped to the corresponding hardware functional units to realize the programming of the P4 device.

[0072] Parser instruction set: used to parse data packet headers and extract key fields, including XCT, MOV, SHFT, etc.

[0073] MAT instruction set: used to perform matching and actions, including MDF, COPY, XOR, etc.;

[0074] Deparser instruction set: used to reassemble data packets and send them, including SNDM, SNDH, SNDP, etc.

[0075] (2.2) Dedicated function instructions for network processing:

[0076] State machine transition instructions: used to implement state machines, including NXTD, NXTH, etc.

[0077] CRC calculation instructions: used to calculate the CRC check value of data packets, including CSET, HCRC32, PCRC32, etc.

[0078] Checksum calculation instructions: used to calculate the checksum of data packets, including HCSUM, PCSUM, etc.

[0079] Hash calculation instructions: used to calculate the hash value of data packets, including HASH, etc.

[0080] Mask calculation instructions: used to calculate the mask value of data packets, including MSKALL, MSKADDR, etc.

[0081] Counter commands: used to count data packets, including COUNT, METER, etc.

[0082] Conditional jump instructions: used for conditional jumps, including J, BEZ, etc.;

[0083] Logical operation instructions: used for logical operations, including AND, OR, XOR, etc.

[0084] Arithmetic operation instructions: used for arithmetic operations, including ADD, SUB, etc.

[0085] (3) P4 Assembler Pseudo-instruction Design: The assembler has designed a series of pseudo-instructions to provide auxiliary information, simplify the programming process, and improve code readability. Among them, the segment control pseudo-instructions are as follows:

[0086] .section: Defines the beginning of a section;

[0087] .key: Defines a P4 table entry, in the format ".key [key_name] {start_entry:end_entry} key_data_path";

[0088] .default_op / .default_action: Define the default action to be executed when no match is found;

[0089] .cache_miss_action / .search_miss_action: Define the default actions when a cache miss or search miss occurs;

[0090] .mat / .cluster / .table: Specifies auxiliary information for the mat table;

[0091] .ad: Defines AD data, in the format ".ad {start_entry : end_entry} file_path [start_line]";

[0092] .mask: Defines the mask data, used for data processing in the Deparser stage;

[0093] .align: Controls instruction alignment, optimizing memory access efficiency.

[0094] Based on the above assembly instructions, this embodiment of the invention provides a specific implementation of a code compilation method based on the P4 assembler, including:

[0095] Step 1: Read the assembly code stored in the .p4a file, one unit at a time.

[0096] Step 2 involves analyzing the contextual relationships between instructions within the assembly code file to split the file into multiple code segments based on these relationships. Contextual relationships refer to strong associations between two instructions, such as the requirement that instruction 2 must be executed after instruction 1 is executed.

[0097] Step 3: Compile the code segments section by section. This process involves compiling the pseudo-instructions contained in the code segment section into auxiliary information and P4 table entry data, and compiling the other instructions contained in the code segment section into machine instruction code, thus obtaining the code segment compilation result.

[0098] Step 4: Based on the type declaration described in the auxiliary information, determine the target component to which the code segment compilation result belongs from the Parser component, Mat component, and Deparser component contained in the Ingress unit and Egress unit. Based on the target component to which the code segment compilation result belongs, classify the code segment compilation result to obtain the code segment group corresponding to each target component.

[0099] In one implementation, the code segments of Parser and Deparser are grouped by the direction attribute based on the auxiliary information of the code segment. The code segments of Mat are grouped by appending the mat / cluster / table number to the direction attribute. mat / cluster / table are the processing sub-components contained in the Mat component.

[0100] Specifically, the assembler implements a section-based compilation mechanism, dividing the network program into three functional sections: Parser, MAT, and Deparser. Each section has an independent processing flow and linking method, with the following specific format:

[0101] .section [module] [section_name]

[0102] pseudo_instruction1

[0103] pseudo_instruction2 ...

[0104] instruction1

[0105] instruction2 ...

[0106] Format instructions:

[0107] [module]: The module to which the section belongs, supporting three types: parser, mat, and deparser;

[0108] [section_name]: The section name, used to identify the function and purpose of the section;

[0109] Each code segment is compiled independently, and the processing algorithm within each segment is as follows:

[0110] Each segment is identified by a unique ID; each assembly instruction is assembled line by line, pseudo-instructions and ordinary assembly instructions are processed independently, and the assembly result is stored in the machine code field; the Parser section supports state transfer through the NXTH instruction, mapping the Parser key to TCAM table entries; the MAT section implements the table entry allocation algorithm, supporting dynamic allocation of TCAM / HASH / CACHE table entry resources; the Deparser section uses the .mask instruction to generate mask data, which is used in conjunction with the SNDM, SNDP, and SNDH instructions.

[0111] Step 5: Link the grouped sections, merge the P4 table entries and instruction machine code, and assign a global action ID.

[0112] The inter-segment linking algorithm is as follows:

[0113] For the code segment groups corresponding to the Parser and Deparser components, the following operations are performed: The compilation order is used as the linking order, and the P4 table entries and machine instruction code within the compiled code segments of the code segment group are linked using the segment start address (start_entry) and segment end address (end_entry) as boundaries. Specifically, the Parser and Deparser group segments according to the direction attribute, and the segments within the group are linked in the compilation order. The complete machine code and table entry data of the merged sections are then linked using the start_entry and end_entry of the key as boundaries. Segments with gaps are filled with default instructions and table entry data.

[0114] The Mat component includes multiple processing sub-components. For the code segment groups corresponding to the Mat component, the following operations are performed: The compilation results of the code segments within the code segment group are categorized by processing sub-component to obtain multiple code segment subgroups. The compilation order is used as the linking order, and the segment start address and end address are used as boundaries to link the P4 table entry data and machine instruction code within the compilation results of the code segments in the code segment subgroups. Specifically, MAT groups sections by processing sub-components, links the segments within a group in the compilation order, and merges the complete machine code and table entry data of the merged sections using the key's start_entry and end_entry as boundaries for inter-segment linking. Sections with gaps are filled with default instructions and table entry data.

[0115] After linking the P4 table entry data and machine instruction code, a global instruction identifier is assigned to the linking result based on the code segment base address in the P4 table entry data. In implementation, the starting instruction address of each segment is recorded, and combined with the instruction's offset within the segment, a globally unique instruction address is generated and filled into the action id table entry. In one implementation, the P4 assembler is configured with a key action programming model. Tailored to the characteristics of P4 programming, the assembler has designed a key action programming model, such as... Figure 3 The diagram illustrates a key-action programming model, which describes the matching relationship between keys and assembly instructions (actions). A key matches at least one assembly instruction (action), or multiple keys match the same assembly instruction (action). Specifically, the number of entries for keys and action IDs is strictly the same. After a key matches, the index stored under the same entry for the action ID is taken as the starting address of the instruction to be executed for that key, based on the key's entry index. The action is a series of assembly instructions, the number and logic of which are determined by the application.

[0116] When writing assembly instructions, the action matching the key should be appended directly after the key as an assembly instruction in a way that aligns with human thinking habits. The specific format is as follows:

[0117] .key [key_name1] {start_entry:end_entry} key_data_path

[0118] instruction1

[0119] instruction2 ...

[0120] .key [key_name2] {start_entry:end_entry} key_data_path

[0121] instruction1

[0122] instruction2 ...

[0123] Based on this, the offset of the instruction in the linking result is determined. The key corresponding to the linking result is determined based on the offset and the code segment base address. Then, according to the key-action programming model and the key corresponding to the link, the global instruction identifier corresponding to the linking result is determined. Specifically, the Action ID inference mechanism is as follows:

[0124] Based on the context of a section and the sequence number of the instruction within that section, an efficient mapping between instructions and hardware entries is achieved. Key design points are as follows: each key is associated with a unique Action ID, and the Action ID stores the starting address of the instruction sequence; instructions within each section are addressed starting from 0; during section linking, each section is assigned a globally unique instruction base address; the integer instruction address = section base address + instruction offset within the section, stored in the Action ID entry; default actions, miss handling, etc., use the same algorithm to ensure correct processing in various network scenarios.

[0125] This mechanism simplifies network application development, allowing developers to focus on business logic rather than underlying implementation, while improving code reusability and execution efficiency.

[0126] Step 6: Add independent section header information to the linked table entries and instruction machine code according to their types to form complete section binary code (i.e., code segment binary code). In implementation, based on the target component to which the code segment group belongs, assign code segment header information to the linked result to obtain the code segment binary code. Specifically, generate a unified segment information header, containing information such as segment type, segment length, segment start address, segment end address, number of segment instructions, and segment instruction addresses. Figure 4 The diagram shows a section binary code.

[0127] Step 7: Link all section binaries, add firmware header information, and output the complete firmware file p4data.bin. See the example below. Figure 5 The diagram shown is of a firmware file p4data.bin, which includes firmware header information such as configuration name, version number, creation time, total file size, header length, number of files, magic number, checksum, and reserved fields.

[0128] In summary, the embodiments of the present invention provide a programming method for programming a self-developed P4 processor. Through a unified assembly instruction set and a flexible programming model, it simplifies the programming process of network processors, improves development efficiency, and closely approximates the self-developed P4 processor. It also allows for deep optimization of network protocols for hardware resources, thereby improving performance.

[0129] Based on the foregoing embodiments, this invention provides a code compilation device based on a P4 assembler. This device is applied to a P4 assembler, which includes an Ingress unit and an Egress unit. Both the Ingress and Egress units contain a Parser component, a Mat component, and a Deparser component. See [link to documentation]. Figure 6 The diagram shown illustrates the structure of a code compilation device based on the P4 assembler. The device includes the following components:

[0130] The file acquisition module 602 is used to acquire the assembly code file to be processed. The assembly code file is written according to the instruction format of the P4 assembler.

[0131] The splitting and compiling module 604 is used to split and compile the assembly code file to obtain multiple code segment compilation results. The code segment compilation results include at least auxiliary information, P4 table entry data and machine instruction code.

[0132] Grouping module 606 is used to classify the code segment compilation results into code segment groups based on auxiliary information, using the Parser component, Mat component and Deparser component contained in the Ingress unit and Egress unit as classification types;

[0133] Linking module 608 is used to link the P4 table entries and machine instruction codes contained in the code segment group, and to assign a global instruction identifier and code segment header information to the linking result to obtain the code segment binary code; wherein, the global instruction identifier is used to describe the target assembly instruction corresponding to the linking result, and the code segment header information is used to describe the classification type to which the linking result belongs;

[0134] Firmware file generation module 610 is used to generate firmware files based on code segment binary code.

[0135] The code compilation device based on the P4 assembler provided in this embodiment of the invention can simplify the compilation process of network processors and support the programming of complex network protocols on the self-developed P4 assembler, thereby improving development efficiency.

[0136] The device provided in this embodiment of the invention has the same implementation principle and technical effect as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the device embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0137] This invention provides an electronic device, specifically, the electronic device includes a processor and a memory; the memory stores a computer program, which, when run by the processor, executes the method described in any of the above embodiments.

[0138] Figure 7The present invention provides a schematic diagram of the structure of an electronic device 100, which includes a processor 70, a memory 71, a bus 72 and a communication interface 73. The processor 70, the communication interface 73 and the memory 71 are connected through the bus 72. The processor 70 is used to execute executable modules, such as computer programs, stored in the memory 71.

[0139] The memory 71 may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 73 (which can be wired or wireless), such as the Internet, wide area network, local area network, metropolitan area network, etc.

[0140] Bus 72 can be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 7 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0141] The memory 71 is used to store programs. After receiving an execution instruction, the processor 70 executes the programs. The method executed by the device for defining the flow process disclosed in any of the foregoing embodiments of the present invention can be applied to the processor 70 or implemented by the processor 70.

[0142] The processor 70 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 70 or by instructions in software form. The processor 70 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this invention can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules may reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 71. Processor 70 reads the information in memory 71 and, in conjunction with its hardware, completes the steps of the above method.

[0143] The computer program product of the readable storage medium provided in the embodiments of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the foregoing method embodiments. For specific implementation, please refer to the foregoing method embodiments, which will not be repeated here.

[0144] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0145] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for code compilation based on P4 assembler, characterized in that, The method is applied to a P4 assembler, the P4 assembler comprises an Ingress unit and an Egress unit, the Ingress unit and the Egress unit each comprise a Parser component, a Mat component and a Deparser component, and the method comprises: obtaining an assembly code file to be processed, the assembly code file being written according to an instruction format of the P4 assembler; splitting and compiling the assembly code file to obtain a plurality of code segment compilation results, the code segment compilation results at least comprising auxiliary information, P4 table item data and machine instruction codes, the auxiliary information at least declaring a direction of entry and exit of the instruction and a component to which the instruction belongs, and the P4 table item data at least comprising key attribute information, the key attribute information comprising a code segment base address, a segment start address and a segment end address; classifying the code segment compilation results according to the auxiliary information and the Parser component, the Mat component and the Deparser component comprised in the Ingress unit and the Egress unit as classification types to obtain a code segment group; linking the P4 table item data and the machine instruction codes comprised in the code segment group, and assigning a global instruction identifier and code segment header information to a linking result to obtain a code segment binary code; wherein the global instruction identifier is used to describe a target assembly instruction corresponding to the linking result, and the code segment header information is used to describe the classification type to which the linking result belongs; generating a firmware file based on the code segment binary code; linking the P4 table item data and the machine instruction codes comprised in the code segment group comprises: for the code segment group corresponding to the Parser component and the Deparser component, performing the following operations: taking a compilation order as a linking order, taking the segment start address and the segment end address as boundaries, and linking the P4 table item data and the machine instruction codes in the code segment compilation results comprised in the code segment group; the Mat component comprises a plurality of processing sub-components, and for the code segment group corresponding to the Mat component, performing the following operations: taking the processing sub-components as classification types, classifying the code segment compilation results comprised in the code segment group to obtain a plurality of code segment sub-groups, taking a compilation order as a linking order, and taking the segment start address and the segment end address as boundaries to link the P4 table item data and the machine instruction codes in the code segment compilation results comprised in the code segment sub-groups.

2. The P4 assembler-based code compilation method of claim 1, wherein, splitting and compiling the assembly code file to obtain a plurality of code segment compilation results comprises: analyzing a context relationship between instructions comprised in the assembly code file to split the assembly code file based on the context relationship to obtain a plurality of code segments; compiling the code segments to compile pseudo-instructions comprised in the code segments into auxiliary information and P4 table item data, and compile other instructions comprised in the code segments into machine instruction codes to obtain code segment compilation results.

3. The P4 assembler-based code compilation method of claim 1, wherein, According to the auxiliary information, the code segment compilation result is classified by the Ingress unit, the Parser component, the Mat component and the Deparser component included in the Egress unit to obtain a code segment group, including: According to the type declaration in the auxiliary information, the target component to which the code segment compilation result belongs is determined from the Ingress unit, the Parser component, the Mat component and the Deparser component included in the Egress unit; Based on the target component to which the code segment compilation result belongs, the code segment compilation result is classified to obtain a code segment group corresponding to each target component.

4. The P4 assembler-based code compilation method of claim 1, wherein, The code segment binary code is obtained by assigning a global instruction identifier and code segment header information to the linking result, including: According to the code segment base address in the P4 table item data, a global instruction identifier is assigned to the linking result, and according to the target component to which the code segment group belongs, code segment header information is assigned to the linking result to obtain code segment binary code.

5. The P4 assembler-based code compilation method of claim 4, wherein, The P4 assembler is configured with a key action programming model, and the key action programming model is used to describe the matching relationship between the key and the assembly instruction. One key matches at least one assembly instruction, or multiple keys match the same assembly instruction. According to the code segment base address in the P4 table item data, a global instruction identifier is assigned to the linking result, including: The offset of the instruction in the linking result is determined, the key corresponding to the linking result is determined based on the offset and the code segment base address, and the global instruction identifier corresponding to the linking result is determined according to the key action programming model and the key corresponding to the linking.

6. The P4 assembler-based code compilation method of claim 1, wherein, Based on the code segment binary code, a firmware file is generated, including: The code segment binary code is linked, and firmware header information is added to the linking result to obtain a firmware file.

7. A code compiling apparatus based on a P4 assembler, characterized by, The device is applied to a P4 assembler, and the P4 assembler includes an Ingress unit and an Egress unit. The Ingress unit and the Egress unit each include a Parser component, a Mat component and a Deparser component. The device includes: A file acquisition module is configured to acquire an assembly code file to be processed. The assembly code file is obtained according to the instruction format of the P4 assembler; A splitting and compiling module is configured to split and compile the assembly code file to obtain a plurality of code segment compilation results. The code segment compilation result at least includes auxiliary information, P4 table item data and machine instruction code. The auxiliary information at least declares the direction of the instruction and the component to which the instruction belongs. The P4 table item data at least includes key attribute information, and the key attribute information includes a code segment base address, a segment start address and a segment end address. a grouping module, configured to group the code segment compilation results according to the auxiliary information into code segment groups according to the classification types of the Parser component, the Mat component and the Deparser component included in the Ingress unit and the Egress unit; a linking module, configured to link the P4 table item data and the machine instruction code included in the code segment groups, and assign global instruction identifiers and code segment header information to the linking results to obtain code segment binary codes; the global instruction identifiers are used to describe target assembly instructions corresponding to the linking results, and the code segment header information is used to describe the classification types to which the linking results belong; a firmware file generation module, configured to generate a firmware file based on the code segment binary codes; the linking module is specifically configured to: perform the following operations on the code segment groups corresponding to the Parser component and the Deparser component: link the P4 table item data and the machine instruction code in the code segment compilation results included in the code segment groups according to the compiling order as the linking order and the segment start address and the segment end address as boundaries; the Mat component includes a plurality of processing sub-components, and the linking module is specifically configured to perform the following operations on the code segment groups corresponding to the Mat component: group the code segment compilation results included in the code segment groups according to the processing sub-components as classification types to obtain a plurality of code segment sub-groups, and link the P4 table item data and the machine instruction code in the code segment compilation results included in the code segment sub-groups according to the compiling order as the linking order and the segment start address and the segment end address as boundaries.

8. An assembler, characterized in that, a processor and a memory, the memory stores computer executable instructions capable of being executed by the processor, and the processor executes the computer executable instructions to implement the method in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer executable instructions, and when the computer executable instructions are called and executed by the processor, the computer executable instructions cause the processor to implement the method in any one of claims 1 to 6.

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