A method and device for optimizing DPU side memory, a DPU chip, an AI cluster acceleration card and a cloud computing host

By utilizing the PCIe link and DMA engine in the DPU system to migrate inactive memory pages to HOST DDR, the problem of insufficient DPU memory resources is solved, achieving low-cost memory expansion and performance improvement, avoiding disk I/O latency, and improving system stability and throughput.

CN121070624BActive Publication Date: 2026-03-20SHENZHEN JAGUAR MICROSYSTEMS CO LTD
2 Cites 0 Cited by

Patent Information

Application Number
CN202511596046.9
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2025-11-04
Publication Date
2026-03-20
Estimated Expiration
2045-11-04

AI Technical Summary

Technical Problem

When existing DPU systems lack memory resources, they rely on slow SATA disks for data swapping, resulting in performance fluctuations and I/O latency. This makes it difficult to effectively expand memory resources and increases the cost of hardware upgrades.

Method used

By using PCIe links and DMA engines, inactive memory pages on the DPU side are migrated to DDR memory on the host side, creating a virtual memory swapping device. This enables cross-device memory collaborative management, avoids reliance on SATA disks, and improves memory utilization efficiency and available capacity.

Benefits of technology

It significantly reduces the IO latency of memory swapping, avoids business jitter, expands the memory capacity of the DPU, and improves the overall system performance and carrying capacity, making it particularly suitable for high-throughput scenarios.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

The application provides a method, device, DPU chip, AI cluster acceleration card and cloud computing host for optimizing DPU side memory, comprising: sending a memory optimization request to a host; receiving a response notification from the host; constructing a virtual memory exchange device according to the response notification; when a memory low water line threshold is triggered, exchanging out DPU side memory into the virtual memory exchange device; when memory in the virtual memory exchange device needs to be accessed, exchanging in corresponding memory in the successfully reserved host side memory address range into the DPU side memory. According to the technical scheme of the application, the memory resource dynamic optimization and expansion of the DPU can be realized at low cost, the disk IO delay is reduced, and the overall system performance is improved.
Need to check novelty before this filing date? Find Prior Art