Ethernet-based power digital recording high-speed sampling data processing method and system

Abstract

The application relates to the technical field of power system digital recording, and provides a power digital recording high-speed sampling data processing method and system based on Ethernet, which comprises the following steps: setting a memory pool; writing a FIFO module to manage the memory pool, wherein the FIFO module sets a quantitative FIFO descriptor; registering a hook function which can be processed by the hook function when power digital recording high-speed sampling data arrives; calling the FIFO module to copy a data packet into a memory block corresponding to the FIFO descriptor; and real-time scanning the data packet in the memory block corresponding to the FIFO descriptor in the FIFO module, sending the data packet to a corresponding data storage module according to a service label in the data packet, and storing the data packet to a hard disk according to the memory block address of the FIFO descriptor. According to the scheme, the application optimizes the collection, transmission and processing flow of high-frequency sampling data, and significantly improves the data processing speed and system reliability.

Description

Technical Field

[0001] This invention relates to the field of digital waveform recording technology for power systems, and in particular to a high-speed sampling data processing method and system for power digital waveform recording based on Ethernet. Background Technology

[0002] In the field of digital power system recording, fault recording devices need to acquire grid operation data at high frequencies (e.g., 10kHz to 100kHz), including parameters such as voltage, current, and power, to capture and analyze transient faults. Traditional Ethernet data processing methods have the following problems when processing high-frequency sampled data:

[0003] 1) High protocol stack overhead: Processing data packets through TCP / IP or UDP protocol stacks introduces significant latency, which cannot meet the stringent real-time requirements of power systems.

[0004] 2) Data packet loss risk: The data traffic generated by high-frequency sampling is huge. Traditional caching mechanisms are prone to data loss under sudden traffic, which affects the integrity of fault recording.

[0005] 3) Limited throughput: The single queue processing mechanism cannot effectively distinguish between different types of waveform data (such as fault-triggered data and regular monitoring data), which limits the system throughput.

[0006] Therefore, there is an urgent need for a high-speed sampling data processing method that can reduce latency, prevent packet loss, and improve throughput to meet the real-time and reliability requirements of power digital waveform recording. Summary of the Invention

[0007] The purpose of this invention is to solve at least one technical problem in the background art and to provide a method and system for high-speed sampling data processing of power digital waveform recording based on Ethernet.

[0008] To achieve the above objectives, the present invention provides a high-speed sampling data processing method for power digital waveform recording based on Ethernet, comprising:

[0009] Configure a memory pool to cache high-speed sampling data packets of digital power waveform recording;

[0010] Write a FIFO module to manage the memory pool. The FIFO module sets a fixed number of FIFO descriptors, and each FIFO descriptor corresponds to a memory block in the memory pool.

[0011] Write and register hook functions at the Ethernet driver packet receiving entry point so that they can be processed when high-speed sampling data from power digital waveform recording arrives;

[0012] Call the FIFO module to copy the data packets processed by the hook function to the memory block managed by the FIFO descriptor;

[0013] The system scans data packets in the memory block corresponding to the FIFO descriptor in the FIFO module in real time. Based on the service tag in the data packet, the data packet is sent to the corresponding data storage module. The data storage module stores the data packet to the hard disk according to the memory block address of the FIFO descriptor. Then the FIFO descriptor is recycled and reused.

[0014] According to one aspect of the present invention, the step of calling the FIFO module to copy the data packet processed by the hook function to the memory block corresponding to the FIFO descriptor is as follows:

[0015] Call the FIFO module to obtain an available FIFO descriptor. Obtain the starting address of the memory block based on the address information in the FIFO descriptor. Then copy the data packet into the memory block based on the starting address of the memory block.

[0016] According to one aspect of the present invention, the FIFO descriptors constitute two FIFO descriptor queues, the first FIFO descriptor queue consists of FIFO descriptors that have already contained data packets, and the second FIFO descriptor queue consists of FIFO descriptors corresponding to free memory blocks;

[0017] When the FIFO module is invoked, a FIFO descriptor corresponding to a free memory block is obtained from the second FIFO descriptor queue. Then, the starting address of the memory block is obtained according to the address information in the FIFO descriptor. The data packet is then copied to the memory block according to the starting address of the memory block. Finally, the FIFO descriptor corresponding to the memory block is linked to the tail of the first FIFO descriptor queue.

[0018] According to one aspect of the present invention, the memory pool for caching high-speed sampling data packets of power digital waveform recording is:

[0019] Reserved memory is used at the beginning of the kernel driver as a memory pool to cache data packets of high-speed sampling data of power digital waveform recording.

[0020] According to one aspect of the present invention, the FIFO module calculates the number of required FIFO descriptors based on the memory pool size and the FIFO memory block size, wherein each FIFO descriptor manages a memory block in the memory pool.

[0021] To achieve the above objectives, the present invention also provides a high-speed sampling data processing system for power digital waveform recording based on Ethernet, comprising:

[0022] The memory pool setting module configures the memory pool for caching high-speed sampling data packets of digital power waveform recording.

[0023] The FIFO module is a writing module that manages the memory pool. The FIFO module sets a certain number of FIFO descriptors, and each FIFO descriptor corresponds to a memory block in the memory pool.

[0024] The hook function registration module writes and registers hook functions at the Ethernet driver packet receiving entry point, so that the high-speed sampling data of the power digital waveform recording can be processed by the hook functions when it arrives.

[0025] The data packet copying module calls the FIFO module to copy the data packets processed by the hook function to the memory block managed by the FIFO descriptor.

[0026] The data packet storage and processing module scans the data packets in the memory block corresponding to the FIFO descriptor in the FIFO module in real time. Based on the service tag in the data packet, it sends the data packet to the corresponding data storage module. The data packet data storage module stores the data packet to the hard disk according to the memory block address of the FIFO descriptor. Then, the FIFO descriptor is recycled and reused.

[0027] To achieve the above objectives, the present invention also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, it implements the Ethernet-based high-speed sampling data processing method for power digital waveform recording as described above.

[0028] To achieve the above objectives, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the Ethernet-based high-speed sampling data processing method for power digital waveform recording as described above.

[0029] According to the present invention, this invention optimizes the acquisition, transmission, and processing flow of high-frequency sampled data by combining Ethernet communication technology with efficient data compression, synchronization, and distribution methods. This keeps the total latency from data reception to storage within milliseconds (50μs interrupt processing + 0.1μs FIFO writing + compression overhead), significantly improving the processing speed of high-frequency sampled data. Simultaneously, the efficient FIFO module ensures data integrity and order even under high load (400Mbps traffic), supports a 10kHz sampling rate, and achieves a critical event capture rate of over 99.9%, meeting the requirements of power systems. Results show that on an embedded platform with a 1GHz dual-core CPU and a 1Gbps Ethernet interface, the system can stably handle 400Mbps traffic with low latency and high reliability, making it suitable for high real-time scenarios such as power digital waveform recording.

[0030] This method is not only applicable to fault recording devices in power systems, but can also be extended to other fields requiring high-speed data processing, such as dynamic monitoring of new energy power generation systems (e.g., wind power, photovoltaic), real-time analysis of electricity market transaction data, and high-frequency signal processing in industrial automation. Furthermore, this invention supports multi-node collaborative operation, meeting the needs of modern smart grids for distributed data processing and remote monitoring. It provides technical support for fault diagnosis, operation optimization, and preventative maintenance of power systems, driving power systems towards greater efficiency and intelligence. Attached Figure Description

[0031] Figure 1 The flowchart illustrates a high-speed sampling data processing method for Ethernet-based digital power waveform recording according to an embodiment of the present invention. Detailed Implementation

[0032] The invention will now be discussed with reference to exemplary embodiments. It should be understood that the described embodiments are merely intended to enable those skilled in the art to better understand and thus implement the invention, and are not intended to imply any limitation on the scope of the invention.

[0033] As used herein, the term "comprising" and its variations are to be interpreted as open-ended terms meaning "including but not limited to". The term "based on" is to be interpreted as "at least partially based on". The terms "one embodiment" and "an embodiment" are to be interpreted as "at least one embodiment".

[0034] Figure 1 This diagram illustrates a flowchart of a high-speed sampling data processing method for Ethernet-based digital power waveform recording according to an embodiment of the present invention. Figure 1 As shown, in this embodiment, the high-speed sampling data processing method for power digital waveform recording based on Ethernet includes:

[0035] Configure a memory pool to cache high-speed sampling data packets of digital waveform recording;

[0036] Write a FIFO module to manage the memory pool. The FIFO module sets a fixed number of FIFO descriptors, and each FIFO descriptor corresponds to a memory block in the memory pool.

[0037] Write and register hook functions at the Ethernet driver packet receiving entry point so that they can be processed when high-speed sampling data from power digital waveform recording arrives;

[0038] Call the FIFO module to copy the data packets processed by the hook function to the memory block managed by the FIFO descriptor;

[0039] The system scans data packets in the memory block corresponding to the FIFO descriptor in the FIFO module in real time. Based on the service tag in the data packet, the data packet is sent to the corresponding data storage module. The data storage module stores the data packet to the hard disk according to the memory block address of the FIFO descriptor. Then the FIFO descriptor is recycled and reused.

[0040] In this embodiment, the FIFO (First In, First Out) module is a data structure module for managing a memory pool, designed to efficiently store and process data arriving in chronological order (such as high-speed sampling data from power digital waveform recording). This module organizes memory blocks in the memory pool by maintaining a set of FIFO descriptors. Each FIFO descriptor manages a fixed-size memory block, providing data write and read operations. The FIFO descriptors function as a circular buffer by maintaining read and write pointers, ensuring data is processed in a first-in, first-out order. In this embodiment, the data message includes custom message header information, containing a sequence number, CRC checksum, service tag, and optional encrypted header information. The sequence number identifies the message order, supports subsequent reassembly operations, and ensures data packets are processed in the correct order; the CRC is used to verify message integrity and detect errors during transmission; the service tag identifies the message's service type or priority, allocating the message to the corresponding processing queue or module (e.g., high-priority service, low-priority service, etc.); if the message involves sensitive data, it is checked against the encrypted header information to ensure compliance with security policies (e.g., mandatory encryption requirements). The hook function in this invention performs message verification, decoding and filtering based on message header information, and stores the obtained valid data in the memory block managed by the FIFO descriptor.

[0041] Furthermore, according to one embodiment of the present invention, the FIFO module is invoked to copy the data packet processed by the hook function to the memory block corresponding to the FIFO descriptor as follows:

[0042] Call the FIFO module to obtain an available FIFO descriptor. Obtain the starting address of the memory block based on the address information in the FIFO descriptor. Then copy the data packet into the memory block based on the starting address of the memory block.

[0043] Furthermore, in this embodiment, the FIFO descriptors constitute two FIFO descriptor queues. The first FIFO descriptor queue consists of FIFO descriptors that already contain data packets (i.e., the memory block corresponding to the FIFO descriptor already stores data packets), and the second FIFO descriptor queue consists of FIFO descriptors corresponding to free memory blocks.

[0044] When the FIFO module is invoked, a FIFO descriptor corresponding to a free memory block is obtained from the second FIFO descriptor queue. Then, the starting address of the memory block is obtained according to the address information in the FIFO descriptor. The data packet is then copied to the memory block according to the starting address of the memory block. Finally, the FIFO descriptor corresponding to the memory block is linked to the tail of the first FIFO descriptor queue.

[0045] Furthermore, according to one embodiment of the present invention, the memory pool for caching high-speed sampling data packets of power digital waveform recording is configured as follows:

[0046] At the beginning of the kernel driver, reserved memory is used as a memory pool to cache data packets of high-speed sampling data from digital power waveform recording. The starting address and size information of the memory pool are stored in global variables.

[0047] Furthermore, according to one embodiment of the present invention, the FIFO module calculates the required number of FIFO descriptors based on the memory pool size and the FIFO memory block size, with each FIFO descriptor corresponding to a memory block in the memory pool. Each memory block is used to store data packets of the sampled data.

[0048] According to the above-described scheme of this invention, the present invention optimizes the acquisition, transmission, and processing flow of high-frequency sampling data by combining Ethernet communication technology with efficient data processing methods, significantly improving data processing speed and system reliability. This method is not only applicable to fault recording devices in power systems, but can also be extended to other fields requiring high-speed data processing, such as dynamic monitoring of new energy power generation systems (e.g., wind power, photovoltaic), real-time analysis of electricity market transaction data, and high-frequency signal processing in industrial automation. Furthermore, this invention supports multi-node collaborative operation, meeting the needs of modern smart grids for distributed data processing and remote monitoring, providing technical support for fault diagnosis, operation optimization, and preventative maintenance of power systems, and promoting the advancement of power systems towards greater efficiency and intelligence.

[0049] Furthermore, to achieve the above objectives, the present invention also provides a high-speed sampling data processing system for power digital waveform recording based on Ethernet, comprising:

[0050] The memory pool setting module configures the memory pool for caching high-speed sampling data packets of digital power waveform recording.

[0051] The FIFO module is a writing module that manages the memory pool. The FIFO module sets a certain number of FIFO descriptors, and each FIFO descriptor corresponds to a memory block in the memory pool.

[0052] The hook function registration module writes and registers hook functions at the Ethernet driver packet receiving entry point, so that the high-speed sampling data of the power digital waveform recording can be processed by the hook functions when it arrives.

[0053] The data packet copying module calls the FIFO module to copy the data packets processed by the hook function to the memory block managed by the FIFO descriptor.

[0054] The data packet storage and processing module scans the data packets in the memory block corresponding to the FIFO descriptor in the FIFO module in real time. Based on the service tag in the data packet, it sends the data packet to the corresponding data storage module. The data packet data storage module stores the data packet to the hard disk according to the memory block address of the FIFO descriptor. Then, the FIFO descriptor is recycled and reused.

[0055] In this embodiment, the FIFO (First In, First Out) module is a data structure module for managing a memory pool, designed to efficiently store and process data arriving in chronological order (such as high-speed sampling data from power digital waveform recording). This module organizes memory blocks in the memory pool by maintaining a set of FIFO descriptors. Each FIFO descriptor manages a fixed-size memory block, providing data write and read operations. The FIFO descriptors function as a circular buffer by maintaining read and write pointers, ensuring data is processed in a first-in, first-out order. In this embodiment, the data message includes custom message header information, containing a sequence number, CRC checksum, service tag, and optional encrypted header information. The sequence number identifies the message order, supports subsequent reassembly operations, and ensures data packets are processed in the correct order; the CRC is used to verify message integrity and detect errors during transmission; the service tag identifies the message's service type or priority, allocating the message to the corresponding processing queue or module (e.g., high-priority service, low-priority service, etc.); if the message involves sensitive data, it is checked against the encrypted header information to ensure compliance with security policies (e.g., mandatory encryption requirements). The hook function in this invention performs message verification, decoding and filtering based on message header information, and stores the obtained valid data in the memory block managed by the FIFO descriptor.

[0056] Furthermore, according to one embodiment of the present invention, the FIFO module is invoked to copy the data packet processed by the hook function to the memory block corresponding to the FIFO descriptor as follows:

[0057] Call the FIFO module to obtain an available FIFO descriptor. Obtain the starting address of the memory block based on the address information in the FIFO descriptor. Then copy the data packet into the memory block based on the starting address of the memory block.

[0058] Furthermore, in this embodiment, the FIFO descriptors constitute two FIFO descriptor queues. The first FIFO descriptor queue consists of FIFO descriptors that already contain data packets (i.e., the memory block corresponding to the FIFO descriptor already stores data packets), and the second FIFO descriptor queue consists of FIFO descriptors corresponding to free memory blocks.

[0059] When the FIFO module is invoked, a FIFO descriptor corresponding to a free memory block is obtained from the second FIFO descriptor queue. Then, the starting address of the memory block is obtained according to the address information in the FIFO descriptor. The data packet is then copied to the memory block according to the starting address of the memory block. Finally, the FIFO descriptor corresponding to the memory block is linked to the tail of the first FIFO descriptor queue.

[0060] Furthermore, according to one embodiment of the present invention, the memory pool for caching high-speed sampling data packets of power digital waveform recording is configured as follows:

[0061] At the beginning of the kernel driver, reserved memory is used as a memory pool to cache data packets of high-speed sampling data from digital power waveform recording. The starting address and size information of the memory pool are stored in global variables.

[0062] Furthermore, according to one embodiment of the present invention, the FIFO module calculates the required number of FIFO descriptors based on the memory pool size and the FIFO memory block size, with each FIFO descriptor corresponding to a memory block in the memory pool. Each memory block is used to store data packets of the sampled data.

[0063] According to the above-described scheme of this invention, the present invention optimizes the acquisition, transmission, and processing flow of high-frequency sampling data by combining Ethernet communication technology with efficient data processing methods, significantly improving data processing speed and system reliability. This method is not only applicable to fault recording devices in power systems, but can also be extended to other fields requiring high-speed data processing, such as dynamic monitoring of new energy power generation systems (e.g., wind power, photovoltaic), real-time analysis of electricity market transaction data, and high-frequency signal processing in industrial automation. Furthermore, this invention supports multi-node collaborative operation, meeting the needs of modern smart grids for distributed data processing and remote monitoring, providing technical support for fault diagnosis, operation optimization, and preventative maintenance of power systems, and promoting the advancement of power systems towards greater efficiency and intelligence.

[0064] Furthermore, to achieve the above objectives, the present invention also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, it implements the Ethernet-based high-speed sampling data processing method for power digital waveform recording as described above.

[0065] Furthermore, to achieve the above objectives, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the Ethernet-based high-speed sampling data processing method for power digital waveform recording as described above.

[0066] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely one preferred embodiment of the invention and are only used to explain the invention. They do not limit the scope of protection of the invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0067] Example 1

[0068] This embodiment proposes a high-speed sampling data processing method for power digital waveform recording based on Ethernet. It directly receives raw packets from the hardware driver, bypassing the traditional protocol stack and significantly reducing data processing latency. A queue caching system based on a shared memory pool effectively prevents packet loss of high-frequency sampling data, ensuring the integrity of the waveform recording data. Specifically, the method of this embodiment includes the following steps:

[0069] Step S1, similar to general device driver development, uses reserved memory as the service's memory pool at the beginning of the Ethernet driver module. The size of the memory pool can be dynamically set by passing parameters from the kernel module. To facilitate the use of the data storage module in step S6 below, the starting address of the memory pool is mapped to user space by writing a character device driver.

[0070] Step S2: Write a FIFO module to manage the memory pool. Calculate the required number of FIFO descriptors based on the memory pool size and the FIFO memory block size. This can be implemented using two FIFO descriptor queues: the next queue (i.e., the first FIFO descriptor queue) represents FIFO descriptors that already contain business data, and the free queue (i.e., the second FIFO descriptor queue) represents FIFO descriptors with free memory blocks.

[0071] Step S3: Register and write a hook function at the Ethernet driver packet receiving entry point. The hook function processes and filters the service packets in the sampled data to obtain valid data.

[0072] Step S4: Obtain the free FIFO descriptor from the free queue through the data receiving module, copy the processed valid data packet to the memory block where the FIFO descriptor is executed, and then link the filled FIFO descriptor to the tail of the next queue.

[0073] Step S5: The data distribution module scans the FIFO descriptors of the next queue in real time. Based on the service tag of the data packet, the FIFO descriptor is passed to the corresponding data storage module for use (the data storage module stores the data packet to the hard disk according to the memory block address of the FIFO descriptor, and then the FIFO descriptor is recycled and reused).

[0074] In step S6, multiple data distribution modules process the FIFO descriptors obtained in step S5 in parallel. After using the FIFO descriptors, they are linked to the end of the free queue for the data receiving module in S4 to use in a loop.

[0075] Those skilled in the art will recognize that the modules and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0076] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described apparatus and equipment can be referred to the corresponding process in the foregoing method implementation, and will not be repeated here.

[0077] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or modules may be electrical, mechanical, or other forms.

[0078] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the objectives of the embodiments of the present invention, depending on actual needs.

[0079] In addition, the functional modules in the embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0080] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the sending / receiving methods of various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0081] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

[0082] It should be understood that the sequence number of each step in the invention and its embodiments does not absolutely imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

Claims

1. A high-speed sampling data processing method for power digital waveform recording based on Ethernet, characterized in that, include: Configure a memory pool to cache high-speed sampling data packets of digital waveform recording; Write a FIFO module to manage the memory pool. The FIFO module sets a fixed number of FIFO descriptors, and each FIFO descriptor corresponds to a memory block in the memory pool. Write and register hook functions at the Ethernet driver packet receiving entry point so that they can be processed when high-speed sampling data from power digital waveform recording arrives; Calling the FIFO module to copy the data packets processed by the hook function to the memory block managed by the FIFO descriptor is as follows: Call the FIFO module, obtain an available FIFO descriptor from the FIFO module, obtain the starting address of the memory block according to the address information in the FIFO descriptor, and then copy the data packets to the memory block according to the starting address of the memory block; The system scans data packets in the memory block corresponding to the FIFO descriptor in the FIFO module in real time, sends the data packets to the corresponding data storage module according to the service tag in the data packets, and the data storage module stores the data packets to the hard disk according to the memory block address of the FIFO descriptor. Then the FIFO descriptor is recycled and reused. The FIFO descriptors constitute two FIFO descriptor queues. The first FIFO descriptor queue consists of FIFO descriptors that already contain data packets, and the second FIFO descriptor queue consists of FIFO descriptors corresponding to free memory blocks. When the FIFO module is invoked, a FIFO descriptor corresponding to a free memory block is obtained from the second FIFO descriptor queue. Then, the starting address of the memory block is obtained according to the address information in the FIFO descriptor. The data packet is then copied to the memory block according to the starting address of the memory block. Finally, the FIFO descriptor corresponding to the memory block is linked to the tail of the first FIFO descriptor queue.

2. The method for high-speed sampling data processing of power digital waveform recording based on Ethernet according to claim 1, characterized in that, The memory pool for caching high-speed sampling data of power digital waveform recording is: Reserved memory is used at the beginning of the kernel driver as a memory pool to cache data packets of high-speed sampling data of power digital waveform recording.

3. The method for high-speed sampling data processing of power digital waveform recording based on Ethernet according to claim 1 or 2, characterized in that, The FIFO module calculates the number of required FIFO descriptors based on the memory pool size and the FIFO memory block size, with each FIFO descriptor corresponding to a memory block in the memory pool.

4. A high-speed sampling data processing system for power digital waveform recording based on Ethernet, characterized in that, include: The memory pool setting module configures the memory pool for caching high-speed sampling data packets of digital power waveform recording. The FIFO module is a writing module that manages the memory pool. The FIFO module sets a certain number of FIFO descriptors, and each FIFO descriptor corresponds to a memory block in the memory pool. The hook function registration module writes and registers hook functions at the Ethernet driver packet receiving entry point, so that the high-speed sampling data of the power digital waveform recording can be processed by the hook functions when it arrives. The data packet copying module calls the FIFO module to copy the data packets processed by the hook function to the memory block managed by the FIFO descriptor. The process is as follows: the FIFO module is called to obtain an available FIFO descriptor. The starting address of the memory block is obtained based on the address information in the FIFO descriptor. Then, the data packets are copied to the memory block based on the starting address of the memory block. The data packet storage and processing module scans the data packets in the memory block corresponding to the FIFO descriptor in the FIFO module in real time, and sends the data packets to the corresponding data storage module according to the service tag in the data packets. The data packet data storage module stores the data packets to the hard disk according to the memory block address of the FIFO descriptor, and then the FIFO descriptor is recycled and reused. The FIFO descriptors constitute two FIFO descriptor queues. The first FIFO descriptor queue consists of FIFO descriptors that already contain data packets, and the second FIFO descriptor queue consists of FIFO descriptors corresponding to free memory blocks. When the FIFO module is invoked, a FIFO descriptor corresponding to a free memory block is obtained from the second FIFO descriptor queue. Then, the starting address of the memory block is obtained according to the address information in the FIFO descriptor. The data packet is then copied to the memory block according to the starting address of the memory block. Finally, the FIFO descriptor corresponding to the memory block is linked to the tail of the first FIFO descriptor queue.

5. An electronic device, characterized in that, The method includes a processor, a memory, and a computer program stored in the memory and executable on the processor. When executed by the processor, the computer program implements the Ethernet-based high-speed sampling data processing method for power digital waveform recording as described in any one of claims 1-3.

6. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, it implements the Ethernet-based high-speed sampling data processing method for power digital waveform recording as described in any one of claims 1-3.

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