Artificial intelligence processor, electronic device, and instruction processing method

Abstract

The present disclosure provides an artificial intelligence processor, an electronic device, and an instruction processing method. The artificial intelligence processor comprises: an instruction processing unit, wherein the instruction processing unit is configured to sequentially obtain a plurality of instructions for processing; and an instruction trajectory tracking device comprising an encoding module, wherein the encoding module is configured to: obtain a first time interval between a start processing time of a first instruction and a start processing time of a second instruction in the plurality of instructions, wherein the second instruction is immediately after the first instruction, determine the first time interval as an instruction delay of the second instruction, and encode the instruction delay in a first encoding format in at least one variable length encoding format. The artificial intelligence processor can determine the execution trajectory of the instructions of the program with lower memory and transmission costs, and further accurately and sufficiently obtain the instruction delay.

Description

Technical Field

[0001] Embodiments of this disclosure relate to artificial intelligence, and more particularly to artificial intelligence processors, electronic devices, and instruction processing methods. Background Technology

[0002] In artificial intelligence scenarios, when a program is executed, the instructions (i.e., assembly instructions) within it exhibit varying execution times. Specifically, different instructions may have significantly different execution latencies. When developers perform processor performance analysis and optimization, they may need to obtain information about the actual execution latency of the instructions in the program for debugging purposes.

[0003] However, the process of obtaining instructions may suffer from incomplete information and excessive memory or transmission resource consumption. Summary of the Invention

[0004] According to at least one embodiment of the present disclosure, an artificial intelligence processor is provided, comprising: an instruction processing unit configured to sequentially acquire a plurality of instructions for processing; and an instruction trajectory tracking device including an encoding module configured to: acquire a first time interval between the start processing time of a first instruction and the start processing time of a second instruction among the plurality of instructions, wherein the second instruction immediately follows the first instruction; determine the first time interval as an instruction delay of the second instruction; and encode the instruction delay in a first encoding format among at least one variable-length encoding format.

[0005] For example, in a processor according to an embodiment of the present disclosure, the encoding module is further configured to: select the first encoding format from the at least one variable-length encoding format based on a delay value of the instruction delay of the second instruction.

[0006] For example, in a processor according to an embodiment of the present disclosure, the encoding module is further configured to: obtain at least one instruction delay range corresponding to the at least one variable-length encoding format; determine the instruction delay range into which the delay value of the instruction delay of the second instruction falls within the at least one instruction delay range; and select from the at least one variable-length encoding format an encoding format corresponding to the instruction delay range into which it falls as the first encoding format.

[0007] For example, in a processor according to an embodiment of the present disclosure, the plurality of instructions correspond to a plurality of instruction delays; each of the at least one instruction delay range corresponds to a probability of the plurality of instruction delays falling into the corresponding instruction delay range; and the encoding length of the encoding format corresponding to the first instruction delay range in the at least one instruction delay range is less than the encoding length of the encoding format corresponding to the second instruction delay range in the at least one instruction delay range, and wherein the probability of falling into the first instruction delay range in the at least one instruction delay range is greater than the probability of falling into the second instruction delay range in the at least one instruction delay range.

[0008] For example, in a processor according to an embodiment of the present disclosure, the encoding length of the encoding format corresponding to the first instruction delay range in the at least one instruction delay range is less than the encoding length of the encoding format corresponding to the second instruction delay range in the at least one instruction delay range, and the delay value of the instruction delay corresponding to the first instruction delay range is less than the delay value of the instruction delay corresponding to the second instruction delay range.

[0009] For example, in a processor according to an embodiment of this disclosure, the encoding module is further configured to: determine whether the second instruction belongs to a first type of instruction, wherein the first type of instruction includes one or more of the following: the last instruction in a program, a jump instruction, a predetermined type instruction that satisfies the execution conditions of a first type but does not satisfy the execution conditions of a second type different from the execution conditions of the first type, the execution conditions of the first type indicating that the execution results of other instructions required by the predetermined type instruction have been generated; wherein selecting the first encoding format from the at least one variable-length encoding format includes: in response to the second instruction not belonging to the first type of instruction, selecting the first encoding format from the at least one variable-length encoding format based on the delay value of the instruction delay of the second instruction, and wherein the encoding module is further configured to: in response to the second instruction belonging to the first type of instruction, select a predetermined encoding method as the first encoding format from the at least one variable-length encoding format.

[0010] For example, in a processor according to an embodiment of the present disclosure, wherein the encoding format corresponding to the first type of instruction has a first indication field and a delay field, the encoding module is further configured to: in response to the second instruction being the last instruction in the program: set the first indication field to a first predetermined value, encode the instruction delay of the second instruction into the delay field, and determine the instruction delay of instructions following the second instruction as unrelated to the program.

[0011] For example, in a processor according to an embodiment of the present disclosure, wherein the encoding format corresponding to the first type of instruction has a second indication field, a delay field, and an address field, the encoding module is further configured to: in response to the second instruction belonging to the jump instruction: set the second indication field to a second predetermined value, delay the encoding of the second instruction into the delay field, and store the address of the second instruction into the address field.

[0012] For example, in a processor according to an embodiment of the present disclosure, the encoding module is further configured to: in response to the second instruction not being a jump instruction: set the second indication field to a third predetermined value, encode the instruction of the second instruction with instruction delay into the delay field, and not store the address of the second instruction.

[0013] For example, in a processor according to an embodiment of the present disclosure, wherein the encoding format corresponding to the first type of instruction has a third indicator field and a delay field, the encoding module is further configured to: in response to the second instruction belonging to the predetermined type of instruction: set the third indicator field to a fourth predetermined value, and delay the encoding of the second instruction into a first delay field in the delay field.

[0014] For example, in a processor according to an embodiment of the present disclosure, the encoding module is further configured to: in response to the second instruction belonging to the predetermined type of instruction, obtain a second time interval between the start processing time of the first instruction and the time when the second instruction satisfies the execution conditions of the first type; and encode the second time interval into a second delay field in the delay field.

[0015] For example, in a processor according to an embodiment of the present disclosure, the second type of execution condition indicates that the hardware resources required to execute the second instruction are ready.

[0016] For example, in a processor according to an embodiment of the present disclosure, the instruction processing unit is further configured to send the start processing time of the first instruction and the start processing time of the second instruction to the encoding module.

[0017] For example, in a processor according to an embodiment of the present disclosure, the instruction trajectory tracking device further includes a configuration register configured to store configuration information indicating at least one of a program, a thread, and a thread bundle monitored by the encoding module, wherein the encoding module is at least one encoding module corresponding to each thread or at least one encoding module corresponding to each thread bundle.

[0018] For example, in a processor according to an embodiment of the present disclosure, the instruction trajectory tracking device further includes a storage module and a control module, wherein the encoding module is one or more, and wherein the storage module is configured to store at least the instruction delay; the control module is configured to determine the timing when the encoding module writes the instruction delay to the storage module.

[0019] For example, in a processor according to an embodiment of the present disclosure, the control module is further configured to: determine whether to encapsulate the instruction delay into a transmission data packet for transmission to an external storage device, wherein the memory footprint of the transmission data packet is greater than the memory footprint of the instruction delay.

[0020] For example, in a processor according to an embodiment of the present disclosure, the instruction processing unit includes a launch unit configured with a launch queue, and one or more instructions to be processed include one or more instructions waiting to be launched in the launch queue.

[0021] For example, in a processor according to an embodiment of the present disclosure, the plurality of instructions belong to a plurality of threads, and the plurality of threads are processed by a plurality of computing cores respectively.

[0022] An electronic device is provided according to at least one embodiment of the present disclosure, including any of the processors described above.

[0023] According to at least one embodiment of the present disclosure, an instruction processing method is provided, comprising: sequentially acquiring a plurality of instructions for processing; acquiring a first time interval between the start processing time of a first instruction and the start processing time of a second instruction among the plurality of instructions, wherein the second instruction immediately follows the first instruction; determining the first time interval as an instruction delay of the second instruction; and encoding the instruction delay in a first encoding format among at least one variable-length encoding format.

[0024] The artificial intelligence processor, electronic device, and instruction processing method provided according to at least one embodiment of this disclosure can obtain the execution trajectory of instructions in a program, thereby accurately and sufficiently determining instruction latency. The artificial intelligence processor, electronic device, and instruction processing method provided according to at least one embodiment of this disclosure can accurately and sufficiently determine instruction latency while consuming relatively low memory and transmission costs. Attached Figure Description

[0025] The above and other aspects, features, and advantages of specific embodiments of the present disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0026] Figure 1 A pipeline of an exemplary processor core is shown.

[0027] Figure 2 A schematic structural diagram of a multi-core processor according to at least one embodiment of the present disclosure is shown.

[0028] Figure 3 A schematic structural diagram of a command trajectory tracking device according to at least one embodiment of the present disclosure is shown.

[0029] Figure 4 A schematic structural diagram of a command trajectory tracking device according to at least one embodiment of the present disclosure is shown.

[0030] Figure 5 A schematic diagram of an instruction delay encoding format according to at least one embodiment of the present disclosure is shown.

[0031] Figure 6 A schematic diagram of an instruction delay encoding process according to at least one embodiment of the present disclosure is shown.

[0032] Figure 7 An instruction processing method according to at least one embodiment of the present disclosure is shown.

[0033] Figure 8 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown. Detailed Implementation

[0034] Before proceeding with the detailed description below, it may be advantageous to define certain words and phrases used throughout this disclosure. The terms “comprising” and “including” and their derivatives mean including but not limited to. The term “or” is inclusive, meaning and / or. The phrase “associated with” and its derivatives mean including, comprising, interconnecting, containing, contained within, connected or connected to, coupled or coupled to, communicating with, cooperating, intertwining, juxtaposing, proximate, binding or bound to, having, possessing attributes, having a relationship or being related to, etc. The term “controller” means any device, system, or part thereof that controls at least one operation. Such a controller may be implemented in hardware, or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, local or remote. The phrase “at least one,” when used with a list of items, means that different combinations of one or more of the listed items may be used, and that only one item from the list may be required. For example, "at least one of A, B, and C" includes any one of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0035] Definitions of other specific words and phrases are provided throughout this disclosure. Those skilled in the art will understand that, in many, if not most, cases, such definitions apply to the prior and future use of the words and phrases thus defined.

[0036] The various embodiments of the principles of this disclosure described below with reference to the accompanying drawings are for illustrative purposes only and should not be construed as limiting the scope of this disclosure in any way. Those skilled in the art will understand that the principles of this disclosure can be implemented in any suitably arranged system or device. In some cases, the actions described in the specification may be performed in a different order and the desired result may still be achieved. Furthermore, the processes depicted in the drawings do not necessarily require a specific order or sequential sequence to achieve the desired result. In certain embodiments, multitasking and parallel processing may be advantageous.

[0037] Artificial intelligence processors can use parallel architectures comprising multiple computing cores to achieve parallel execution of multiple programs, or they can achieve parallel execution of multiple programs within a single computing core through mechanisms such as task scheduling. However, during the parallel execution of multiple programs, due to access conflicts to hardware resources (e.g., transmission bandwidth, cache, and arithmetic units) and logical or data dependencies between programs, the execution times of the instructions (i.e., assembly instructions) included in the programs may differ. Specifically, different instructions may have significantly different execution latencies.

[0038] When users, such as developers, perform processor performance analysis and optimization, they may need to obtain latency data of the instructions included in the program during actual execution in order to locate bottlenecks and adjust scheduling strategies or resource configurations.

[0039] However, the process of obtaining instructions may suffer from incomplete information and excessive memory or transmission resource consumption.

[0040] Figure 1 A schematic structural diagram of an artificial intelligence processor is shown.

[0041] Artificial intelligence processors may include parallel processors such as general-purpose graphics processing units (GPGPUs), but this disclosure is not limited thereto. Figure 1 As shown, an artificial intelligence processor is actually an array of programmable multiprocessors. For example, a programmable multiprocessor can be a streaming processor cluster (SPC), such as including... Figure 1The diagram shows streaming processor clusters 1, ..., M, where M is a positive integer greater than 1. In an AI processor, one streaming processor cluster processes one computational task, or multiple streaming processor clusters process one computational task. Multiple streaming processor clusters share data through a global cache or global memory.

[0042] like Figure 1 As shown, taking streaming processor cluster 1 as an example, one streaming processor cluster includes multiple computing units, such as... Figure 1 The system is structured as Computation Unit 1, Computation Unit 2, ..., Computation Unit N, where N is a positive integer. Each Computation Unit (CU) performs arithmetic and logical operations, such as accumulation, reduction, and standard addition, subtraction, multiplication, and division. A Computation Unit includes multiple Cores (also called computational cores), each of which includes an Arithmetic Logic Unit (ALU), a floating-point unit, etc. These Cores are used to execute specific computational tasks. Furthermore, a Computation Unit may also include registers (e.g., ...). Figure 1 The register file and shared memory in a computing unit are used to store source and destination data related to computing tasks in a hierarchical manner. The shared memory in a computing unit is used to share data between the cores of that computing unit.

[0043] like Figure 1 As shown, each computing unit also provides a tensor core for performing tensor-related computations, such as tensor shrinking operations. Tensor cores can accelerate tensor operations such as matrix multiplication. Tensor cores in multiple computing units can be scheduled and controlled uniformly.

[0044] like Figure 1 As shown, each streaming processor cluster also provides a buffer for caching data from the N computing units within the streaming processor cluster.

[0045] In parallel computing, computational tasks are typically executed through multiple threads. These threads are divided into multiple thread blocks before execution in the artificial intelligence processor (or general-purpose graphics processor or parallel computing processor), and then dispatched via a thread block dispatch module. Figure 1(Not shown in the diagram) Multiple thread blocks are distributed to various computing units. All threads in a thread block must be assigned to the same computing unit for execution. Simultaneously, thread blocks are broken down into minimum execution thread bundles (or simply warps), each containing a fixed number (or less than this fixed number) of threads, for example, 32 threads. Multiple threads from multiple thread blocks can execute on multiple computing cores within the same computing unit, or on multiple computing cores in different computing units, sharing registers, shared memory, and other data transfer mechanisms.

[0046] In each computing unit, the thread beam scheduling / distribution module ( Figure 1 (Not shown in the diagram) Thread bundles are scheduled and allocated so that multiple computing cores within the computing unit can run thread bundles. Depending on the number of computing cores in the computing unit, multiple thread bundles within a thread block can execute concurrently or in a time-sharing manner. Multiple threads within each thread bundle execute the same instructions. Memory-executed instructions are issued to shared memory within the computing unit or further issued to intermediate-level caches, global caches, or global memory (e.g., [example cache]). Figure 1 It is used for reading and writing operations in high-bandwidth memory (HBM).

[0047] Figure 2 A schematic structural diagram of a multi-core processor according to at least one embodiment of the present disclosure is shown.

[0048] like Figure 2 As shown, a multi-core processor may include multiple computing cores such as 32, but this disclosure is not limited thereto. For example, those skilled in the art will understand that the number of computing cores provided above is merely illustrative, and a multi-core processor according to at least one embodiment of this disclosure may include more or fewer computing cores. Figure 2 The multi-core processor in the middle can correspond to Figure 1 The computing unit, Figure 2 The computational kernel in the middle can correspond to Figure 1 The core of it will not be described again here for the sake of brevity.

[0049] Each computing core in a multi-core processor can include one or more instruction processing units, such as, but not limited to, instruction fetch units, decode units, issue units, and artificial intelligence units, to perform processing operations on instructions. For example, instructions in a computing core go through instruction fetch, instruction decode, instruction issue, instruction execution, and write-back.

[0050] According to at least one embodiment of this disclosure, the instruction fetch unit can be configured to fetch instructions to be executed subsequently. The decode unit can be configured to decode the fetched instructions into control signals executable by the underlying hardware. The issue unit can monitor the execution status of a thread or thread bundle (e.g., waiting for operands or hardware resources to be ready) and issue instructions that meet the issue conditions to the execution unit, such as the artificial intelligence computing unit. The artificial intelligence computing unit can be configured to perform artificial intelligence-related calculations based on the issued instructions. The write-back unit can write the data output by the artificial intelligence computing unit back to memory or cache.

[0051] According to at least one embodiment of this disclosure, waiting queues are provided between each pipeline stage as needed. These queues are typically First-In-First-Out (FIFO) queues. For example, after the instruction fetch unit, an instruction buffer FIFO may be provided to buffer fetched instructions; after the decode unit, a decode FIFO may be provided to buffer decoded instructions. Simultaneously, the issue unit of the computation core is also configured with an issue queue to buffer instructions waiting to be executed by, for example, an artificial intelligence computation unit. After the issue unit, a write-back FIFO may be provided to buffer instructions awaiting confirmation of completion after execution.

[0052] According to at least one embodiment of this disclosure, the computing core can forward instruction information during instruction processing. For example, the instruction processing unit included in the computing core (e.g., instruction fetch unit, decoding unit, dispatch unit, artificial intelligence computing unit) can include or be used as an instruction trajectory generation module to forward instruction information to the instruction trajectory tracking device. The instruction information can include one or more of the following: instruction start processing time, instruction address, information indicating whether the instruction is a jump instruction, information indicating whether the instruction is the last instruction in the program, etc., but this disclosure is not limited thereto. In this way, the instruction trajectory tracking device can obtain the execution trajectory of the instructions in the program and thus accurately and sufficiently determine the instruction delay.

[0053] Figure 3 A schematic structural diagram of a command trajectory tracking device according to at least one embodiment of the present disclosure is shown.

[0054] According to at least one embodiment of this disclosure, the instruction fetch unit can be configured to fetch instructions to be executed subsequently. The decode unit can be configured to decode the fetched instructions into control signals executable by the underlying hardware. The issue unit can monitor the execution status of a thread or thread bundle (e.g., waiting for operands or hardware resources to be ready) and issue instructions that meet the issue conditions to the artificial intelligence computing unit. The artificial intelligence computing unit can be configured to perform artificial intelligence-related calculations based on the issued instructions. The write-back unit can write the data output by the artificial intelligence computing unit back to memory or cache.

[0055] According to at least one embodiment of this disclosure, the computing core can forward instruction information during instruction processing. For example, the instruction processing unit included in the computing core (e.g., instruction fetch unit, decoding unit, dispatch unit, artificial intelligence computing unit) can include or be used as an instruction trajectory generation module to forward instruction information to the instruction trajectory tracking device. The instruction information can include one or more of the following: instruction start processing time, instruction address, information indicating whether the instruction is a jump instruction, information indicating whether the instruction is the last instruction in the program, etc., but this disclosure is not limited thereto. In this way, the instruction trajectory tracking device can obtain the execution trajectory of the instructions in the program and thus accurately and sufficiently determine the instruction delay.

[0056] Figure 3 A schematic structural diagram of a command trajectory tracking device according to at least one embodiment of the present disclosure is shown.

[0057] like Figure 3 As shown, the instruction trajectory tracking device 3000 can receive instruction information from the instruction processing unit 3001, and the instruction trajectory tracking device 3000 may include an encoding module 3100.

[0058] According to at least one embodiment of the present disclosure, the instruction processing unit 3001 may include, as referred to Figure 2 This disclosure is not limited to one or more of the instruction fetch unit, decoding unit, dispatch unit, artificial intelligence computing unit, and write-back unit of at least one of the plurality of computing cores. The instruction processing unit 3001 can be configured to sequentially fetch multiple instructions for processing. For example, the instruction processing unit 3001 may have a sequentially arranged queue to process multiple instructions sequentially, but this disclosure is not limited to this. Taking the dispatch unit as an example, the dispatch unit may be configured with a dispatch queue including sequentially arranged instructions, and the instruction at the end of the dispatch queue may need to satisfy one or more dispatch conditions to be dispatched from the end of the dispatch queue, thereby being executed by downstream pipeline hardware (e.g., the artificial intelligence computing unit, etc.). The multiple instructions processed sequentially in the instruction fetch unit, decoding unit, artificial intelligence computing unit, and write-back unit also have conditions that need to be satisfied for processing; therefore, the multiple instructions processed sequentially in the instruction fetch unit, decoding unit, artificial intelligence computing unit, and write-back unit also have a waiting process, which is not described in detail here to avoid obscuring the focus of the present invention.

[0059] According to at least one embodiment of this disclosure, the instruction processing unit 3001 can provide instruction information to the instruction trajectory tracking device 3000 when processing instructions. As described above, the instruction information may include one or more of the following: the instruction start processing time, the instruction address, information indicating whether the instruction is a jump instruction, information indicating whether the instruction is the last instruction in the program, etc., but the embodiments of this disclosure are not limited thereto. Taking the transmitting unit as an example, the instruction start processing time may indicate the transmission time when the instruction is transmitted from the end of the transmitting queue, but the embodiments of this disclosure are not limited thereto. Similarly, corresponding start processing times can be set for the instruction fetch unit, decoding unit, artificial intelligence computing unit, write-back unit, etc., which will not be described in detail here to avoid obscuring the focus of the present invention.

[0060] According to at least one embodiment of this disclosure, the instruction processing unit 3001 can send the instruction information of the instruction to the instruction trajectory tracking device 3000 (e.g., the encoding module 3100) within the same clock cycle as the start processing time of the instruction. In this way, the encoding module 3100 can accurately record the start processing time of the instruction.

[0061] although Figure 3 A single encoding module 3100 is shown, but the instruction trajectory tracking device 3000 may include multiple encoding modules. These multiple encoding modules are configured to monitor the instruction latency of corresponding (or assigned) threads and / or thread bundles, respectively. According to at least one embodiment of this disclosure, the instruction itself may carry identification information about the thread and / or thread bundle to which it belongs. In this way, the instruction latency of multiple instructions belonging to one or more threads and / or thread bundles can be monitored. For example, the instruction processing unit 3001 may execute 32 thread bundles, and four encoding modules 3100 may be configured to monitor the instruction latency of instructions in four selected (e.g., selected by a multiplexer) thread bundles out of the 32 thread bundles, or 32 encoding modules 3100 may be configured to monitor the instruction latency of instructions in all 32 thread bundles.

[0062] According to at least one embodiment of this disclosure, the encoding module 3100 can acquire a first time interval between the start processing time of a first instruction and the start processing time of a second instruction among a plurality of instructions. The second instruction may immediately follow the first instruction; for example, there may be no other instructions between the second and first instructions. For example, the encoding module 3100 may be configured with a timer to determine the aforementioned first time interval. For example, if the encoding module 3100 receives instruction information from the corresponding instruction processing unit for instructions in the monitored thread and / or thread bundle within the current clock cycle, the value of the timer may be encoded along with at least a portion of the instruction information, and the timer may be reset to 0. If the encoding module 3100 does not receive instruction information from the corresponding instruction processing unit for instructions in the monitored thread and / or thread bundle within the current clock cycle, the value of the timer will increment by one.

[0063] According to at least one embodiment of this disclosure, the encoding module 3100 can determine a first time interval as the instruction delay of a second instruction, and encode the instruction delay using a first encoding format among at least one variable-length encoding formats. Taking a transmitting unit as an example, the time interval between the transmission time of the first instruction being transmitted from the end of the transmission queue and the transmission time of the second instruction being transmitted from the end of the transmission queue can be used as the instruction delay of the second instruction (e.g., transmission delay). For example, the encoding module 3100 can select an encoding format from at least one variable-length encoding format based on the characteristics of the instruction delay. Therefore, different instruction delays can correspond to different encoding formats. A variable-length encoding format can refer to a different number of bits in the encoded result. That is, different instruction delays can correspond to encoding results with different numbers of bits. In this way, the storage space and bit width occupied by storing and transmitting the encoded instruction delay can be reduced.

[0064] Compared to methods that calculate the percentage of time each instruction takes to execute during the entire program execution process, the processor according to at least one embodiment of this disclosure can accurately and sufficiently record the specific instruction latency of each instruction, thus providing more detailed information granularity. Furthermore, since the processor according to at least one embodiment of this disclosure records a smaller number of bits of specific instruction latency, rather than a larger number of bits of the aforementioned start-processing timestamp, storage space and transmission bandwidth can be saved. Moreover, by employing variable-length encoding, the storage space and transmission bandwidth occupied by fine-grained instruction latency information can be further reduced.

[0065] Figure 4 A schematic structural diagram of a command trajectory tracking device according to at least one embodiment of the present disclosure is shown. Figure 4As shown, the instruction trajectory tracking device 4000 can receive instruction information from the instruction processing unit 4001, and can send instruction delays to the external storage device 4002. The instruction trajectory tracking device 4000 may include an encoding module 4100, a configuration register 4200, a storage module 4300, and a control module 4400. Descriptions of the instruction processing unit 4001 and the encoding module 4100 that are similar to those of the instruction processing unit 3001 and the encoding module 3100 will not be repeated to avoid redundancy.

[0066] According to at least one embodiment of this disclosure, the encoding module 3100 can select a first encoding format from at least one variable-length encoding format based on the delay value of the instruction delay of the second instruction. That is, instruction delays with different delay values ​​can correspond to different encoding formats.

[0067] According to at least one embodiment of this disclosure, the encoding module 4100 can be configured to obtain at least one instruction delay range corresponding to at least one variable-length encoding format. For example, reference can be made to the following... Figure 5 The encoding format that describes instruction delay.

[0068] Figure 5 A schematic diagram of an instruction delay encoding format according to at least one embodiment of the present disclosure is shown. Wherein, Figure 5 Four encoding formats are shown, corresponding to delay ranges of [0,1] clock cycles, [2,63] clock cycles, [64,2407] clock cycles, and [2048,2^25 -1] clock cycles, respectively. However, this disclosure is not limited to these and may include more or fewer encoding formats.

[0069] like Figure 5 As shown, the encoding method with sequence number 1 can specifically include an encoding format field for indicating the encoding format and a 1-bit delay field for indicating the delay value. The encoding method with sequence number 2 can specifically include an encoding format field for indicating the encoding format and a 6-bit delay field for indicating the delay value. The encoding method with sequence number 3 can specifically include an encoding format field for indicating the encoding format and an 11-bit delay field for indicating the delay value. The encoding method with sequence number 4 can specifically include an encoding format field for indicating the encoding format, a 25-bit delay field for indicating the delay value, a 1-bit first indicator field for indicating whether the instruction belongs to the last instruction in the program, a 1-bit second indicator field for indicating whether the instruction belongs to a jump instruction, a 1-bit third indicator field for indicating whether the instruction belongs to a predetermined type instruction, and a 32-bit address field for indicating the instruction address. According to at least one embodiment of this disclosure, Figure 5The encoding format fields included in the encoding methods shown may have the same or different bit lengths, and this disclosure does not limit this. For example, the bit length of the encoding format field may vary. Figure 5 The sequence number of the encoding method shown in the figure gradually increases.

[0070] According to at least one embodiment of this disclosure, the encoding module 4100 can obtain at least one of the four instruction delay ranges described above.

[0071] Furthermore, the encoding module 4100 can determine the instruction delay range into which the delay value of the second instruction's instruction delay falls within at least one instruction delay range, and select from at least one variable-length encoding format the encoding format corresponding to the instruction delay range into which it falls as the first encoding format. For example, if the delay value of the second instruction's instruction delay is 0 clock cycles, then the delay value of the second instruction's instruction delay falls within the instruction delay range of [0,1] clock cycles. Therefore, for an instruction delay with a delay value of 0 clock cycles, a first encoding format can be selected. Figure 5 The encoding method with serial number 1 in the table is used. For example, if the instruction delay value of the second instruction is 3000 clock cycles, then the instruction delay value of the second instruction falls within the instruction delay range of [2048, 2^25 - 1] clock cycles. Therefore, for an instruction delay value of 3000 clock cycles, the encoding method that can be selected is... Figure 5 The encoding method for table number 4 in the middle.

[0072] According to at least one embodiment of this disclosure, the instruction processing unit 4001 can process multiple instructions, and the multiple instructions can correspond to multiple instruction delays. Each of the aforementioned at least one instruction delay range can correspond to the probability of multiple instruction delays falling into the corresponding instruction delay range. For example, the probability of multiple instruction delays falling into the corresponding instruction delay range can be obtained or predicted based on reference information such as statistical data and historical execution results. Accordingly, an encoding format with a relatively short encoding length (i.e., fewer bits in the encoded result) can be configured for the instruction delay range with a relatively high probability of falling into the range, and an encoding format with a relatively long encoding length (i.e., more bits in the encoded result) can be configured for the instruction delay range with a relatively low probability of falling into the range. For example, the probability of falling into the range corresponding to the first instruction delay range (e.g., a delay range of [0,1] clock cycles) in at least one instruction delay range can be greater than the probability of falling into the range corresponding to the second instruction delay range (e.g., an instruction delay range of [64,2407] clock cycles). In this case, the encoding length of the encoding format corresponding to the first instruction delay range (e.g., a delay range of [0,1] clock cycles) within at least one instruction delay range can be configured to be less than the encoding length of the encoding format corresponding to the second instruction delay range (e.g., an instruction delay range of [64,2407] clock cycles). For example, the encoding length of the delay field corresponding to the delay range of [0,1] clock cycles can be 1 bit, and the encoding length of the delay field corresponding to the instruction delay range of [64,2407] clock cycles can be 11 bits. In this way, the encoding length of instruction delays falling into instruction delay ranges with a high probability can be reduced, thereby saving storage space and transmission bit width.

[0073] According to at least one embodiment of this disclosure, an encoding format with a relatively short encoding length (i.e., fewer bits in the encoded result) can be configured for the instruction delay range with a relatively small corresponding instruction delay value, and an encoding format with a relatively long encoding length (i.e., more bits in the encoded result) can be configured for the instruction delay range with a relatively large corresponding instruction delay value.

[0074] For example, such as Figure 5As shown, the instruction delay ranges corresponding to different encoding formats may not overlap. The delay value of the instruction delay corresponding to the first instruction delay range (e.g., a delay range of [0,1] clock cycles) in at least one instruction delay range may be less than the delay value of the instruction delay corresponding to the second instruction delay range (e.g., an instruction delay range of [64,2407] clock cycles) in at least one instruction delay range. In this case, the encoding length of the encoding format corresponding to the first instruction delay range (e.g., a delay range of [0,1] clock cycles) in at least one instruction delay range can be configured to be less than the encoding length of the encoding format corresponding to the second instruction delay range (e.g., an instruction delay range of [64,2407] clock cycles). For example, the encoding length of the delay field corresponding to the delay range of [0,1] clock cycles can be 1 bit, and the encoding length of the delay field corresponding to the instruction delay range of [64,2407] clock cycles can be 11 bits. In this way, even in the absence of reference information such as statistical data and historical execution results, the corresponding encoding length (e.g., the encoding length of the delay field) can be determined for different instruction delay ranges.

[0075] According to at least one embodiment of this disclosure, the encoding module 4100 may select the first encoding format based on the instruction delay value as described above only when the instruction does not belong to the first type of instruction. That is, the encoding module 4100 can identify whether an instruction belongs to the first type of instruction; if the instruction belongs to the first type of instruction, the encoding module 4100 may select the first encoding format without based on the instruction delay value. The first type of instruction may include one or more of the following: the last instruction in the program, a jump instruction, and a predetermined type of instruction that satisfies the execution conditions of the first type but not the execution conditions of the second type, which are different from the execution conditions of the first type. The execution conditions of the first type may indicate that the execution results of other instructions required by the predetermined type of instruction have been generated. That is, the execution conditions of the first type of instruction may indicate that the dependency relationship or synchronization condition of the predetermined type of instruction on other instructions has been satisfied. The predetermined type of instruction may indicate that the execution conditions of the first type have been satisfied, but the execution conditions of other types have not yet been satisfied, and therefore further processing is still required.

[0076] According to at least one embodiment of this disclosure, in response to the second instruction belonging to a first type of instruction, the encoding module 4100 can select a predetermined encoding method as the first encoding format from at least one variable-length encoding format. For example, in response to the second instruction belonging to a first type of instruction, the encoding module 4100 can select the encoding method with sequence number 4 to encode the instruction delay.

[0077] Specifically, according to at least one embodiment of this disclosure, in response to the second instruction being the last instruction in a program, the encoding module 4100 may set the first indicator field to a first predetermined value (e.g., one of 0 and 1, which is not limited in this disclosure); in response to the second instruction not being the last instruction in a program, the encoding module 4100 may set the first indicator field to, for example, another of 0 and 1, which is not limited in this disclosure. In response to the second instruction being the last instruction in a program, the encoding module 4100 may delay the instruction encoding into a delay field (e.g., a 25-bit delay field with sequence number 4) according to a predetermined encoding format (e.g., an encoding format with sequence number 4). The instruction delay can be statistically analyzed for each program. Since instructions following the last instruction in a program belong to other programs, the encoding module 4100 can determine that the instruction delay of instructions following the second instruction is unrelated to that program. In this way, the instruction delays of instructions for each program can be obtained, thereby providing the user with more detailed and sufficient instruction delay information.

[0078] According to at least one embodiment of this disclosure, in response to the second instruction being a jump instruction, the encoding module 4100 can set the second indicator field to a second predetermined value (e.g., one of 0 and 1, which is not limited in this disclosure); in response to the second instruction not being a jump instruction, the encoding module 4100 can set the second indicator field to a third predetermined value (e.g., the other of 0 and 1, which is not limited in this disclosure). In response to the second instruction being the last instruction in the program, the encoding module 4100 can delay encoding the instruction into a delay field (e.g., a 25-bit delay field with sequence number 4) according to a predetermined encoding format (e.g., an encoding format with sequence number 4). A jump instruction can refer to an instruction executed after a jump from other instructions. By setting the second indicator field, the jump situation of the instruction during execution can be understood, thereby obtaining a clear execution trajectory. Compared with the scheme of calculating the percentage of time occupied by each instruction to the total execution time of the program during the entire execution process, the scheme of this disclosure can collect instruction delay information more accurately. For example, if an instruction is executed multiple times via jumps, the percentage of time occupied by that instruction relative to the total program execution time may be significant. According to the solution disclosed herein, users can understand that the large overall instruction latency is due to the instruction being executed multiple times via jumps. Furthermore, users can also understand the number of times the instruction is executed and during which execution the latency is significant, thus enabling them to make more informed debugging decisions.

[0079] Furthermore, since users typically only have static assembly programs, in the absence of jump instructions, the delayed encoding result of one instruction corresponds to the instruction address of a sequentially executed instruction. However, when a jump occurs during program execution (i.e., a jump instruction exists), the user does not know the address of the instruction after the jump. In response to the second instruction being a jump instruction, the encoding module 4100 can store the instruction address of the second instruction in, for example, a 32-bit address field. In response to the second instruction not being a jump instruction, the encoding module 4100 may not store the instruction address of the second instruction. That is, if it is a non-jump instruction, the user can obtain the instruction address of the non-jump instruction based on the storage order of the encoding results; if it is a jump instruction, the user can obtain the instruction address of the jump instruction based on the instruction address stored by the encoding module 4100. Instruction addresses are generally relatively long, thus occupying a large amount of storage space and transmission bit width. In this way, the encoding module 4100 can selectively store instruction addresses instead of storing the instruction addresses of all instructions, thereby further saving storage space and transmission bit width.

[0080] According to at least one embodiment of the present disclosure, in response to the second instruction being a predetermined type instruction, the encoding module 4100 may set the third indicator field to a fourth predetermined value (e.g., one of 0 and 1, which is not limited in the present disclosure); in response to the second instruction not being a predetermined type instruction, the encoding module 4100 may set the third indicator field to, for example, another of 0 and 1, which is not limited in the present disclosure.

[0081] According to at least one embodiment of this disclosure, the encoding format for sequence number 4 may include two delay fields. In response to the second instruction belonging to a predetermined type of instruction, the encoding module 4100 may delay encoding the instruction according to a predetermined encoding format (e.g., the encoding format for sequence number 4). Figure 5 The 25-bit delay field with sequence number 4 is shown. Figure 5 The 25-bit delay field with serial number 4 shown can be used as the first delay field for storing instruction delays.

[0082] According to at least one embodiment of this disclosure, the encoding format with sequence number 4 may further include a second delay field ( Figure 5 (Not shown in the image). For example, in response to the second instruction belonging to a predetermined type of instruction, the encoding module 4100 can also be configured to obtain a second time interval between the start processing time of the first instruction and the time when the second instruction satisfies the execution conditions of the first type. The execution conditions of the second type can indicate that the hardware resources required to execute the second instruction are ready. The encoding module 4100 can also be configured to encode the second time interval into a second delay field in the delay field. In this way, the completion time of the synchronous behavior required by the instruction (e.g., memory access, etc.) can be obtained, thereby further improving the accuracy of the user's analysis of processor performance.

[0083] like Figure 4 As shown, the instruction trajectory tracking device 4000 may further include a configuration register 4200. The configuration register 4200 can store configuration information that indicates at least one of the programs, threads, and thread bundles monitored by the encoding modules. As previously mentioned, there may be one or more encoding modules. The configuration information can configure the threads and / or thread bundles that each encoding module(s) needs to monitor, for example, to control the corresponding multiplexers to select the corresponding threads and / or thread bundles. The configuration information can be stored in the configuration register 4200 as default configuration information, and the configuration information can also be configured by the user through external input, for example, by inputting it into the configuration register 4200 via a corresponding interface through software.

[0084] like Figure 4 As shown, the instruction trajectory tracking device 4000 may further include a storage module 4300 and a control module 4400. The storage module 4300 is configured to store at least instruction delays, such as information like instruction delays encoded by the encoding module 4100. Furthermore, as described above, there may be one or more encoding modules 4100. Therefore, the control module 4400 can be configured to determine when (one or more) encoding modules write (e.g., encoded) instruction delay information to the storage module 4300, thereby avoiding write conflicts. Furthermore, the control module 4400 can control the start and end of the encapsulation of instruction delays by the storage module 4300, the transmission to the external storage device 4002, and the specific storage address to which the information is sent to the external storage device 4002.

[0085] According to at least one embodiment of this disclosure, the control module 4400 can determine whether to encapsulate instruction delays into transmission data packets for transmission to an external storage device. For example, the bit width of a single instruction delay or similar information may be small. If single instruction delays or similar information are frequently transmitted to the external storage device 4002, the transmission bus may be frequently occupied. The memory footprint of the transmission data packet may be larger than the memory footprint of a single instruction delay. By encapsulating multiple instruction delays with small memory footprints into transmission data packets with large memory footprints, the occupation of the transmission bus can be reduced.

[0086] Figure 6 A schematic diagram of an instruction delay encoding process according to at least one embodiment of the present disclosure is shown.

[0087] According to at least one embodiment of this disclosure, Figure 6 Instructions 0-6 shown may not belong to the first type of instructions. Therefore, the instruction delays of instructions 0-6 can be encoded according to the delay value.

[0088] like Figure 6 As shown, instructions 0, 2, and 6 can be executed directly without waiting; therefore, the instruction latency for instructions 0, 2, and 6 is 0 clock cycles. Options can be selected for instructions 0, 2, and 6. Figure 5 Encode using the encoding method with sequence number 1. The encoding results of instructions 0, 2, and 6 can be "1'0", where "1" can be an encoding format field and "0" can be a 1-bit delay field.

[0089] The instruction delay for instruction 1 can be one clock cycle. Instruction 1 can be selected... Figure 5 Encoding is performed using the encoding method with sequence number 1. The encoding result of instruction 1 can be "1'1", where the first "1" can be an encoding format field, and the second "1" can be a 1-bit delay field. The instruction delay of instruction 3 can be 2 clock cycles. Instruction 3 can be selected... Figure 5 Encode using the encoding method with sequence number 2.

[0090] The encoding result of instruction 3 can be "01'000010", where the "01" before the single quote (') can be the encoding format field, and the "000010" after the single quote (') can be a 6-bit delay field. The instruction delay for instruction 4 can be 5 clock cycles. Options can be selected for instruction 4. Figure 5 Encode using the encoding method with sequence number 2. The encoding result of instruction 4 can be "01'000101", where "01" before the "'" can be the encoding format field, and "000101" after the "'" can be the 6-bit delay field.

[0091] The instruction delay for instruction 5 can be 15 clock cycles. This can be selected for instruction 5. Figure 5 Encode using the encoding method with sequence number 2. The encoding result of instruction 5 can be "01'001111", where "01" before the "'" can be the encoding format field, and "001111" after the "'" can be the 6-bit delay field.

[0092] Users can Figure 6 The encoded results shown in the figure reconstruct the instruction execution trajectory and determine the instruction latency, thereby accurately evaluating processor performance.

[0093] Figure 7 An instruction processing method according to at least one embodiment of the present disclosure is illustrated. For example... Figure 7 As shown, method 700 includes steps S710-S730.

[0094] In step S710, multiple instructions can be sequentially acquired for processing. Step S710 can be executed by the instruction processing unit as described above.

[0095] In step S720, a first time interval between the start processing time of the first instruction and the start processing time of the second instruction among a plurality of instructions can be obtained, wherein the second instruction immediately follows the first instruction. Step S720 can be executed by the encoding module described above.

[0096] In step S730, the first time interval can be determined as the instruction delay of the second instruction. Step S730 can be executed by the encoding module as described above.

[0097] In step S740, the instruction delay can be encoded in a first encoding format among at least one variable-length encoding format. Step S740 can be performed by the encoding module described above.

[0098] The instruction processing method according to at least one embodiment of the present disclosure further includes selecting a first encoding format from at least one variable-length encoding format by an encoding module based on a delay value of the instruction delay of the second instruction.

[0099] The instruction processing method according to at least one embodiment of the present disclosure further includes obtaining at least one instruction delay range corresponding to at least one variable-length encoding format through an encoding module; determining the instruction delay range into which the delay value of the instruction delay of the second instruction falls within the at least one instruction delay range; and selecting an encoding format corresponding to the instruction delay range into which the instruction delay falls as a first encoding format from the at least one variable-length encoding format.

[0100] According to at least one embodiment of the instruction processing method of this disclosure, a plurality of instructions correspond to a plurality of instruction delays; at least one instruction delay range each corresponds to a probability of falling into the corresponding instruction delay range; and the encoding length of the encoding format corresponding to the first instruction delay range in at least one instruction delay range is less than the encoding length of the encoding format corresponding to the second instruction delay range in at least one instruction delay range, and wherein the probability of falling into the first instruction delay range in at least one instruction delay range is greater than the probability of falling into the second instruction delay range in at least one instruction delay range.

[0101] According to at least one embodiment of the instruction processing method of the present disclosure, the encoding length of the encoding format corresponding to the first instruction delay range in at least one instruction delay range is less than the encoding length of the encoding format corresponding to the second instruction delay range in at least one instruction delay range, and the delay value of the instruction delay corresponding to the first instruction delay range is less than the delay value of the instruction delay corresponding to the second instruction delay range.

[0102] The instruction processing method according to at least one embodiment of the present disclosure further includes determining whether a second instruction belongs to a first type of instruction by an encoding module, wherein the first type of instruction includes one or more of the following: the last instruction in the program, a jump instruction, a predetermined type instruction that satisfies the execution conditions of a first type but does not satisfy the execution conditions of a second type that are different from the execution conditions of the first type, wherein the execution conditions of the first type indicate that the execution results of other instructions required by the predetermined type instruction have been generated; wherein selecting a first encoding format from at least one variable-length encoding format includes: in response to the second instruction not belonging to the first type of instruction, selecting a first encoding format from at least one variable-length encoding format based on the delay value of the instruction delay of the second instruction, and wherein the method further includes selecting a predetermined encoding method as the first encoding format from at least one variable-length encoding format by the encoding module in response to the second instruction belonging to the first type of instruction.

[0103] According to at least one embodiment of the instruction processing method of this disclosure, wherein the encoding format corresponding to the first type of instruction has a first indication field and a delay field, and the encoding module is further configured to: in response to the second instruction being the last instruction in the program: set the first indication field to a first predetermined value, encode the instruction delay of the second instruction into the delay field, and determine the instruction delay of instructions following the second instruction as irrelevant to the program.

[0104] According to at least one embodiment of the instruction processing method of this disclosure, wherein the encoding format corresponding to the first type of instruction has a second indicator field, a delay field, and an address field, and the encoding module is further configured to: in response to the second instruction being a jump instruction: set the second indicator field to a second predetermined value, delay the encoding of the second instruction into the delay field, and store the address of the second instruction into the address field.

[0105] The instruction processing method according to at least one embodiment of the present disclosure further includes, in response to the second instruction not being a jump instruction, setting a second indication field to a third predetermined value, encoding the instruction of the second instruction into a delay field, and not storing the address of the second instruction.

[0106] According to at least one embodiment of the instruction processing method of the present disclosure, the encoding format corresponding to the first type of instruction has a third indicator field and a delay field, and the encoding module is further configured to: in response to the second instruction belonging to a predetermined type of instruction: set the third indicator field to a fourth predetermined value, and delay the instruction of the second instruction into the first delay field of the delay field.

[0107] The instruction processing method according to at least one embodiment of the present disclosure further includes, in response to the second instruction belonging to a predetermined type of instruction, obtaining a second time interval between the start processing time of the first instruction and the time when the second instruction satisfies the execution conditions of the first type by an encoding module; and encoding the second time interval into a second delay field in a delay field.

[0108] According to at least one embodiment of the instruction processing method of this disclosure, a second type of execution condition indicates that the hardware resources required to execute a second instruction are ready.

[0109] The instruction processing method according to at least one embodiment of the present disclosure further includes sending the start processing time of the first instruction and the start processing time of the second instruction to the encoding module through the instruction processing unit.

[0110] According to at least one embodiment of the instruction processing method of the present disclosure, the instruction trajectory tracking device further includes a configuration register, and the method further includes storing configuration information through the configuration register, wherein the configuration information indicates at least one of a program, a thread, and a thread bundle monitored by the encoding module, and the encoding module is at least one encoding module corresponding to a thread or at least one encoding module corresponding to a thread bundle.

[0111] According to at least one embodiment of the instruction processing method of this disclosure, the instruction trajectory tracking device further includes a storage module and a control module, wherein the encoding module is one or more, and wherein the method further includes storing at least an instruction delay through the storage module; the method further includes determining, through the control module, the timing of the encoding module writing the instruction delay to the storage module.

[0112] The instruction processing method according to at least one embodiment of the present disclosure further includes determining, by a control module, whether to encapsulate the instruction delay into a transmission data packet for transmission to an external storage device, wherein the memory footprint of the transmission data packet is greater than the memory footprint of the instruction delay.

[0113] According to at least one embodiment of the instruction processing method of the present disclosure, the instruction processing unit includes a transmitting unit, the transmitting unit is configured with a transmitting queue, and one or more instructions to be processed include one or more instructions waiting to be transmitted in the transmitting queue.

[0114] According to at least one embodiment of the instruction processing method of this disclosure, a plurality of instructions belong to a plurality of threads, and the plurality of threads are processed by a plurality of computing cores respectively.

[0115] Figure 8 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0116] like Figure 8As shown, the electronic device 300 is, for example, suitable for implementing the data processing method provided in the embodiments of this disclosure. It should be noted that... Figure 8 The components of the electronic device 300 shown are merely exemplary and not limiting. The electronic device 300 may have other components as needed for the actual application.

[0117] For example, such as Figure 8 As shown, in some examples, electronic device 300 includes processing means (e.g., an artificial intelligence processor including parallel processors such as graphics processors, general-purpose graphics processors, etc.) 301, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 302 or a program loaded from storage device 308 into random access memory (RAM) 303 to achieve various functions, such as performing the data processing method provided in at least one embodiment of this disclosure.

[0118] For example, when the computer-readable instructions are executed by the processing device 301, one or more steps of the data processing method according to any of the above embodiments can be performed. It should be noted that a detailed description of the processing procedure of the data processing method can be found in the relevant descriptions in the embodiments of the above data processing method, and repeated descriptions will not be repeated here.

[0119] RAM 303 also stores various programs and data required for the operation of the computer system. Processing device 301, ROM 302, and RAM 303 are connected via bus 304. Input / output (I / O) interface 305 is also connected to bus 304.

[0120] For example, the memory may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) 303 and / or cache memory, etc., whereby computer-readable instructions can be loaded from storage device 308 into RAM 303 to execute. Non-volatile memory may include, for example, read-only memory (ROM) 302, hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB storage, flash memory, etc. Various applications and various data, such as style images, and various data used and / or generated by the applications, may also be stored in the computer-readable storage medium.

[0121] Typically, the following devices can be connected to I / O interface 305: input devices 306 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 307 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 308 including, for example, magnetic tapes, hard disks, flash memory, etc.; and communication devices 309. Communication device 309 allows electronic device 300 to communicate wirelessly or wiredly with other electronic devices to exchange data. Drive 310 is also connected to I / O interface 305 as needed. Removable media 311, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 310 as needed so that computer programs read from them can be installed into storage device 308 as needed. Although Figure 8 An electronic device 300 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively. For example, a processor 301 may control other components in the electronic device 300 to perform desired functions. The processing device 301 may be a central processing unit (CPU), a general-purpose graphics processing unit (GPGPU), a parallel processor, an artificial intelligence processor, a tensor processor (TPU), or a graphics processing unit (GPU)—a device with data processing and / or program execution capabilities. The CPU may be based on an x86 or ARM architecture, etc. The GPU may be integrated directly onto the motherboard or built into the motherboard's northbridge chip. The GPU may also be built into the CPU.

[0122] For example, the electronic device 300 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 309 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0123] For example, electronic device 300 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, or navigator, or any combination of electronic devices and hardware. The embodiments disclosed herein do not limit this.

[0124] For example, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For instance, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication device 309, or installed from storage device 308, or installed from ROM 302. When the computer program is executed by processing device 301, the data processing methods defined in the embodiments of this disclosure are performed.

[0125] It should be noted that the computer-readable medium described above in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In embodiments of this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In embodiments of this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0126] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0127] The artificial intelligence processor, electronic device, and instruction processing method provided according to at least one embodiment of this disclosure can obtain the execution trajectory of instructions in a program, thereby accurately and sufficiently determining instruction latency. The artificial intelligence processor, electronic device, and instruction processing method provided according to at least one embodiment of this disclosure can accurately and sufficiently determine instruction latency while consuming relatively low memory and transmission costs.

[0128] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0129] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0130] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0131] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0132] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0133] The following points should be noted regarding this disclosure:

[0134] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0135] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0136] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. An artificial intelligence processor, comprising: An instruction processing unit, wherein the instruction processing unit is configured to sequentially acquire multiple instructions for processing; A command trajectory tracking device includes an encoding module, wherein the encoding module is configured to: Obtain a first time interval between the start processing time of the first instruction and the start processing time of the second instruction among the plurality of instructions, wherein the second instruction immediately follows the first instruction. The first time interval is determined as the instruction delay of the second instruction. The instruction delay is encoded in a first encoding format of at least one variable-length encoding format.

2. The processor according to claim 1, wherein, The encoding module is also configured to: Based on the delay value of the instruction delay of the second instruction, the first encoding format is selected from the at least one variable-length encoding format.

3. The processor according to claim 1, wherein, The encoding module is also configured to: Obtain at least one instruction delay range corresponding to the at least one variable-length encoding format; Determine the instruction delay range into which the delay value of the second instruction falls within the at least one instruction delay range; and Select the encoding format that corresponds to the instruction delay range falling within from the at least one variable-length encoding format as the first encoding format.

4. The processor according to claim 3, wherein, The multiple instructions correspond to multiple instruction delays; Each of the at least one instruction delay range corresponds to the probability of the plurality of instruction delays falling into the corresponding instruction delay range; and The encoding length of the encoding format corresponding to the first instruction delay range in the at least one instruction delay range is less than the encoding length of the encoding format corresponding to the second instruction delay range in the at least one instruction delay range, and wherein the probability of falling into the first instruction delay range in the at least one instruction delay range is greater than the probability of falling into the second instruction delay range in the at least one instruction delay range.

5. The processor according to claim 3, wherein, The encoding length of the encoding format corresponding to the first instruction delay range in the at least one instruction delay range is less than the encoding length of the encoding format corresponding to the second instruction delay range in the at least one instruction delay range, and wherein the delay value of the instruction delay corresponding to the first instruction delay range is less than the delay value of the instruction delay corresponding to the second instruction delay range.

6. The processor according to claim 1, wherein, The encoding module is also configured to: Determine whether the second instruction belongs to the first type of instruction, wherein the first type of instruction includes one or more of the following: The last instruction in the program, Jump instruction, A predetermined type instruction that satisfies the execution conditions of the first type but does not satisfy the execution conditions of the second type, which are different from the execution conditions of the first type, wherein the execution conditions of the first type indicate that the execution results of other instructions required by the predetermined type instruction have been generated; The selection of the first encoding format from the at least one variable-length encoding format includes: in response to the second instruction not belonging to the first type of instruction, selecting the first encoding format from the at least one variable-length encoding format based on the delay value of the instruction delay of the second instruction, and The encoding module is further configured as follows: In response to the second instruction belonging to the first type of instruction, a predetermined encoding method is selected from the at least one variable-length encoding format as the first encoding format.

7. The processor according to claim 6, wherein, The encoding format corresponding to the first type of instruction has a first indicator field and a delay field, and the encoding module is further configured to: In response to the second instruction being the last instruction in the program: Set the first indication field to a first predetermined value. The instruction of the second instruction is delayed and encoded into the delay field, and The instruction delay of the instruction following the second instruction is determined to be irrelevant to the program.

8. The processor according to claim 6, wherein, The encoding format corresponding to the first type of instruction has a second indicator field, a delay field, and an address field, and the encoding module is further configured to: In response to the second instruction belonging to the jump instruction: Set the second indicator field to the second predetermined value. The instruction of the second instruction is delayed and encoded into the delay field, and The address of the second instruction is stored in the address field.

9. The processor according to claim 8, wherein, The encoding module is also configured to: In response to the second instruction not being a jump instruction: Set the second indicator field to a third predetermined value. The instruction of the second instruction is delayed and encoded into the delay field, and The address of the second instruction is not stored.

10. The processor according to claim 6, wherein, The encoding format corresponding to the first type of instruction has a third indicator field and a delay field, and the encoding module is further configured to: In response to the second instruction belonging to the predetermined type of instruction: Set the third indicator field to a fourth predetermined value, and The instruction of the second instruction is delayed and encoded into the first delay field of the delay field.

11. The processor according to claim 10, wherein, The encoding module is also configured to: In response to the second instruction belonging to the predetermined type of instruction, a second time interval is obtained between the start processing time of the first instruction and the time when the second instruction satisfies the execution condition of the first type; as well as The second time interval is encoded into the second delay field in the delay field.

12. The processor according to claim 6, wherein, The second type of execution condition indicates that the hardware resources required to execute the second instruction are ready.

13. The processor according to any one of claims 1-12, wherein, The instruction processing unit is further configured to: The start time of the first instruction and the start time of the second instruction are sent to the encoding module.

14. The processor according to any one of claims 1-12, wherein, The instruction trajectory tracking device also includes a configuration register. The configuration register is configured to store configuration information indicating at least one of the program, thread, and thread bundle monitored by the encoding module, wherein the encoding module is at least one encoding module corresponding to each thread or at least one encoding module corresponding to each thread bundle.

15. The processor according to any one of claims 1-12, wherein, The instruction trajectory tracking device further includes a storage module and a control module, wherein the encoding module is one or more, and wherein, The storage module is configured to store at least the instruction delay; The control module is configured to determine the timing of the delay in the encoding module writing the instruction to the storage module.

16. The processor of claim 15, wherein, The control module is also configured to: Determine whether to encapsulate the instruction delay into a transmission data packet for transmission to an external storage device, wherein the memory footprint of the transmission data packet is greater than the memory footprint of the instruction delay.

17. The processor according to any one of claims 1-12, wherein, The instruction processing unit includes a transmission unit, which is configured with a transmission queue, and the one or more instructions to be processed include one or more instructions waiting to be transmitted in the transmission queue.

18. An electronic device comprising a processor according to any one of claims 1-17.

19. An instruction processing method, comprising: Sequentially fetch multiple instructions for processing; Obtain a first time interval between the start processing time of the first instruction and the start processing time of the second instruction among the plurality of instructions, wherein the second instruction immediately follows the first instruction; The first time interval is determined as the instruction delay of the second instruction; and The instruction delay is encoded in a first encoding format of at least one variable-length encoding format.

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