A high heat dissipation chip packaging structure

Abstract

To overcome the problem of insufficient heat dissipation efficiency in existing chip packaging structures, this invention provides a high-heat-dissipation chip packaging structure, including a PCB board, a chip substrate, a packaging layer, and a chip wafer. The chip substrate includes a first circuit board, a prepreg, and a second circuit board stacked sequentially. The first circuit board includes a first substrate and first circuit patterns located on both sides of the first substrate. The chip wafer is located on the surface of the first circuit board opposite to the prepreg. The second circuit board includes a second substrate and second circuit patterns located on both sides of the second substrate. The prepreg includes a fiber layer and a resin layer completely impregnated with the fiber layer. The fiber layer includes a thermally conductive area corresponding to the chip wafer and an electrical connection area located on the outer periphery of the thermally conductive area. The PCB board has a copper block at the position corresponding to the thermally conductive area, and a thermally conductive coating layer is disposed between the copper block and the thermally conductive area of ​​the prepreg.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor chip packaging structure technology, and specifically relates to a high heat dissipation chip packaging structure. Background Technology

[0002] In the field of chip manufacturing, chip wafer packaging is a key step in achieving electrical connection, physical protection, and interface with external circuits. The packaging process commonly used in the industry is as follows: First, the chip wafer is fixed and coated onto the surface of a chip substrate (usually a ceramic substrate or organic polymer substrate with high-density integrated circuits) using encapsulation resins such as epoxy resin, completing the physical isolation and initial protection of the chip wafer; then, with the help of the solder ball array (BGA packaging structure) pre-set at the bottom of the chip substrate, the chip substrate is soldered and assembled with a printed circuit board (PCB) to achieve signal transmission and power supply connection between the chip wafer and external circuits.

[0003] However, the conventional packaging structure described above has significant drawbacks in terms of heat dissipation performance: On the one hand, the top of the chip wafer is completely covered by encapsulating resin, and the thermal conductivity of encapsulating resin is usually low (generally in the range of 0.1-0.5 W / (m・K)), making it difficult for the heat generated by the chip wafer during operation to be effectively dissipated outward through the top encapsulating resin; on the other hand, the bottom of the chip wafer is in direct contact with the chip substrate, and the heat must first be conducted to the chip substrate, and then transferred to the PCB board through the solder balls. The relatively high thermal resistance of the chip substrate (especially organic substrate) and the PCB board hinders the downward transfer of heat, ultimately causing the chip wafer to be in a state of heat accumulation for a long time, which can seriously affect the working stability and lifespan of the chip.

[0004] To address the aforementioned heat dissipation issues, existing technologies have proposed several improvement solutions. For example, attaching heat pipes, vapor chambers, or heat sinks to the surface of the encapsulation resin layer on top of the chip can enhance heat exchange efficiency on the outer surface of the package and accelerate heat dissipation. Alternatively, embedding high thermal conductivity metal structures such as copper blocks or pillars within the PCB board can improve the PCB board's own thermal conductivity and help channel heat from the solder balls to the PCB board. However, these solutions are essentially external heat dissipation optimizations, only addressing heat outside the package or at the PCB board level. They fail to directly target the source of heat generation and cannot break through core heat dissipation barriers, thus failing to fundamentally solve the chip wafer's own heat dissipation problem. Summary of the Invention

[0005] To address the problem of insufficient heat dissipation efficiency in existing chip packaging structures, this invention provides a high-heat-dissipation chip packaging structure.

[0006] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows:

[0007] This invention provides a high-heat-dissipation chip packaging structure, including a PCB board, a chip substrate, a packaging layer, and a chip wafer. The chip substrate includes a first circuit board, a prepreg, and a second circuit board stacked sequentially. The first circuit board includes a first substrate and first circuit patterns located on both sides of the first substrate. The chip wafer is located on the surface of the first circuit board opposite to the prepreg and is electrically connected to the first circuit patterns. The second circuit board includes a second substrate and second circuit patterns located on both sides of the second substrate. The second circuit patterns are electrically connected to the PCB board. The prepreg encapsulates the chip wafer. The PCB board includes a fiber layer and a resin layer that completely impregnates the fiber layer. The fiber layer includes a thermally conductive region corresponding to the chip wafer and an electrical connection region located on the outer periphery of the thermally conductive region. The fiber layer includes interwoven insulating fibers. A graphene layer is disposed on the outer wall of the insulating fibers in the thermally conductive region. The graphene layer is not disposed on the outer wall of the insulating fibers in the electrical connection region. A copper block is disposed on the PCB board at the position corresponding to the thermally conductive region. A thermally conductive coating layer is disposed between the copper block and the thermally conductive region of the prepreg. The encapsulation layer is located on the PCB board. The chip wafer and the chip substrate are encapsulated in the encapsulation layer.

[0008] Optionally, the chip substrate has a plurality of through electrical connection holes in the electrical connection area, and the electrical connection holes electrically connect two or more of the two first circuit patterns and two second circuit patterns.

[0009] Optionally, the chip wafer is provided with a first pad, the first circuit pattern forms a second pad at a position away from the prepreg, the first pad and the second pad are electrically connected to each other by a lead, the second circuit pattern forms a third pad at a position away from the prepreg, the PCB board is provided with a fourth pad on the outer periphery of the copper block, and the third pad and the fourth pad are connected by solder balls.

[0010] Optionally, the electrical connection area is arranged around the heat-conducting area, and the projection of the heat-conducting area on the PCB board coincides with the projection of the chip wafer on the PCB board, with the copper block located inside the projection of the heat-conducting area on the PCB board.

[0011] Optionally, the second circuit board has a heat-conducting window at the position corresponding to the copper block, through which the heat-conducting area of ​​the prepreg is exposed. The heat-conducting coating layer is bonded to the heat-conducting area and the copper block respectively. The heat-conducting coating layer is obtained by curing graphene heat-conducting paste.

[0012] Optionally, the PCB board has a through-hole at the position corresponding to the heat conduction area, and the copper block is embedded in the through-hole.

[0013] Optionally, the insulating fiber is glass fiber, and the resin layer is one or more of epoxy resin, polyimide resin, and polyphenylene ether resin.

[0014] Optionally, the prepreg is prepared by the following method:

[0015] A fiber layer formed of insulating fibers is taken, and nickel is deposited on the insulating fibers in the heat-conducting region of the fiber layer under the cover of a mask, so as to form a nickel layer on the insulating fibers in the heat-conducting region.

[0016] The nickel-deposited fiber layer was placed in a quartz tube, and methane and hydrogen were introduced. Graphene was grown at 900℃~1100℃ by nickel catalysis, resulting in a fiber layer with graphene.

[0017] The fiber layer containing graphene is impregnated in a resin layer and pre-cured to obtain a semi-cured sheet.

[0018] Optionally, the thickness of the first substrate is 30~400μm, the thickness of the prepreg is 40~350μm, and the thickness of the second substrate is 30~400μm.

[0019] Optionally, the encapsulation layer includes a first encapsulation layer and a second encapsulation layer, wherein the first encapsulation layer is located on the chip substrate, the chip wafer is located in the first encapsulation layer, and the second encapsulation layer is located on the PCB board, and both the first encapsulation layer and the chip substrate are located in the second encapsulation layer;

[0020] The first encapsulation layer is obtained by curing a first encapsulation resin, which comprises the following components by weight:

[0021] 25-38 parts epoxy resin, 13-26 parts epoxy-modified silicone resin, 21-38 parts fumed silica, 5-13 parts m-phenylenediamine, 0.1-1 parts silane coupling agent, and 30-60 parts first solvent;

[0022] The second encapsulation layer is obtained by curing a second encapsulation resin, which comprises the following components by weight:

[0023] The composition includes 32-59 parts epoxy resin, 21-38 parts flake silica, 4-12 parts dicyclopentadiene-type phenolic resin, 3-7 parts hexamethylene diisocyanate trimer, 0.1-1 parts silane coupling agent, and 30-60 parts second solvent.

[0024] According to the high heat dissipation chip packaging structure provided by the present invention, a graphene layer is disposed on the thermally conductive area of ​​the prepreg corresponding to the chip wafer (the electrical connection area is not disposed to avoid electrical interference), and a copper block is embedded in the corresponding thermally conductive area of ​​the PCB board. A thermally conductive coating layer is added between the copper block and the thermally conductive area of ​​the prepreg. The high thermal conductivity of graphene significantly improves the heat conduction efficiency of the thermally conductive area, and a direct heat dissipation path of chip wafer → chip substrate → PCB copper block is constructed, which directly conducts heat from the chip source to the PCB board, avoiding heat accumulation in the chip substrate and breaking the thermal resistance barrier of traditional chip substrates. At the same time, the chip substrate is directly modified with graphene on the fiber layer of the prepreg, and is no different from traditional chip substrates in terms of thickness and shape. It does not affect the support function and electrical connection carrier function of the chip substrate itself, and is compatible with existing packaging processes. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the high heat dissipation chip packaging structure provided by the present invention.

[0026] The reference numerals in the accompanying drawings are as follows:

[0027] 1. Chip wafer; 11. First pad; 12. Lead; 2. Chip substrate; 21. First circuit board; 211. First substrate; 212. First circuit pattern; 2121. Second pad; 22. Second circuit board; 221. Second substrate; 222. Second circuit pattern; 2221. Third pad; 23. Prepreg; 231. Fiber layer; 2311. Thermally conductive area; 2312. Electrical connection area; 24. Electrical connection hole; 3. PCB board; 31. Copper block; 32. Fourth pad; 4. Thermally conductive coating layer; 5. Encapsulation layer; 51. First encapsulation layer; 52. Second encapsulation layer. Detailed Implementation

[0028] To make the technical problems solved, the technical solutions, and the beneficial effects of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0029] like Figure 1As shown, an embodiment of the present invention provides a high heat dissipation chip packaging structure, including a PCB board 3, a chip substrate 2, a packaging layer 5, and a chip wafer 1; the chip substrate 2 includes a first circuit board 21, a prepreg 23, and a second circuit board 22 stacked sequentially. The first circuit board 21 includes a first substrate 211 and a first circuit pattern 212 located on both sides of the first substrate 211. The chip wafer 1 is located on the surface of the first circuit board 21 away from the prepreg 23, and the chip wafer 1 is electrically connected to the first circuit pattern 212; the second circuit board 22 includes a second substrate 221 and a second circuit pattern 222 located on both sides of the second substrate 221. The second circuit pattern 222 is electrically connected to the PCB board 3, and the prepreg 23 encapsulates the chip wafer 1. The PCB board 3 includes a fiber layer 231 and a resin layer that completely impregnates the fiber layer 231. The fiber layer 231 includes a thermally conductive area 2311 corresponding to the chip wafer 1 and an electrical connection area 2312 located on the outer periphery of the thermally conductive area 2311. The fiber layer 231 includes interwoven insulating fibers. A graphene layer is disposed on the outer wall of the insulating fibers in the thermally conductive area 2311. The graphene layer is not disposed on the outer wall of the insulating fibers in the electrical connection area 2312. A copper block 31 is disposed on the PCB board 3 at the position corresponding to the thermally conductive area 2311. A thermally conductive coating layer 4 is disposed between the copper block 31 and the thermally conductive area 2311 of the prepreg 23. The encapsulation layer 5 is located on the PCB board 3. The chip wafer 1 and the chip substrate 2 are encapsulated in the encapsulation layer 5.

[0030] The prepreg 23 has a graphene layer in the thermally conductive area 2311 of the corresponding chip wafer 1 (the electrical connection area 2312 is not provided to avoid electrical interference). The PCB board embeds a copper block 31 in the corresponding thermally conductive area 2311. A thermally conductive coating layer 4 is added between the copper block 31 and the thermally conductive area 2311 of the prepreg 23. The high thermal conductivity of graphene significantly improves the heat conduction efficiency of the thermally conductive area 2311, and constructs a direct heat dissipation path from chip wafer 1 to chip substrate 2 to PCB copper block 31. Heat is directly conducted from the chip source to the PCB board, avoiding heat accumulation in the chip substrate 2 and breaking the thermal resistance barrier of the traditional chip substrate 2. At the same time, the chip substrate 2 is directly modified with graphene on the fiber layer 231 of the prepreg 23. It is no different from the traditional chip substrate 2 in terms of thickness and shape, and does not affect the support function and electrical connection carrier function of the chip substrate 2 itself, and is compatible with existing packaging processes.

[0031] In some embodiments, the chip substrate 2 has a plurality of through electrical connection holes 24 in the electrical connection area 2312, and the electrical connection holes 24 electrically connect two or more of the two first circuit patterns 212 and the two second circuit patterns 222.

[0032] By placing the electrical connection hole 24 in the electrical connection area 2312, the electrical connectivity of each circuit layer of the chip substrate 2 can be ensured without damaging the heat dissipation function of the heat conduction area 2311. This satisfies the signal transmission and power supply requirements between the chip wafer 1 and the PCB board, while avoiding the risk of electrical connection failure caused by the addition of heat dissipation structure, thus achieving synergistic compatibility between heat dissipation optimization and electrical performance assurance.

[0033] In some embodiments, a first pad 11 is provided on the chip wafer 1, a second pad 2121 is formed on the first circuit pattern 212 at a position away from the prepreg 23, the first pad 11 and the second pad 2121 are electrically connected to each other by a lead 12, a third pad 2221 is formed on the second circuit pattern 222 at a position away from the prepreg 23, and a fourth pad 32 is provided on the outer periphery of the copper block 31 on the PCB board 3, the third pad 2221 and the fourth pad 32 are connected by solder balls.

[0034] In some embodiments, the electrical connection area 2312 is disposed around the heat-conducting area 2311, and the projection of the heat-conducting area 2311 on the PCB board 3 coincides with the projection of the chip wafer 1 on the PCB board 3, and the copper block 31 is located inside the projection of the heat-conducting area 2311 on the PCB board 3.

[0035] By aligning the projection of the heat-conducting area 2311 with the projection of the chip wafer 1, it can be ensured that the heat generated by the chip wafer 1 can be conducted vertically downward to the heat-conducting area 2311, reducing heat loss in lateral transfer and improving the directionality and efficiency of heat conduction.

[0036] In some embodiments, the second circuit board 22 has a heat-conducting window at the position corresponding to the copper block 31, through which the heat-conducting area 2311 of the prepreg 23 is exposed, and the heat-conducting coating layer 4 is bonded to the heat-conducting area 2311 and the copper block 31 respectively, and the heat-conducting coating layer 4 is obtained by curing graphene heat-conducting paste.

[0037] By opening a heat-conducting window on the second circuit board 22, the contact thermal resistance caused by the second circuit board 22 can be significantly reduced. At the same time, the heat-conducting coating layer 4 prepared by using graphene heat-conducting paste can further reduce the contact thermal resistance between the heat-conducting area 2311 of the prepreg 23 and the copper block 31, realize low-resistance heat conduction from heat-conducting area 2311 to heat-conducting coating layer 4 to copper block 31, avoid heat accumulation at the interface, and further improve the efficiency of the core heat dissipation path.

[0038] In some embodiments, the graphene thermally conductive paste comprises the following components by weight:

[0039] The ingredients are: 20-30 parts epoxy resin, 8-12 parts curing agent, 8-15 parts graphene, 0.5-2 parts polycarboxylate dispersant, 3-10 parts fumed silica, and 20-90 parts solvent.

[0040] In some embodiments, the PCB board 3 has a through mounting hole at the position corresponding to the heat conduction area 2311, and the copper block 31 is embedded in the mounting hole.

[0041] The through-hole allows the copper block 31 to dissipate heat to both the top and bottom sides of the PCB board simultaneously (traditional surface mount type can only dissipate heat to one side), increasing the heat dissipation area and heat exchange path, which is especially suitable for heat dissipation of high-power chips and further alleviates the heat accumulation problem of chip wafer 1.

[0042] In some embodiments, the insulating fiber is glass fiber, and the resin layer is one or more of epoxy resin, polyimide resin, and polyphenylene ether resin.

[0043] Epoxy resin, polyimide resin, etc. have good heat resistance and chemical resistance. When combined with glass fiber, they can ensure that the prepreg 23 maintains structural stability in the high temperature environment of chip operation (usually 60-120℃) and does not affect the heat dissipation function of the heat conduction area 2311 due to high temperature aging, thus taking into account both heat dissipation performance and long-term reliability of the packaging structure.

[0044] In some embodiments, the prepreg 23 is prepared by the following method:

[0045] Take a fiber layer 231 formed of insulating fibers, and under the cover of a mask, deposit nickel on the insulating fibers of the heat-conducting region 2311 in the fiber layer 231 to form a nickel layer on the insulating fibers of the heat-conducting region 2311.

[0046] The nickel-deposited fiber layer 231 was placed in a quartz tube, and methane and hydrogen were introduced. Graphene was grown at 900℃~1100℃ by nickel catalysis, and the fiber layer 231 with graphene was obtained.

[0047] The fiber layer 231 containing graphene is impregnated in the resin layer and pre-cured to obtain a semi-cured sheet 23.

[0048] Masking allows for precise control of graphene growth only in the thermally conductive region 2311, preventing electrical performance abnormalities in the electrical connection region 2312 due to the presence of graphene and ensuring process precision. Nickel-catalyzed graphene exhibits strong adhesion to insulating fibers (the nickel layer acts as a transition layer to enhance bonding strength), and the graphene layer has high uniformity, ensuring consistent heat conduction in the thermally conductive region 2311 and avoiding localized thermal resistance differences caused by uneven graphene distribution.

[0049] In some embodiments, the thickness of the first substrate 211 is 30~400μm, the thickness of the prepreg 23 is 40~350μm, and the thickness of the second substrate 221 is 30~400μm.

[0050] By limiting the thickness of the first substrate 211, the prepreg 23, and the second substrate 221, the chip substrate 2 can be guaranteed to have sufficient support strength while shortening the heat conduction path.

[0051] While the encapsulating resin layer effectively isolates impurities such as moisture, oxygen, and dust from the external environment, preventing chemical corrosion or physical contamination of the chip wafer 1, its coefficient of thermal expansion (CTE) differs significantly from that of the chip wafer 1 (for example, the CTE of the chip wafer 1 is approximately 3-5 ppm / ℃, while that of the epoxy resin encapsulating resin is approximately 15-25 ppm / ℃). During chip operation, the temperature of the chip wafer 1 rises due to heat generation, and then drops back to ambient temperature when not in operation. This periodic temperature difference causes a difference in deformation due to thermal expansion and contraction between the encapsulating resin layer and the chip wafer 1, resulting in continuous thermal stress at their contact surface. Especially for the metal leads 12 (such as gold wires or copper wires) used to achieve electrical connection between the chip wafer 1 and the chip substrate 2, one end is fixed to the pad of the chip wafer 1, and the other end is connected to the electrode of the chip substrate 2. In addition, some areas are covered by encapsulating resin. The difference in the coefficient of thermal expansion between the encapsulating resin and the metal leads 12 will further aggravate the thermal stress borne by the metal leads 12. When the chip wafer 1 has excessively high local temperature due to poor heat dissipation, the thermal stress will increase significantly. Under long-term action, the metal leads 12 are prone to fatigue damage or even breakage, which directly leads to the failure of the electrical connection of the chip and seriously affects the reliability of the packaged product.

[0052] To address the aforementioned issues, the present invention provides further improvements to the encapsulation layer 5.

[0053] Specifically, the encapsulation layer 5 includes a first encapsulation layer 51 and a second encapsulation layer 52. The first encapsulation layer 51 is located on the chip substrate 2, and the chip wafer 1 is located in the first encapsulation layer 51. The second encapsulation layer 52 is located on the PCB board 3. Both the first encapsulation layer 51 and the chip substrate 2 are located in the second encapsulation layer 52.

[0054] The first encapsulation layer 51 is obtained by curing a first encapsulation resin, which comprises the following components by weight:

[0055] 25-38 parts epoxy resin, 13-26 parts epoxy-modified silicone resin, 21-38 parts fumed silica, 5-13 parts m-phenylenediamine, 0.1-1 parts silane coupling agent, and 30-60 parts first solvent;

[0056] The second encapsulation layer 52 is obtained by curing a second encapsulation resin, which comprises the following components by weight:

[0057] The composition includes 32-59 parts epoxy resin, 21-38 parts flake silica, 4-12 parts dicyclopentadiene-type phenolic resin, 3-7 parts hexamethylene diisocyanate trimer, 0.1-1 parts silane coupling agent, and 30-60 parts second solvent.

[0058] The first encapsulation layer 51 is in direct contact with the wafer and is used to encapsulate the wafer and the leads 12 on the wafer. The first encapsulation layer 51 is made of epoxy resin with added epoxy-modified silicone resin. While taking into account the high adhesion of epoxy resin, the epoxy-modified silicone resin can provide the first encapsulation layer 51 with a certain elasticity. At the same time, the use of m-phenylenediamine can reduce the crosslinking density and optimize the elastic modulus of the resin after curing. This makes the first encapsulation layer 51 have flexible buffering ability in the periodic deformation of the chip wafer 1 during heating and cooling, directly reducing the rigid stress impact on the metal leads 12. While the first encapsulation layer 51 effectively buffers the thermal stress between the lead 12 and the first encapsulation layer 51, its moisture barrier performance is poor. Therefore, adding a second encapsulation layer 52 can address this weakened moisture barrier performance. The second encapsulation layer 52 uses dicyclopentadiene phenolic resin as a curing agent and adds hexamethylene diisocyanate trimer as a crosslinking agent, forming a network crosslinking structure that improves the rigidity and density of the second encapsulation layer 52. Simultaneously, lamellar silica is added; the layering of lamellar silica creates tortuous moisture barrier channels on the outside of the first encapsulation layer 51, increasing the difficulty of moisture penetration into the first encapsulation layer 51. Therefore, the combination of the first encapsulation layer 51 and the second encapsulation layer 52 effectively reduces the risk of lead 12 breakage due to temperature differences without compromising the moisture barrier performance of the encapsulation layer 5, thereby improving the long-term reliability and lifespan of the chip package.

[0059] The present invention will be further illustrated by the following examples.

[0060] Example 1

[0061] This embodiment illustrates the chip packaging structure and its fabrication method disclosed in this invention, and includes the following steps:

[0062] I. Preparation of Prepreg

[0063] Nickel deposition by mask: A stainless steel mask (80 μm thick, with a 4 mm × 4 mm opening in the heat-conducting area) is used to cover a glass fiber cloth (12 mm × 12 mm in size), exposing only the heat-conducting area; a nickel layer is deposited by magnetron sputtering for 15 min to form a 50-80 nm thick nickel layer on the glass fiber surface in the heat-conducting area.

[0064] Graphene growth: A fiber cloth with a nickel layer is placed in a quartz tube, and a methane / hydrogen mixed gas (flow rate 50 sccm, volume ratio 1:100) is introduced. The temperature is raised to 1000℃ and held for 2 hours to grow graphene (total thickness 0.7 nm) using nickel catalysis. The graphene is then naturally cooled to room temperature.

[0065] Resin impregnation pre-curing: The graphene-containing fiber cloth is placed in a vacuum impregnation tank (vacuum degree -0.098MPa, temperature 70℃) and impregnated in epoxy resin for 45min. After removal, it is pre-cured in an oven at 130℃ for 1.5h, and the pre-curing degree is controlled at 60% to obtain a semi-cured sheet (thickness 100μm, thermally conductive area 4mm×4mm, electrical connection area surrounding the thermally conductive area).

[0066] II. Chip Substrate Lamination

[0067] Stacking assembly: Stack the circuit boards in the order of "first circuit board (with first circuit pattern) → prepreg → second circuit board (with second circuit pattern)" to ensure that the heat-conducting area of ​​the prepreg is aligned with the center of the first circuit board;

[0068] Hot pressing: Place the composite into a hot press, set the temperature to 180℃ and the pressure to 25MPa, and keep it at the temperature and pressure for 90 minutes to allow the prepreg to fully cure and the layers to bond tightly.

[0069] Electrical connection hole preparation: Drill electrical connection holes with a diameter of 0.15 mm (array distribution, hole spacing 0.4 mm) in the electrical connection area of ​​the prepreg. Use the process of copper plating (thickness 8 μm) + nickel plating (1.5 μm) + gold plating (0.15 μm) to conduct the first circuit pattern and the second circuit pattern. The on-resistance was measured to be 3 mΩ.

[0070] III. PCB Board and Copper Block Assembly

[0071] PCB board opening: Drill through mounting holes at the center of the PCB board;

[0072] Copper block embedding: Place the copper block into the mounting hole, fill the gap (0.025mm) between the copper block and the hole wall with thermally conductive silicone, and cure at 120℃ for 1.5h to ensure that the copper block is tightly bonded to the PCB board without any air bubbles remaining;

[0073] Thermal conductive paste coating: Graphene thermal conductive paste with a thickness of 20μm is coated on the upper surface of the copper block and pre-baked at 80℃ for 1h to form a thermal conductive coating layer.

[0074] IV. Chip Wafer Bonding and Electrical Connection

[0075] Chip wafer mounting: The diced chip wafer (including the first pad) is mounted on the surface of the first circuit board away from the prepreg, ensuring that the center of the chip wafer is aligned with the center of the prepreg thermal conductive area (deviation ≤ 0.1mm).

[0076] Wire bonding: Using a gold wire bonding machine, the temperature is set to 180℃ and the pressure to 50N, the first pad of the chip wafer is connected to the second pad of the first circuit board through copper wire.

[0077] First encapsulation layer coating and curing: The first encapsulation resin is coated on the chip substrate to completely cover the chip wafer. Vacuum is used to remove air bubbles, and step curing is adopted: 80℃ / 1h→120℃ / 1h.

[0078] The first encapsulating resin comprises the following components by weight: 28 parts epoxy resin, 20 parts epoxy-modified silicone resin (terminated epoxy polydimethylsiloxane, epoxy value 0.08 eq / 100g), 30 parts fumed silica (particle size D50: 15nm, hydrophobic), 8 parts m-phenylenediamine, 0.5 parts silane coupling agent, and 40 parts ethanol.

[0079] Solder ball soldering: 0.4mm diameter solder balls are placed on the third pad of the second circuit board, the chip substrate is aligned with the fourth pad of the PCB board, and soldered in a reflow oven to form a reliable solder joint.

[0080] Second encapsulation layer coating and curing: The second encapsulation resin is coated on the PCB board to completely cover the first encapsulation layer and the chip substrate. Step curing: 100℃ / 2h→140℃ / 1.5h;

[0081] The second encapsulating resin comprises the following components by weight: 45 parts epoxy resin, 30 parts flake silica (diameter-to-thickness ratio 40:1, particle size 10μm), 8 parts dicyclopentadiene-type phenolic resin, 5 parts hexamethylene diisocyanate trimer, 0.5 parts silane coupling agent, and 40 parts ethanol.

[0082] The chip packaging structure is obtained.

[0083] Example 2

[0084] This embodiment illustrates the chip packaging structure and its fabrication method disclosed in this invention, including most of the operational steps in Embodiment 1, with the following differences:

[0085] In step four, during chip wafer bonding and electrical connection, the second encapsulation resin is replaced with the same material as the first encapsulation resin.

[0086] Example 3

[0087] This embodiment illustrates the chip packaging structure and its fabrication method disclosed in this invention, including most of the operational steps in Embodiment 1, with the following differences:

[0088] In step four, during chip wafer bonding and electrical connection, the first encapsulation resin is replaced with the same material as the second encapsulation resin.

[0089] Comparative Example 1

[0090] This comparative example is used to illustrate the chip packaging structure and its fabrication method disclosed in this invention, including most of the operation steps in Example 1, the difference being:

[0091] In step one, the preparation of the prepreg does not involve the preparation of the nickel layer and graphene layer. Instead, the prepreg is prepared by directly impregnating the fiber cloth with epoxy resin.

[0092] Performance testing

[0093] The chip packaging structure prepared above was subjected to the following performance tests:

[0094] 1. Heat dissipation performance test

[0095] A DC power supply was used to power the chip packaging structure. The heating power was set to 10W. After 20 minutes of power-on, a non-contact infrared thermometer was used to detect the surface temperature and record the operating temperature at 10W / 20 minutes. After the power was turned off and the device was left to stand for 10 minutes, a non-contact infrared thermometer was used to detect the surface temperature and record the temperature after 10 minutes of standing.

[0096] 2. Hot and cold cycle test

[0097] To test the pin-to-pin continuity resistance of the chip package structure, place the chip package structure in a thermal cycling chamber (temperature range -40~125℃, heating rate 5℃ / min, cooling rate 5℃ / min); cycling conditions: low temperature section (-40±2)℃, hold for 30min; high temperature section (125±2)℃, hold for 30min; number of cycles: 1000; after 1000 cycles, test the pin-to-pin continuity resistance of the chip package structure again. If the resistance growth rate is greater than 1000%, it is determined that an open circuit has occurred.

[0098] 3. Water vapor barrier performance test

[0099] Before testing, the chip package structure was dried in a 100℃ oven for 2 hours, cooled to room temperature, and weighed (recorded as m0). The insulation resistance between the package layer and the PCB board was tested (recorded as R0). The package structure was placed in a constant temperature and humidity chamber for 1000 hours, then removed, the surface moisture was wiped dry with a lint-free cloth, and the weight was recorded as m1. The water absorption rate was calculated as (m1-m0) / m0×100%. The insulation resistance between the package layer and the PCB board was tested simultaneously (recorded as R1), and the insulation resistance reduction rate was calculated as (R0-R1) / R0×100%.

[0100] The test results are entered into Table 1.

[0101] Table 1

[0102]

[0103] As can be seen from the test results in Table 1, the chip packaging structure provided by this invention has high heat dissipation efficiency, which can dissipate the accumulated temperature to the external environment in a timely manner during chip operation, avoid heat accumulation inside the chip packaging structure, and improve the chip's service life.

[0104] Comparing the test results of Examples 1 to 3, it can be seen that the combination of the first encapsulation layer and the second encapsulation layer can effectively improve the moisture barrier performance of the encapsulation layer, while effectively buffering high and low temperature deformation stress and reducing the risk of lead wires peeling off from the pads.

[0105] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high heat dissipation chip packaging structure, characterized in that, The chip substrate includes a first circuit board, a prepreg and a second circuit board which are sequentially stacked, the first circuit board includes a first substrate and first circuit patterns on both sides of the first substrate, the chip wafer is located on the surface of the first circuit board away from the prepreg, and the chip wafer is electrically connected with the first circuit patterns; the second circuit board includes a second substrate and second circuit patterns on both sides of the second substrate, the second circuit patterns are electrically connected with the PCB, the prepreg includes a fiber layer and a resin layer which completely impregnates the fiber layer, the fiber layer includes a heat conduction area corresponding to the chip wafer and an electrical connection area located at the periphery of the heat conduction area, the fiber layer includes mutually interwoven insulating fibers, a graphene layer is arranged on the outer wall of the insulating fibers in the heat conduction area, and the insulating fibers in the electrical connection area are not provided with the graphene layer, the PCB is provided with a copper block at a position corresponding to the heat conduction area, a heat conduction paint layer is arranged between the copper block and the heat conduction area of the prepreg, the packaging layer is located on the PCB, and the chip wafer and the chip substrate are packaged in the packaging layer.

2. The high heat dissipation chip package structure of claim 1, wherein, The chip substrate is provided with a plurality of through electrical connection holes in the electrical connection area, and two or more of two first circuit patterns and two second circuit patterns are electrically connected through the electrical connection holes.

3. The high heat dissipation chip package structure of claim 1, wherein, The chip wafer is provided with a first pad, the first circuit patterns are formed with a second pad at a position away from the prepreg, the first pad and the second pad are electrically connected with each other through a lead, the second circuit patterns are formed with a third pad at a position away from the prepreg, the PCB is provided with a fourth pad at the periphery of the copper block, and the third pad and the fourth pad are connected through a tin ball.

4. The high heat dissipation chip package structure of claim 1, wherein, The electrical connection area surrounds the heat conduction area, and the projection of the heat conduction area on the PCB coincides with the projection of the chip wafer on the PCB, and the copper block is located inside the projection of the heat conduction area on the PCB.

5. The high heat dissipation chip package structure of claim 1, wherein, The second circuit board is provided with a heat conduction window at a position corresponding to the copper block, the heat conduction area of the prepreg is exposed through the heat conduction window, the heat conduction paint layer respectively bonds the heat conduction area and the copper block, and the heat conduction paint layer is obtained by curing graphene heat conduction paste.

6. The high heat dissipation chip package structure of claim 1, wherein, The PCB is provided with a mounting hole penetrating through the PCB at a position corresponding to the heat conduction area, and the copper block is embedded in the mounting hole.

7. The high heat dissipation chip package structure of claim 1, wherein, The insulating fibers are glass fibers, and the resin layer is one or more of epoxy resin, polyimide resin and polyphenyl ether resin.

8. The high heat dissipation chip package structure of claim 1, wherein, The prepreg is prepared by the following method: A fiber layer formed by insulating fibers is taken, and nickel is deposited on the insulating fibers in the heat conduction area of the fiber layer under the shielding of a mask to form a nickel layer on the insulating fibers in the heat conduction area; The fiber layer after nickel deposition is placed in a quartz tube, methane and hydrogen are introduced, and graphene is grown at 900-1100 DEG C under the catalysis of nickel to obtain a fiber layer formed with graphene. The fiber layer with graphene formed is impregnated in a resin layer and pre-cured to obtain a prepreg.

9. The high heat dissipation chip package structure of claim 1, wherein, The first substrate has a thickness of 30-400 μm, the prepreg has a thickness of 40-350 μm, and the second substrate has a thickness of 30-400 μm.

10. The high heat dissipation chip package structure of claim 1, wherein, The packaging layer comprises a first packaging layer and a second packaging layer, the first packaging layer is located on the chip substrate, the chip wafer is located in the first packaging layer, the second packaging layer is located on the PCB board, and the first packaging layer and the chip substrate are located in the second packaging layer. The first packaging layer is obtained by curing a first packaging resin, and the first packaging resin comprises the following components by weight: epoxy resin 25-38 parts, epoxy-modified silicone resin 13-26 parts, fumed silica 21-38 parts, m-phenylenediamine 5-13 parts, silane coupling agent 0.1-1 part, and first solvent 30-60 parts; The second packaging layer is obtained by curing a second packaging resin, and the second packaging resin comprises the following components by weight: epoxy resin 32-59 parts, flaky silica 21-38 parts, dicyclopentadiene type phenolic resin 4-12 parts, hexamethylene diisocyanate trimer 3-7 parts, silane coupling agent 0.1-1 part, and second solvent 30-60 parts.

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