Power-on reset circuit and radio frequency chip

Abstract

The invention is suitable for the technical field of communication, and particularly relates to a power-on reset circuit and a radio frequency chip. The power-on reset circuit comprises a power-on reset unit and a buffer unit. The input end of the power-on reset unit is used for being connected with power supply voltage, the output end of the power-on reset unit is connected with the input end of the buffer unit, and the power-on reset unit is used for generating an initial reset logic signal and sending the initial reset logic signal to the buffer unit in the power-on process of the power supply voltage; the output end of the buffer unit is used for outputting a reset signal; the buffer unit is used for generating reset signal output according to the initial reset logic signal. Compared with the prior art, the power-on reset circuit provided by the invention has the advantages of simple structure, no static power consumption after resetting, high reliability and capability of normally resetting under the conditions of power supply power-on time fluctuation or continuous power-on and power-off and the like.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a power-on reset circuit and a radio frequency chip. Background Technology

[0002] The Power-On Reset (POR) circuit, as a key module in an integrated circuit system, has the core function of providing a reliable reset signal to the system during the power-on process and in the initial stage of power-up stabilization. This ensures that all functional modules within the chip start operating from a preset initial state, preventing logic errors or functional failures caused by power-on timing disorder. Currently, two relatively common POR circuit implementation schemes have emerged in the industry, each with its own unique structure and operating principle. The first type of POR circuit is an RC delay type power-on reset circuit, such as... Figure 1 As shown, Figure 1 This is a schematic diagram of a power-on reset circuit in related technologies. This type of circuit is the simplest implementation of a POR circuit, and its core design concept is based on the resistor-capacitor (RC) charging and discharging principle. The typical structure of this circuit consists of a resistor, a capacitor, and a subsequent inverter. The specific working process is as follows: When the power supply is turned on, the power supply voltage gradually rises from 0V. Due to the physical characteristic that the voltage across the capacitor cannot change abruptly, the initial voltage of the upper plate of the capacitor remains at a low level. At this time, the reset signal output is low, and the system enters the reset state. As the power supply continues to provide power, current charges the capacitor through the resistor, and the voltage of the upper plate of the capacitor gradually increases. When this voltage rises to the threshold voltage of the subsequent inverter, the inverter output state flips, the reset signal changes from low to high and remains stable, the reset process ends, and the system enters the normal operating state.

[0003] In this structure, the rise rate of the voltage on the upper plate of the capacitor is naturally delayed compared to the rise rate of the power supply voltage due to the charging process. By utilizing the sensitivity of the inverter in the subsequent stage to the threshold voltage, a low-level reset signal of a certain duration can be generated to meet the basic power-on reset requirements. The second type of POR circuit is the voltage / current detection comparator type power-on reset circuit. This type of circuit monitors power supply voltage changes in real time through a dedicated voltage detection module (such as a bandgap reference source with a comparator) or a current detection module. When the power supply voltage reaches a preset stability threshold, the reset signal is switched by flipping the comparator output level. The generation and maintenance of its reset signal rely more on accurate voltage / current threshold judgment than on a simple RC delay effect. This type of circuit has significant advantages in terms of the stability and consistency of the reset signal, and can more accurately match the system's requirements for reset timing. However, although the two types of POR circuits can achieve the basic power-on reset function, there are still significant performance short boards and application limitations in practical applications, as follows: The RC delay type power-on reset circuit has RC delay effect, so after the delay capacitor is powered off, the stored charge amount will seriously affect the next power-on delay, and is greatly affected by the power-on speed, which easily leads to the problems of too narrow reset level time or failure to generate reset level. The voltage / current detection comparison type power-on reset circuit has a more complex structure and higher power consumption, and often has a normally open branch in the circuit. If the power consumption is reduced, the impedance of the normally open branch needs to be increased, i.e. a larger area is needed.

[0004] Therefore, there is an urgent need for a new power-on reset circuit and radio frequency chip to solve the above technical problems. SUMMARY

[0005] The application provides a power-on reset circuit and a radio frequency chip, which solve the problems of the existing power-on reset circuit structure that cannot be normally reset and is easily affected by power-on time when continuously powered on and powered off, and provide a power-on reset circuit with simple structure, zero static power consumption and high reliability.

[0006] In a first aspect, the application provides a power-on reset circuit, which comprises a power-on reset unit and a buffer unit. The input end of the power-on reset unit is used for connecting a power supply voltage, and the output end of the power-on reset unit is connected to the input end of the buffer unit. The power-on reset unit is used for generating an initial reset logic signal and sending it to the buffer unit during the power-on process of the power supply voltage. The output end of the buffer unit is used for outputting a reset signal. The buffer unit is used for generating the reset signal according to the initial reset logic signal and outputting it.

[0007] Preferably, the power-on reset unit comprises a first resistor, a first capacitor, a second capacitor, a first MOS tube, a second MOS tube and a first inverter. The source of the first MOS tube is used as the input end of the power-on reset unit, the gate of the first MOS tube is connected to the first end of the first resistor, the drain of the first MOS tube is connected to the first end of the first capacitor and the gate of the second MOS tube respectively, and the second end of the first resistor, the second end of the first capacitor and the source of the second MOS tube are all grounded. The drain of the second MOS tube is connected to the input end of the first inverter, the output end of the first inverter is used as the output end of the power-on reset unit, the first end of the second capacitor is connected to the source of the first MOS tube, and the second end of the second capacitor is connected to the drain of the second MOS tube.

[0008] Preferably, the first MOS transistor is a PMOS transistor.

[0009] Preferably, the second MOS transistor is an NMOS transistor.

[0010] Preferably, the buffer unit is a Schmitt trigger or an even-stage inverter.

[0011] Preferably, the buffer unit comprises a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a second inverter, a second resistor and a third resistor. The source of the third MOS transistor is connected to the power supply voltage, the gate of the third MOS transistor, the gate of the fourth MOS transistor, the gate of the fifth MOS transistor and the gate of the sixth MOS transistor are connected to each other and serve as the input terminal of the buffer unit, the drain of the third MOS transistor and the source of the fourth MOS transistor are connected to the source of the seventh MOS transistor, the drain of the fourth MOS transistor, the drain of the fifth MOS transistor, the gate of the seventh MOS transistor and the gate of the eighth MOS transistor are connected to the input terminal of the second inverter, the source of the fifth MOS transistor and the drain of the sixth MOS transistor are connected to the source of the eighth MOS transistor, the source of the sixth MOS transistor is grounded, the drain of the seventh MOS transistor is connected to the first terminal of the second resistor, the second terminal of the second resistor is grounded, the drain of the eighth MOS transistor is connected to the first terminal of the third resistor, the second terminal of the third resistor is connected to the power supply voltage, and the output terminal of the second inverter serves as the output terminal of the buffer unit.

[0012] Preferably, the third MOS transistor, the fourth MOS transistor and the seventh MOS transistor are PMOS transistors, and the fifth MOS transistor, the sixth MOS transistor and the eighth MOS transistor are NMOS transistors.

[0013] In a second aspect, the present application also provides a radio frequency chip comprising the power-on reset circuit according to any one of the above embodiments.

[0014] Compared with the prior art, the present application comprises a power-on reset unit and a buffer unit, the input terminal of the power-on reset unit is connected to the power supply voltage, the output terminal of the power-on reset unit is connected to the input terminal of the buffer unit, the power-on reset unit is used to generate an initial reset logic signal and send it to the buffer unit during the power-on process of the power supply voltage, the output terminal of the buffer unit is used to output a reset signal, and the buffer unit is used to generate the reset signal according to the initial reset logic signal. Thus, the power-on reset circuit provided by the present application has a simple structure, no static power consumption after reset is completed, and high reliability, and can be normally reset under the conditions of power supply power-on time fluctuation or continuous power-on and power-off. Attached Figure Description

[0015] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings: Figure 1 This is a circuit diagram of a power-on reset circuit in related technologies; Figure 2 This is a circuit diagram of the power-on reset circuit provided in Embodiment 1 of the present invention; Figure 3 This is a circuit diagram of the power-on reset circuit provided in Embodiment 2 of the present invention; Figure 4 This is a simulation diagram of the power-on reset circuit provided in the embodiments of the present invention under continuous fast power-on, fast power-off and fast power-on conditions; Figure 5 This is a simulation diagram of the power-on reset circuit provided in the embodiments of the present invention during continuous slow power-on, slow power-off, and slow power-on. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0017] Example 1 Please refer to Figure 2 The present invention provides a power-on reset circuit 100, which includes a power-on reset unit 1 and a buffer unit 2. The input terminal of the power-on reset unit 1 is used to connect to the power supply voltage VDD, and the output terminal of the power-on reset unit 1 is connected to the input terminal of the buffer unit 2. The power-on reset unit 1 is used to generate an initial reset logic signal and send it to the buffer unit 2 during the power supply voltage power-on process. The output terminal of the buffer unit 2 is used to output the reset signal RST_N; the buffer unit 2 is used to generate the reset signal RST_N according to the initial reset logic signal and output it.

[0018] In this embodiment of the invention, the power-on reset unit 1 includes a first resistor R1, a first capacitor C1, a second capacitor C2, a first MOSFET M1, a second MOSFET M2, and a first inverter INV1; The source of the first MOS transistor M1 is the input terminal of the power-on reset unit 1, the gate of the first MOS transistor M1 is connected with the first terminal of the first resistor R1, the drain of the first MOS transistor M1 is connected with the first terminal of the first capacitor C1 and the gate of the second MOS transistor M2 respectively, the second terminal of the first resistor R1, the second terminal of the first capacitor C1 and the source of the second MOS transistor M2 are grounded; the drain of the second MOS transistor M2 is connected with the input terminal of the first inverter INV1, the output terminal of the first inverter INV1 is the output terminal of the power-on reset unit 1, the first terminal of the second capacitor C2 is connected with the source of the first MOS transistor M1, and the second terminal of the second capacitor C2 is connected with the drain of the second MOS transistor M2.

[0019] In the embodiment of the application, the first MOS transistor M1 is a PMOS transistor. Meanwhile, the gate length of the first MOS transistor M1 can be increased according to actual requirements, so that the impedance can be improved, the delay effect of the power-on reset unit 1 can be improved, and the threshold value can be reversed.

[0020] In the embodiment of the application, the second MOS transistor M2 is an NMOS transistor. Meanwhile, the gate length of the second MOS transistor M2 can be increased according to actual requirements, so that the impedance can be improved, the delay effect of the power-on reset unit 1 can be improved, and the threshold value can be reversed.

[0021] In the embodiment of the application, the buffer unit 2 is a Schmitt trigger or an even-stage inverter.

[0022] In the embodiment of the application, the third MOS transistor M3, the fourth MOS transistor M4 and the seventh MOS transistor M7 are PMOS transistors, and the fifth MOS transistor M5, the sixth MOS transistor M6 and the eighth MOS transistor M8 are NMOS transistors.

[0023] Specifically, the working principle of the power-on reset circuit 100 provided by the application is as follows: With the power-on of the power supply voltage VDD starting from 0, the first MOS transistor M1 is first turned on, the first capacitor C1 starts to charge, and when the voltage of the upper plate of the first capacitor C1 has not risen to the threshold voltage of the second MOS transistor M2, the voltage of the lower plate of the second capacitor C2 is still high, and the output reset signal RST_N is low; when the voltage of the upper plate of the first capacitor C1 rises to the threshold voltage of the second MOS transistor M2, the second MOS transistor M2 is turned on to pull down the voltage of the lower plate of the second capacitor C2, the output reset signal RST_N becomes high, and the reset is completed.

[0024] After the first reset is completed, the power voltage VDD is powered off, the stored charge of the first capacitor C1 is discharged by the first MOS transistor M1 through the power voltage VDD, but a small amount of charge still exists, that is, the upper plate of the first capacitor C1 still has a voltage of about several hundred millivolts but is lower than the threshold voltage of the second MOS transistor M2, at this time the second MOS transistor M2 is weakly turned on to make the reset signal RST_N follow the power voltage VDD to drop; when the power voltage VDD is powered on for the second time, the lower plate voltage of the second capacitor C2 will be high following the power voltage VDD under the coupling action of the second capacitor C2 before the voltage of the upper plate of the first capacitor C1 rises to the threshold voltage of the second MOS transistor M2, the reset signal RST_N is low; when the voltage of the upper plate of the first capacitor C1 rises to the threshold voltage of the second MOS transistor M2, the second MOS transistor M2 is turned on to pull down the lower plate voltage of the second capacitor C2, the reset signal RST_N is high again, and the second reset is completed. Thus, the corresponding reset signal RST_N can be stably output in the case of continuous power on and off, and there is no static current after the reset is completed in the power-on reset circuit 100 structure shown in Figure 2 and Figure 3 .

[0025] Embodiment Two Please refer to Figure 3 , Figure 3 is a circuit diagram of the power-on reset circuit provided in the embodiment two of the present application, Figure 3 The power-on reset circuit 200 in the embodiment two is basically the same as the power-on reset circuit 100 in the embodiment one in circuit structure, and the following is the difference: The buffer unit 2 includes a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a second inverter INV2, a second resistor R2 and a third resistor R3. The source of the third MOS transistor M3 is used for connecting the power supply voltage VDD, the gate of the third MOS transistor M3, the gate of the fourth MOS transistor M4, the gate of the fifth MOS transistor M5 and the gate of the sixth MOS transistor M6 are connected with each other and serve as the input end of the power-on reset circuit 100, the drain of the third MOS transistor M3 and the source of the fourth MOS transistor M4 are respectively connected with the source of the seventh MOS transistor M7, the drain of the fourth MOS transistor M4, the drain of the fifth MOS transistor M5, the gate of the seventh MOS transistor M7 and the gate of the eighth MOS transistor M8 are respectively connected with the input end of the second inverter INV2, the source of the fifth MOS transistor M5 and the drain of the sixth MOS transistor M6 are respectively connected with the source of the eighth MOS transistor M8, the source of the sixth MOS transistor M6 is grounded, the drain of the seventh MOS transistor M7 is connected with the first end of the second resistor R2, the second end of the second resistor R2 is grounded, the drain of the eighth MOS transistor M8 is connected with the first end of the third resistor R3, the second end of the third resistor R3 is used for connecting the power supply voltage VDD, and the output end of the second inverter INV2 serves as the output end of the buffer unit 2.

[0026] Please refer to Figure 4 , Figure 4 is a simulation result schematic diagram of the power-on reset circuit provided by the embodiment of the present application in continuous fast power-on, fast power-off and fast power-on, and the fast power-on and fast power-off time is 100 ms. Please refer to Figure 5 , Figure 5 is a simulation result schematic diagram of the power-on reset circuit provided by the embodiment of the present application in continuous slow power-on, slow power-off and slow power-on, and the slow power-on and slow power-off time is 400 ms. It can be verified from the above simulation that the power-on reset circuit 100 proposed by the present application is basically not affected by the power-on time of the power supply voltage VDD, and can still normally generate the corresponding reset signal RST_N in the continuous power-on and power-off process.

[0027] Compared with the prior art, the present application comprises a power-on reset unit and a buffer unit; the input end of the power-on reset unit is used for connecting the power supply voltage, the output end of the power-on reset unit is connected with the input end of the buffer unit, the power-on reset unit is used for generating an initial reset logic signal and sending the initial reset logic signal to the buffer unit in the power-on process of the power supply voltage; the output end of the buffer unit is used for outputting a reset signal; and the buffer unit is used for generating the reset signal according to the initial reset logic signal. In this way, the power-on reset circuit proposed by the present application has a simple structure, no static power consumption after reset is completed, and high reliability, and can normally reset under the conditions of power supply power-on time fluctuation or continuous power-on and power-off.

[0028] Embodiment three The application further provides a radio frequency chip comprising the power-on reset circuit 100 of the first embodiment or the power-on reset circuit 200 of the second embodiment, and can achieve the same technical effects, and refer to the description in the above embodiments, which will not be repeated here.

[0029] It should be noted that in this document, the terms "comprise", "comprising", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0030] The embodiments of the application are described above in conjunction with the drawings, which are disclosed only as the preferred embodiments of the application, but the application is not limited to the specific embodiments described above. The specific embodiments described above are only illustrative, not restrictive, and those of ordinary skill in the art can make many equivalent changes under the inspiration of the application without departing from the purpose of the application and the scope of the claims, which are all within the protection of the application.

Claims

1. A power-on reset circuit, characterized by comprising: The power-on reset circuit comprises a power-on reset unit and a buffer unit; An input end of the power-on reset unit is used for connecting a power supply voltage, and an output end of the power-on reset unit is connected to an input end of the buffer unit, and the power-on reset unit is used for generating an initial reset logic signal and sending the initial reset logic signal to the buffer unit during power-on of the power supply voltage; An output end of the buffer unit is used for outputting a reset signal, and the buffer unit is used for generating the reset signal according to the initial reset logic signal and outputting the reset signal.

2. The power-on reset circuit of claim 1, wherein, The power-on reset unit comprises a first resistor, a first capacitor, a second capacitor, a first MOS tube, a second MOS tube and a first inverter; An input end of the power-on reset unit is used for connecting a power supply voltage, and an output end of the power-on reset unit is connected to an input end of the buffer unit, and the power-on reset unit is used for generating an initial reset logic signal and sending the initial reset logic signal to the buffer unit during power-on of the power supply voltage; 3. The power-on reset circuit of claim 2, wherein, The first MOS tube is a PMOS tube.

4. The power-on reset circuit of claim 2, wherein, The second MOS tube is an NMOS tube.

5. The power-on reset circuit of claim 1, wherein, The buffer unit is a Schmitt trigger or an even-stage inverter.

6. The power-on reset circuit of claim 1, wherein, The buffer unit comprises a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a second inverter, a second resistor and a third resistor; An input end of the power-on reset unit is used for connecting a power supply voltage, and an output end of the power-on reset unit is connected to an input end of the buffer unit, and the power-on reset unit is used for generating an initial reset logic signal and sending the initial reset logic signal to the buffer unit during power-on of the power supply voltage; 7. The power-on reset circuit of claim 6, wherein, The third MOS tube, the fourth MOS tube and the seventh MOS tube are PMOS tubes, and the fifth MOS tube, the sixth MOS tube and the eighth MOS tube are NMOS tubes.

8. A radio frequency chip, characterized by The radio frequency chip comprises the power-on reset circuit as claimed in any one of claims 1-7.

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