Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises an array substrate, a counter substrate and a frame glue. The array substrate comprises a substrate and a plurality of thin film transistors, a passivation layer and a first transparent conductive layer. The thin film transistor comprises a gate, a gate insulating layer, an active layer and an electrode layer. The electrode layer comprises a first electrode and a second electrode. The second electrode is close to a display area. A first metal layer partially forms the gate. The first transparent conductive layer comprises a first conductive part and a second conductive part. The first conductive part is electrically connected to the first electrode. The second conductive part is electrically connected to the second electrode. The second electrode of at least the thin film transistor closest to the display area is electrically connected to the first metal layer through the second conductive part. The first electrode is not electrically connected to the first metal layer. The counter substrate comprises a second transparent conductive layer. The second transparent conductive layer is electrically connected to at least the second conductive part. Through the above arrangement, the problem that metal wiring is easily corroded is solved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] TFT-LCD (Thin Film Transistor Liquid Crystal Display) holds an unshakeable position in the field of large, medium, and small flat panel displays due to the following characteristics: low voltage and low power consumption; flat panel structure; passive display (no glare, no eye strain, independently controlled dedicated light source for adjustable brightness); large display information capacity; easy to colorize; no electromagnetic radiation; and long lifespan. As consumer demands continue to rise, TFT-LCD products need constant upgrades. For example, TFT-LCD products are moving towards narrower bezel designs, and narrow or bezel-less designs place even stricter requirements on the high temperature and humidity testing of the LCD panel.

[0003] For narrow-bezel or borderless products, the alignment film extends to the frame adhesive coating area and beyond the frame adhesive boundary due to the narrow bezel. Because the bonding ability between the alignment film and the frame adhesive is poor, and the moisture resistance of the alignment film is weakened under high temperature and high humidity conditions, moisture can easily enter the display panel through the bonding area between the alignment film and the frame adhesive during high temperature and high humidity tests. This can lead to corrosion of the metal traces and affect the performance of the display panel. Summary of the Invention

[0004] This application provides a display panel and display device to solve the problem that the metal traces of narrow-bezel or borderless display panels are easily corroded in the related art.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide a display panel, including an array substrate and a counter substrate disposed opposite to each other, and a frame adhesive connecting the array substrate and the counter substrate; the display panel includes a display area and a non-display area disposed around the periphery of the display area;

[0006] The array substrate includes a substrate and a plurality of thin-film transistors disposed on one side of the substrate, the plurality of thin-film transistors being disposed in the non-display area; each thin-film transistor includes a gate, a gate insulating layer, an active layer, and an electrode layer stacked sequentially; the electrode layer includes a first electrode and a second electrode spaced apart from each other, the second electrode being located on the side of the first electrode closer to the display area; one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode; a first metal layer portion of the display panel is located between the active layer and the substrate to form the gate electrode, and a second metal layer of the display panel includes the electrode layer;

[0007] The array substrate further includes a passivation layer and a first transparent conductive layer sequentially disposed on the side of the electrode layer away from the substrate. The passivation layer covers the plurality of thin film transistors. The first transparent conductive layer includes a first conductive portion and a second conductive portion spaced apart from each other. The first conductive portion is disposed corresponding to the first electrode and is electrically connected to the first electrode through a via. The second conductive portion is disposed corresponding to the second electrode and is electrically connected to the second electrode through a via.

[0008] At least the second electrode of the thin-film transistor closest to the display area is electrically connected to the first metal layer through a via of the second conductive portion; the first electrode is not electrically connected to the first metal layer.

[0009] The substrate includes a second transparent conductive layer, which is electrically connected to at least the second conductive portion.

[0010] In some embodiments, a first portion of the first electrode of the thin-film transistor overlaps with the active layer, and a second portion of the first electrode extends to the side of the active layer away from the display area;

[0011] The projection of the first metal layer onto the substrate at least partially overlaps with the projection of the second portion of the first electrode onto the substrate.

[0012] In some embodiments, the projection of the second portion of the first electrode onto the substrate lies within the projection of the first metal layer onto the substrate.

[0013] In some embodiments, the gate insulating layer covers the side of the first metal layer away from the display area, and the second portion of the first electrode extends from the end of the first metal layer away from the display area onto the gate insulating layer on the side of the first metal layer away from the display area.

[0014] In some embodiments, the plurality of thin-film transistors are arranged circumferentially along the array substrate;

[0015] The gates of the plurality of thin-film transistors are interconnected, and / or the second electrodes of the plurality of thin-film transistors are interconnected;

[0016] The first electrodes of the plurality of thin-film transistors are electrically connected to each other.

[0017] In some embodiments, a plurality of the thin-film transistors are provided in the direction from the non-display area to the display area;

[0018] The non-display area includes a first non-display area and a second non-display area arranged adjacent to each other, wherein the first non-display area is located on the side of the second non-display area away from the display area;

[0019] In the direction from the non-display area to the display area, the second electrode of the thin-film transistor closest to the display area is located in the second non-display area, the first electrode is located in the first non-display area, and the remaining thin-film transistors are located in the first non-display area.

[0020] In some embodiments, in the direction from the non-display area to the display area, in any two adjacent thin-film transistors, the second electrode of the thin-film transistor on the side away from the display area is electrically connected to the first electrode of the thin-film transistor on the side closer to the display area.

[0021] The gates of the plurality of thin-film transistors are interconnected, and the first electrode and the second electrode of the thin-film transistor located in the first non-display area are not electrically connected to the gate.

[0022] In some embodiments, in the direction from the non-display area to the display area, the second electrode of the thin-film transistor on the side away from the display area of ​​two adjacent thin-film transistors is electrically connected to the first electrode of the thin-film transistor on the side closer to the display area.

[0023] In the direction from the non-display area to the display area, in two adjacent thin-film transistors, the second conductive portion corresponding to the thin-film transistor on the side away from the display area is electrically connected to the first conductive portion corresponding to the thin-film transistor on the side closer to the display area, and is electrically connected to the second electrode and the first electrode of the corresponding two adjacent thin-film transistors through vias.

[0024] Alternatively, in the direction from the non-display area to the display area, in two adjacent thin-film transistors, the second electrode of the thin-film transistor on the side away from the display area is spaced apart from the first electrode of the thin-film transistor on the side closer to the display area;

[0025] The passivation layer has vias at the second electrode position of the thin-film transistor on the side away from the display area and at the first electrode position of the thin-film transistor on the side close to the display area; the second conductive portion corresponding to the thin-film transistor on the side away from the display area is in contact with and electrically connected to the first conductive portion corresponding to the thin-film transistor on the side close to the display area, and extends into the corresponding vias.

[0026] In some embodiments, in the direction from the non-display area to the display area, the thin-film transistor closest to the display area is spaced apart from the other thin-film transistors; the gate of the thin-film transistor closest to the display area is spaced apart from the gates of the other thin-film transistors.

[0027] The gates of the remaining thin-film transistors are electrically connected to each other; among the remaining thin-film transistors, in two adjacent thin-film transistors, the second electrode of the thin-film transistor on the side away from the display area is electrically connected to the first electrode of the thin-film transistor on the side closer to the display area; among the remaining thin-film transistors, the second electrode of the thin-film transistor closest to the display area is electrically connected to the corresponding gate through the second conductive portion.

[0028] Alternatively, in the direction from the non-display area to the display area, the plurality of thin-film transistors are spaced apart from each other; in any two adjacent thin-film transistors, the second electrode of the thin-film transistor on the side away from the display area is spaced apart from the first electrode of the thin-film transistor on the side closer to the display area; the gates of the plurality of thin-film transistors are spaced apart from each other.

[0029] In the direction from the non-display area to the display area, the first conductive portion corresponding to each thin-film transistor is electrically connected to the corresponding first electrode through a via; the second conductive portion corresponding to each thin-film transistor is electrically connected to the corresponding second electrode through a via, and the second electrode and the gate of each thin-film transistor are electrically connected through the corresponding second conductive portion via.

[0030] In some embodiments, the array substrate includes a first metal layer, an insulating layer, a semiconductor layer, and a second metal layer stacked sequentially; the first metal layer includes a plurality of gates, the insulating layer includes a plurality of gate insulating layers, the semiconductor layer includes a plurality of active layers, and the second metal layer includes a plurality of electrode layers; the passivation layer covers the second metal layer;

[0031] The non-display area includes a first protection zone and a second protection zone, with the second protection zone located on the side of the first protection zone closer to the display area; the thin-film transistor is located in the second protection zone.

[0032] The second metal layer further includes a protective metal disposed in the first protected area, and the first transparent conductive layer further includes a third conductive portion disposed in the first protected area; the protective metal is disposed at a distance from the electrode layer, and the first conductive portion and the second conductive portion are both disposed at a distance from the third conductive portion;

[0033] The third conductive part is electrically connected to the protective metal through a through-hole contact.

[0034] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a display device, comprising:

[0035] Any of the display panels described above;

[0036] A backlight module is disposed on one side of the display panel and is used to provide backlight for the display panel.

[0037] The beneficial effects of this application are as follows: Unlike the prior art, this application discloses a display panel and a display device. The display panel includes an array substrate and a counter substrate disposed opposite each other, and a frame adhesive connecting the array substrate and the counter substrate. The display panel includes a display area and a non-display area disposed around the display area. The array substrate includes a substrate and a plurality of thin-film transistors disposed on one side of the substrate, with the plurality of thin-film transistors disposed in the non-display area. Each thin-film transistor includes a gate, a gate insulating layer, an active layer, and an electrode layer stacked sequentially. The electrode layer includes a first electrode and a second electrode spaced apart from each other, with the second electrode located on the side of the first electrode closer to the display area. One of the first electrode and the second electrode is a source, and the other is a drain. A portion of the first metal layer of the display panel is located in the area where the array substrate is located. A gate is formed between the source layer and the substrate. The second metal layer of the display panel includes an electrode layer. The array substrate also includes a passivation layer and a first transparent conductive layer sequentially disposed on the side of the electrode layer away from the substrate. The passivation layer covers a plurality of thin-film transistors. The first transparent conductive layer includes a first conductive portion and a second conductive portion spaced apart from each other. The first conductive portion is disposed corresponding to the first electrode and is electrically connected to the first electrode through a via. The second conductive portion is disposed corresponding to the second electrode and is electrically connected to the second electrode through a via. At least the second electrode of the thin-film transistor closest to the display area is electrically connected to the first metal layer through a via of the second conductive portion. The first electrode is not electrically connected to the first metal layer. The substrate includes a second transparent conductive layer, and the second transparent conductive layer is electrically connected to at least the second conductive portion. By setting multiple thin-film transistors in the non-display area, with the first and second electrodes of the thin-film transistors spaced apart, and since the second electrode is located on the side of the first electrode closer to the display area, and the first conductive portion is set corresponding to the first electrode and electrically connected to the first electrode through a via, even if moisture enters the non-display area along the alignment film, it will first undergo electrochemical corrosion at the via corresponding to the first electrode, where the first conductive portion, moisture, and the first electrode come into contact, thus consuming most of the moisture. Furthermore, since the first electrode is not electrically connected to the first metal layer, and the first and second conductive portions of the first transparent conductive layer are spaced apart, even if the first electrode and the first conductive portion are corroded, the corrosion is unlikely to spread to the second electrode side. This effectively avoids corrosion of the second conductive portion, the second electrode, and the first metal layer on the side closer to the display area, preventing moisture from affecting the first metal layer and other components in the display area. This effectively solves the problem of easy corrosion of metal traces in narrow-bezel or borderless display panels in related technologies, improves the performance of the display panel, and ensures that the first metal layer with sufficient area is electrically connected to the second transparent conductive layer of the opposing substrate through the second conductive portion, ensuring the conductivity between the array substrate and the opposing substrate. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0039] Figure 1 This is a top view of an embodiment of the display panel provided in the first embodiment of this application;

[0040] Figure 2 yes Figure 1 A partially enlarged schematic diagram of area S of the provided display panel according to the first embodiment;

[0041] Figure 3 yes Figure 2 A cross-sectional schematic diagram of an embodiment of the provided display panel (A1-A2);

[0042] Figure 4 yes Figure 2 A cross-sectional schematic diagram of another embodiment of the provided display panel, A1-A2;

[0043] Figure 5 yes Figure 2 A cross-sectional schematic diagram of an embodiment of the provided display panel (A3-A4);

[0044] Figure 6 yes Figure 2 A schematic diagram of the electrical connections of multiple thin-film transistors in an embodiment of the array substrate of the provided display panel;

[0045] Figure 7 yes Figure 2 A schematic diagram of the distribution structure of multiple thin-film transistors in one embodiment of the provided display panel;

[0046] Figure 8 yes Figure 1 A partially enlarged schematic diagram of area S of the provided display panel according to the second embodiment;

[0047] Figure 9 yes Figure 8 A cross-sectional schematic diagram of an embodiment of the provided display panel (A1-A2);

[0048] Figure 10 yes Figure 8 A cross-sectional schematic diagram of an embodiment of the provided display panel (A3-A4);

[0049] Figure 11 yes Figure 1 A partially enlarged schematic diagram of area S of the provided display panel in the third embodiment;

[0050] Figure 12 yes Figure 11 A cross-sectional schematic diagram of the first embodiment of the provided display panel (A1-A2);

[0051] Figure 13 yes Figure 11 A cross-sectional schematic diagram of the second embodiment of the provided display panel, A1-A2;

[0052] Figure 14 yes Figure 11 A cross-sectional schematic diagram of the third embodiment of the provided display panel (A1-A2);

[0053] Figure 15 yes Figure 11 A cross-sectional schematic diagram of the fourth embodiment of the provided display panel (A1-A2);

[0054] Figure 16 This is a schematic diagram of an embodiment of the display device provided in the second embodiment of this application.

[0055] Icon labels:

[0056] 300, Display device; 200, Backlight module; 100, Display panel; 1, Array substrate; 11, Substrate; 12, Thin film transistor; 13, First metal layer; 131, Gate; 14, Insulating layer; 141, Gate insulating layer; 15, Semiconductor layer; 151, Active layer; 16, Second metal layer; 161, Electrode layer; 162, First electrode; 1621, First portion; 1622, Second portion; 163, Second electrode; 164, Protective metal; 17, Passivation layer; 18, First transparent conductive layer; 181, First conductive portion; 182, Second conductive portion; 183, Third conductive portion; 19, Alignment film; 2, Alignment substrate; 3, Frame adhesive; 4, Circuit board; X, Display area; F, Non-display area; F1, First non-display area; F2, Second non-display area; F3, First protection zone; F4, Second protection zone; B, Bonding area. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0058] The terms "first," "second," and "third" used in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0059] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0060] See Figures 1 to 15 , Figure 1 This is a top view schematic diagram of an embodiment of the display panel provided in the first embodiment of this application. Figure 2 yes Figure 1 A partially enlarged schematic diagram of area S of the provided display panel according to the first embodiment. Figure 3 yes Figure 2 A cross-sectional schematic diagram of an embodiment of the provided display panel, A1-A2. Figure 4 yes Figure 2 A cross-sectional schematic diagram of another embodiment of the provided display panel, A1-A2. Figure 5 yes Figure 2 The provided display panel, A3-A4, is a cross-sectional schematic diagram of one embodiment. Figure 6 yes Figure 2 A schematic diagram of the electrical connections of multiple thin-film transistors in an embodiment of the array substrate of the provided display panel. Figure 7 yes Figure 2 A schematic diagram of the distribution structure of multiple thin-film transistors in one embodiment of the provided display panel. Figure 8 yes Figure 1 A partially enlarged schematic diagram of area S of the provided display panel in the second embodiment. Figure 9 yes Figure 8 A cross-sectional schematic diagram of an embodiment of the provided display panel, A1-A2. Figure 10 yes Figure 8The provided display panel, A3-A4, is a cross-sectional schematic diagram of one embodiment. Figure 11 yes Figure 1 A partially enlarged schematic diagram of area S of the provided display panel in the third embodiment. Figure 12 yes Figure 11 A cross-sectional schematic diagram of the first embodiment of the provided display panel, A1-A2. Figure 13 yes Figure 11 A cross-sectional schematic diagram of the second embodiment of the provided display panel, A1-A2. Figure 14 yes Figure 11 The provided display panel is shown in cross-sectional schematic diagrams A1-A2 of the third embodiment. Figure 15 yes Figure 11 A cross-sectional schematic diagram of the fourth embodiment of the provided display panel, A1-A2.

[0061] See Figures 1 to 15 The first embodiment of this application provides a display panel 100, which includes an array substrate 1 and a counter substrate 2 disposed opposite to each other, and a frame adhesive 3 connecting the array substrate 1 and the counter substrate 2. The display panel 100 includes a display area X and a non-display area F disposed around the display area X. Specifically, as shown... Figure 1 As shown, in one embodiment, the size of the array substrate 1 is larger than the size of the counter substrate 2, and one side of the array substrate 1 protrudes from the counter substrate 2 to form a bonding area B, which is used to bond other components such as the circuit board 4.

[0062] See Figures 1 to 15In the non-display area F, the array substrate 1 includes a substrate 11 and a plurality of thin-film transistors (TFTs) disposed on one side of the substrate 11. Each TFT includes a gate 131, a gate insulator 141 (GI), an active semiconductor layer 151 (AS), and an electrode layer 161 stacked sequentially. The electrode layer 161 includes a first electrode 162 and a second electrode 163 spaced apart from each other. The second electrode 163 is located on the side of the first electrode 162 closer to the display area X, and both the first electrode 162 and the second electrode 163 are at least partially in contact with the active layer 151. One of the first electrode 162 and the second electrode 163 is the source and the other is the drain. For example, the first electrode 162 is the source and the second electrode 163 is the drain. The display panel 100 includes a first metal layer 13 and a second metal layer 16. The first metal layer 13 is partially located between the active layer 151 and the substrate 11 and forms the aforementioned gate 131. The second metal layer 16 includes the aforementioned electrode layer 161. That is, the gate 131 is formed on the first metal layer 13, and the source and drain are formed on the second metal layer 16. Specifically, the second metal layer 16 can be made of conductive metal materials such as titanium or aluminum, and the active layer 151 can be made of amorphous silicon or oxide semiconductor materials. Amorphous silicon or oxide semiconductor materials have strong corrosion resistance, and the active layer 151 is not easily corroded by moisture.

[0063] Specifically, the array substrate 1 further includes a passivation layer 17 (PV) and a first transparent conductive layer 18 sequentially disposed on the side of the electrode layer 161 away from the substrate 11. The passivation layer 17 covers a plurality of thin-film transistors 12, and the first transparent conductive layer 18 is disposed on the side of the passivation layer 17 away from the substrate 11. Figure 3 , Figure 4 , Figure 9 As shown, the first transparent conductive layer 18 includes a first conductive portion 181 and a second conductive portion 182 spaced apart from each other, i.e., the first conductive portion 181 and the second conductive portion 182 are disconnected. The first conductive portion 181 is disposed corresponding to the first electrode 162 and is electrically connected to the first electrode 162 through a via, and the second conductive portion 182 is disposed corresponding to the second electrode 163 and is electrically connected to the second electrode 163 through a via. Specifically, the passivation layer 17 can be made of silicon nitride or silicon oxide, and the material of the first transparent conductive layer 18 is indium tin oxide (ITO) or zinc tin oxide (ZTO), etc. In some embodiments, an alignment film 19 is further disposed on the side of the first transparent conductive layer 18 of the array substrate 1 away from the substrate 11, and the alignment film 19 extends to the non-display area F.

[0064] In this embodiment, at least the second electrode 163 of the thin-film transistor 12 closest to the display area X is electrically connected to the first metal layer 13 through a via of the second conductive portion 182. That is, the second electrode 163 of the thin-film transistor 12 closest to the display area X is electrically connected to the first metal layer 13 through the second conductive portion 182. The second electrode 163 and the gate 131 of the thin-film transistor 12 are electrically connected to each other, and the second electrode 163 and the gate 131 are connected to the same electrical signal. In some embodiments, the first metal layer 13 is the VCOM trace of the display panel 100, and the first metal layer 13 of the display panel 100 is connected to the VCOM signal. The second electrode 163 of the thin-film transistor 12 is electrically connected to the first metal layer 13, and the second electrode 163 is also connected to the VCOM signal. The first electrode 162 of the thin-film transistor 12 is not electrically connected to the first metal layer 13; that is, the first electrode 162 is only electrically connected to the first conductive portion 181 of the first transparent conductive layer 18 at the via location, and the first electrode 162 is not electrically connected to either the second conductive portion 182 or the first metal layer 13.

[0065] The opposing substrate 2 of the display panel 100 includes a second transparent conductive layer (not shown). The second transparent conductive layer is electrically connected to at least a second conductive portion 182. That is, the second conductive portion 182 of the first transparent conductive layer 18 is electrically connected to the first metal layer 13 through a via. Connecting the second transparent conductive layer to the second conductive portion 182 allows the VCOM signal of the first metal layer 13 to be conducted to the second transparent conductive layer of the opposing substrate 2 through the second conductive portion 182. This facilitates control of the deflection of liquid crystal molecules in the liquid crystal layer (not shown) between the array substrate 1 and the opposing substrate 2 of the display panel 100, thereby achieving the image display function. Specifically, the second transparent conductive layer of the substrate 2 and the second conductive portion 182 of the first transparent conductive layer 18 of the array substrate 1 can be electrically connected by conductive components such as conductive gold balls. Alternatively, a color resist stack layer can be provided on the substrate 2 at the position corresponding to the second conductive portion 182, and the second transparent conductive layer can be disposed on the surface of the color resist stack layer, so that the second transparent conductive layer of the substrate 2 and the second conductive portion 182 of the first transparent conductive layer 18 of the array substrate 1 can be in direct contact, thereby achieving electrical connection.

[0066] It is understood that in this embodiment of the application, by setting multiple thin-film transistors 12 in the non-display area F, and the first electrode 162 and the second electrode 163 of the thin-film transistors 12 are spaced apart from each other, a portion of the first metal layer 13 of the array substrate 1 is formed as the gate 131 of the thin-film transistor 12. Since the second electrode 163 is located on the side of the first electrode 162 that is close to the display area X, the first conductive portion 181 is set corresponding to the first electrode 162 and is electrically connected to the first electrode 162 through a via. When the thin-film transistor 12 is turned on, even if water vapor enters the non-display area F along the alignment film 19, it will first undergo electrochemical corrosion at the via corresponding to the first electrode 162, where the first conductive portion 181, water vapor and the first electrode 162 come into contact, thereby consuming most of the water vapor. Furthermore, since the first metal layer 13 is only electrically connected to the second electrode 163 through the second conductive portion 182, and the first electrode 162 is not electrically connected to the first metal layer 13, and the first conductive portion 181 and the second conductive portion 182 of the first transparent conductive layer 18 are spaced apart from each other, and the active layer 151 is made of amorphous silicon or oxide semiconductor material, the active layer 151 is not easily corroded. Even if the first electrode 162 and the first conductive portion 181 are corroded at the via location, the corrosion is not likely to extend to the second electrode 163 side. The corrosion of the first electrode 162 will not affect the second electrode 163 and the first metal layer 13, which can effectively prevent the second electrode 163 from being near the display area X side. The corrosion of conductive part 182, second electrode 163 and first metal layer 13 effectively blocks the extension of corrosion path. The spacing between the first conductive part 181 and the second conductive part 182, as well as the spacing between the first electrode 162 and the second electrode 163, limits the corrosion range and avoids the influence of moisture on the first metal layer 13 and other components in the display area X. This effectively solves the problem of easy corrosion of metal traces in narrow bezel or frameless display panels 100 in related technologies, significantly improves the reliability of narrow bezel or frameless display panels 100 in high temperature and high humidity environments, reduces display abnormalities caused by metal corrosion, and improves the performance of display panel 100. Simultaneously, when the thin-film transistor 12 is turned on, the first metal layer 13 also generates heat. The heat generated by the first metal layer 13 can heat the remaining film layer structure of the thin-film transistor 12 located on top of it, which is beneficial to improve the reaction rate between the first electrode 162 and water vapor, increase the water vapor consumption rate, and thus improve the corrosion resistance of the display panel 100. Moreover, the structure of the first metal layer 13 does not require special design, ensuring that the first metal layer 13 with sufficient area is electrically connected to the second transparent conductive layer of the opposing substrate 2 through the second conductive portion 182, ensuring the conduction effect between the array substrate 1 and the opposing substrate 2, and corrosion is not easily diffused along the second conductive portion 182 to the second transparent conductive layer of the opposing substrate 2.

[0067] Specifically, in some embodiments, the alignment film 19 is at least partially located between the frame adhesive 3 and the substrate 11, that is, the alignment film 19 extends to the coating position of the frame adhesive 3. The material of the alignment film 19 is PI (Polyimide). The display panel 100 can be a narrow-bezel or frameless display panel. Since the bezel of the display panel 100 is narrow, when the alignment film 19 is coated using a coating equipment with lower precision, the alignment film 19 easily spreads to the connection position between the frame adhesive 3 and the array substrate 1 in the non-display area F and exceeds the boundary of the frame adhesive 3. That is, the alignment film 19 easily spreads to the side of the frame adhesive 3 away from the display area X. The alignment film 19 is a low-hygroscopic material. Under high temperature and high humidity conditions, the moisture absorption capacity of the alignment film 19 weakens. That is, the moisture absorption capacity of the alignment film 19 is enhanced in the high temperature and high humidity environment, and it easily absorbs water vapor. When the display panel 100 is subjected to high temperature and high humidity testing, water vapor easily comes into contact with the alignment film 19 and enters the display panel 100. In this embodiment, even if moisture enters the display panel 100 along the alignment film 19, it will only corrode the first electrode 162 and the first conductive portion 181 at the via position corresponding to the first electrode 162 of the thin film transistor 12 in the non-display area F, due to an electrochemical reaction. The first electrode 162 is spaced apart from the second electrode 163, and the first conductive portion 181 is spaced apart from the second conductive portion 182. Therefore, the second electrode 163 and the second conductive portion 182 are not easily corroded, and the remaining traces in the display area X will not be corroded. By sacrificing only the first electrode 162 and the first conductive portion 181, the corrosion resistance of the narrow-bezel or borderless display panel 100 can be improved, thereby improving the display performance of the display panel 100.

[0068] Therefore, for narrow-bezel or borderless display panels 100, by setting the array substrate 1 to the above structure, the alignment film 19 can be coated using a low-precision coating equipment. Even if the alignment film 19 spreads to the coating position of the frame adhesive 3, it will not have a significant impact on the corrosion resistance of the narrow-bezel or borderless display panel 100. This can effectively reduce the precision requirements of the alignment film 19 coating equipment, reduce production costs, and optimize and improve the design. It solves the limitation of large fluctuations in the coating of the alignment film 19 for narrow-bezel or borderless products using PI Inject equipment, and realizes that the alignment film 19 can be coated using PI Inject equipment for narrow-bezel or borderless products.

[0069] In some implementations, such as Figure 3 , Figure 4 and Figure 9As shown, the first electrode 162 of the thin-film transistor 12 includes a first portion 1621 and a second portion 1622 connected to each other. The first portion 1621 of the first electrode 162 overlaps with the active layer 151, and the second portion 1622 of the first electrode 162 extends to the side of the active layer 151 away from the display area X. That is, the first electrode 162 only partially overlaps with the active layer 151. The projection of the first metal layer 13 on the substrate 11 at least partially overlaps with the projection of the second portion 1622 of the first electrode 162 on the substrate 11. That is, the end of the first metal layer 13, i.e., the gate 131, away from the display area X can extend to the side of the active layer 151 away from the display area X. The projection of the active layer 151 of the thin-film transistor 12 on the substrate 11 is located within the projection of the first metal layer 13 on the substrate 11, thereby ensuring that the thin-film transistor 12 can be effectively turned on. The first metal layer 13 can be made of aluminum, copper, or an alloy thereof.

[0070] It is understood that the first portion 1621 of the first electrode 162 of the thin-film transistor 12 overlaps with the active layer 151, and the projection of the first metal layer 13 on the substrate 11 at least partially overlaps with the projection of the second portion 1622 of the first electrode 162 on the substrate 11. This ensures that the thin-film transistor 12 can be effectively turned on. At the same time, it also ensures that when the thin-film transistor 12 is turned on, the heat generated by the first metal layer 13 can heat the first portion 1621 of the first electrode 162 located on top of it and the second portion 1622 that overlaps with it, thereby further accelerating the reaction rate of the first electrode 162 with water vapor, increasing the water vapor consumption rate, further improving the corrosion resistance of the display panel 100, and effectively preventing water vapor from spreading to the second electrode 163 side.

[0071] In some implementations, such as Figure 3 As shown, the projection of the first metal layer 13 onto the substrate 11 only partially overlaps with the projection of the second portion 1622 of the first electrode 162 onto the substrate 11. This arrangement ensures that the first metal layer 13 has sufficient distance from the edge of the array substrate 1, effectively preventing external moisture from reacting with and corroding the first metal layer 13 when it enters the display panel 100. Simultaneously, the heat generated by the first metal layer 13 can heat the first portion 1621 of the first electrode 162 located on top of it and the overlapping portion 1622, accelerating the consumption of moisture.

[0072] In other implementations, such as Figure 9As shown, the projection of the second portion 1622 of the first electrode 162 onto the substrate 11 is located within the projection of the first metal layer 13 onto the substrate 11. That is, the end of the first metal layer 13 away from the display area X is located on the side of the first electrode 162 away from the display area X, and the second portion 1622 of the first electrode 162 does not extend beyond the edge of the first metal layer 13. It can be understood that in this embodiment, the projection of the first electrode 162 of the thin-film transistor 12 onto the substrate 11 is completely located within the projection of the first metal layer 13 onto the substrate 11. When the first metal layer 13 is connected to the VCOM signal and the thin-film transistor 12 is turned on, the heat generated by the first metal layer 13 can heat the first portion 1621 and all the second portions 1622 of the first electrode 162 located on top of it, thereby further improving the water vapor consumption rate of the first electrode 162 and further improving the corrosion resistance of the display panel 100.

[0073] In some other implementations, such as Figure 4 As shown, the gate insulating layer 141 covers the side of the first metal layer 13 away from the display area X, and the second portion 1622 of the first electrode 162 extends from the end away from the display area X onto the gate insulating layer 141 on the side of the first metal layer 13 away from the display area X. That is, the end of the first metal layer 13 away from the display area X is wrapped by the gate insulating layer 141, and the end of the first electrode 162 away from the display area X is wrapped by the gate insulating layer 141. It is understood that the projection of the first metal layer 13 on the substrate 11 largely overlaps with the projection of the second part 1622 of the first electrode 162 on the substrate 11. When the first metal layer 13 is connected to the VCOM signal and the thin film transistor 12 is turned on, the heat generated by the first metal layer 13 can heat the first part 1621 and most of the second part 1622 of the first electrode 162 located on top of it, thereby further improving the water vapor consumption rate of the first electrode 162. At the same time, the gate insulating layer 141 covers the side of the first metal layer 13 away from the display area X, so that the first metal layer 13 is not exposed. The second part 1622 of the first electrode 162 extends to the gate insulating layer 141 on the side of the first metal layer 13 away from the display area X, so that when water vapor enters the display panel 100, it can react with the second part 1622 of the first electrode 162 and be consumed. It can also further prevent the first metal layer 13 from being corroded by water vapor. The above settings can maximize the water vapor consumption rate while effectively preventing the first metal layer 13 from being corroded.

[0074] In other embodiments, the projection of the first metal layer 13 onto the substrate 11 may not overlap with the projection of the second portion 1622 of the first electrode 162 onto the substrate 11. For example, the end of the first metal layer 13 away from the display area X may be flush with the end of the active layer 151 away from the display area X, that is, the end of the first metal layer 13 away from the display area X may be located at the junction of the first portion 1621 and the second portion 1622 of the first electrode 162. It can be understood that the non-overlapping projection of the first metal layer 13 onto the substrate 11 and the projection of the second portion 1622 of the first electrode 162 onto the substrate 11 results in a larger distance between the first metal layer 13 and the edge of the array substrate 1, which can more effectively prevent external moisture from reacting with and corroding the first metal layer 13 when it enters the display panel 100.

[0075] See Figure 1 , Figure 2 and Figure 8 In some embodiments, a plurality of thin-film transistors 12 in the non-display area F of the array substrate 1 are arranged along the circumference of the array substrate 1. That is, the plurality of thin-film transistors 12 are arranged only along the circumference of the array substrate 1, and only one thin-film transistor 12 is arranged in the direction from the display area X to the non-display area F.

[0076] For details, see Figure 7 The non-display area F may include a first non-display area F1 and a second non-display area F2 arranged adjacent to each other. The second non-display area F2 is located on the side of the first non-display area F1 that is closer to the display area X. In this embodiment, the first electrodes 162 of the plurality of thin film transistors 12 are all located in the first non-display area F1, and the second electrodes 163 of the plurality of thin film transistors 12 are all located in the second non-display area F2. This can effectively prevent the second electrodes 163 of the plurality of thin film transistors 12 located in the second non-display area F2 from being corroded, and effectively prevent moisture from spreading to the second non-display area F2.

[0077] Specifically, multiple thin-film transistors 12 are connected in parallel (see...). Figure 6 In this configuration, the gates 131 of multiple thin-film transistors 12 are connected to the same signal. Specifically, the gates 131 of multiple thin-film transistors 12 are all connected to the VCOM signal.

[0078] In one embodiment, the gates 131 of a plurality of thin-film transistors 12 are interconnected. Specifically, the gates 131 of the plurality of thin-film transistors 12 are directly contacted and connected, rather than being electrically connected through the first transparent conductive layer 18; and / or, the second electrodes 163 of the plurality of thin-film transistors 12 are interconnected. Specifically, the second electrodes 163 of the plurality of thin-film transistors 12 are directly contacted and connected. Since the second electrode 163 of each thin-film transistor 12 is electrically connected to the gate 131 through a via via the second conductive portion 182, the second electrodes 163 of the plurality of thin-film transistors 12 are also connected to the VCOM signal. The plurality of thin-film transistors 12 may be interconnected only by their gates 131, or only by their second electrodes 163, or both their gates 131 and second electrodes 163 may be interconnected. Specifically, the gates 131 of multiple thin-film transistors 12 are interconnected and / or the second electrodes 163 are interconnected, so that the gates 131 of multiple thin-film transistors 12 are connected to the same signal, which can control multiple thin-film transistors 12 to conduct simultaneously, making it easier to control, and can also provide corrosion resistance to multiple positions in the circumferential direction of the display panel 100 at the same time.

[0079] like Figure 6 As shown, the first electrodes 162 of the multiple thin-film transistors 12 are also electrically connected to each other. It can be understood that since the multiple thin-film transistors 12 are arranged along the circumference of the array substrate 1, the first electrodes 162 of the multiple thin-film transistors 12 are electrically connected to each other, which can extend the corrosion path of the first electrodes 162 in the circumference of the array substrate 1. After the first electrodes 162 of the thin-film transistors 12 at some locations come into contact with the first conductive portion 181 and water vapor and undergo an electrochemical reaction and corrosion, they can diffuse along the circumference of the array substrate 1 and along the extension path of the first electrodes 162 to the positions of the first electrodes 162 of other thin-film transistors 12, thereby further consuming water vapor and preventing water vapor from diffusing to the second electrode 163 side, which is more conducive to preventing the second electrode 163 and the first metal layer 13 from being corroded.

[0080] See Figures 11 to 15 In this embodiment, multiple thin-film transistors 12 are disposed along the circumference of the array substrate 1, that is, multiple thin-film transistors 12 are disposed in both the circumference of the array substrate 1 and the direction from the non-display area F to the display area X. In other embodiments, the multiple thin-film transistors 12 may be disposed only along the direction from the non-display area F to the display area X, and no multiple thin-film transistors 12 may be disposed in the circumference of the array substrate 1.

[0081] See Figures 11 to 15The non-display area F includes a first non-display area F1 and a second non-display area F2 arranged adjacent to each other. The first non-display area F1 is located on the side of the second non-display area F2 away from the display area X. In the direction from the non-display area F to the display area X, the second electrode 163 of the thin-film transistor 12 closest to the display area X is located in the second non-display area F2, the first electrode 162 is located in the first non-display area F1, and the remaining thin-film transistors 12 are located in the first non-display area F1. That is, in the direction from the non-display area F to the display area X, only the second electrode 163 of the innermost thin-film transistor 12 is located in the second non-display area F2.

[0082] It is understood that in this embodiment, in the direction from the non-display area F to the display area X, only the second electrode 163 of the thin-film transistor 12 closest to the display area X is located in the second non-display area F2. The first electrode 162 of the thin-film transistor 12 and the remaining thin-film transistors 12 are all located in the first non-display area F1. Moisture diffuses from the side away from the display area X to the side closer to the display area X. There are multiple thin-film transistors 12 along this path that can consume moisture. The remaining thin-film transistors 12 in the first non-display area F1 can consume moisture. Most of the moisture is consumed by the remaining thin-film transistors 12 in the first non-display area F1, and it is less likely to diffuse into the second non-display area F2 and affect the second electrode 163 of the thin-film transistor 12 closest to the display area X and the first metal layer 13. In this embodiment, a plurality of thin-film transistors 12 are provided in the direction from the non-display area F to the display area X. The multiple thin-film transistors 12 can be used to consume water vapor, increase the water vapor consumption path, and are more conducive to preventing water vapor from spreading to the display area X side. This is also more conducive to avoiding corrosion of the first metal layer 13 and further improving the corrosion resistance of the display panel 100.

[0083] In some implementations, such as Figure 12 and Figure 13 As shown, in the direction from the non-display area F to the display area X, the second electrode 163 of any two adjacent thin-film transistors 12 on the side furthest from the display area X is electrically connected to the first electrode 162 of the thin-film transistor 12 on the side closest to the display area X. In the direction from the non-display area F to the display area X, the gates 131 of the plurality of thin-film transistors 12 are interconnected, and the first electrode 162 and the second electrode 163 of the thin-film transistors 12 located in the first non-display area F1 are not electrically connected to the gate 131. That is, in the direction from the non-display area F to the display area X, the plurality of thin-film transistors 12 are connected in series.

[0084] In the direction from the non-display area F to the display area X, except for the second electrode 163 of the thin film transistor 12 closest to the display area X which is electrically connected to the first metal layer 13, i.e., the gate 131, the first electrodes 162 and second electrodes 163 of the remaining thin film transistors 12 in the first non-display area F1 are not electrically connected to the gate 131. This ensures that only the electrode layers 161, i.e., the first electrodes 162 and second electrodes 163, of the remaining thin film transistors 12 in the first non-display area F1 are corroded, while their gates 131, i.e., the first metal layer 13, are not corroded, thus preventing the corrosion of the first metal layer 13 from spreading towards the display area X.

[0085] With the above configuration, since the second electrode 163 of the thin film transistor 12 closest to the display area X is electrically connected to the first metal layer 13 through the second conductive portion 182 via, and the first metal layer 13 is connected to the VCOM signal, the second electrode 163 of the thin film transistor 12 closest to the display area X is also connected to the VCOM signal. After the thin film transistor 12 closest to the display area X is turned on, the VCOM signal of its second electrode 163 is transmitted to the first electrode 162 through the active layer 151. Since the second electrode 163 of any two adjacent thin-film transistors 12, located away from the display area X, is electrically connected to the first electrode 162 of the thin-film transistor 12 located closer to the display area X, the VCOM signal at the first electrode 162 of the thin-film transistor 12 closest to the display area X is transmitted to the second electrode 163 of the next thin-film transistor 12 electrically connected to it. This causes the next thin-film transistor 12 adjacent to the thin-film transistor 12 closest to the display area X to conduct. The VCOM signal of the second electrode 163 of this thin-film transistor 12 is transmitted through its active layer 151 to its first electrode 162. This process continues, allowing multiple thin-film transistors 12 to conduct sequentially from the display area X to the non-display area F. For the multiple thin-film transistors 12 in the direction from the non-display area F to the display area X, moisture corrodes the electrode layers 161 of the multiple thin-film transistors 12, contacting them sequentially from the non-display area F to the display area X.

[0086] In one specific implementation, such as Figure 12 As shown, in the direction from the non-display area F to the display area X, among two adjacent thin-film transistors 12, the second electrode 163 of the thin-film transistor 12 on the side away from the display area X is electrically connected to the first electrode 162 of the thin-film transistor 12 on the side closer to the display area X. That is, the second electrode 163 of the thin-film transistor 12 on the side away from the display area X is directly connected to the first electrode 162 of the thin-film transistor 12 on the side closer to the display area X, and the second electrode 163 of the thin-film transistor 12 on the side away from the display area X and the first electrode 162 of the thin-film transistor 12 on the side closer to the display area X belong to a continuous extension of the same film.

[0087] In this embodiment, in the direction from the non-display area F to the display area X, the second conductive portion 182 corresponding to the thin film transistor 12 on the side away from the display area X is electrically connected to the first conductive portion 181 corresponding to the thin film transistor 12 on the side closer to the display area X, and is electrically connected to the second electrode 163 and the first electrode 162 of the corresponding two adjacent thin film transistors 12 through a via, so that water vapor can react with the second electrode 163 and the first electrode 162 of the two adjacent thin film transistors 12 at the via at the connection position of the second electrode 163 and the first electrode 162 of the two adjacent thin film transistors 12, thereby consuming water vapor and preventing water vapor from diffusing into the second electrode 163 of the thin film transistor 12 in the second non-display area F2.

[0088] In another specific implementation, such as Figure 13 As shown, in the direction from the non-display area F to the display area X, among two adjacent thin-film transistors 12, the second electrode 163 of the thin-film transistor 12 on the side away from the display area X is spaced apart from the first electrode 162 of the thin-film transistor 12 on the side closer to the display area X. That is, the second electrode 163 of the thin-film transistor 12 on the side away from the display area X and the first electrode 162 of the thin-film transistor 12 on the side closer to the display area X are not directly in contact. Specifically, in this embodiment, the passivation layer 17 has vias at the positions corresponding to the second electrode 163 of the thin-film transistor 12 on the side away from the display area X and the first electrode 162 of the thin-film transistor 12 on the side closer to the display area X. The second conductive portion 182 corresponding to the thin-film transistor 12 on the side away from the display area X is in contact with and electrically connected to the first conductive portion 181 corresponding to the thin-film transistor 12 on the side closer to the display area X, and extends into the corresponding vias. The second electrode 163 of the thin film transistor 12 on the side away from the display area X is electrically connected to the first electrode 162 of the thin film transistor 12 on the side close to the display area X through a second conductive portion 182 and a first conductive portion 181 that are interconnected and extend into the corresponding vias, respectively.

[0089] It can be understood that, in the direction from the non-display area F to the display area X, the second electrode 163 of the thin film transistor 12 on the side away from the display area X and the first electrode 162 of the thin film transistor 12 on the side closer to the display area X are spaced apart from each other and are not directly connected. They are only electrically connected through the first transparent conductive layer 18. This can further slow down the rate at which water vapor diffuses to the first electrode 162 of the thin film transistor 12 on the side closer to the display area X, thereby more effectively preventing water vapor from diffusing to the second non-display area F2.

[0090] In some implementations, see Figure 14In the direction from the non-display area F to the display area X, the thin-film transistor 12 closest to the display area X is spaced apart from the other thin-film transistors 12. That is, the other thin-film transistors 12 are disconnected from the thin-film transistor 12 closest to the display area X and are not electrically connected.

[0091] Specifically, in the direction from the non-display area F to the display area X, the gate 131 of the thin-film transistor 12 closest to the display area X is spaced apart from the gates 131 of the other thin-film transistors 12, and the gates 131 of the other thin-film transistors 12 are electrically connected to each other. In this embodiment, the first metal layer 13 can be divided into two parts, one part being the gate 131 of the thin-film transistor 12 closest to the display area X, and the other part being the interconnected gates 131 of the other thin-film transistors 12.

[0092] In the remaining thin-film transistors 12, specifically those within the first non-display area F1, the second electrode 163 of the thin-film transistor 12 on the side furthest from the display area X is electrically connected to the first electrode 162 of the thin-film transistor 12 on the side closest to the display area X. In other words, the remaining thin-film transistors 12 within the first non-display area F1 are connected in series. Specifically, the second electrode 163 of the thin-film transistor 12 furthest from the display area X can be directly connected to the first electrode 162 of the thin-film transistor 12 closest to the display area X, or the electrical connection can be achieved through vias connecting to the corresponding first conductive portion 181 and second conductive portion 182 of the first transparent conductive layer 18.

[0093] In the remaining thin-film transistors 12, the second electrode 163 of the thin-film transistor 12 closest to the display area X is electrically connected to its corresponding gate 131 through the second conductive portion 182. That is, in the remaining thin-film transistors 12 in the first non-display area F1, the second electrode 163 of the thin-film transistor 12 closest to the display area X is electrically connected to its gate 131 through the second conductive portion 182. In the remaining thin-film transistors 12 in the first non-display area F1, the thin-film transistor 12 closest to the display area X is turned on first. After it is turned on, the next adjacent thin-film transistor 12 in the direction from the display area X to the non-display area F is turned on, and so on. The remaining thin-film transistors 12 are turned on sequentially from the display area X side to the non-display area F side. It is understood that the gates 131 of the remaining thin film transistors 12 are electrically connected to each other, and the second electrode 163 of the thin film transistor 12 closest to the display area X is electrically connected to the corresponding gate 131 through the second conductive portion 182. When the remaining thin film transistors 12 are turned on in sequence, the heat generated by the gates 131 of the remaining thin film transistors 12 can heat the first electrode 162 and the second electrode 163 located on top of them, which can further accelerate the consumption rate of water vapor in the first non-display area F1, thereby improving the corrosion resistance of the display panel 100.

[0094] In this embodiment, the thin-film transistor 12 closest to the display area X is disconnected from the gate 131 and electrode layer 161 of the remaining thin-film transistors 12 in the first non-display area F1. This allows the remaining thin-film transistors 12 in the first non-display area F1 to absorb moisture. The gate 131, first electrode 162, and second electrode 163 of the remaining thin-film transistors 12 in the first non-display area F1 can all serve as sacrificial metals for consuming moisture, which helps to increase the moisture consumption path and the area of ​​metal that can absorb moisture, thereby further improving the moisture consumption rate and enhancing the corrosion resistance of the display panel 100. Furthermore, the closest... One thin-film transistor 12 near the display area X is disconnected from the gate 131 and electrode layer 161 of the other thin-film transistors 12 in the first non-display area F1. Even if the gate 131, first electrode 162 and second electrode 163 of the other thin-film transistors 12 in the first non-display area F1 are corroded, they are not likely to extend to the side of the thin-film transistor 12 closest to the display area X. This is more conducive to blocking the path of water vapor diffusion to the display area X and more effectively preventing water vapor from diffusing to the gate 131 of the thin-film transistor 12 closest to the display area X, i.e., the first metal layer 13, and effectively preventing the first metal layer 13 near the display area X from being corroded.

[0095] In other implementations, see Figure 15In the direction from the non-display area F to the display area X, multiple thin-film transistors 12 are spaced apart from each other. That is, the thin-film transistor 12 closest to the display area X and the remaining thin-film transistors 12 in the first non-display area F1 are all spaced apart from each other. Specifically, in the direction from the non-display area F to the display area X, in any two adjacent thin-film transistors 12, the second electrode 163 of the thin-film transistor 12 away from the display area X is spaced apart from the first electrode 162 of the thin-film transistor 12 close to the display area X, and the gates 131 of the multiple thin-film transistors 12 are spaced apart from each other. That is, in the direction from the non-display area F to the display area X, in any two adjacent thin-film transistors 12, the second electrode 163 of the thin-film transistor 12 away from the display area X is disconnected from the first electrode 162 of the thin-film transistor 12 close to the display area X, and the two are not electrically connected. The gates 131 of any two adjacent thin-film transistors 12 are also not connected.

[0096] In the direction from the non-display area F to the display area X, the first conductive portion 181 of each thin-film transistor 12 is electrically connected to the corresponding first electrode 162 through a via, and the second conductive portion 182 of each thin-film transistor 12 is electrically connected to the corresponding second electrode 163 through a via. Furthermore, the second electrode 163 and the gate 131 of each thin-film transistor 12 are electrically connected through the corresponding second conductive portion 182 via. That is, in the direction from the non-display area F to the display area X, the gate 131 of each thin-film transistor 12 is electrically connected to its second electrode 163 through the second conductive portion 182. Each thin-film transistor 12 can be independently turned on. Multiple thin-film transistors 12 within the non-display area F can serve as independent consumption paths, which is beneficial for increasing the moisture consumption path. Moreover, corrosion of the gate 131 and electrode layer 161 of a single thin-film transistor 12 will not affect other thin-film transistors 12, making it less likely for moisture to diffuse towards the display area X, thus further improving the corrosion resistance of the display panel 100.

[0097] See Figure 1 , Figure 2 , Figure 5 , Figure 8 and Figure 10 In some embodiments, the array substrate 1 includes a first metal layer 13, an insulating layer 14, a semiconductor layer 15, and a second metal layer 16 stacked sequentially. The first metal layer 13 includes a plurality of gates 131, the insulating layer 14 includes a plurality of gate insulating layers 141, the plurality of gate insulating layers 141 are interconnected, the semiconductor layer 15 includes a plurality of active layers 151, the second metal layer 16 includes a plurality of electrode layers 161, and a passivation layer 17 covers the second metal layer 16.

[0098] The non-display area F includes a first protection zone F3 and a second protection zone F4. The second protection zone F4 is located on the side of the first protection zone F3 that is close to the display area X. The thin film transistor 12 of the array substrate 1 is located in the second protection zone F4. That is, the thin film transistor 12 is not disposed in the first protection zone F3.

[0099] For details, see Figure 2 , Figure 5 , Figure 8 and Figure 10 The second metal layer 16 also includes a protective metal 164 disposed in the first protective zone F3, and the first transparent conductive layer 18 also includes a third conductive portion 183 disposed in the first protective zone F3. The protective metal 164 is disposed at a distance from the electrode layer 161, and the first conductive portion 181 and the second conductive portion 182 are both disposed at a distance from the third conductive portion 183. The third conductive portion 183 and the protective metal 164 are electrically connected through a via. It is understood that by setting the thin-film transistor 12 in the second protection zone F4, further setting the first protection zone F3 on the side of the second protection zone F4 away from the display area X, and setting a protective metal 164 independent of the electrode layer 161 and a third conductive part 183 independent of the first conductive part 181 and the second conductive part 182 in the first protection zone F3, and electrically connecting the third conductive part 183 with the through hole of the protective metal 164, when water vapor enters the display panel 100, it can react with the protective metal 164 and the third conductive part 183 located in the outermost first protection zone F3 at the through hole position. The water vapor first corrodes the protective metal 164 and the third conductive part 183, thereby further enhancing the corrosion resistance of the display panel 100. Most of the water vapor is first consumed and absorbed by the protective metal 164 and the third conductive part 183 in the first protection zone F3, and is less likely to diffuse to the display area X side, effectively preventing the first metal layer 13 and other components in the display area X from being corroded.

[0100] In one specific implementation, such as Figure 2 and Figure 5 As shown, the gate 131 of the thin-film transistor 12, i.e., the first metal layer 13, may not extend into the first protective zone F3. The first protective zone F3 may not have the first metal layer 13; water vapor can be consumed directly through the reaction between the protective metal 164 at the via location and the third conductive portion 183 with the water vapor. In another specific embodiment, as... Figure 8 and Figure 10As shown, the gate 131 of the thin-film transistor 12, i.e., the first metal layer 13, can extend into the first protective zone F3. Within the first protective zone F3, the first metal layer 13 can be disposed between the insulating layer 14 and the substrate 11. The protective metal 164 is disposed on top of the first metal layer 13. It can be understood that when the thin-film transistor 12 is turned on, the heat generated by the first metal layer 13 can heat the protective metal 164 located on top of it within the first protective zone F3, which is more conducive to accelerating the reaction between water vapor and the protective metal 164 and the third conductive portion 183, and is more conducive to accelerating water vapor consumption, thereby further preventing water vapor from spreading to the display area X side.

[0101] See Figure 16 , Figure 16 This is a schematic diagram of an embodiment of the display device provided in the second embodiment of this application.

[0102] The second embodiment of this application provides a display device 300, which includes a display panel 100 and a backlight module 200. The backlight module 200 is disposed on one side of the display panel 100 and is used to provide backlight for the display panel 100 so that the display panel 100 can realize the screen display function.

[0103] Specifically, the specific structure of the display panel 100 can be any of the display panels 100 described in the above embodiments, and can be designed or selected as needed.

[0104] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A display panel, comprising an array substrate and a counter substrate arranged oppositely, and a frame glue connected between the array substrate and the counter substrate; the display panel comprises a display area and a non-display area arranged at a periphery of the display area; characterized in that, the array substrate comprises a substrate and a plurality of thin film transistors arranged at one side of the substrate, the plurality of thin film transistors are arranged in the non-display area; each of the thin film transistors comprises a gate electrode, a gate insulating layer, an active layer and an electrode layer arranged in sequence; the electrode layer comprises a first electrode and a second electrode spaced from each other, the second electrode is located at a side of the first electrode close to the display area; one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode; a first metal layer of the display panel is partially located between the active layer and the substrate to form the gate electrode, and a second metal layer of the display panel comprises the electrode layer; the array substrate further comprises a passivation layer and a first transparent conductive layer arranged in sequence at a side of the electrode layer away from the substrate, the passivation layer covers the plurality of thin film transistors; the first transparent conductive layer comprises a first conductive part and a second conductive part spaced from each other, the first conductive part is arranged corresponding to the first electrode and is electrically connected to the first electrode through a via hole, and the second conductive part is arranged corresponding to the second electrode and is electrically connected to the second electrode through a via hole; the second electrode of at least the thin film transistor closest to the display area is electrically connected to the first metal layer through the via hole of the second conductive part; the first electrode is not electrically connected to the first metal layer; the counter substrate comprises a second transparent conductive layer, the second transparent conductive layer is electrically connected to at least the second conductive part. 2.The display panel of claim 1, characterized in that, a first part of the first electrode of the thin film transistor is arranged overlapping the active layer, and a second part of the first electrode extends to a side of the active layer away from the display area; a projection of the first metal layer on the substrate at least partially overlaps a projection of the second part of the first electrode on the substrate. 3.The display panel of claim 2, characterized in that, the projection of the second part of the first electrode on the substrate is located within the projection of the first metal layer on the substrate. 4.The display panel of claim 2, characterized in that, the gate insulating layer covers a side of an end of the first metal layer away from the display area, and the second part of the first electrode extends to the gate insulating layer on the side of the end of the first metal layer away from the display area. 5.The display panel of claim 1, characterized in that, the plurality of thin film transistors are arranged along a circumferential direction of the array substrate; the gate electrodes of a plurality of the thin film transistors are connected to each other, and / or the second electrodes of a plurality of the thin film transistors are connected to each other; the first electrodes of a plurality of the thin film transistors are electrically connected to each other.

6. The display panel of claim 1, wherein, A plurality of the thin film transistors are arranged in a direction from the non-display area to the display area; The non-display area comprises a first non-display area and a second non-display area arranged adjacently, and the first non-display area is located on a side of the second non-display area away from the display area; In the direction from the non-display area to the display area, the second electrode of the thin film transistor closest to the display area is located in the second non-display area, the first electrode is located in the first non-display area, and the remaining thin film transistors are located in the first non-display area.

7. The display panel of claim 6, wherein, In the direction from the non-display area to the display area, in any two adjacent thin film transistors, the second electrode of the thin film transistor away from the display area is electrically connected to the first electrode of the thin film transistor close to the display area; The gates of the plurality of thin film transistors are connected to each other, and the first electrode and the second electrode of the thin film transistor located in the first non-display area are not electrically connected to the gate.

8. The display panel of claim 7, wherein, In the direction from the non-display area to the display area, in any two adjacent thin film transistors, the second electrode of the thin film transistor away from the display area is in contact with the first electrode of the thin film transistor close to the display area; In the direction from the non-display area to the display area, in any two adjacent thin film transistors, the second conductive part corresponding to the thin film transistor away from the display area is in contact with the first conductive part corresponding to the thin film transistor close to the display area, and is in contact with the second electrode and the first electrode of the corresponding two adjacent thin film transistors through a via hole; Or, in the direction from the non-display area to the display area, in any two adjacent thin film transistors, the second electrode of the thin film transistor away from the display area is arranged separately from the first electrode of the thin film transistor close to the display area; The passivation layer is provided with a via hole at a position corresponding to the second electrode of the thin film transistor away from the display area and at a position corresponding to the first electrode of the thin film transistor close to the display area; the second conductive part corresponding to the thin film transistor away from the display area is in contact with the first conductive part corresponding to the thin film transistor close to the display area, and respectively extends into the corresponding via hole.

9. The display panel of claim 6, wherein, In the direction from the non-display area to the display area, the thin film transistor closest to the display area is arranged separately from the remaining thin film transistors; the gate of the thin film transistor closest to the display area is arranged separately from the gates of the remaining thin film transistors. The gate electrodes of the rest of the thin film transistors are electrically connected to each other; in the rest of the thin film transistors, the second electrode of the thin film transistor far from the display area side and the first electrode of the thin film transistor close to the display area side in any two adjacent thin film transistors are electrically connected to each other; and the second electrode of the thin film transistor closest to the display area and the corresponding gate electrode are electrically connected through the second conductive part in the rest of the thin film transistors; Or, in the direction from the non-display area to the display area, the plurality of thin film transistors are spaced apart from each other; in any two adjacent thin film transistors, the second electrode of the thin film transistor far from the display area side and the first electrode of the thin film transistor close to the display area side are spaced apart from each other; and the gate electrodes of the plurality of thin film transistors are spaced apart from each other; In the direction from the non-display area to the display area, the first conductive part corresponding to each thin film transistor is electrically connected to the corresponding first electrode through a via hole; the second conductive part corresponding to each thin film transistor is electrically connected to the corresponding second electrode through a via hole, and the second electrode and the gate electrode of each thin film transistor are electrically connected through the corresponding second conductive part via hole.

10. The display panel according to any one of claims 1-9, wherein The array substrate comprises the first metal layer, the insulating layer, the semiconductor layer and the second metal layer which are sequentially stacked; the first metal layer comprises a plurality of gate electrodes, the insulating layer comprises a plurality of gate insulating layers, the semiconductor layer comprises a plurality of active layers, and the second metal layer comprises a plurality of electrode layers; and the passivation layer covers the second metal layer; The non-display area comprises a first protection area and a second protection area, and the second protection area is located on the side of the first protection area close to the display area; and the thin film transistor is located in the second protection area; The second metal layer further comprises a protection metal arranged in the first protection area, and the first transparent conductive layer further comprises a third conductive part arranged in the first protection area; the protection metal is spaced apart from the electrode layer, and the first conductive part and the second conductive part are both spaced apart from the third conductive part; The third conductive part and the protection metal are electrically connected through a via hole.

11. A display device comprising: The display panel according to any one of claims 1-10; The backlight module is arranged on one side of the display panel and is used for providing backlight for the display panel. ​

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