Energy storage system control method based on interrupt task and energy storage system

Abstract

The application provides a kind of energy storage system control method and energy storage system based on interrupt task, the unassigned interrupt vector of processor in energy storage system is configured as target interrupt vector, and the interrupt priority of target interrupt vector is set as the highest priority of system;When detecting that any energy storage device in energy storage system appears preset emergency event, target interrupt vector is triggered, so that processor jumps to execute target interrupt service program pointed by target interrupt vector;Wherein, target interrupt service program is used to process emergency event of energy storage device, and target interrupt service program execution process cannot be preempted by other interrupt program.By configuring unassigned interrupt vector of processor as target interrupt vector with highest priority, the fast processing of emergency event can be realized without affecting other processes, and the service program is not preempted by other interrupts due to the highest priority feature, so that the emergency task is completed efficiently without delay.

Description

Technical Field

[0001] This application relates to the field of energy storage, specifically to a control method and system for an energy storage system based on interruption tasks. Background Technology

[0002] In the field of energy storage control, when an energy storage system detects a preset emergency event (such as abnormal equipment over-temperature), it is usually necessary to trigger an emergency interrupt task to execute the corresponding handling scheme (such as issuing a shutdown command). In order to ensure that the emergency interrupt task is not interfered with by other interrupt tasks triggered subsequently, existing technologies usually use global interrupt shutdown or lock the emergency interrupt task to achieve this.

[0003] The above methods will incur certain performance overhead, and globally disabling interrupts or locking will also delay the execution time of emergency tasks, which may lead to the inability to quickly handle emergency events, causing equipment damage and affecting the normal operation of the energy storage system. Summary of the Invention

[0004] In view of this, this application provides a control method and energy storage system based on interrupted tasks, in order to solve the problems of difficulty in timely response and high cost in handling emergency tasks in the prior art.

[0005] In a first aspect, embodiments of this application provide a control method for an energy storage system based on interrupted tasks, including:

[0006] Configure the unspecified interrupt vector of the processor in the energy storage system as the target interrupt vector;

[0007] Set the interrupt priority of the target interrupt vector to the highest priority in the system;

[0008] When a preset emergency event is detected in any energy storage device in the energy storage system, the target interrupt vector is triggered, so that the processor jumps to execute the target interrupt service routine pointed to by the target interrupt vector;

[0009] The target interrupt service routine is used to handle emergency events of the energy storage device, and the target interrupt service routine cannot be preempted by other interrupt routines during its execution.

[0010] In one optional embodiment, the interrupt priority includes: preemption priority and response priority;

[0011] Setting the interrupt priority of the target interrupt vector to the highest system priority includes:

[0012] Set both the preemption priority and response priority of the target interrupt vector to the highest system priority.

[0013] In one optional embodiment, the preemption priority and the response priority are stored in the priority register inside the processor, each occupying 4 bits;

[0014] Setting both the preemption priority and response priority of the target interrupt vector to the highest system priority includes:

[0015] Set both the preemption priority and the response priority to 0, where the smaller the value, the higher the interrupt priority.

[0016] In one optional embodiment, triggering the target interrupt vector includes:

[0017] Write the number of the target interrupt vector to the software-triggered interrupt register of the nested vector interrupt controller, so that the software-triggered interrupt register triggers the target interrupt vector.

[0018] In one optional embodiment, the emergency event includes any of the following:

[0019] Issue emergency control commands to energy storage devices;

[0020] Real-time analysis and response to received key data.

[0021] In one optional embodiment, issuing an emergency control command to the energy storage device includes:

[0022] When a serious fault is detected in the energy storage device, a shutdown command is issued to the energy storage device based on the target interrupt service routine.

[0023] In one optional embodiment, the critical data is temporarily stored in a primary buffer and transferred to a secondary buffer by an idle interrupt service routine;

[0024] The real-time parsing and response to the received key data includes:

[0025] When the caching time of the secondary buffer data is detected to exceed the first threshold, the key data is parsed and responded to in real time based on the target interrupt service routine.

[0026] In one optional embodiment, the energy storage device includes: an energy storage converter PCS;

[0027] The serious fault includes at least one of the following: the DC side voltage of the PCS exceeds the safety threshold, the battery temperature exceeds the preset temperature threshold, or the upper-level equipment issues an emergency shutdown command.

[0028] In one alternative embodiment, the target interrupt service routine is stored in random access memory.

[0029] In one optional embodiment, the target interrupt service routine is implemented as a raw function, and when the interrupt service routine is executed, the processor only saves the context of the internal general-purpose registers and link registers.

[0030] In one optional embodiment, the processor is an STM32F7 microcontroller, and the unspecified interrupt vector is a reserved interrupt vector that is not officially defined in the interrupt vector table of the STM32F7 microcontroller.

[0031] In one optional embodiment, the unspecified interrupt vector includes: reserved interrupt vectors numbered from 110 to 255 in the interrupt vector table.

[0032] In a second aspect, embodiments of this application provide an energy storage system, including: a memory for storing computer program instructions and a processor for executing the program instructions, wherein when the computer program instructions are executed by the processor, the energy storage system performs the method described in any one of the first aspects.

[0033] Thirdly, embodiments of this application provide a computer-readable storage medium including a stored program, wherein, when the program is executed, it controls the device where the computer-readable storage medium is located to perform the method described in any of the first aspects.

[0034] Fourthly, embodiments of this application provide a computer program product comprising executable instructions that, when executed on a computer, cause the computer to perform the method described in any of the first aspects.

[0035] The solution provided in this application configures an unspecified interrupt vector of the processor in the energy storage system as a target interrupt vector, and sets the interrupt priority of the target interrupt vector to the highest priority in the system. When a preset emergency event is detected in any energy storage device in the energy storage system, the target interrupt vector is triggered, causing the processor to jump to execute the target interrupt service routine pointed to by the target interrupt vector. The target interrupt service routine is used to handle the emergency event of the energy storage device, and its execution cannot be preempted by other interrupt routines. By configuring the unspecified interrupt vector of the processor as the highest priority target interrupt vector, rapid handling of emergency events can be achieved without affecting other processes. Furthermore, the service routine, due to its highest priority characteristic, cannot be preempted by other interrupts, thus ensuring that emergency tasks are completed efficiently and without delay. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 A schematic diagram illustrating an example of an energy storage system control method based on interrupted tasks, provided in an embodiment of this application;

[0038] Figure 2 A schematic diagram illustrating another example of an energy storage system control method based on interrupted tasks provided in this application embodiment;

[0039] Figure 3 A flowchart illustrating an energy storage system control method based on interrupted tasks, provided in an embodiment of this application;

[0040] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0041] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0042] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0043] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0044] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0045] The interrupt triggering process can be found in [reference]. Figure 1The top layer is the Peripheral Interface, used to connect the chip's internal bus (AMBA APB bus) and the interrupt controller, responsible for "receiving configuration" and "reporting status". The peripheral clock PCLK2 is used to provide the controller with a working rhythm signal (such as how often to check external signals). Alternate Function I / O (AFIO) is used for I / O configuration, such as specifying a pin to trigger an interrupt.

[0046] The middle layer includes interrupt sources and control registers. This layer determines the interrupt triggering logic, such as which signals will trigger an interrupt. Among them, the control registers mainly include the following five types: (1) Pending request register, which is used to record whether an external signal has triggered an interrupt request; (2) Interrupt mask register, which is used to determine which interrupt requests will be executed. For example, if you want to ignore a key interrupt, you can set the corresponding flag to 1 to mask it; (3) Software interrupt event register, which is used to support "manually triggering interrupts with software". For example, you can directly write to this register to simulate an external interrupt through a program; (4) Rising / Falling trigger selection register, which is used to set which changes in external signals can trigger an interrupt.

[0047] External signals first enter the edge detect circuit and are matched for trigger type (rising / falling edge). Then, the suspend request register is set to 1, and the AND gate output is sent to the nested interrupt controller (NVIC), which finally triggers the central processing unit (CPU) to respond to the interrupt.

[0048] The lowest layer includes events and a pulse generator, used to trigger internal hardware operations (such as starting ADC sampling or triggering a timer). The event mask register determines which signals will trigger an event, and the pulse generator outputs a hardware pulse after an event is triggered.

[0049] Based on the above interrupt-driven principle, the CPU execution flow can be as follows: Figure 2As shown. During the execution of a normal program, if interrupt A is received, the CPU pauses the execution of the normal program, saves the normal program context, and jumps to execute the interrupt A response function. During the execution of the interrupt A response function, if interrupt B is received, the CPU pauses the execution of interrupt A, saves the interrupt A context, and jumps to execute the interrupt B response function. After the interrupt B response function completes execution, the CPU restores the interrupt A context and continues executing the interrupt A response function. After the interrupt A response function completes execution, the CPU restores the normal program context and continues executing the normal program.

[0050] In the field of energy storage, when an emergency occurs (such as the battery temperature exceeding a safety threshold), the energy storage system can issue a corresponding shutdown command. During the execution of the shutdown command, if the CPU continuously receives interrupt tasks, it will repeatedly jump to different tasks until all interrupt tasks are completed before continuing to execute the shutdown command. If interrupt tasks are continuously triggered, the shutdown command will not be issued in a timely manner, and the emergency may have serious consequences, affecting the safety of the energy storage system.

[0051] To address the aforementioned issues, this application provides an energy storage system control method based on interrupt tasks. This method enables the rapid triggering of emergency events through interrupt tasks and ensures that emergency events are not interfered with by subsequent new interrupt tasks based on interrupt priority settings, thereby ensuring that emergency tasks are completed efficiently and without delay.

[0052] Figure 2 This is a flowchart illustrating a control method for an energy storage system based on interrupt tasks, provided as an embodiment of this application. This method can be applied to energy storage systems. Figure 1 As shown, the method may include:

[0053] Step 301: Configure the unspecified interrupt vector of the processor in the energy storage system as the target interrupt vector.

[0054] Unspecified interrupt vectors refer to interrupt vectors in the processor's interrupt vector table that are not officially defined as specific peripheral functions. They are usually "unassigned interrupt numbers" reserved by the chip manufacturer. Taking the STM32F7 chip commonly used in energy storage systems as an example, interrupts numbered 110~255 in its interrupt vector table are not officially defined and will not conflict with the chip's default functions. Users can flexibly configure the functions of unspecified interrupt vectors and achieve rapid response to emergency events through the interrupt task interruption mechanism.

[0055] Step 302: Set the interrupt priority of the target interrupt vector to the highest priority of the system.

[0056] Step 303: When a preset emergency event is detected in any energy storage device in the energy storage system, the target interrupt vector is triggered so that the processor jumps to execute the target interrupt service routine pointed to by the target interrupt vector.

[0057] The energy storage system configures its emergency event handlers as the target interrupt service routines corresponding to the target interrupt vectors. When a preset emergency event is detected, an interrupt task is triggered, the energy storage system suspends the currently executing program, and saves the context. The target interrupt vector stores the memory address of the target interrupt service routine. The energy storage system can perform address jumps based on the target interrupt vector to execute the target interrupt service routine. The target interrupt service routine is used to handle emergency events in the energy storage device in a timely manner, and its execution cannot be preempted by other interrupt routines.

[0058] In this embodiment, by configuring the processor's unspecified interrupt as the emergency event handler, conflicts with the chip's default functions are avoided, and emergency events do not need to be queued like ordinary programs. Instead, they directly interrupt the currently executing task and are processed with priority, thus achieving a rapid response to emergency events.

[0059] When other interrupt tasks exist before and after an emergency event is triggered, their execution order can be determined according to their interrupt priorities. Optionally, interrupt priorities can include preemption priority and response priority. Interrupt tasks are first sorted based on preemption priority, and when preemption priorities are the same, they are then sorted based on response priority. When the processor is executing an interrupt task, if a higher preemption priority interrupt task requests to be triggered, the current interrupt task will be paused, and the processor will switch to executing the higher preemption priority interrupt task. If the new interrupt task has a lower or the same preemption priority, it must wait for the current interrupt task to complete before responding. If multiple interrupt tasks are triggered simultaneously with the same preemption priority, the processor will execute them in descending order of response priority; if the response priorities are also the same, the default numbering order in the interrupt vector table will be followed.

[0060] The processor has an internal priority register for storing preemption and response priorities. Optionally, preemption and response priorities can each occupy 4 bits. 0000 (0) is the highest priority, and 1111 (15) is the lowest priority. The smaller the value, the higher the interrupt priority. The energy storage system can set both the preemption and response priorities of the target interrupt vector to 0. When an emergency occurs, if the processor is processing other interrupt tasks, the processor will pause the execution of the current interrupt routine and execute the target interrupt service routine with priority because the target interrupt vector has a higher interrupt priority. During the execution of the target interrupt service routine, if a new interrupt task is triggered, the processor will detect that the target interrupt service routine has a higher interrupt priority and will keep the current program running.

[0061] In this embodiment, by setting interrupt priorities, the execution order of multiple interrupt tasks is clearly defined. When an emergency event is triggered, the target interrupt can interrupt other interrupt tasks being processed by the processor, and its own execution will not be disturbed by subsequent new interrupts. This ultimately ensures that emergency events are handled with the highest priority, avoiding delays caused by other interrupts. Compared to traditional methods of globally disabling or locking interrupts, this method of setting interrupt priorities reduces the impact of emergency events on other tasks and improves the overall operating efficiency of the system.

[0062] In one optional embodiment, the energy storage system can trigger the target interrupt vector by writing the target interrupt vector's number to the Software Triggered Interrupt Register (STIR) of the Nested Vectored Interrupt Controller (NVIC). After the CPU writes the target interrupt vector's number to STIR, the NVIC immediately checks the interrupt priority of the target interrupt vector. If the interrupt priority is determined to be the highest, the NVIC determines the memory address of the target interrupt service routine based on the number and then executes the target interrupt service routine.

[0063] In this embodiment, the energy storage system actively triggers interrupts by writing the target interrupt vector number to STIR. This eliminates the dependence on hardware trigger signals and ensures that emergency events can be responded to and processed in the most efficient and delay-free manner through priority verification and precise address jumps, significantly improving the energy storage system's performance in handling emergency events.

[0064] In one optional embodiment, the target interrupt service routine can be loaded into the random access memory (RAM) in advance after the energy storage system is powered on, so as to ensure that the target interrupt service routine can be executed quickly.

[0065] The following code example illustrates the interrupt triggering process:

[0066] (1) Configure interrupt priority:

[0067] HAL_NVIC_SetPriority(Reserved110_IRQn, 0, 0); / / Reserved110_IRQn is the number of the target interrupt vector. This interrupt code sets both the preemption priority and response priority of Reserved110_IRQn to 0.

[0068] HAL_NVIC_EnableIRQ(Reserved110_IRQn); / / Enable the target interrupt vector.

[0069] (2) Interrupt triggering is implemented through software:

[0070] NVIC->STIR = Reserved110_IRQn; / / Writes the target interrupt vector number Reserved110_IRQn into STIR. STIP is a dedicated register of NVIC. By writing the interrupt number (such as Reserved110_IRQn), the interrupt task can be actively triggered without relying on hardware signals (such as pin level changes). This mechanism allows the target interrupt handler corresponding to an emergency event to be triggered by software, overcoming the limitation of traditional hardware interrupts that "can only respond to external signals".

[0071] (3) Interrupt service routine execution:

[0072] __attribute__((naked, aligned(4), section(".ramfunc"))) / / Instructs the compiler not to generate additional stack frame code, avoiding redundant instructions (the traditional method will automatically save more registers, increasing latency; storing the code in RAM for execution utilizes RAM's high-speed access characteristics to reduce code execution latency;

[0073] void Custom_FastIRQ_Handler(void) {

[0074] __asm ​​volatile(…… / / Implemented through a bare function, with less code context content, to speed up the saving of context;

[0075] "push {r0-r3, lr} …… / / By saving only r0-r3 (general purpose registers) and lr (return address), compared to the conventional method of saving 16 registers (such as r0-r15), approximately 80% of context switching time can be saved;

[0076] / Interrupt handling code /

[0077] "pop {r0-r3, lr}…… / / Restore context;

[0078] "bx lr ……………… / / return; );

[0080] }

[0081] Referring to the code above, the target interrupt service routine is implemented in the form of a naked function. When the interrupt service routine is executed, the processor only saves the context of the internal general-purpose registers and link registers, which reduces the content and time of context switching, speeds up the interrupt response, and ensures the rapid handling of emergency events.

[0082] In one optional embodiment, emergency events may include: issuing emergency control commands to the energy storage device or performing real-time parsing and response to received critical data. For example, when a serious fault is detected in the energy storage device (such as severe battery overheating), the energy storage system can issue a shutdown command to the energy storage device based on the target interrupt service routine. As another example, critical data received by the energy storage system from other devices is temporarily stored in a primary buffer and transferred to a secondary buffer by an idle interrupt service routine. However, if CPU resources are constantly preempted by other interrupt tasks, the data in the secondary buffer may be difficult to process in a timely manner, potentially causing some important events to be delayed for extended periods, affecting the normal operation of the system. Therefore, when the energy storage system detects that the buffering time of the secondary buffer data exceeds a first threshold, it can trigger the target interrupt service routine to perform real-time parsing and response to the critical data (such as heartbeat response, emergency command response, or setting state machine flags). Optionally, the primary buffer is a fixed-size storage area, typically an array or a circular buffer. When the serial port receives a byte of data, the Direct Memory Access (DMA) controller can automatically place this byte into the next position in the primary buffer without going through the CPU. The secondary buffer is a dynamically allocated memory area whose size is exactly matched to the amount of data received this time.

[0083] The following specific examples illustrate the execution of emergency events:

[0084] (1) Emergency handling of serious faults in the power conversion system (PCS):

[0085] When an emergency event such as battery fire or short circuit risk occurs in the PCS of the energy storage system, the energy storage system issues an "emergency shutdown command". Specifically, the energy storage system detects abnormalities in key parameters (such as battery temperature > 85°C, DC-side voltage > 1000V, exceeding the safety threshold). It then issues a "forced shutdown command" to the Digital Signal Processing (DSP) chip via the target interrupt service routine, directly driving the hardware circuit to disconnect the DC-side high-voltage relay.

[0086] Based on interrupt handling, energy storage systems can ensure millisecond-level response to emergencies and prevent the spread of faults (such as battery thermal runaway and high-voltage electric shock risks). Compared with traditional interrupts (which may be delayed by other tasks), setting interrupt priorities can quickly and efficiently achieve emergency event handling without interruption and with minimal impact on other tasks.

[0087] (2) Real-time parsing of sudden massive amounts of packets from the server:

[0088] When an energy storage system can wirelessly communicate with a server, and the server suddenly sends a large number of messages (such as sending multiple control commands or data at once), the energy storage system needs to process them quickly to avoid data loss. To avoid data overwriting, energy storage systems typically use a "dual buffer," consisting of a primary buffer and a secondary buffer. After receiving data, the energy storage system first buffers it in the primary buffer. However, the capacity of the primary buffer is limited (usually in bytes). If new data continues to arrive, older data that hasn't been processed in time will be directly overwritten. Therefore, the energy storage system needs to "copy" the data from the primary buffer to the secondary buffer in real time. To avoid frequent data processing triggers, when there is an "idle period" in data reception (e.g., no new data for 50 µs), the energy storage system can determine that a "complete message" has been received, triggering an idle interrupt service routine to transfer the data from the primary buffer to the secondary buffer.

[0089] If the server sends messages continuously, the data in the secondary buffer will be delayed in parsing and response. This will consume more memory and may also affect the normal operation of the system due to the failure to respond to certain critical data in a timely manner. To address this issue, the energy storage system can enable a timeout trigger mechanism. A time threshold is set; if the data in the secondary buffer exceeds the first threshold without being processed, the target interrupt service routine is triggered. Since this interrupt is configured with the highest priority, the main program will immediately suspend all current tasks (including other interrupt handling) and jump to the target interrupt service routine, exclusively using CPU resources to parse the data in the secondary buffer (e.g., extracting server instructions, verifying data integrity).

[0090] In one optional embodiment, the secondary buffer is a dynamically allocated memory space for the energy storage system, and its capacity is not fixed. The energy storage system can determine a first threshold based on the capacity of the secondary memory and the average transmission rate of critical data. Optionally, the formula may include: First threshold = (Secondary buffer capacity / Average transmission rate of critical data) × M, where M is a redundancy coefficient used to cope with fluctuations in data transmission rate.

[0091] In this embodiment, the first threshold is dynamically determined by the capacity of the secondary buffer and the average transmission rate of key data. This allows the first threshold to adapt to different data transmission scenarios, ensuring real-time parsing and response to key data (such as emergency stop instructions and battery status messages), reducing the frequency of invalid interrupts, lowering CPU resource consumption, and achieving a balance between flexible adaptation and efficient processing.

[0092] In one optional embodiment, as server data is continuously sent to the primary buffer, the idle interrupt service routine will wait indefinitely. Once the primary buffer is full, previous data may be overwritten. Therefore, the target interrupt service routine in this embodiment can also be configured to transfer data from the primary buffer to the secondary buffer. Specifically, when the energy storage system detects that the time interval between the last execution of the idle interrupt service routine exceeds a second threshold, it can transfer data from the primary buffer to the secondary buffer based on the target interrupt service routine. Based on the characteristics of the target interrupt service routine, the energy storage system can suspend other operations and prioritize the data transfer operation to ensure data integrity.

[0093] Corresponding to the above embodiments, this application also provides an electronic device that can serve as the actual control device for the above energy storage system and implement the above method flow. Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device 400 may include a processor 401, a memory 402, and a communication unit 403. These components communicate through one or more buses. Those skilled in the art will understand that the structure of the electronic device shown in the figure does not constitute a limitation on the embodiment of this application. It may be a bus-shaped structure or a star-shaped structure, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0094] The communication unit 403 is used to establish a communication channel, enabling the electronic device to communicate with other devices. It receives user data from other devices or sends user data to other devices.

[0095] The processor 401 serves as the control center of the electronic device, connecting various parts of the device via interfaces and lines. It executes software programs, instructions, and / or modules stored in the memory 402, and calls data stored in the memory to perform various functions and / or process data. The processor may be composed of integrated circuits (ICs), such as a single packaged IC or multiple packaged ICs with the same or different functions connected together. For example, the processor 401 may consist only of a central processing unit (CPU). In this embodiment, the CPU may have a single processing core or include multiple processing cores.

[0096] The memory 402 is used to store the execution instructions of the processor 401. The memory 402 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0097] When the execution instructions in memory 402 are executed by processor 401, the electronic device 400 is able to perform some or all of the steps in the above embodiments.

[0098] In a specific implementation, this application also provides a computer storage medium, wherein the computer storage medium may store a program, which, when executed, may include some or all of the steps of the various embodiments of the interrupt-task-based energy storage system control method provided in this application. The storage medium may be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0099] In a specific implementation, this application also provides a computer program product, wherein the computer program product includes executable instructions, which, when executed on a computer, cause the computer to perform some or all of the steps in various embodiments of the interrupt-based energy storage system control method provided in this application.

[0100] This application also provides a non-transitory computer-readable storage medium that stores computer instructions, which cause the computer to execute the interrupt-based energy storage system control method provided in this application.

[0101] The aforementioned non-transitory computer-readable storage medium may be any combination of one or more computer-readable media. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or flash memory, optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in connection with an instruction execution system, apparatus, or device.

[0102] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including—but not limited to—electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of transmitting, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0103] The program code contained on a computer-readable medium may be transmitted using any suitable medium, including—but not limited to—wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0104] Those skilled in the art will clearly understand that the techniques in the embodiments of this application can be implemented using software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of this application, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application or some parts of the embodiments.

[0105] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the device embodiments and terminal embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

Claims

1. A control method for an energy storage system based on interrupting a task, characterized by, The method comprises the following steps: configuring an unspecified interrupt vector of a processor in an energy storage system as a target interrupt vector; setting an interrupt priority of the target interrupt vector as a system highest priority; triggering the target interrupt vector when a preset emergency event occurs in any energy storage device in the energy storage system, so as to make the processor jump to execute a target interrupt service program pointed by the target interrupt vector; the target interrupt service program is used for processing the emergency event of the energy storage device, and the target interrupt service program cannot be preempted by other interrupt programs during execution, and the target interrupt service program is realized in the form of a bare function; a memory space of the energy storage system is provided with a first buffer area and a second buffer area, and critical data received by the energy storage system is temporarily stored in the first buffer area and transferred to the second buffer area by an idle interrupt service program; the method further comprises the following steps: determining a first threshold value based on a capacity of the second buffer area and an average transmission rate of the critical data, and when a cache duration of data in the second buffer area exceeds the first threshold value, performing real-time analysis and response on the critical data based on the target interrupt service program; the first buffer area is a fixed-size storage area, the second buffer area is a dynamically applied memory area, and the first threshold value=(second buffer area capacity / critical data average transmission rate)×M, wherein M is a redundancy coefficient determined by data transmission rate fluctuation.

2. The interrupt task-based energy storage system control method of claim 1, wherein, the interrupt priority comprises a preemption priority and a response priority; the step of setting the interrupt priority of the target interrupt vector as the system highest priority comprises the following steps: setting the preemption priority and the response priority of the target interrupt vector as the system highest priority.

3. The interrupt task-based energy storage system control method of claim 2, wherein, the preemption priority and the response priority are stored in a priority register inside the processor, and each occupies 4 bits; the step of setting the preemption priority and the response priority of the target interrupt vector as the system highest priority comprises the following steps: setting the preemption priority and the response priority as 0, wherein the smaller the value is, the higher the interrupt priority is.

4. The interrupt task-based energy storage system control method of claim 1, wherein, the step of triggering the target interrupt vector comprises the following steps: writing a number of the target interrupt vector into a software-triggered interrupt register of a nested vector interrupt controller, so that the software-triggered interrupt register triggers the target interrupt vector.

5. The interrupt task-based energy storage system control method of claim 1, wherein, the emergency event comprises any one of the following: issuing an emergency control instruction to the energy storage device; performing real-time analysis and response on the received critical data.

6. The interrupt task-based energy storage system control method of claim 5, wherein, the step of issuing an emergency control instruction to the energy storage device comprises the following steps: when a serious fault occurs in the energy storage device, issuing a shutdown instruction to the energy storage device based on the target interrupt service program.

7. The interrupt task-based energy storage system control method of claim 5, wherein, the critical data is temporarily stored in the first buffer area and transferred to the second buffer area by the idle interrupt service program; the step of performing real-time analysis and response on the received critical data comprises the following steps: when a cache duration of data in the second buffer area exceeds a first threshold value, performing real-time analysis and response on the critical data based on the target interrupt service program.

8. The interrupt task-based energy storage system control method of claim 6, wherein, the energy storage device comprises an energy storage converter PCS. The serious fault includes at least one of the following: a direct current side voltage of the PCS exceeding a safety threshold, a battery temperature exceeding a preset temperature threshold, and an emergency shutdown instruction issued by a superior device.

9. The interrupt task-based energy storage system control method of claim 1, wherein, The target interrupt service program is stored in a random access memory.

10. The interrupt task-based energy storage system control method of claim 1, wherein, The target interrupt service program is implemented in a form of a naked function, and when the interrupt service program is executed, the processor only saves contexts of internal general registers and a link register.

11. The interrupt task-based energy storage system control method of claim 1, wherein, The processor is a microcontroller STM32F7, and the unspecified interrupt vector is a reserved interrupt vector in an interrupt vector table of the microcontroller STM32F7 and is not defined officially.

12. The interrupt task-based energy storage system control method of claim 11, wherein, The unspecified interrupt vector includes reserved interrupt vectors numbered from 110 to 255 in the interrupt vector table.

13. An energy storage system characterized by, A computer program product including a memory for storing computer program instructions and a processor for executing the program instructions, wherein the computer program instructions, when executed by the processor, cause the energy storage system to perform the method of any one of claims 1 to 12.

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