Driving circuit, display panel and display device

Abstract

The application provides a driving circuit, a display panel and a display device. The driving circuit is composed of cascaded driving units. The driving unit is composed of a gate driving unit and a light-emitting driving unit. The output end of the light-emitting driving unit is used for outputting a light-emitting signal. The gate driving unit comprises a first pull-up control module, a first pull-up module, a first pull-down module, a first pull-up control node and a first pull-down control node. The first pull-up module and the first pull-down module control output of a row scanning signal. The first pull-down control node of the gate driving unit and the first pull-down module are connected with the output end of the light-emitting driving unit and multiplex the light-emitting signal as a pull-down control signal. The structure of the gate driving unit and the driving circuit is simplified, so that the narrow frame design of the display panel can be further realized.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display panel, and particularly relates to a driving circuit, a display panel and a display device. BACKGROUND

[0002] An OLED panel is generally composed of a driving circuit and a pixel array, the pixel array includes pixel units arranged in an array, each pixel unit is composed of a plurality of thin film transistors and a light emitting diode, the driving circuit outputs corresponding driving signals to the pixel units to control the pixel units to write data signals and drive the light emitting diodes to emit light.

[0003] The driving circuit is composed of a plurality of cascaded driving units, each driving unit is composed of a GOA (Gate Driver on Array) unit and an EOA (Emission driver On Array) unit, the GOA unit outputs a data writing control signal required by the pixel units of a current row and controls the pixel units to write data signals, and the EOA unit outputs a light emitting signal required by the pixel units of the current row to drive the pixel units to emit light based on the data signals.

[0004] The GOA unit is composed of at least a pull-up control module, a pull-down control module, a pull-up module and a pull-down module, the pull-up control module is used to control the pull-up module to output a row opening signal, and the pull-down control module of the GOA unit is used to control the pull-down module to output a row closing signal, since the GOA unit needs to be provided with at least four modules, the structure is complex, and it is difficult to achieve a narrow frame for the display panel. SUMMARY

[0005] The present application aims to provide a driving circuit, and aims to solve the problem that the GOA unit of the conventional driving circuit is complex in structure and difficult to achieve a narrow frame.

[0006] A first aspect of the embodiment of the present application provides a driving circuit, which includes a plurality of cascaded driving units, each driving unit is connected with a row of pixel units, and each driving unit includes a GOA unit and an EOA unit.

[0007] The output end of the EOA unit is used to output a light emitting signal.

[0008] The GOA unit includes a first pull-up control module, a first pull-up module, a first pull-down module, a first pull-up control node and a first pull-down control node.

[0009] The first pull-up control module, the first pull-up module and the first pull-up control node are connected, the first pull-down module, the first pull-down control node and the output end of the light-emitting driving unit are connected, and the first pull-up module and the first pull-down module control the output of the row scanning signal.

[0010] Optionally, the light-emitting driving unit comprises a second pull-up control module, a pull-down control module, a second pull-up module, a second pull-down module, a second pull-up control node and a second pull-down control node.

[0011] The second pull-up control module, the second pull-up module and the second pull-up control node are connected, the pull-down control module, the second pull-down module and the second pull-down control node are connected, and the second pull-up module and the second pull-down module control the output of the light-emitting signal.

[0012] Optionally, the second pull-up control module comprises a first thin film transistor, a first end of the first thin film transistor is used for inputting a first start signal or a light-emitting signal of a previous stage light-emitting driving unit, a control end of the first thin film transistor is used for inputting a first clock signal of the current stage, and a second end of the first thin film transistor is connected with the second pull-up control node.

[0013] The pull-down control module comprises a first capacitor, a second thin film transistor and a third thin film transistor.

[0014] A first end of the first capacitor, a first end of the second thin film transistor and a control end of the first thin film transistor are connected, a second end of the first capacitor and a control end of the second thin film transistor are connected, a second end of the second thin film transistor, a first end of the third thin film transistor and the second pull-down control node are connected, a second end of the third thin film transistor is used for inputting a row closing signal, and a control end of the third thin film transistor is connected with the second pull-up control node.

[0015] The second pull-up module comprises a fourth thin film transistor and a second capacitor, a control end of the fourth thin film transistor, a first end of the second capacitor and the second pull-up control node are connected, a first end of the fourth thin film transistor is used for inputting a row opening signal, a second end of the fourth thin film transistor, a second end of the second capacitor and an output end of the second pull-up module are connected to constitute the output end of the light-emitting driving unit.

[0016] The second pull-down module comprises a third capacitor, a fifth thin film transistor and a sixth thin film transistor, a first end of the third capacitor, a control end of the fifth thin film transistor, a control end of the sixth thin film transistor and the second pull-down control node are connected, a second end of the third capacitor and a second end of the sixth thin film transistor are connected and used for inputting a row closing signal, a second end of the fifth thin film transistor and a first end of the sixth thin film transistor are connected, and a first end of the fifth thin film transistor is connected with an output end of the second pull-up module.

[0017] Optionally, the first pull-up module comprises a seventh thin film transistor, a first end of the seventh thin film transistor is used for inputting a second clock signal of the current stage, a control end of the seventh thin film transistor is connected with the first pull-up control node, and a second end of the seventh thin film transistor is connected with an output end of the first pull-down module to constitute an output end of the gate driving unit.

[0018] The first pull-down module comprises an eighth thin film transistor, a second end of the eighth thin film transistor is used for inputting a row closing signal, a control end of the eighth thin film transistor, an output end of the light-emitting driving unit and the first pull-down control node are connected, and a first end of the eighth thin film transistor is connected with an output end of the first pull-up module.

[0019] The first pull-up control module comprises a fourth capacitor and a ninth thin film transistor, the fourth capacitor is connected between a control end and a second end of the seventh thin film transistor, a first end of the ninth thin film transistor is connected with the first pull-up control node, a second end of the ninth thin film transistor is used for inputting a row closing signal, and a control end of the ninth thin film transistor is connected with the first pull-down control node.

[0020] Optionally, the light-emitting driving unit further comprises a first stage transmission trigger module, the first stage transmission trigger module is connected with the pull-down control module, and the first stage transmission trigger module is used for outputting a row closing signal according to a first start signal or a light-emitting signal of the light-emitting driving unit of a previous stage, so as to control the pull-down control module to output a pull-down control signal to the second pull-down module.

[0021] The gate driving unit further comprises a second stage transmission trigger module, the second stage transmission trigger module is connected with the first pull-up control module, and the second stage transmission trigger module is used for outputting a row opening signal according to a second start signal or a row scanning signal output by the gate driving unit of a previous stage, so as to control the first pull-up control module to output a pull-up control signal to the first pull-up module.

[0022] Optionally, the first-stage transmission trigger module comprises a tenth thin film transistor, a second end of the tenth thin film transistor is configured to input a row-off signal, a control end of the tenth thin film transistor is configured to input a first start signal or a light-emitting signal of the light-emitting driving unit of a previous stage, and a first end of the tenth thin film transistor, a second end of the first capacitor and a control end of the second thin film transistor are connected.

[0023] The second-stage transmission trigger module comprises an eleventh thin film transistor, a control end of the eleventh thin film transistor is configured to input a second start signal or a row scanning signal output by the gate driving unit of a previous stage, a first end of the eleventh thin film transistor is configured to input a row-on signal, and a second end of the eleventh thin film transistor is connected with the first pull-up control node.

[0024] Optionally, the light-emitting driving unit further comprises a first-stage transmission reset module, the first-stage transmission reset module is connected with the second pull-up control node, and the first-stage transmission reset module is configured to output a reset signal according to a light-emitting signal of the light-emitting driving unit of a next stage, so as to reset the second pull-up control node.

[0025] The gate driving unit further comprises a second-stage transmission reset module, the second-stage transmission reset module is connected with the first pull-up control node, and the second-stage transmission reset module is configured to output a reset signal according to a row scanning signal of the gate driving unit of a next stage, so as to reset the first pull-up control node.

[0026] Optionally, the gate driving unit further comprises a frame-preemptive emptying module, the frame-preemptive emptying module is connected with the first pull-up control node, and the frame-preemptive emptying module is configured to output a reset signal according to a reset control signal, so as to reset the first pull-up control node.

[0027] A second aspect of the embodiment of the present application provides a display panel, comprising an array substrate and the driving circuit as described above, and the driving circuit is arranged on one side or both sides of the array substrate.

[0028] A third aspect of the embodiment of the present application provides a display device, comprising a driving control board and the display panel as described above, and the display panel and the driving control board are connected.

[0029] The beneficial effects of the embodiment of the present application compared with the prior art are that: the driving circuit is composed of cascaded driving units, the driving unit is composed of a gate driving unit and a light emitting driving unit, the output end of the light emitting driving unit is used for outputting a light emitting signal, the gate driving unit includes a first pull-up control module, a first pull-up module, a first pull-down module, a first pull-up control node and a first pull-down control node, wherein the first pull-up module and the first pull-down module control output of a row scanning signal, the first pull-down control node of the gate driving unit and the first pull-down module are connected with the output end of the light emitting driving unit and reuse the light emitting signal as a pull-down control signal, the structure of the gate driving unit and the driving circuit are simplified, so that the narrow frame design of the display panel can be further realized. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 Structure schematic diagrams of the driving circuit, the display panel and the display device provided for the first, the sixth and the seventh embodiments of the present application;

[0031] Figure 2 The first structure schematic diagram of the driving unit provided for the first embodiment of the present application;

[0032] Figure 3 The structure schematic diagram of the pixel unit provided for the first embodiment of the present application;

[0033] Figure 4 The timing schematic diagram of the driving signal of the pixel unit provided for the first embodiment of the present application;

[0034] Figure 5 The second structure schematic diagram of the driving unit provided for the first embodiment of the present application;

[0035] Figure 6 The third structure schematic diagram of the driving unit provided for the first embodiment of the present application;

[0036] Figure 7 The circuit schematic diagram of the driving unit provided for the first embodiment of the present application;

[0037] Figure 8 The structure schematic diagram of the driving unit provided for the second embodiment of the present application;

[0038] Figure 9 The circuit schematic diagram of the driving unit provided for the second embodiment of the present application;

[0039] Figure 10 The structure schematic diagram of the driving unit provided for the third embodiment of the present application;

[0040] Figure 11 The circuit schematic diagram of the driving unit provided for the third embodiment of the present application;

[0041] Figure 12This is a schematic diagram of the structure of the driving unit provided in Embodiment 4 of the present invention;

[0042] Figure 13 This is a circuit diagram of the driving unit provided in Embodiment 4 of the present invention;

[0043] Figure 14 The above are schematic diagrams of the signal timing of the driving unit provided in Embodiments 2, 3 and 4 of the present invention.

[0044] The figures in the diagram are labeled as follows:

[0045] 100. Array substrate; 200. Driving control board; 110. Display area; 120. Non-display area; 121. Driving circuit; 122. Driving unit; 10. Gate driving unit; 20. Light-emitting driving unit; 11. First pull-up control module; 12. First pull-up module; 13. First pull-down module; 14. Second-stage trigger module; 15. Second-stage reset module; 16. Frame pre-clear module; 21. Second pull-up control module; 22. Pull-down control module; 23. Second pull-up module; 24. Second pull-down module; 25. First-stage trigger module; 26. First-stage reset module;

[0046] T01, First sub-thin film transistor; T02, Second sub-thin film transistor; T03, Third sub-thin film transistor; T04, Fourth sub-thin film transistor; T05, Fifth sub-thin film transistor; T06, Sixth sub-thin film transistor; DT, Driver transistor; OLED, Light-emitting diode; T1, First thin film transistor; T2, Second thin film transistor; T3, Third thin film transistor; T4, Fourth thin film transistor; T5, Fifth thin film transistor; T6, Sixth thin film transistor; T7, Seventh thin film transistor; T8, Eighth thin film transistor; T9, Ninth thin film transistor; T10, Tenth thin film transistor; T11, Eleventh thin film transistor; T12, Twelfth thin film transistor; T13, Thirteenth thin film transistor; T14, Fourteenth thin film transistor; C1, First capacitor; C2, Second capacitor; C3, Third capacitor; C4, Fourth capacitor;

[0047] GPU, first pull-up control node; GPD, first pull-down control node; EPD, second pull-up control node; EPU, second pull-down control node;

[0048] VGH, Horizontal Enable Signal; VGL, Horizontal Disable Signal; CKn, Second Clock Signal; CKn+1, Second Clock Signal of the Next-Level Gate Driver Unit; ECKn, First Clock Signal; En, Light Emitting Signal; Gn, Horizontal Scan Signal of the Current Gate Driver Unit; Gn-1, Horizontal Scan Signal of the Previous-Level Gate Driver Unit; STV, Second Start Signal; STE, First Start Signal; En-1, Light Emitting Signal of the Previous-Level Light Emitting Driver Unit; Data, Data Signal; ELVDD, Positive Voltage; RST, Reset Control Signal; H1, Reset Period; H2, Data Write Period; H3, Light Emitting Period. Detailed Implementation

[0049] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0050] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0052] Example 1

[0053] A first aspect of the present invention provides a driving circuit 121, such as... Figure 1 As shown, the driving circuit 121 is disposed in the non-display area 120 of the array substrate 100. The array substrate 100 also includes a display area 110, which is provided with an array of pixel units 111. The driving circuit 121 includes multiple cascaded driving units 122, each driving unit 122 being connected to a row of pixel units 111, as shown. Figure 2 As shown, the driving unit 122 includes a light-emitting driving unit 20 and a gate driving unit 10. The light-emitting driving units 20 of each driving unit 122 are cascaded in sequence, and the gate driving units 10 of each driving unit 122 are cascaded in sequence. At the same time, the gate driving unit 10 and the light-emitting driving unit 20 of each stage of the driving unit 122 are respectively connected to the pixel unit 111 of the corresponding row.

[0054] The gate driving unit 10 outputs a row scanning signal Gn as a data write control signal to the pixel unit 111 during row scanning. The light-emitting driving unit 20 outputs a light-emitting signal En to the pixel unit 111. The pixel unit 111 is composed of multiple thin-film transistors and light-emitting diodes (OLEDs). The multiple thin-film transistors include at least a data write transistor, a driving transistor, and a light-emitting transistor, and may also include a corresponding reset transistor, for example... Figure 3 As shown, pixel unit 111 has a 7T1C structure, consisting of seven thin-film transistors, one capacitor C01, and a light-emitting diode (OLED). The first sub-thin-film transistor T01 and the second sub-thin-film transistor T02 are reset transistors; the third sub-thin-film transistor T03 and the fourth sub-thin-film transistor T04 are data writing transistors; the driving transistor DT is used to acquire the data signal Data; and the fifth sub-thin-film transistor T05 and the sixth sub-thin-film transistor T06 are light-emitting transistors. During line-by-line scanning, when scanning to pixel unit 111 of the previous line, as... Figure 4 As shown, during the reset period H1, the first sub-thin film transistor T01 and the second sub-thin film transistor T02 receive the row scan signal Gn-1 from the previous gate driving unit 10 and reset node N1. When scanning to the current row, i.e., during the data writing period H2, the third sub-thin film transistor T03 and the fourth sub-thin film transistor T04 receive the row scan signal Gn from the gate driving unit 10 of the current row and are triggered to conduct, writing the data signal Data to the driving transistor DT. During the light emission period H3, the fifth sub-thin film transistor T05 and the sixth sub-thin film transistor T06 receive the light emission signal En output by the light emission driving unit 20 and are triggered to conduct. The positive voltage ELVDD at the positive power supply terminal and the data signal Data are output to the light-emitting diode OLED through the light-emitting transistor and drive the light-emitting diode OLED to emit light.

[0055] In this process, each sub-thin film transistor is triggered to turn on upon receiving a first level signal and to turn off upon receiving a second level signal. During the reset period H1 and the light-emitting period H3, the gate driving unit 10 of this stage outputs the second level signal, and during the light-emitting period H3, the gate driving unit 10 of this stage outputs a data write control signal of the first level signal. During the reset period H1 and the data write period H2, the light-emitting driving unit 20 outputs the second level signal, and during the light-emitting period H3, the light-emitting driving unit 20 outputs a light-emitting signal En of the first level signal. The first level and the second level signal can be high or low levels respectively. In an optional embodiment, the first level signal is high and the second level signal is low.

[0056] To simplify the circuit structure and achieve the goal of a narrow bezel, such as Figure 5 As shown, in this embodiment, the output terminal of the light-emitting driving unit 20 is used to output the light-emitting signal En;

[0057] The gate driving unit 10 includes a first pull-up control module 11, a first pull-up module 12, a first pull-down module 13, a first pull-up control node GPU, and a first pull-down control node GPD;

[0058] The first pull-up control module 11, the first pull-up module 12 and the first pull-up control node GPU are connected, the first pull-down module 13, the first pull-down control node GPD and the output terminal of the light-emitting driving unit 20 are connected, and the first pull-up module 12 and the first pull-down module 13 control the output of the line scanning signal Gn.

[0059] In this embodiment, multiple gate driving units 10 are connected in sequence, and multiple light-emitting driving units 20 are connected in sequence. During line-by-line scanning, the first-level gate driving unit 10 receives the second start signal STV and starts working. The second to nth level gate driving units 10 respectively receive the row scanning signal Gn-1 of the previous level gate driving unit 10 and start working. At the same time, the row scanning signal Gn of the current level gate driving unit 10 can also be output as a stage-by-stage reset signal to the previous level gate driving unit 10, thereby resetting the previous level gate driving unit 10.

[0060] Similarly, during the row-by-row driving of light emission, the first-level light emission driving unit 20 receives the first start signal STE and starts working. The second to nth level light emission driving units 20 respectively receive the light emission signal En-1 from the previous level light emission driving unit 20 and start working. At the same time, the light emission signal En of the current level light emission driving unit 20 can also be output as a stage-by-stage reset signal to the previous level light emission driving unit 20, thereby resetting the previous level light emission driving unit 20.

[0061] During the current frame and when scanning to the current line, during the reset period H1, the light-emitting driving unit 20 outputs a low-level light-emitting signal En to the corresponding connected pixel unit 111 and the first pull-down control node GPD of the gate driving unit 10, and the first pull-down module 13 is turned off. At the same time, during the reset period H1, the first pull-up control module 11 controls the first pull-up module 12 to output a low level, and both the light-emitting driving unit 20 and the gate driving unit 10 output a low level to the pixel unit 111, and the corresponding node of the pixel unit 111 is reset.

[0062] During the data writing period H2, the light-emitting driving unit 20 outputs a low-level light-emitting signal En to the corresponding connected pixel unit 111 and the first pull-down control node GPD of the gate driving unit 10. At this time, the pixel unit 111 has no high-level light-emitting signal En input, the pixel unit 111 does not emit light, and the first pull-down module 13 is turned off.

[0063] Meanwhile, during the data writing period H2, the first pull-up control module 11 controls the first pull-up module 12 to turn on and output a high level. At this time, the gate driving unit 10 outputs a high-level row scanning signal Gn. The row scanning signal Gn controls the data writing transistor in the pixel unit 111 to turn on and write the data signal Data to the driving transistor DT.

[0064] During the light emission period H3, the light emission driving unit 20 outputs a high-level light emission signal to the corresponding connected pixel unit 111 and the first pull-down control node GPD of the gate driving unit 10. At this time, the pixel unit 111 inputs a high-level light emission signal En, the light emitting transistor in the pixel unit 111 is turned on, and the positive voltage ELVDD and data signal Data at the positive power supply terminal are output to the light emitting diode OLED through the light emitting transistor, and drive the light emitting diode OLED to emit light.

[0065] At the same time, after receiving the row enable signal VGH, the first pull-down module 13 is triggered to conduct and outputs the row disable signal VGL to the pixel unit 111, thereby realizing the purpose of the gate drive unit 10 to output a low-level signal during the light emission period H3.

[0066] The light emission signal En output by the light emission driving unit 20 has the same waveform and phase as the output signal of the pull-down control module originally used to control the operation of the first pull-down module 13. By multiplexing the light emission driving unit 20 to complete the pull-down control of the first pull-down module 13, the structural design of the pull-down control module can be omitted, simplifying the structure of the gate driving unit 10 and the display panel, thereby further achieving the goal of narrow bezel.

[0067] Meanwhile, the timing of the second pull-up control signal of the GPU in the first pull-up control node and the light emission signal En is adjustable, and the corresponding phase difference can be set to avoid the simultaneous high level state. Correspondingly, the first pull-up module 12 and the first pull-down module 13 have no through current, reducing the power consumption of the display panel.

[0068] The first pull-up control module 11, the first pull-up module 12, and the first pull-down module 13 can be composed of corresponding thin-film transistors and can be used to input the required clock signal, start signal, etc.

[0069] The light-emitting driving unit can also adopt the corresponding pull-up module, pull-down module, pull-up control module, pull-down control module and other structures.

[0070] In one alternative embodiment, as in another alternative embodiment, such as Figure 6 As shown, the light-emitting driving unit 20 includes a second pull-up control module 21, a pull-down control module 22, a second pull-up module 23, a second pull-down module 24, a second pull-up control node EPD, and a second pull-down control node EPU;

[0071] The second pull-up control module 21 and the second pull-up module 23 are connected to the second pull-up control node EPD, and the pull-down control module 22, the second pull-down module 24 and the second pull-down control node EPU are connected. The second pull-up module 23 and the second pull-down module 24 control the output of the light-emitting signal En.

[0072] During the current frame and when scanning to the current line, in the reset period H1, the second pull-up control module 21 of the light-emitting driving unit 20 outputs a low-level first pull-up control signal to the second pull-up control node EPD according to the received corresponding signal, the second pull-up module 23 is turned off, the pull-down control module 22 outputs a high-level first pull-down control signal to the second pull-down control node EPU according to the received signal, the second pull-down module 24 is turned on and outputs a low-level row turn-off signal VGL to the corresponding connected pixel unit 111 and the first pull-down control node GPD of the gate driving unit 10, the first pull-down module 13 is turned off, and at the same time, in the reset period H1, the first pull-up control module 11 controls the first pull-up module 12 to output a low level, the light-emitting driving unit 20 and the gate driving unit 10 both output a low level to the pixel unit 111, and the corresponding node of the pixel unit 111 is reset.

[0073] During the data writing period H2, the second pull-up control module 21 maintains a low-level first pull-up control signal output to the second pull-up control node EPD, the second pull-up module 23 is turned off, the pull-down control module 22 maintains a high-level first pull-down control signal output, the second pull-down module 24 maintains a conducting state and outputs a low-level row turn-off signal VGL to the first pull-down control node GPD of the corresponding connected pixel unit 111 and gate drive unit 10. At this time, the pixel unit 111 has no high-level light emission signal En input, the pixel unit 111 does not emit light, and the first pull-down module 13 is turned off.

[0074] Meanwhile, during the data writing period H2, the first pull-up control module 11 controls the first pull-up module 12 to turn on and output a high level. At this time, the gate driving unit 10 outputs a high-level row scanning signal Gn. The row scanning signal Gn controls the data writing transistor in the pixel unit 111 to turn on and write the data signal Data to the driving transistor DT.

[0075] During the light emission period H3, the second pull-up control module 21 outputs a high-level first pull-up control signal to the second pull-up control node EPD, the second pull-up module 23 is turned on, and outputs a high-level row enable signal VGH to the first pull-down control node GPD of the corresponding connected pixel unit 111 and gate drive unit 10. At this time, the pixel unit 111 inputs a high-level light emission signal En, the light emitting transistor in the pixel unit 111 is turned on, and the positive voltage ELVDD and data signal Data at the positive power supply terminal are output to the light emitting diode OLED through the light emitting transistor, driving the light emitting diode OLED to emit light.

[0076] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The driving circuit 121 described above is composed of cascaded driving units 122. The driving unit 122 is composed of a gate driving unit 10 and a light-emitting driving unit 20. The light-emitting driving unit 20 includes a second pull-up control module 21, a pull-down control module 22, a second pull-up module 23 and a second pull-down module 24, a second pull-up control node EPD and a second pull-down control node EPU. The gate driving unit 10 includes a first pull-up control module 11, a first pull-up module 12, a first pull-down module 13, a first pull-up control node GPU and a first pull-down control node GPD. The first pull-down control node GPD and the first pull-down module 13 of the gate driving unit 10 are connected to the output terminal of the light-emitting driving unit 20 and the light-emitting signal En is multiplexed as the pull-down control signal, which simplifies the structure of the gate driving unit 10 and the driving circuit, thereby further realizing the narrow bezel design of the display panel.

[0077] Example 2

[0078] In an alternative embodiment, such as Figure 7 As shown, the second pull-up control module 21 includes a first thin-film transistor T1. The first terminal of the first thin-film transistor T1 is used to input the first start signal STE or the light emission signal En-1 of the previous stage light emission driving unit 20. The control terminal of the first thin-film transistor T1 is used to input the first clock signal ECKn of this stage. The second terminal of the first thin-film transistor T1 is connected to the second pull-up control node EPD.

[0079] The pull-down control module 22 includes a first capacitor C1, a second thin-film transistor T2, and a third thin-film transistor T3;

[0080] The first terminal of the first capacitor C1, the first terminal of the second thin film transistor T2, and the control terminal of the first thin film transistor T1 are connected. The second terminal of the first capacitor C1 and the control terminal of the second thin film transistor T2 are connected. The second terminal of the second thin film transistor T2, the first terminal of the third thin film transistor T3, and the second pull-down control node EPU are connected. The second terminal of the third thin film transistor T3 is used to input the row turn-off signal VGL. The control terminal of the third thin film transistor T3 is connected to the second pull-up control node EPD.

[0081] The second pull-up module 23 includes a fourth thin film transistor T4 and a second capacitor C2. The control terminal of the fourth thin film transistor T4, the first terminal of the second capacitor C2 and the second pull-up control node EPD are connected. The first terminal of the fourth thin film transistor T4 is used to input the row enable signal VGH. The second terminal of the fourth thin film transistor T4, the second terminal of the second capacitor C2 and the output terminal of the second pull-up module 23 are connected to form the output terminal of the light-emitting driving unit 20.

[0082] The second pull-down module 24 includes a third capacitor C3, a fifth thin-film transistor T5, and a sixth thin-film transistor T6. The first terminal of the third capacitor C3, the control terminal of the fifth thin-film transistor T5, the control terminal of the sixth thin-film transistor T6, and the second pull-down control node EPU are connected. The second terminal of the third capacitor C3 and the second terminal of the sixth thin-film transistor T6 are connected and used to input the row turn-off signal VGL. The second terminal of the fifth thin-film transistor T5 and the first terminal of the sixth thin-film transistor T6 are connected. The first terminal of the fifth thin-film transistor T5 is connected to the output terminal of the second pull-up module 23.

[0083] The first pull-up module 12 includes a seventh thin-film transistor T7. The first terminal of the seventh thin-film transistor T7 is used to input the second clock signal CKn of this stage. The control terminal of the seventh thin-film transistor T7 is connected to the first pull-up control node GPU. The second terminal of the seventh thin-film transistor T7 and the output terminal of the first pull-down module 13 are connected to form the output terminal of the gate driving unit 10.

[0084] The first pull-down module 13 includes an eighth thin-film transistor T8. The second terminal of the eighth thin-film transistor T8 is used to input the row turn-off signal VGL. The control terminal of the eighth thin-film transistor T8, the output terminal of the light-emitting driving unit 20 and the first pull-down control node GPD are connected. The first terminal of the eighth thin-film transistor T8 is connected to the output terminal of the first pull-up module 12.

[0085] The first pull-up control module 11 includes a fourth capacitor C4 and a ninth thin-film transistor T9. The fourth capacitor C4 is connected between the control terminal and the second terminal of the seventh thin-film transistor T7. The first terminal of the ninth thin-film transistor T9 is connected to the first pull-up control node GPU. The second terminal of the ninth thin-film transistor T9 is used to input the row turn-off signal VGL. The control terminal of the ninth thin-film transistor T9 is connected to the first pull-down control node GPD.

[0086] In this embodiment, reference Figure 14 As shown, in the current frame and when scanning to the current line, during the reset period H1, the first start signal STE or the light emission signal En-1 of the previous stage light emission driving unit 20 is at a low level, the first clock signal ECKn is at a high level, the first thin-film transistor T1 is triggered to turn on and outputs a low-level first pull-up control signal to the second pull-up control node EPD, the fourth thin-film transistor T4 of the second pull-up module 23 is triggered to turn off, at the same time, the third thin-film transistor T3 is turned off, the second thin-film transistor T2 receives a high level through the first capacitor C1, the second thin-film transistor T2 turns on, and the second thin-film transistor T2 outputs a high-level first pull-down control signal to The second pull-down control node EPU, the fifth thin-film transistor T5 and the sixth thin-film transistor T6 are turned on and output a low-level row turn-off signal VGL to the corresponding connected pixel unit 111 and the first pull-down control node GPD of the gate driving unit 10. The eighth thin-film transistor T8 of the first pull-down module 13 is turned off. At the same time, during the reset period H1, the second clock signal CKn input to the seventh thin-film transistor T7 is at a low level, the fourth capacitor C4 is coupled to a low level, the seventh thin-film transistor T7 outputs a low level, the light-emitting driving unit 20 and the gate driving unit 10 both output a low level to the pixel unit 111, and the corresponding node of the pixel unit 111 is reset.

[0087] During the data writing period H2, the first clock signal ECKn of the first thin-film transistor T1 is low, and the first start signal STE or the light emission signal En-1 of the previous stage light-emitting driving unit 20 is high. The first thin-film transistor T1 is triggered to turn off. The second pull-up control node EPD is maintained at a low level due to the presence of the second capacitor C2. The fourth thin-film transistor T4 is turned off, the second thin-film transistor T2 is triggered to turn off, the third capacitor C3 maintains the output of the first pull-down control signal at a high level, and the fifth thin-film transistor T5 and the sixth thin-film transistor T6 maintain the conduction state and output a low-level row turn-off signal VGL to the corresponding connected pixel unit 111 and the first pull-down control node GPD of the gate driving unit 10. At this time, the pixel unit 111 has no high-level light emission signal En input, the pixel unit 111 does not emit light, and the first pull-down module 13 is turned off.

[0088] Meanwhile, during the data writing period H2, the second clock signal CKn switches to a high level, the first pull-up control node GPU is coupled up through the fourth capacitor C4, the seventh thin film transistor T7 is triggered to conduct and output a high level, and at this time the gate drive unit 10 outputs a high level row scan signal Gn, the row scan signal Gn controls the data writing transistor in the pixel unit 111 to conduct and write the data signal Data to the drive transistor DT.

[0089] During the light emission period H3, the first clock signal ECKn switches to a high level, and the first start signal STE or the light emission signal En-1 of the previous stage light emission driving unit 20 switches to a high level. The first thin film transistor T1 is triggered and turns on, and outputs a high-level first pull-up control signal to the second pull-up control node EPD. The fourth thin film transistor T4 turns on and outputs a high-level row enable signal VGH to the corresponding connected pixel unit 111 and the first pull-down control node GPD of the gate driving unit 10. The row enable signal VGH serves as the light emission signal En. At this time, the pixel unit 111 inputs a high-level light emission signal En, and the light emitting transistor in the pixel unit 111 turns on. The positive voltage ELVDD and the data signal Data at the positive power supply terminal are output to the light-emitting diode OLED through the light emitting transistor, and drive the light-emitting diode OLED to emit light.

[0090] Meanwhile, after receiving the row enable signal VGH, the eighth thin-film transistor T8 is triggered to conduct and outputs the row disable signal VGL to the pixel unit 111, thereby realizing the purpose of the gate drive unit 10 to output a low-level signal during the light emission period H3. The ninth thin-film transistor T9 is turned on and pulls the first pull-up control node GPU down to a low potential, while the seventh thin-film transistor T7 is turned off.

[0091] The output signal of the light-emitting driving unit 20 is the same as the output signal of the pull-down control module 22 originally used to control the first pull-down module 13. By reusing the light-emitting driving unit 20 to complete the pull-down control of the first pull-down module 13, the structural design of the pull-down control module 22 can be omitted, simplifying the structure of the gate driving unit 10 and the display panel, thereby further achieving the goal of narrow bezel.

[0092] Example 3

[0093] In an alternative embodiment, such as Figure 8 As shown, the light-emitting driving unit 20 also includes a first-level trigger module 25, which is connected to the pull-down control module 22. The first-level trigger module 25 is used to output a row-off signal VGL according to the first start signal STE or the light-emitting signal En-1 of the previous light-emitting driving unit 20, so as to control the pull-down control module 22 to output a pull-down control signal to the second pull-down module 24.

[0094] The gate driving unit 10 also includes a second-stage trigger module 14, which is connected to the first pull-up control module 11. The second-stage trigger module 14 is used to output a row enable signal VGH according to the second start signal STV or the row scan signal Gn-1 output by the gate driving unit 10 of the previous stage, so as to control the first pull-up control module 11 to output a pull-up control signal to the first pull-up module 12.

[0095] In this embodiment, during the data writing period H2 or the light emission period H3, the first start signal STE or the light emission signal En-1 of the previous stage light emission driving unit 20 is at a high level. The first stage trigger module 25 is turned on and outputs a low-level row close signal VGL to the pull-down control module 22. The pull-down control module 22 is then turned on. The pull-down control module 22 can output a high-level or low-level first pull-down control signal to the second pull-down module 24. The second pull-down module 24 is then turned on or off accordingly.

[0096] During the reset period H1, the second start signal STV or the row scan signal Gn-1 output by the gate drive unit 10 of the previous stage is at a high level. The second stage trigger module 14 is turned on and outputs the row enable signal VGH to the first pull-up control node GPU. The first pull-up control module 11 controls the first pull-up module 12 to be turned on. At this time, the second clock signal CKn is at a low level, and the first pull-up module 12 outputs a low level.

[0097] The first-stage trigger module 25 and the second-stage trigger module 14 can be composed of corresponding thin-film transistors, and can be used to input the required clock signal, start signal, etc.

[0098] like Figure 9 As shown, in an optional embodiment, the first-stage trigger module 25 includes a tenth thin-film transistor T10. The second terminal of the tenth thin-film transistor T10 is used to input a row turn-off signal VGL. The control terminal of the tenth thin-film transistor T10 is used to input the light emission signal En-1 or the first start signal STE of the previous stage light emission driving unit 20. The first terminal of the tenth thin-film transistor T10, the second terminal of the first capacitor C1, and the control terminal of the second thin-film transistor T2 are connected.

[0099] The second-level trigger module 14 includes an eleventh thin-film transistor T11. The control terminal of the eleventh thin-film transistor T11 is used to input the second start signal STV or the row scan signal Gn-1 output by the gate drive unit 10 of the previous stage. The first terminal of the eleventh thin-film transistor T11 is used to input the row enable signal VGH. The second terminal of the eleventh thin-film transistor T11 is connected to the first pull-up control node GPU.

[0100] In this embodiment, refer to Figure 14As shown, during the reset period H1, the first start signal STE or the light emission signal En-1 of the previous stage light-emitting driving unit 20 is at a low level, the first clock signal ECKn is at a high level, the first thin-film transistor T1 is triggered to turn on and outputs a low-level first pull-up control signal to the second pull-up control node EPD, the fourth thin-film transistor T4 of the second pull-up module 23 is triggered to turn off, at the same time, the third thin-film transistor T3 is turned off, the second thin-film transistor T2 receives a high level through the first capacitor C1, the tenth thin-film transistor T10 is turned off, the second thin-film transistor T2 is turned on, the second thin-film transistor T2 outputs a high-level first pull-down control signal to the second pull-down control node EPU, the fifth thin-film transistor T5 and the sixth thin-film transistor T10 are triggered to turn off, and the second thin-film transistor T2 outputs a high-level first pull-down control signal to the second pull-down control node EPU. When the body transistor T6 is turned on, it outputs a low-level row turn-off signal VGL to the corresponding connected pixel unit 111 and the first pull-down control node GPD of the gate driving unit 10. The eighth thin-film transistor T8 of the first pull-down module 13 is turned off. At the same time, during the reset period H1, the second start signal STV is high, the eleventh thin-film transistor T11 is turned on, and outputs a high-level second pull-up control signal to the seventh thin-film transistor T7. The seventh thin-film transistor T7 is turned on, the second clock signal CKn input to the seventh thin-film transistor T7 is low, the seventh thin-film transistor T7 outputs a low level, the light-emitting driving unit 20 and the gate driving unit 10 both output a low level to the pixel unit 111, and the corresponding node of the pixel unit 111 is reset.

[0101] During the data writing period H2, the first clock signal ECKn of the first thin-film transistor T1 is low, and the first start signal STE or the light emission signal En-1 of the previous stage light emission driving unit 20 is high. The first thin-film transistor T1 is triggered to turn off, the tenth thin-film transistor T10 is triggered to turn on, and outputs a low-level row turn-off signal VGL to the second thin-film transistor T2. The second thin-film transistor T2 is turned off, and the second pull-up control node EPD is maintained at a low level due to the presence of the second capacitor C2. The fourth thin-film transistor T4 is turned off, the third capacitor C3 maintains the output of a high-level first pull-down control signal, and the fifth thin-film transistor T5 and the sixth thin-film transistor T6 remain on and output a low-level row turn-off signal VGL to the corresponding connected pixel unit 111 and the first pull-down control node GPD of the gate driving unit 10. At this time, the pixel unit 111 has no high-level light emission signal En input, the pixel unit 111 does not emit light, and the first pull-down module 13 is turned off.

[0102] Meanwhile, during the data writing period H2, the second clock signal CKn switches to a high level, the first pull-up control node GPU is coupled up through the fourth capacitor C4, the seventh thin film transistor T7 outputs a high level, and at this time the gate drive unit 10 outputs a high level row scan signal Gn. The row scan signal Gn controls the data writing transistor in the pixel unit 111 to turn on and write the data signal Data to the drive transistor DT.

[0103] During the light-emitting period H3, the first clock signal ECKn switches to a high level, the first start signal STE or the light-emitting signal En-1 of the previous stage light-emitting driving unit 20 switches to a high level, the first thin-film transistor T1 and the tenth thin-film transistor T10 are triggered to conduct, and output a high-level first pull-up control signal to the second pull-up control node EPD, the fourth thin-film transistor T4 is turned on, and outputs a high-level row enable signal VGH to the corresponding connected pixel unit 111 and the first pull-down control node GPD of the gate driving unit 10, the second thin-film transistor T2 is turned off, the second pull-down control node EPU is at a low level, the fifth thin-film transistor T5 and the sixth thin-film transistor T6 are turned off, and the row enable signal VGH serves as the light-emitting signal En. At this time, the pixel unit 111 inputs a high-level light-emitting signal En, the light-emitting transistor in the pixel unit 111 is turned on, the positive voltage ELVDD at the positive power supply terminal and the data signal Data are output to the light-emitting diode OLED through the light-emitting transistor, and drive the light-emitting diode OLED to emit light.

[0104] Simultaneously, the eighth thin-film transistor T8 is triggered to conduct after receiving the row enable signal VGH and outputs the row disable signal VGL to the pixel unit 111. The second start signal STV is low, and the eleventh thin-film transistor T11 is turned off, thereby realizing the purpose of the gate drive unit 10 to output a low-level signal during the light emission period H3. The ninth thin-film transistor T9 is turned on and pulls down the first pull-up control node GPU to maintain it at a low potential, while the seventh thin-film transistor T7 is turned off.

[0105] Example 4

[0106] In an alternative embodiment, such as Figure 10 As shown, the light-emitting driving unit 20 also includes a first-stage reset module 26. The first-stage reset module 26 is connected to the second pull-up control node EPD. The first-stage reset module 26 is used to output a reset signal according to the light-emitting signal En+1 of the next-stage light-emitting driving unit 20 to reset and clear the second pull-up control node EPD.

[0107] The gate drive unit 10 also includes a second-stage reset module 15, which is connected to the first pull-up control node GPU. The second-stage reset module 15 is used to output a reset signal according to the row scan signal of the next-stage gate drive unit 10 to reset and clear the first pull-up control node GPU.

[0108] In this embodiment, reference Figure 14 As shown, the light-emitting driving unit 20 can also be reset according to the light-emitting signal En+1 of the next-level light-emitting driving unit 20, and the gate driving unit 10 can also be reset according to the row scanning signal of the next-level gate driving unit 10, and the charge of the second pull-up control node EPD and the first pull-up control node GPU can be cleared and reset.

[0109] When the first-stage reset module 26 receives the light emission signal En+1 from the next-stage light emission driving unit 20, the first-stage reset module 26 is triggered to conduct and outputs a low-level reset signal. The high level of the second pull-up control node EPD is discharged and its charge is cleared through the first-stage reset module 26. Similarly, when the second-stage reset module 15 receives the row scan signal from the next-stage gate driving unit 10, the second-stage reset module 15 is triggered to conduct and outputs a low-level reset signal. The high level of the first pull-up control node GPU is discharged and its charge is cleared through the second-stage reset module 15.

[0110] The first-stage reset module 26 and the second-stage reset module 15 can be composed of corresponding thin-film transistors. In an optional embodiment, such as... Figure 11 As shown, the first-stage reset module 26 includes a twelfth thin-film transistor T12. The first terminal of the twelfth thin-film transistor T12 is connected to the second pull-up control node EPD. The second terminal of the twelfth thin-film transistor T12 is used to input the row turn-off signal VGL. The control terminal of the twelfth thin-film transistor T12 is used to input the light emission signal En+1 of the next-stage light-emitting driving unit 20.

[0111] The second-stage reset module 15 includes a thirteenth thin-film transistor T13. The first terminal of the thirteenth thin-film transistor T13 is connected to the first pull-up control node GPU. The second terminal of the thirteenth thin-film transistor T13 is used to input the row turn-off signal VGL. The control terminal of the thirteenth thin-film transistor T13 is used to input the row scan signal of the next-stage gate drive unit 10.

[0112] In this embodiment, after the gate driving unit 10 and the light-emitting driving unit 20 of this stage output the corresponding row scanning signal Gn and light-emitting signal En, the gate driving unit 10 and the light-emitting driving unit 20 of the next stage start working and output the row scanning signal Gn and light-emitting signal En of the next stage. At this time, the row scanning signal Gn of the next stage is output to the thirteenth thin-film transistor T13 of the second stage reset module 15 of the gate driving unit 10 of the previous stage. The thirteenth thin-film transistor T13 is turned on, and the high level of the first pull-up control node GPU is discharged through the thirteenth thin-film transistor T13 and the charge is cleared.

[0113] Simultaneously, the next-level light emission signal En is output to the twelfth thin-film transistor T12 of the first-level transmission reset module 26 of the previous-level light emission driving unit 20. The twelfth thin-film transistor T12 is turned on, and the high level of the second pull-up control node EPD is discharged through the twelfth thin-film transistor T12 and the charge is cleared.

[0114] In this process, the row scanning signal of the next-level gate driving unit 10 is in phase with the second clock signal CKn of the next level, and the control terminal of the second-level reset module 15 of the previous-level gate driving unit 10 can also input the second clock signal CKn+1 of the next-level gate driving unit 10.

[0115] Example 5

[0116] In an alternative embodiment, such as Figure 12 As shown, the gate drive unit 10 also includes a frame pre-clear module 16. The frame pre-clear module 16 is connected to the first pull-up control node GPU. The frame pre-clear module 16 is used to output a reset signal according to the reset control signal RST to reset and clear the first pull-up control node GPU.

[0117] In this embodiment, after scanning the current frame and before scanning the next frame, the gate drive unit 10 can also receive the corresponding reset control signal RST. At this time, the frame pre-clear module 16 is turned on and outputs a reset signal to reset and clear the first pull-up control node GPU.

[0118] The pre-frame clearing module 16 may employ a corresponding thin-film transistor, as in an optional embodiment, such as... Figure 13 As shown, the frame pre-clear module 16 includes a fourteenth thin-film transistor T14. The first terminal of the fourteenth thin-film transistor T14 is connected to the first pull-up control node GPU. The second terminal of the fourteenth thin-film transistor T14 is used to input the line close signal VGL. The control terminal of the fourteenth thin-film transistor T14 is used to input the reset control signal RST.

[0119] In this embodiment, after scanning the current frame and before scanning the next frame, the reset control signal RST controls the fourteenth thin-film transistor T14 to turn on. At this time, the first pull-up control node GPU discharges through the fourteenth thin-film transistor T14 and resets and clears the charge of the first pull-up control node GPU.

[0120] Example 6

[0121] The present invention also proposes a display panel, such as Figure 1 As shown, the display panel includes an array substrate 100 and a driving circuit 121. The specific structure of the driving circuit 121 is as described in the above embodiments. Since this display panel adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here. The driving circuit 121 is disposed on one side or both sides of the array substrate 100.

[0122] The driving circuit 121 is disposed in the non-display area 120 of the array substrate 100. The array substrate 100 also includes a display area 110, which is provided with an array of pixel units 111. The driving circuit 121 includes multiple cascaded driving units 122, each driving unit 122 being connected to a row of pixel units 111. Each driving unit 122 includes a light-emitting driving unit 20 and a gate driving unit 10. The light-emitting driving units 20 of each driving unit 122 are cascaded sequentially, and the gate driving units 10 of each driving unit 122 are cascaded sequentially. Meanwhile, as... Figure 2 As shown, the gate driving unit 10 and the light-emitting driving unit 20 of each stage driving unit 122 are respectively connected to the pixel unit 111 of the corresponding row.

[0123] The gate driving unit 10 is used to output at least the data write control signal of the current stage to the pixel unit 111 during line scanning. The light emission driving unit 20 is used to output the light emission signal En of the current stage to the pixel unit 111. The pixel unit 111 is composed of multiple thin film transistors and light emission diodes (OLEDs). The multiple thin film transistors include at least a data write transistor, a driving transistor, and a light emission transistor, and may also include a corresponding reset transistor.

[0124] Example 7

[0125] The present invention also proposes a display device, such as Figure 1 As shown, the display device includes a drive control board 200 and a display panel. The specific structure of the display panel is as described in the above embodiments. Since this display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here. The display panel and the drive control board 200 are connected.

[0126] In this embodiment, the drive control board 200 can be bonded to the array substrate 100. The drive control board 200 is connected to the drive circuit 121 and the data line of the array substrate 100. On the one hand, the drive control board 200 outputs corresponding control signals to the drive circuit 121. The control signals can be row enable signal VGH, row disable signal VGL, corresponding clock signal, start signal, etc. On the other hand, it outputs data signal Data to the data line and each column of pixel units 111 connected to the data line, and controls the drive circuit 121 to output corresponding drive signals to the pixel units 111 and output its own data signal Data to the pixel units 111, thereby driving the pixel units 111 on the array substrate 100 to display corresponding image information.

[0127] The drive control board 200 includes a corresponding circuit board and a drive control unit. The drive control unit may include a source drive circuit for outputting data signal Data and a timing controller for outputting control signal, and the specific structure is not limited.

[0128] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A driving circuit, characterized in that, It includes multiple cascaded driving units, each of which is connected to a row of pixel units, and the driving unit includes a gate driving unit and a light-emitting driving unit; The output terminal of the light-emitting driving unit is used to output a light-emitting signal; The gate driving unit includes a first pull-up control module, a first pull-up module, a first pull-down module, a first pull-up control node, and a first pull-down control node; The first pull-up control module, the first pull-up module, and the first pull-up control node are connected; the first pull-down module, the first pull-down control node, and the output terminal of the light-emitting driving unit are connected; the first pull-up module and the first pull-down module control the output of the line scanning signal. The light-emitting driving unit includes a second pull-up control module, a pull-down control module, a second pull-up module, a second pull-down module, a second pull-up control node, and a second pull-down control node; The second pull-up control module includes a first thin-film transistor. The first terminal of the first thin-film transistor is used to input a first start signal or the light emission signal of the previous stage light-emitting driving unit. The control terminal of the first thin-film transistor is used to input the first clock signal of this stage. The second terminal of the first thin-film transistor, the second pull-up control node, and the second pull-up module are connected. The pull-down control module includes a first capacitor, a second thin-film transistor, and a third thin-film transistor; The first terminal of the first capacitor, the first terminal of the second thin-film transistor, and the control terminal of the first thin-film transistor are connected. The second terminal of the first capacitor and the control terminal of the second thin-film transistor are connected. The second terminal of the second thin-film transistor, the first terminal of the third thin-film transistor, the second pull-down control node, and the second pull-down module are connected. The second terminal of the third thin-film transistor is used to input a row turn-off signal. The control terminal of the third thin-film transistor is connected to the second pull-up control node.

2. The driving circuit as described in claim 1, characterized in that, The second pull-up control module and the second pull-up module are connected to the second pull-up control node, and the pull-down control module, the second pull-down module and the second pull-down control node are connected. The second pull-up module and the second pull-down module control the output of the light emission signal.

3. The driving circuit as described in claim 2, characterized in that, The second pull-up module includes a fourth thin-film transistor and a second capacitor. The control terminal of the fourth thin-film transistor, the first terminal of the second capacitor, and the second pull-up control node are connected. The first terminal of the fourth thin-film transistor is used to input a row enable signal. The second terminal of the fourth thin-film transistor, the second terminal of the second capacitor, and the output terminal of the second pull-up module are connected to form the output terminal of the light-emitting driving unit. The second pull-down module includes a third capacitor, a fifth thin-film transistor, and a sixth thin-film transistor. The first terminal of the third capacitor, the control terminal of the fifth thin-film transistor, the control terminal of the sixth thin-film transistor, and the second pull-down control node are connected. The second terminal of the third capacitor and the second terminal of the sixth thin-film transistor are connected and used to input a row turn-off signal. The second terminal of the fifth thin-film transistor and the first terminal of the sixth thin-film transistor are connected. The first terminal of the fifth thin-film transistor is connected to the output terminal of the second pull-up module.

4. The driving circuit as described in claim 3, characterized in that, The first pull-up module includes a seventh thin-film transistor. The first terminal of the seventh thin-film transistor is used to input the second clock signal of this stage. The control terminal of the seventh thin-film transistor is connected to the first pull-up control node. The second terminal of the seventh thin-film transistor and the output terminal of the first pull-down module are connected to form the output terminal of the gate driving unit. The first pull-down module includes an eighth thin-film transistor. The second terminal of the eighth thin-film transistor is used to input a row turn-off signal. The control terminal of the eighth thin-film transistor, the output terminal of the light-emitting driving unit, and the first pull-down control node are connected. The first terminal of the eighth thin-film transistor is connected to the output terminal of the first pull-up module. The first pull-up control module includes a fourth capacitor and a ninth thin-film transistor. The fourth capacitor is connected between the control terminal and the second terminal of the seventh thin-film transistor. The first terminal of the ninth thin-film transistor is connected to the first pull-up control node. The second terminal of the ninth thin-film transistor is used to input a row turn-off signal. The control terminal of the ninth thin-film transistor is connected to the first pull-down control node.

5. The driving circuit as described in claim 3, characterized in that, The light-emitting driving unit further includes a first-level trigger module, which is connected to the pull-down control module. The first-level trigger module is used to output a row-off signal according to a first start signal or the light-emitting signal of the previous-level light-emitting driving unit, so as to control the pull-down control module to output a pull-down control signal to the second pull-down module. The gate driving unit further includes a second-stage trigger module, which is connected to the first pull-up control module. The second-stage trigger module is used to output a row enable signal according to a second start signal or a row scan signal output by the gate driving unit of the previous stage, so as to control the first pull-up control module to output a pull-up control signal to the first pull-up module.

6. The driving circuit as described in claim 5, characterized in that, The first-stage trigger module includes a tenth thin-film transistor. The second terminal of the tenth thin-film transistor is used to input a row turn-off signal, and the control terminal of the tenth thin-film transistor is used to input a first start signal or the light emission signal of the previous stage light-emitting driving unit. The first terminal of the tenth thin-film transistor, the second terminal of the first capacitor, and the control terminal of the second thin-film transistor are connected. The second-stage trigger module includes an eleventh thin-film transistor. The control terminal of the eleventh thin-film transistor is used to input a second start signal or a row scan signal output by the gate driving unit of the previous stage. The first terminal of the eleventh thin-film transistor is used to input a row enable signal. The second terminal of the eleventh thin-film transistor is connected to the first pull-up control node.

7. The driving circuit according to any one of claims 3 to 6, characterized in that, The light-emitting driving unit further includes a first-stage reset transmission module, which is connected to the second pull-up control node. The first-stage reset transmission module is used to output a reset signal according to the light-emitting signal of the next-stage light-emitting driving unit to reset and clear the second pull-up control node. The gate driving unit further includes a second-stage reset transmission module, which is connected to the first pull-up control node. The second-stage reset transmission module is used to output a reset signal according to the row scan signal of the next-stage gate driving unit to reset and clear the first pull-up control node.

8. The driving circuit according to any one of claims 1 to 6, characterized in that, The gate driving unit further includes a frame pre-clear module, which is connected to the first pull-up control node. The frame pre-clear module is used to output a reset signal according to the reset control signal to reset and clear the first pull-up control node.

9. A display panel, characterized in that, It includes an array substrate and a driving circuit as described in any one of claims 1-8, wherein the driving circuit is disposed on one side or both sides of the array substrate.

10. A display device, characterized in that, It includes a drive control board and a display panel as described in claim 9, wherein the display panel and the drive control board are connected.

Images