Frequency jittering method, frequency jittering circuit and energy storage equipment

Abstract

The invention discloses a frequency jittering method, a frequency jittering circuit and energy storage equipment. The method comprises the steps that a digital signal processor obtains an initial driving signal used for driving a first driving circuit and obtains the maximum magnetic flux density of a first transformer of a first power supply circuit; obtaining a first frequency of the initial driving signal, and obtaining a jitter frequency based on the maximum magnetic flux density and the first frequency; and obtaining a jitter period of the jitter frequency circuit, and performing jitter frequency processing on the jitter frequency, the jitter period and the first frequency to obtain a first driving signal, so that the first driving circuit drives the first power supply circuit to output a first voltage based on the first driving signal. By means of the mode, periodic frequency jittering can be conducted on the frequency of the first driving signal, the EMC effect of the frequency jittering circuit is improved, electronic components do not need to be additionally arranged, and the cost of the frequency jittering circuit is reduced.

Description

Technical Field

[0001] This application relates to the field of frequency dithering technology, and in particular to a frequency dithering method, frequency dithering circuit, and energy storage device. Background Technology

[0002] As market demands vary, energy storage devices are becoming increasingly powerful and feature-rich. For example, energy storage devices include energy storage circuits, inverter circuits, boost circuits, and can also be connected to photovoltaic circuits.

[0003] In the prior art, both the inverter circuit and the boost circuit require independent drive power supply circuits for power supply. Each drive power supply circuit includes a drive transformer, thus requiring multiple drive transformers, which leads to an increase in the size of the energy storage device in the prior art.

[0004] To reduce the size of energy storage devices, existing technologies increase the switching frequency of the drive power circuit, resulting in poor EMC (Electromagnetic Compatibility) performance of the energy storage devices. Summary of the Invention

[0005] In view of the above problems, this application provides a frequency dithering method, frequency dithering circuit and energy storage device, which improves EMC performance by dithering the dithering frequency, dithering period and first frequency.

[0006] In a first aspect, this application provides a frequency dithering method applied to a frequency dithering circuit, the frequency dithering circuit including a digital signal processor, a first driving circuit, and a first power supply circuit, the digital signal processor being electrically connected to the first power supply circuit through the first driving circuit, the method comprising:

[0007] The digital signal processor acquires an initial drive signal for driving the first drive circuit, and acquires the maximum magnetic flux density of the first transformer of the first power supply circuit.

[0008] Obtain the first frequency of the initial drive signal, and obtain the jitter frequency based on the maximum magnetic flux density and the first frequency;

[0009] The dithering period of the dithering circuit is obtained, and the dithering frequency, the dithering period, and the first frequency are dithered to obtain a first driving signal, so that the first driving circuit drives the first power supply circuit to output a first voltage based on the first driving signal.

[0010] In some embodiments, obtaining the jitter frequency based on the maximum magnetic flux density and the first frequency includes:

[0011] The digital signal processor acquires the input voltage, duty cycle, and effective core cross-sectional area of ​​the first transformer, and obtains the operating frequency of the first transformer based on the input voltage, the duty cycle, the effective core cross-sectional area, and the maximum magnetic flux density.

[0012] The jitter frequency is obtained by calculating the absolute value of the difference between the first frequency and the operating frequency.

[0013] In some embodiments, the step of performing frequency dithering processing on the dithering frequency, the dithering period, and the first frequency to obtain the first driving signal includes:

[0014] The digital signal processor obtains a jitter frequency range based on the jitter frequency and the first frequency, wherein the maximum frequency in the jitter frequency range is equal to the sum of the first frequency and the jitter frequency, and the minimum frequency in the jitter frequency range is equal to the difference between the first frequency and the jitter frequency.

[0015] According to the jitter period, the first frequency is periodically updated to a frequency value within the jitter frequency range to obtain the first driving signal.

[0016] In some embodiments, periodically updating the first frequency to a frequency value within the jitter frequency range includes:

[0017] Within each jitter cycle, the jitter cycle includes a first jitter period, a second jitter period, a third jitter period, and a fourth jitter period, which are sequentially set; and,

[0018] During the first jitter period, the digital signal processor updates the first frequency to the maximum frequency in the jitter frequency range within a first preset duration.

[0019] During the second jitter period, the digital signal processor updates the maximum frequency in the jitter frequency range to the first frequency within a second preset duration;

[0020] During the third jitter period, the digital signal processor updates the first frequency to the minimum frequency in the jitter frequency range within a preset duration of the third year.

[0021] During the fourth jitter period, the digital signal processor updates the minimum frequency in the jitter frequency range to the first frequency within a fourth preset duration.

[0022] In some embodiments, the ratio of the first preset duration to the duration of the first jitter period is between 1 / 10 and 1 / 5; and / or, the ratio of the second preset duration to the duration of the second jitter period is between 1 / 10 and 1 / 5; and / or, the ratio of the third preset duration to the duration of the third jitter period is between 1 / 10 and 1 / 5; and / or, the ratio of the fourth preset duration to the duration of the fourth jitter period is between 1 / 10 and 1 / 5.

[0023] In some embodiments, the frequency dithering circuit further includes an inverter circuit, wherein the digital signal processor and the first power supply circuit are electrically connected to the inverter circuit, and the first power supply circuit provides the first voltage to the inverter circuit; after the step of performing frequency dithering processing on the dithering frequency, the dithering period, and the first frequency to obtain the first driving signal, the method further includes:

[0024] The digital signal processor generates a first control signal, and controls the inverter circuit to operate based on the first control signal.

[0025] In some embodiments, the frequency dithering circuit further includes a second driving circuit and a second power supply circuit, wherein the digital signal processor is electrically connected to the second power supply circuit through the second driving circuit, and the method further includes:

[0026] The digital signal processor generates a second driving signal based on the first driving signal, so that the second driving circuit drives the second power supply circuit to output a second voltage based on the second driving signal;

[0027] The second driving signal and the first driving signal are complementary waveforms.

[0028] In some embodiments, the frequency dithering circuit further includes a boost circuit or a buck circuit, the digital signal processor and the second power supply circuit are electrically connected to the boost circuit or the buck circuit respectively, and the second power supply circuit provides the second voltage to the boost circuit or the buck circuit; after the step of the digital signal processor generating a second driving signal based on the first driving signal, the method further includes:

[0029] The digital signal processor generates a second control signal, and controls the operation of the boost circuit or the buck circuit based on the second control signal.

[0030] Secondly, this application provides a frequency dithering circuit, including a digital signal processor, a first driving circuit, and a first power supply circuit, wherein the digital signal processor is electrically connected to the first power supply circuit through the first driving circuit; the digital signal processor is used for:

[0031] Obtain the initial drive signal used to drive the first drive circuit, and obtain the maximum magnetic flux density of the first transformer of the first power supply circuit;

[0032] Obtain the first frequency of the initial drive signal, and obtain the jitter frequency based on the maximum magnetic flux density and the first frequency;

[0033] The dithering period of the dithering circuit is obtained, and the dithering frequency, the dithering period, and the first frequency are dithered to obtain a first driving signal, so that the first driving circuit drives the first power supply circuit to output a first voltage based on the first driving signal.

[0034] Thirdly, this application provides a frequency dithering circuit, including the frequency dithering circuit described above.

[0035] Unlike existing technologies, the digital signal processor of this application obtains the jitter frequency based on the maximum magnetic flux density and the first frequency; it acquires the jitter period of the jitter circuit, and performs jitter processing on the jitter frequency, the jitter period, and the first frequency to obtain a first driving signal, so that the first driving circuit drives the first power supply circuit to output a first voltage based on the first driving signal. By performing jitter processing on the jitter frequency, the jitter period, and the first frequency to obtain the first driving signal, the frequency of the first driving signal is periodically jittered, improving the EMC performance of the jitter circuit, eliminating the need for additional electronic components, and reducing the cost of the jitter circuit. Attached Figure Description

[0036] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiments below. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0037] Figure 1 This is a schematic diagram of the frame of the first embodiment of the frequency dithering circuit of this application;

[0038] Figure 2 yes Figure 1 A flowchart illustrating the first embodiment of the frequency dithering method in the intermediate frequency dithering circuit;

[0039] Figure 3 yes Figure 2 A flowchart illustrating the first embodiment of step S102;

[0040] Figure 4 yes Figure 2 A flowchart illustrating the first embodiment of step S103;

[0041] Figure 5 yes Figure 4 A schematic diagram of the first embodiment of performing periodic jitter frequency in step S302;

[0042] Figure 6 yes Figure 5 A waveform diagram of the first embodiment of the first driving signal;

[0043] Figure 7 This is a circuit diagram of the second embodiment of the frequency dithering circuit of this application;

[0044] Figure 8 yes Figure 7 A flowchart illustrating the second embodiment of the frequency dithering method in the mid-frequency dithering circuit;

[0045] Figure 9 yes Figure 7 A flowchart illustrating the third embodiment of the frequency dithering method for the intermediate frequency dithering circuit;

[0046] Figure 10 yes Figure 7 The simulation diagram shows that the frequency dithering circuit in the diagram does not perform frequency dithering according to the frequency dithering method.

[0047] Figure 11 yes Figure 7 The simulation diagram of the frequency dithering circuit performing frequency dithering according to the frequency dithering method is shown in the figure. Detailed Implementation

[0048] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0050] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0051] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0052] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0053] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple groups" refers to two or more (including two groups), and "multiple pieces" refers to two or more (including two pieces).

[0054] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0055] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0056] This application provides a frequency dithering method. Please refer to [link / reference]. Figures 1-2 As shown, Figure 1 This is a schematic diagram of the frame of the first embodiment of the frequency dithering circuit of this application; Figure 2 yes Figure 1A flowchart illustrating the first embodiment of the dithering method in the dithering circuit. The dithering circuit 10 in this embodiment includes a digital signal processor (DSP) 11, a first driving circuit 12, and a first power supply circuit 13. The DSP 11 is electrically connected to the first power supply circuit 13 through the first driving circuit 12.

[0057] Optionally, the frequency dithering circuit 10 also includes a switch power supply (SPS) 18, which is electrically connected to the digital signal processor 11 and the first drive circuit 12 respectively, and is used to supply power to the digital signal processor 11 and the first drive circuit 12 respectively.

[0058] The frequency dithering method in this embodiment includes the following steps:

[0059] S101: The digital signal processor 11 acquires the initial drive signal for driving the first drive circuit 12, and acquires the maximum magnetic flux density Bmax of the first transformer of the first power supply circuit 13.

[0060] The digital signal processor 11 generates an initial drive signal for driving the first drive circuit 12, and then the digital signal processor 11 acquires the initial drive signal.

[0061] The digital signal processor 11 acquires the maximum magnetic flux density Bmax of the first transformer in the first power supply circuit 13; wherein the first power supply circuit 13 includes a first transformer, and the digital signal processor 11 acquires the maximum magnetic flux density Bmax of the first transformer in the first power supply circuit 13. For example, the maximum magnetic flux density Bmax of the first transformer refers to the maximum value of the magnetic flux density of the iron core of the first transformer, and the magnetic flux density of the iron core of the first transformer refers to the number of magnetic field lines perpendicularly passing through a unit area of ​​the iron core of the first transformer.

[0062] S102: Obtain the first frequency f1 of the initial drive signal, and obtain the jitter frequency f based on the maximum magnetic flux density and the first frequency f1.

[0063] The digital signal processor 11 acquires the first frequency f1 of the initial drive signal and obtains the jitter frequency f based on the maximum magnetic flux density and the first frequency f1. The first frequency f1 of the initial drive signal is a fixed frequency, for example, 200 kHz.

[0064] S103: Obtain the jitter period T of the jitter circuit 10, and perform jitter processing on the jitter frequency f, jitter period T and first frequency f1 to obtain the first drive signal PWM1, so that the first drive circuit 12 drives the first power supply circuit 13 to output the first voltage V1 based on the first drive signal PWM1.

[0065] The digital signal processor 11 obtains the jitter period T of the frequency dithering circuit 10; for example, the frequency dithering circuit 10 is connected to the mains power (industrial frequency AC power), and the jitter period T of the frequency dithering circuit 10 can be set to 1 / 25 to 2 / 5 of the mains power period, such as the jitter period T of the frequency dithering circuit 10 being 2 / 5 of the mains power period.

[0066] The digital signal processor 11 performs frequency dithering processing on the dithering frequency f, the dithering period T, and the first frequency f1 to obtain the first driving signal PWM1; that is, the digital signal processor 11 periodically updates the frequency of the first driving signal PWM1 according to the dithering period T. The frequency of the first driving signal PWM1 is between the difference between the first frequency f1 and the dithering frequency f, and between the sum of the first frequency f1 and the dithering frequency f.

[0067] For example, the frequency of the first driving signal PWM1 is the first frequency f1; or, the frequency of the first driving signal PWM1 is the difference between the first frequency f1 and the jitter frequency f; or, the frequency of the first driving signal PWM1 is the sum of the first frequency f1 and the jitter frequency f, so as to realize the frequency of the first driving signal PWM1 is periodically jittered.

[0068] The first driving circuit 12 drives the first power supply circuit 13 to output a first voltage V1 based on the first driving signal PWM1. Specifically, the first driving circuit 12 receives the first driving signal PWM1 from the digital signal processor 11, and drives the first power supply circuit 13 to output the first voltage V1 based on the first driving signal PWM1.

[0069] For example, the first drive circuit 12 includes at least one switch, which is turned on or off based on the first drive signal PWM1 to drive the first power supply circuit 13 to output a first voltage V1.

[0070] In other embodiments, the digital signal processor 11 performs frequency dithering processing on the dithering frequency f, the dithering period T, and the first frequency f1, or the digital signal processor 11 performs spread spectrum processing on the dithering frequency f, the dithering period T, and the first frequency f1.

[0071] In this embodiment, the digital signal processor 11 performs frequency dithering processing on the dithering frequency f, the dithering period T, and the first frequency f1 to obtain a first driving signal PWM1, so that the first driving circuit 12 drives the first power supply circuit 13 to output a first voltage V1 based on the first driving signal PWM1. By performing frequency dithering processing on the dithering frequency f, the dithering period T, and the first frequency f1 to obtain the first driving signal PWM1, the frequency of the first driving signal PWM1 is periodically dithered, improving the EMC performance of the frequency dithering circuit 10, without the need for additional electronic components, thus reducing the cost of the frequency dithering circuit 10.

[0072] According to some embodiments of this application, please refer to Figure 3 As shown, Figure 3 yes Figure 2 A flowchart illustrating the first embodiment of step S102. Step S102 in this embodiment includes the following steps:

[0073] S201: The digital signal processor 11 obtains the input voltage V, duty cycle D, and effective core cross-sectional area Ae of the first transformer, and obtains the operating frequency f2 of the first transformer based on the input voltage V, duty cycle D, effective core cross-sectional area Ae, and maximum magnetic flux density Bmax.

[0074] The digital signal processor 11 acquires the input voltage V, duty cycle D, and effective core cross-sectional area Ae of the first transformer; the digital signal processor 11 obtains the operating frequency f2 of the first transformer based on the input voltage V, duty cycle D, effective core cross-sectional area Ae, and maximum magnetic flux density Bmax.

[0075] Specifically, step S201 further includes the digital signal processor 11 dividing the product of the input voltage V and the duty cycle D by the product of the effective core cross-sectional area Ae and the maximum magnetic flux density Bmax to obtain the operating frequency f2. Therefore, the operating frequency f2 of the first transformer satisfies the following formula:

[0076] f2=(V*D) / (A2*Bmax) (1)

[0077] The digital signal processor 11 calculates the operating frequency f2 of the first transformer based on formula (1).

[0078] S202: Calculate the absolute value of the difference between the first frequency f1 and the operating frequency f2 to obtain the jitter frequency f.

[0079] The digital signal processor 11 calculates the absolute value of the difference between the first frequency f1 and the operating frequency f2 to obtain the jitter frequency f; therefore, the digital signal processor 11 obtains the jitter frequency f as |f1-f2|.

[0080] In this embodiment, the digital signal processor 11 obtains the operating frequency f2 of the first transformer based on the input voltage V, duty cycle D, effective core cross-sectional area Ae, and maximum magnetic flux density Bmax, and calculates the absolute value of the difference between the first frequency f1 and the operating frequency f2 to obtain the jitter frequency f. By calculating the operating frequency f2 using the input voltage V, duty cycle D, effective core cross-sectional area Ae, and maximum magnetic flux density Bmax, the accuracy of the operating frequency f2 is improved, thus improving the jitter accuracy of the frequency jitter circuit 10.

[0081] According to some embodiments of this application, please refer to Figure 4 As shown, Figure 4 yes Figure 2A flowchart illustrating the first embodiment of step S103. Step S103 in this embodiment includes the following steps:

[0082] S301: The digital signal processor 11 obtains a jitter frequency range based on the jitter frequency f and the first frequency f1. The maximum frequency in the jitter frequency range is equal to the sum of the first frequency f1 and the jitter frequency f, and the minimum frequency in the jitter frequency range is equal to the difference between the first frequency f1 and the jitter frequency f.

[0083] The digital signal processor 11 obtains a jitter frequency range based on the jitter frequency f and the first frequency f1; wherein, the digital signal processor 11 takes the sum of the first frequency f1 and the jitter frequency f as the maximum frequency in the jitter frequency range, and takes the difference between the first frequency f1 and the jitter frequency f as the minimum frequency in the jitter frequency range, that is, the jitter frequency range obtained by the digital signal processor 11 based on the jitter frequency f and the first frequency f1 is f1-|f1-f2| to f1+|f1-f2|.

[0084] S302: According to the jitter period T, the first frequency f1 is periodically updated to a frequency value in the jitter frequency range to obtain the first drive signal PWM1.

[0085] Since the digital signal processor 11 generates an initial drive signal for driving the first drive circuit 12, and the frequency of the initial drive signal is a first frequency f1; therefore, after the digital signal processor 11 obtains the jitter frequency range, the digital signal processor 11 updates the first frequency f1 to a frequency value within the jitter frequency range according to the jitter period T. For example, the digital signal processor 11 updates the first frequency f1 to f1-|f1-f2| within the jitter period T, or the digital signal processor 11 updates the first frequency f1 to f1+|f1-f2| within the jitter period T, or the frequency of the first drive signal PWM1 is the first frequency f1 within the jitter period T.

[0086] In this embodiment, the digital signal processor 11 obtains a jitter frequency range based on the jitter frequency f and the first frequency f1. The digital signal processor 11 periodically updates the first frequency f1 to a frequency value within the jitter frequency range to obtain the first drive signal PWM1. This achieves periodic frequency jittering of the first drive signal PWM1, improving the EMC performance of the frequency jittering circuit 10 without the need for additional electronic components, thus reducing the cost of the frequency jittering circuit.

[0087] According to some embodiments of this application, please refer to Figures 5-6 As shown, Figure 5 yes Figure 4 A schematic diagram of the first embodiment of performing periodic jitter frequency in step S302; Figure 6 yes Figure 5A waveform diagram of the first embodiment of the first driving signal. Step S302 of this embodiment includes:

[0088] Within each jitter cycle T, the jitter cycle T includes a first jitter period T1, a second jitter period T2, a third jitter period T3, and a fourth jitter period T4, set sequentially; and,

[0089] During the first jitter period T1, the digital signal processor 11 updates the first frequency f1 to the maximum frequency f1+|f1-f2| in the jitter frequency range within the first preset duration T5.

[0090] During the second jitter period T2, the digital signal processor 11 updates the maximum frequency f1+|f1-f2| in the jitter frequency range to the first frequency f1 within the second preset duration T6.

[0091] During the third jitter period T3, the digital signal processor 11 updates the first frequency to the minimum frequency f1-|f1-f2| in the jitter frequency range within the third preset duration T7.

[0092] During the fourth jitter period T4, the digital signal processor 11 updates the minimum frequency f1-|f1-f2| in the jitter frequency range to the first frequency f1 within the fourth preset duration T8.

[0093] During the next jitter period T, the digital signal processor 11 repeatedly executes the actions corresponding to the first jitter period T1, the second jitter period T2, the third jitter period T3, and the fourth jitter period T4 in sequence to periodically update the first frequency f1 to a frequency value within the jitter frequency range.

[0094] The duration of the jitter period T is equal to the sum of the durations of the first jitter period T1, the second jitter period T2, the third jitter period T3, and the fourth jitter period T4.

[0095] Optionally, the durations of the first jitter period T1, the second jitter period T2, the third jitter period T3, and the fourth jitter period T4 are equal, with the duration of the first jitter period T1 being 1 / 10 of the mains cycle duration. The durations of the first jitter period T1, the second jitter period T2, the third jitter period T3, and the fourth jitter period T4 can be selected with different values ​​according to the actual situation.

[0096] Taking the frequency of the initial drive signal as the first frequency f1, and the frequency of the first drive signal PWM1 obtained by the digital signal processor 11 as the first frequency f1, during the first jitter period T1, the digital signal processor 11 updates the first frequency f1 to the maximum frequency f1+|f1-f2| in the jitter frequency range within the first preset duration T5. That is, the digital signal processor 11 abruptly changes the frequency of the first drive signal PWM1 from the first frequency f1 to the maximum frequency f1+|f1-f2| in the jitter frequency range within the first preset duration T5. After the abrupt change, the frequency of the first drive signal PWM1 is f1+|f1-f2|.

[0097] During the second jitter period T2, the digital signal processor 11 updates the maximum frequency f1+|f1-f2| in the jitter frequency range to the first frequency f1 within the second preset duration T6. That is, the digital signal processor 11 abruptly changes the maximum frequency f1+|f1-f2| in the jitter frequency range to the first frequency f1 within the second preset duration T6. After the abrupt change, the frequency of the first drive signal PWM1 is f1.

[0098] During the third jitter period T3, the digital signal processor 11 updates the first frequency f1 to the minimum frequency f1-|f1-f2| in the jitter frequency range within the third preset duration T7. That is, the digital signal processor 11 abruptly changes the first frequency f1 to the minimum frequency f1-|f1-f2| in the jitter frequency range within the third preset duration T7. After the abrupt change, the frequency of the first drive signal PWM1 is f1-|f1-f2|.

[0099] During the fourth jitter period T4, the digital signal processor 11 updates the minimum frequency f1-|f1-f2| in the jitter frequency range to the first frequency f1 within the fourth preset duration T8. That is, the digital signal processor 11 abruptly changes the minimum frequency f1-|f1-f2| in the jitter frequency range to the first frequency f1 within the fourth preset duration T8. After the abrupt change, the frequency of the first drive signal PWM1 is f1. Therefore, the frequency of the first drive signal PWM1 is f1 during the fourth jitter cycle T, thereby periodically updating the first frequency f1 to the frequency value within the jitter frequency range; achieving periodic frequency jittering of the first drive signal PWM1, and improving the EMC performance of the frequency jittering circuit 10.

[0100] In other embodiments of this application, during the first jitter period T1, the digital signal processor 11 updates the first frequency f1 to the minimum frequency f1-|f1-f2| in the jitter frequency range within a first preset duration T5; during the second jitter period T2, the digital signal processor 11 updates the minimum frequency f1-|f1-f2| in the jitter frequency range to the first frequency f1 within a second preset duration T6; during the third jitter period T3, the digital signal processor 11 updates the first frequency f1 to the maximum frequency f1+|f1-f2| in the jitter frequency range within a third preset duration T7; and during the fourth jitter period T4, the digital signal processor 11 updates the maximum frequency f1+|f1-f2| in the jitter frequency range to the first frequency f1 within a fourth preset duration T8.

[0101] Optionally, the ratio of the first preset duration T5 to the duration of the first jitter period T1 is between 1 / 10 and 1 / 5; and / or, the ratio of the second preset duration T6 to the duration of the second jitter period T2 is between 1 / 10 and 1 / 5; and / or, the ratio of the third preset duration T7 to the duration of the third jitter period T3 is between 1 / 10 and 1 / 5; and / or, the ratio of the fourth preset duration T8 to the duration of the fourth jitter period T4 is between 1 / 10 and 1 / 5.

[0102] Optionally, the first preset duration T5, the second preset duration T6, the third preset duration T7, and the fourth preset duration T8 are equal. In other embodiments, at least one or two of the first preset duration T5, the second preset duration T6, the third preset duration T7, and the fourth preset duration T8 are not equal.

[0103] For example, the first preset duration T5 is 1 / 10 of the duration of the first jitter period T1, the second preset duration T6 is 1 / 10 of the duration of the second jitter period T2, the third preset duration T7 is 1 / 10 of the duration of the third jitter period T3, and the fourth preset duration T8 is 1 / 10 of the duration of the fourth jitter period T4.

[0104] In this embodiment, the ratio of the first preset duration T5 to the duration of the first jitter period T1 is between 1 / 10 and 1 / 5, and / or the ratio of the second preset duration T6 to the duration of the second jitter period T2 is between 1 / 10 and 1 / 5, and / or the ratio of the third preset duration T7 to the duration of the third jitter period T3 is between 1 / 10 and 1 / 5, and / or the ratio of the fourth preset duration T8 to the duration of the fourth jitter period T4 is between 1 / 10 and 1 / 5. As a result, the frequency of the first drive signal PWM1 can be jittered quickly, improving the EMC effect of the jitter circuit 10.

[0105] Please see Figures 7-8 As shown, Figure 7 This is a circuit diagram of the second embodiment of the frequency dithering circuit of this application; Figure 8yes Figure 7 A flowchart illustrating a second embodiment of the frequency dithering method in the frequency dithering circuit. The frequency dithering circuit 10 in this embodiment further includes an inverter circuit 14, with the digital signal processor 11 and the first power supply circuit 13 electrically connected to the inverter circuit 14.

[0106] The frequency dithering method in this embodiment includes the following steps:

[0107] S401: The digital signal processor 11 acquires the initial drive signal for driving the first drive circuit 12, and acquires the maximum magnetic flux density Bmax of the first transformer of the first power supply circuit 13.

[0108] S402: Obtain the first frequency f1 of the initial drive signal, and obtain the jitter frequency f based on the maximum magnetic flux density and the first frequency f1.

[0109] S403: Obtain the jitter period T of the jitter circuit 10, and perform jitter processing on the jitter frequency f, jitter period T and first frequency f1 to obtain the first drive signal PWM1, so that the first drive circuit 12 drives the first power supply circuit 13 to output the first voltage V1 based on the first drive signal PWM1.

[0110] Steps S401-S403 are the same as steps S101-S103 in the above embodiment, and will not be described again here. In step S403, the first power supply circuit 13 provides a first voltage V1 to the inverter circuit 14. That is, the digital signal processor 11 controls the first drive circuit 12 through the first drive signal PWM1, so that the first power supply circuit 13 outputs the first voltage V1, thereby providing the first voltage V1 to the inverter circuit 14 to supply power to the inverter circuit 14.

[0111] S404: Digital signal processor 11 generates a first control signal PWM3, and controls the inverter circuit 14 to work based on the first control signal PWM3.

[0112] The digital signal processor 11 further generates a first control signal PWM3, and controls the operation of the inverter circuit 14 based on the first control signal PWM3. Optionally, the frequency of the first control signal PWM3 is a fixed frequency. For example, the digital signal processor 11 controls the switch of the inverter circuit 14 to close or open through the first control signal PWM3.

[0113] In this embodiment, the digital signal processor 11 performs frequency dithering processing on the dithering frequency f, the dithering period T, and the first frequency f1 to obtain the first drive signal PWM1; it then generates a first control signal PWM3, and controls the inverter circuit 14 to operate based on the first control signal PWM3. By performing periodic frequency dithering through the first drive signal PWM1, there is no need to perform frequency dithering processing on the first control signal PWM3 of the inverter circuit 14, thus improving the EMC performance of the inverter circuit 14 and making it easy to implement.

[0114] According to some embodiments of this application, please continue to refer to Figure 7 As shown, the frequency dithering circuit 10 in this embodiment also includes a second driving circuit 15, a second power supply circuit 16, and a boost circuit 17. The digital signal processor 11 is electrically connected to the second power supply circuit 16 through the second driving circuit 15, and the digital signal processor 11 and the second power supply circuit 16 are electrically connected to the boost circuit 17, respectively.

[0115] Optionally, the frequency dithering circuit 10 further includes a switching power supply 18, which is electrically connected to the digital signal processor 11, the first driving circuit 12, and the second driving circuit 15, respectively. The switching power supply 18 is used to supply power to the digital signal processor 11, the first driving circuit 12, and the second driving circuit 15, respectively.

[0116] Please see Figure 9 As shown, Figure 9 yes Figure 7 A flowchart illustrating the third embodiment of the frequency dithering method for the frequency dithering circuit. The frequency dithering method in this embodiment includes the following steps:

[0117] The frequency dithering method in this embodiment includes the following steps:

[0118] S501: The digital signal processor 11 acquires the initial drive signal for driving the first drive circuit 12, and acquires the maximum magnetic flux density Bmax of the first transformer of the first power supply circuit 13.

[0119] S502: Obtain the first frequency f1 of the initial drive signal, and obtain the jitter frequency f based on the maximum magnetic flux density and the first frequency f1.

[0120] S503: Obtain the jitter period T of the jitter circuit 10, and perform jitter processing on the jitter frequency f, jitter period T and first frequency f1 to obtain the first drive signal PWM1, so that the first drive circuit 12 drives the first power supply circuit 13 to output the first voltage V1 based on the first drive signal PWM1.

[0121] S504: The digital signal processor 11 generates a first control signal PWM3, and controls the inverter circuit 14 to work based on the first control signal PWM3.

[0122] Steps S501-S504 are the same as steps S401-S404 in the above embodiment, and will not be repeated here.

[0123] S505: The digital signal processor 11 generates a second drive signal PWM2 based on the first drive signal PWM1, so that the second drive circuit 15 drives the second power supply circuit 16 to output the second voltage V2 based on the second drive signal PWM2.

[0124] Digital signal processor 11 generates a second drive signal PWM2 based on the first drive signal PWM1, wherein the second drive signal PWM2 and the first drive signal PWM1 are complementary waveforms, such as... Figure 6 As shown. Since the second drive signal PWM2 and the first drive signal PWM1 are complementary waveforms, the frequency of the second drive signal PWM2 is the same as the frequency of the first drive signal PWM1.

[0125] After the digital signal processor 11 generates the second drive signal PWM2, the digital signal processor 11 controls the second drive circuit 15 through the second drive signal PWM2, so that the second drive circuit 15 drives the second power supply circuit 16 to output the second voltage V2 based on the second drive signal PWM2; the digital signal processor 11 provides the second voltage V2 to the boost circuit 17 through the second power supply circuit 16 to realize the power supply of the boost circuit 17.

[0126] S506: Digital signal processor 11 generates a second control signal PWM4, and controls the boost circuit 17 to work based on the second control signal PWM4.

[0127] The digital signal processor 11 further generates a second control signal PWM4, which controls the operation of the boost circuit 17. Optionally, the frequency of the second control signal PWM4 is a fixed frequency. For example, the digital signal processor 11 controls the switch of the boost circuit 17 to close or open via the second control signal PWM4.

[0128] In this embodiment, the digital signal processor 11 generates a second driving signal PWM2 based on the first driving signal PWM1; the digital signal processor 11 also generates a second control signal PWM4, and controls the boost circuit 17 to operate based on the second control signal PWM4. Periodic frequency dithering of the first driving signal PWM1 is used to achieve periodic frequency dithering of the second driving signal PWM2, eliminating the need for frequency dithering of the second control signal PWM4, thus improving the EMC performance of the boost circuit 17 and making it easy to implement.

[0129] In other embodiments of this application, the frequency dithering circuit 10 further includes a second driving circuit 15, a second power supply circuit 16, and a step-down circuit (not shown). The digital signal processor 11 is electrically connected to the second power supply circuit 16 through the second driving circuit 15, and the digital signal processor 11 and the second power supply circuit 16 are respectively electrically connected to the step-down circuit. The second power supply circuit 16 provides a second voltage V2 to the step-down circuit; the digital signal processor 11 generates a second control signal PWM4, and controls the operation of the step-down circuit based on the second control signal PWM4.

[0130] In other embodiments of this application, the digital signal processor 11 can periodically dither the second driving signal PWM2 using the dithering method described above, and then generate the first driving signal PWM1 based on the second driving signal PWM2, which will not be elaborated further here.

[0131] It is worth noting that the first driving circuit 12 and the second driving circuit 15 of this application can be driving circuits in the prior art, the first power supply circuit 13 and the second power supply circuit 16 of this application can be power supply circuits in the prior art, the inverter circuit 14 of this application can be an inverter circuit in the prior art, and the boost circuit 17 of this application can be a boost circuit in the prior art, which will not be described in detail here.

[0132] Please see Figures 10-11 As shown, Figure 10 yes Figure 7 The simulation diagram shows that the frequency dithering circuit in the diagram does not perform frequency dithering according to the frequency dithering method. Figure 11 yes Figure 7 The simulation diagram of the frequency dithering circuit in the image shows the frequency dithering process performed according to the frequency dithering method. For example... Figure 7 The frequency dithering circuit 10 shown is not in accordance with... Figure 9 The frequency dithering method shown is used to perform frequency dithering. EMC testing is performed on the frequency dithering circuit 10, and the simulation diagram is as follows. Figure 10 As shown. Figure 7 The frequency dithering circuit 10 shown is configured as follows: Figure 9 The frequency dithering method shown is used to perform frequency dithering. EMC testing is performed on the frequency dithering circuit 10, and the simulation diagram is as follows. Figure 11 As shown.

[0133] in, Figure 10 Curve A1 in the diagram represents the peak value in the EMC test of the frequency dithering circuit 10 without frequency dithering, and curve B1 represents the average value in the EMC test of the frequency dithering circuit 10 without frequency dithering. The peak value in the EMC test refers to the maximum amplitude at a specific point in time under the maximum electromagnetic interference, while the average value in the EMC test refers to the average level of electromagnetic interference over a period of time. Figure 10 The peak value of curve A1 at a frequency of 8.98MHz is 52.43dB. Figure 10The peak value of curve B1 at a frequency of 8.98MHz is 47.91dB.

[0134] Figure 11 Curve A2 in the figure represents the peak value in the EMC test of the frequency dithering circuit 10, and curve B2 represents the average value in the EMC test of the frequency dithering circuit 10. Figure 11 The peak value of curve A2 at a frequency of 8.98MHz is 52dB. Figure 11 The peak value of curve B2 at 8.98MHz is 44.17dB. (Comparison) Figure 10 and Figure 11 It can be concluded that after the frequency dithering circuit 10 of this application performs frequency dithering according to the frequency dithering method of the above embodiment, it can improve the EMC effect of the frequency dithering circuit 10, without the need to add additional electronic components, thus reducing the cost of the frequency dithering circuit 10.

[0135] This application also provides a frequency dithering circuit 10, such as Figure 7 As shown, the frequency dithering circuit 10 in this embodiment includes a digital signal processor 11, a first driving circuit 12, a first power supply circuit 13, an inverter circuit 14, a second driving circuit 15, a second power supply circuit 16, and a boost circuit 17.

[0136] The digital signal processor 11 is electrically connected to the first power supply circuit 13 via the first driving circuit 12, and the digital signal processor 11 and the first power supply circuit 13 are respectively electrically connected to the inverter circuit 14. The digital signal processor 11 is electrically connected to the second power supply circuit 16 via the second driving circuit 15, and the digital signal processor 11 and the second power supply circuit 16 are respectively electrically connected to the boost circuit 17.

[0137] The digital signal processor 11 is configured to: acquire an initial drive signal for driving the first drive circuit 12; acquire the maximum magnetic flux density Bmax of the first transformer of the first power supply circuit 13, and acquire the first frequency f1 of the initial drive signal, and obtain a jitter frequency f based on the maximum magnetic flux density and the first frequency f1; acquire the jitter period T of the jitter circuit 10; perform jitter processing on the jitter frequency f, the jitter period T and the first frequency f1 to obtain a first drive signal PWM1, so that the first drive circuit 12 drives the first power supply circuit 13 to output a first voltage V1 based on the first drive signal PWM1; and generate a second drive signal PWM2 based on the first drive signal PWM1, so that the second drive circuit 15 drives the second power supply circuit 16 to output a second voltage V2 based on the second drive signal PWM2.

[0138] Optionally, the first power supply circuit 13 includes a first transformer 131, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first diode D1, a second diode D2, and a first Zener diode D3. The first input terminal of the first transformer 131 is electrically connected to the first drive circuit 12, and the second input terminal of the first transformer 131 is grounded through the first capacitor C1. One end of the second capacitor C2 is electrically connected to the first output terminal of the first transformer 131, and the other end of the second capacitor C2 is electrically connected to the cathode of the first diode D1 and the anode of the second diode D2, respectively. The second output terminal of the first transformer 131 is electrically connected to the anode of the first diode D1 and one end of the fourth capacitor C4, and the other end of the fourth capacitor C4 is electrically connected to the cathode of the second diode D2 through the third capacitor C3. The anode of the first Zener diode D3 is electrically connected to the other end of the fourth capacitor C4, and the cathode of the first Zener diode D3 is electrically connected to the cathode of the second diode D2. The inverter circuit 14 is electrically connected to the negative terminal of the second diode D2 and the second output terminal of the first transformer 131 to receive the first voltage V1.

[0139] Optionally, the second power supply circuit 16 includes a second transformer 161, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a third diode D4, a fourth diode D5, and a second Zener diode D6. The first input terminal of the second transformer 161 is electrically connected to the first drive circuit 12, and the second input terminal of the second transformer 161 is grounded through the fifth capacitor C5. One end of the sixth capacitor C6 is electrically connected to the first output terminal of the second transformer 161, and the other end of the sixth capacitor C6 is electrically connected to the negative terminal of the third diode D4 and the positive terminal of the fourth diode D5, respectively. The second output terminal of the second transformer 161 is electrically connected to the positive terminal of the third diode D4 and one end of the eighth capacitor C8, and the other end of the eighth capacitor C8 is electrically connected to the negative terminal of the fourth diode D5 through the seventh capacitor C7. The positive terminal of the second Zener diode D6 is electrically connected to the other end of the eighth capacitor C8, and the negative terminal of the second Zener diode D6 is electrically connected to the negative terminal of the fourth diode D5. The boost circuit 17 is electrically connected to the negative terminal of the fourth diode D5 and the second output terminal of the second transformer 161 to receive the second voltage V2.

[0140] This application also provides an energy storage device, which includes the frequency dithering circuit 10 of the above embodiments.

[0141] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A frequency dithering method, characterized in that, The method is applied to a frequency dithering circuit, the frequency dithering circuit including a digital signal processor, a first driving circuit, and a first power supply circuit, the digital signal processor being electrically connected to the first power supply circuit through the first driving circuit, the method comprising: The digital signal processor acquires an initial drive signal for driving the first drive circuit, and acquires the maximum magnetic flux density of the first transformer of the first power supply circuit. Obtain the first frequency of the initial drive signal, and obtain the jitter frequency based on the maximum magnetic flux density and the first frequency; The dithering period of the dithering circuit is obtained, and the dithering frequency, the dithering period, and the first frequency are dithered to obtain a first driving signal, so that the first driving circuit drives the first power supply circuit to output a first voltage based on the first driving signal.

2. The frequency dithering method according to claim 1, characterized in that, The process of obtaining the jitter frequency based on the maximum magnetic flux density and the first frequency includes: The digital signal processor acquires the input voltage, duty cycle, and effective core cross-sectional area of ​​the first transformer, and obtains the operating frequency of the first transformer based on the input voltage, the duty cycle, the effective core cross-sectional area, and the maximum magnetic flux density. The jitter frequency is obtained by calculating the absolute value of the difference between the first frequency and the operating frequency.

3. The frequency dithering method according to claim 2, characterized in that, The step of performing frequency dithering processing on the dithering frequency, the dithering period, and the first frequency to obtain the first driving signal includes: The digital signal processor obtains a jitter frequency range based on the jitter frequency and the first frequency, wherein the maximum frequency in the jitter frequency range is equal to the sum of the first frequency and the jitter frequency, and the minimum frequency in the jitter frequency range is equal to the difference between the first frequency and the jitter frequency. According to the jitter period, the first frequency is periodically updated to a frequency value within the jitter frequency range to obtain the first driving signal.

4. The frequency dithering method according to claim 3, characterized in that, The periodic updating of the first frequency to a frequency value within the jitter frequency range includes: Within each jitter cycle, the jitter cycle includes a first jitter period, a second jitter period, a third jitter period, and a fourth jitter period, which are sequentially set; and, During the first jitter period, the digital signal processor updates the first frequency to the maximum frequency in the jitter frequency range within a first preset duration. During the second jitter period, the digital signal processor updates the maximum frequency in the jitter frequency range to the first frequency within a second preset duration; During the third jitter period, the digital signal processor updates the first frequency to the minimum frequency in the jitter frequency range within a preset duration of the third year. During the fourth jitter period, the digital signal processor updates the minimum frequency in the jitter frequency range to the first frequency within a fourth preset duration.

5. The frequency dithering method according to claim 4, characterized in that, The ratio of the first preset duration to the duration of the first jitter period is between 1 / 10 and 1 / 5; and / or, The ratio of the second preset duration to the duration of the second jitter period is between 1 / 10 and 1 / 5; and / or, The ratio of the third preset duration to the duration of the third jitter period is between 1 / 10 and 1 / 5; and / or, The ratio of the fourth preset duration to the duration of the fourth shaking period is between 1 / 10 and 1 / 5.

6. The frequency dithering method according to claim 1, characterized in that, The frequency dithering circuit also includes an inverter circuit, and the digital signal processor and the first power supply circuit are electrically connected to the inverter circuit respectively, and the first power supply circuit provides the first voltage to the inverter circuit. After the step of performing frequency dithering processing on the dithering frequency, the dithering period, and the first frequency to obtain the first driving signal, the method further includes: The digital signal processor generates a first control signal, and controls the inverter circuit to operate based on the first control signal.

7. The frequency dithering method according to claim 1, characterized in that, The frequency dithering circuit further includes a second driving circuit and a second power supply circuit. The digital signal processor is electrically connected to the second power supply circuit through the second driving circuit. The method further includes: The digital signal processor generates a second driving signal based on the first driving signal, so that the second driving circuit drives the second power supply circuit to output a second voltage based on the second driving signal; The second driving signal and the first driving signal are complementary waveforms.

8. The frequency dithering method according to claim 7, characterized in that, The frequency dithering circuit further includes a boost circuit or a buck circuit. The digital signal processor and the second power supply circuit are electrically connected to the boost circuit or the buck circuit, respectively, and the second power supply circuit provides the second voltage to the boost circuit or the buck circuit. After the step of the digital signal processor generating a second drive signal based on the first drive signal, the method further includes: The digital signal processor generates a second control signal, and controls the operation of the boost circuit or the buck circuit based on the second control signal.

9. A frequency dithering circuit, characterized in that, The system includes a digital signal processor, a first driving circuit, and a first power supply circuit. The digital signal processor is electrically connected to the first power supply circuit through the first driving circuit. The digital signal processor is used for: Obtain the initial drive signal used to drive the first drive circuit, and obtain the maximum magnetic flux density of the first transformer of the first power supply circuit; Obtain the first frequency of the initial drive signal, and obtain the jitter frequency based on the maximum magnetic flux density and the first frequency; The dithering period of the dithering circuit is obtained, and the dithering frequency, the dithering period, and the first frequency are dithered to obtain a first driving signal, so that the first driving circuit drives the first power supply circuit to output a first voltage based on the first driving signal.

10. An energy storage device, characterized in that, Includes the frequency dithering circuit as described in claim 9.

Images