A low-power single bus communication encryption chip and an encryption authentication system

Abstract

The application belongs to the technical field of communication, and particularly relates to a low-power single bus communication encryption chip and an encryption authentication system. The encryption authentication system comprises an interface circuit, a voltage stabilizing circuit and a bias circuit, a power-on reset circuit and a clock circuit, a data decoding circuit and a coding modulation circuit, the data decoding circuit is used for decoding data received through a PA port and outputting demodulated data to a digital control circuit, the coding modulation circuit is used for coding and modulating modulation data sent by the digital control circuit and outputting the modulation data to the PA port, a digital control circuit, an encryption algorithm circuit and a memory. The application is based on low-power design technology, proportional code level transmission and communication timing optimization, and solves the problem of high power consumption of single-chip encryption authentication function and the need for external energy storage capacitor power supply.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, and specifically relates to a low-power single-bus communication encryption chip and encryption authentication system. Background Technology

[0002] Encryption authentication chips are application-specific integrated circuits (ASICs) that integrate cryptographic algorithms, key management, and secure storage functions. Their core purpose is to solve the three problems of "identity authenticity," "data integrity," and "information confidentiality" through cryptographic means, providing a reliable security foundation for hardware devices, data transmission, and product ecosystems. Their application scenarios have penetrated into almost all fields that require security protection, such as consumer electronics, industrial control, the Internet of Things, and finance.

[0003] Existing encryption authentication chips are broadly classified into two categories: contact and contactless. Contact-based encryption authentication systems use contact communication, where the communication host device and the authentication slave device are connected via contacts or wires. These wire connections include power and ground wires, as well as control terminals such as clock, signal, interrupt, and enable pins. Such numerous contact wire connections often require specially customized sockets or clamps. If the authentication slave device cannot obtain power from the communication host device, an external battery is required on its side. Therefore, the system is complex and costly. Contactless encryption authentication systems use contactless communication, requiring antennas on both the communication host device and the authentication slave device to establish a communication link. The antenna size is related to the communication frequency and is generally several centimeters or more. Similarly, if the authentication slave device cannot obtain power from the communication host device via electromagnetic fields, an external battery is also required on its side. On the authentication slave device side, the implementation of antennas and power supplies increases the overall physical size and system complexity of the authentication target, thereby increasing the design difficulty and cost of the system and limiting the application scope of the encryption authentication system.

[0004] Because contact-based encryption authentication schemes use physical contacts for connection, communication is more reliable than contactless encryption authentication schemes. Existing technologies, based on traditional multi-contact schemes, allow the slave device to achieve interactive authentication with the host via a single-bus communication. Current single-bus encryption chip products have only two wires (signal and ground), and are widely used in applications requiring fewer contacts, as fewer contacts result in higher connection reliability and lower product cost. Some existing single-bus encryption chip solutions integrate interface circuits, digital processing circuits, and storage circuits within a single chip to achieve encryption authentication. However, due to excessive power consumption during communication and data read / write processes, external or encapsulated capacitors are required to achieve encryption authentication.

[0005] Therefore, this invention proposes a low-power single-bus communication encryption chip and encryption authentication system to solve the problem that the above-mentioned single chip has excessive power consumption and requires external energy storage capacitor for power supply to implement encryption authentication function. Summary of the Invention

[0006] The purpose of this invention is to provide a low-power single-bus communication encryption chip and encryption authentication system. Based on low-power design technology, proportional code level transmission and communication timing optimization, this invention solves the problem of excessive power consumption and the need for external energy storage capacitors to power the encryption authentication function with a single chip. Only a small built-in capacitor is needed to meet the requirements of the encryption authentication process.

[0007] To address the aforementioned technical problems, this invention provides a low-power single-bus communication encryption chip, comprising:

[0008] An interface circuit, wherein the input / output terminals of the interface circuit are connected to the PA port and the PB port;

[0009] The interface circuit includes a voltage regulator circuit and a bias circuit. The power supply terminal of the interface circuit is connected to the voltage regulator circuit, and the power supply terminal of the voltage regulator circuit is connected to the bias circuit. The voltage regulator circuit adopts a voltage detection feedback type voltage adjustment circuit, and the bias circuit adopts a bias circuit that generates nA-level bias current.

[0010] The system includes a power-on reset circuit and a clock circuit. The power-on reset circuit generates a reset signal for the chip system upon power-on and sends it to the digital control circuit. The clock circuit generates a clock signal for the chip system and sends it to the digital control circuit. The power-on reset circuit is an AC reset circuit with a capacitor charging and discharging structure. The clock circuit is an oscillation circuit with a constant current source of mirror bias current for a capacitor charging and discharging structure.

[0011] The system includes a data decoding circuit and an encoding / modulation circuit. The data decoding circuit decodes the data received through the PA port and outputs demodulated data to the digital control circuit. The encoding / modulation circuit encodes and modulates the modulation data sent by the digital control circuit and outputs it to the PA port.

[0012] Digital control circuits are used to control the operating state of the chip system in order to realize encryption operations and memory read / write control;

[0013] An encryption algorithm circuit and a memory are provided. The encryption algorithm circuit performs encryption operations based on a key, a UID, and host information. The memory is used to store the key and UID information of the encryption algorithm circuit.

[0014] Preferably, the voltage regulator circuit includes: PMOS transistors P1~P10, NMOS transistors N1~N5, transistor Q1, resistors R1~R2, and capacitors C1~C3; the source terminals of PMOS transistors P1~P3 are connected to a pulsating voltage T2; the drain and gate terminals of PMOS transistor P1 are connected to the gate terminal of PMOS transistor P2 and the drain terminal of NMOS transistor N3; the drain terminal of PMOS transistor P2 is connected to one end of resistor R1, the gate terminal of PMOS transistor P3, and the drain terminal of NMOS transistor N1; PMOS transistor P3... The drain of NMOS transistor N1 is connected to one end of capacitor C1 and outputs the operating power supply VDD. The other end of capacitor C1 is connected to the source of NMOS transistor N1 and grounded. The other end of resistor R1 is connected to the source of NMOS transistors N2-N3 and grounded. The gate and drain of NMOS transistor N2 are connected to the gate of NMOS transistor N3, the source of NMOS transistor N4, and the source of NMOS transistor N5. The gate and drain of NMOS transistor N4 are connected to the gate and drain of PMOS transistor P6. The source of PMOS transistor P6 is connected to the NMOS transistor P5. The drain terminals of transistors N5 and P5 are connected to the gate terminal of P5, the source terminal of P8, the drain terminal of P7, and one end of capacitor C2. The source terminal of P5 is connected to the drain terminal of P4. The source terminal of P4 is connected to the sources of P7 and P10 and then to the operating power supply VDD. The gate terminal of P4 is connected to the gate terminal of N1 and the control signal VDD_T2. In CTL, the gate terminals of PMOS transistors P7 and P10 are connected to the bias voltage VBP0. The drain terminal of PMOS transistor P10 is connected to one end of resistor R2 and capacitor C3, the gate terminals of PMOS transistors P8~P9, and the reference voltage VREF. The other end of resistor R2 is connected to the emitter of transistor Q1. The base and collector of transistor Q1 are connected to the other end of capacitors C2~C3 and the drain terminal of PMOS transistor P9 and grounded. The source terminal of PMOS transistor P9 is connected to the drain terminal of PMOS transistor P8.

[0015] Preferably, the bias circuit includes: PMOS transistors PA1~PA4, NMOS transistors NA1~NA5, and resistor RA1; the source terminals of PMOS transistors PA1~PA4 are connected to the operating power supply VDD; the gate terminal of PMOS transistor PA1 is connected to the gate and drain terminals of PMOS transistor PA2, the gate terminal of PMOS transistor PA3, and the drain terminal of NMOS transistor NA3 to generate a bias voltage VBP0; the drain terminal of PMOS transistor PA1 is connected to the gate and drain terminals of NMOS transistor NA1, the gate terminals of NMOS transistors NA2~NA5, and... The drain of PMOS transistor PA4 is connected to the drain of PMOS transistor PA3 and NMOS transistor NA4. The gates of NMOS transistors NA4-NA5 are connected to the operating power supply VDD. The source of NMOS transistor NA4 is connected to the drain of NMOS transistor NA5. The source of NMOS transistor NA5 is connected to the source of NMOS transistor NA2 and one end of resistor RA1 and grounded. The other end of resistor RA1 is connected to the source of NMOS transistor NA3. The drain of NMOS transistor NA2 is connected to the source of NMOS transistor NA1.

[0016] Preferably, the power-on reset circuit includes: PMOS transistors P11~P19, NMOS transistors N11~N13, inverter INV1, Schmitt trigger SMT1, delay unit DLA1, and capacitors C11~C12; the source terminal of PMOS transistor P11 is connected to the operating power supply VDD, the gate terminal of PMOS transistor P11 is connected to the output terminal of inverter INV1, and the input terminal of inverter INV1 is connected to the enable signal POR_FAST_ENH. The drain of transistor P11 is connected to the source of PMOS transistor P12, the drain of PMOS transistor P12 is connected to the source of PMOS transistor P13, the drain of PMOS transistor P13 is connected to the source of PMOS transistor P14, the gates of PMOS transistors P12~P14 are connected to the gates of PMOS transistors P15~P16, the output of delay unit DLA1, one end of capacitor C12, and the reset signal RST_H, and the drain of PMOS transistor P14 is connected to PMOS transistor P16, PM The drain terminals of MOSFET P18 and NMOS transistor N11, and the gate terminals of PMOS transistors P19 and NMOS transistor N13, the source terminals of PMOS transistors P15, PMOS transistors P17 and PMOS transistor P19, and the other ends of capacitors C11-C12 are connected to the operating power supply VDD. The drain terminal of PMOS transistor P15 is connected to the source terminal of PMOS transistor P16, and the gate terminal of PMOS transistor P17 is connected to the gate terminals of PMOS transistors P18 and NMOS transistors N11-N12. With bias voltage VBN0, the drain of PMOS transistor P17 is connected to the source of PMOS transistor P18, the drain of PMOS transistor P19 is connected to the drain of NMOS transistor N12, one end of capacitor C11, and the input of Schmitt trigger SMT1, the output of Schmitt trigger SMT1 is connected to the input of delay unit DLA1, the source of NMOS transistor N12 is connected to the drain of NMOS transistor N13, and the sources of NMOS transistors N11 and NMOS transistor N13 are grounded.

[0017] Preferably, the clock circuit includes: PMOS transistors PM3~PM8, NMOS transistors NM4~NM7, AND gates AND1~AND2, NOT gates NOT1~NOT10, and capacitors CM1~CM2; the source terminals of PMOS transistors PM3~PM4 and PMOS transistors PM6~PM7 are connected to the operating power supply VDD, the gate terminals of PMOS transistors PM3~PM4 and PMOS transistors PM6~PM7 are connected to the bias voltage VBP1, the drain terminal of PMOS transistor PM3 is connected to the drain terminal of NMOS transistor NM4, and the input terminal of NOT gate NOT5; NMOS transistor NM4... The source terminal of M4 is grounded. The gate terminal of NMOS transistor NM4 is connected to the drain terminals of NMOS transistor NM5 and PMOS transistor PM5, as well as the grounded capacitor CM1. The source terminal of NMOS transistor NM5 is grounded. The gate terminal of NMOS transistor NM5 is connected to the input terminal of NOT gate NOT4 and the output terminal of NOT gate NOT3. The source terminal of PMOS transistor PM5 is connected to the drain terminal of PMOS transistor PM4. The gate terminal of PMOS transistor PM5 is connected to the substrate terminal SUB. The drain terminal of PMOS transistor PM6 is connected to the drain terminal of NMOS transistor NM6 and the input terminal of NOT gate NOT1. The source terminal of NMOS transistor NM6 is connected to... The gate of NMOS transistor NM6 is connected to the drain of NMOS transistor NM7 and PMOS transistor PM8, as well as to the grounded capacitor CM2. The source of NMOS transistor NM7 is grounded. The gate of NMOS transistor NM7 is connected to the output of NOT gate NOT4. The gate of PMOS transistor PM8 is connected to the substrate SUB. The source of PMOS transistor PM8 is connected to the drain of PMOS transistor PM7. The output of NOT gate NOT1 is connected to input one of AND gate AND1. Input two of AND gate AND1 is connected to the output of AND gate AND2 and the input of NOT gate NOT7. AND gate AND1... The output of NOT gate 1 is connected to the input of AND gate AND2 and NOT gate NOT2. The output of NOT gate NOT2 is connected to the input of NOT gate NOT3. The second input of AND gate AND2 is connected to the output of NOT gate NOT6. The input of NOT gate NOT6 is connected to the output of NOT gate NOT5. The output of NOT gate NOT7 is connected to the input of NOT gate NOT8. The output of NOT gate NOT8 is connected to the input of NOT gate NOT9. The output of NOT gate NOT9 is connected to the input of NOT gate NOT10. The output of NOT gate NOT10 outputs the oscillation clock OSC_OUT.

[0018] Preferably, each of the capacitors CM1 to CM2 is composed of multiple parallel-connected, grounded capacitors.

[0019] Preferably, the circuit further includes a bias voltage generating circuit, which includes: PMOS transistors PM1~PM2 and NMOS transistors NM1~NM3; the source terminals of PMOS transistors PM1~PM2 are connected to the operating power supply VDD, the gate terminal of PMOS transistor PM1 is connected to the bias voltage VBP0, the drain terminal of PMOS transistor PM1 is connected to the gate and drain terminals of NMOS transistor NM1, the gate terminal of NMOS transistor NM2, and the drain terminal of NMOS transistor NM3, the gate terminal of NMOS transistor NM3 is connected to the enable signal EN1, the source terminal of NMOS transistor NM3 is grounded, the source terminal of NMOS transistor NM1 is connected to the source terminal of NMOS transistor NM2, and the drain terminal of NMOS transistor NM2 is connected to the gate and drain terminals of PMOS transistor PM2 to generate the bias voltage VBP1.

[0020] Preferably, the digital control circuit includes:

[0021] The control module includes a single-wire communication control state machine and a memory read / write control state machine; the single-wire communication control state machine has a built-in decoding module and an encoding module, the decoding module is used to decrypt the demodulated data output by the data decoding circuit, and the encoding module is used to encrypt the data read from the memory and output the modulated data.

[0022] The reset synchronization module is used to input the chip system reset signal output by the power-on reset circuit and output a low-level active reset signal rst_n to the control module.

[0023] The memory control module is connected to both the memory read / write control state machine and the memory.

[0024] Preferably, the register REG1 in the decoding module, the encoding module, and the memory read / write control state machine is clocked by a gate-controlled clock module. The gate-controlled clock module includes a gated clock gclk; the output of the gated clock gclk is connected to the clock terminal of the register REG1. The gated clock gclk includes a register REG2 and an AND gate; the input of the register REG2 is connected to an enable signal EN2; the clock terminal of the register REG2 is connected to a clock signal CLK and the first input of the AND gate; the second input of the AND gate is connected to the output of the register REG2; and the output of the AND gate serves as the output of the gated clock gclk.

[0025] This invention also provides a single-bus communication encryption authentication system, employing a low-power single-bus communication encryption chip as described above, comprising:

[0026] The host side includes a main control MCU and a power supply circuit; the power supply circuit includes a battery and a PMOS transistor PM; the power supply terminal of the main control MCU is connected to the positive terminal of the battery and the source terminal of the PMOS transistor PM, the ground terminal of the main control MCU is connected to the negative terminal of the battery and ground connection point B, the GPIO1 terminal of the main control MCU is connected to the gate terminal of the PMOS transistor PM, the drain terminal of the PMOS transistor PM is connected to one end of the DC blocking capacitor C and the power supply connection point A, the GPIO2 terminal of the main control MCU is connected to the output terminal of the comparator CMP, the two input terminals of the comparator CMP are respectively connected to the differential output terminal of the low-pass filter LPF, and the input terminal of the low-pass filter LPF is connected to the other end of the DC blocking capacitor C;

[0027] The slave device includes a load RL and an encryption chip; one end of the load RL is connected to power connection point A' and PA port, and the other end of the load RL is connected to ground connection point B' and PB port.

[0028] During communication, the host sends low-level and high-level digital logic "0" and "1" via a proportional code. During the high-level period of the proportional code, the host charges the built-in capacitor of the encryption chip through the bus voltage. During the low-level period of the proportional code, the encryption chip discharges the charge stored in the built-in capacitor to maintain system operation. The charge injected into the built-in capacitor during the high-level period of the proportional code is always higher than the charge consumed by the encryption chip during the low-level period, ensuring that the voltage of the built-in capacitor during the low-level period is always higher than the minimum operating voltage of the encryption chip to guarantee continuous power supply. At other times, the host pulls the bus high to continuously supply power, ensuring continuous power supply during high-power operations inside the encryption chip.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] 1. This invention reduces the power consumption of analog circuits. It employs an nA-level bias circuit to generate the basic bias current; an AC reset circuit with a capacitor charging and discharging structure; a clock circuit with a constant current source using a mirror bias current to charge and discharge the capacitor; and a voltage detection feedback voltage regulator circuit. These design features an AC structure to reduce the duration of power consumption and high-impedance devices to reduce DC power consumption, ensuring that the analog power consumption during host communication code transmission is <5μA.

[0031] 2. This invention reduces the power consumption of the digital control circuit during communication. The digital control circuit of this invention mainly consists of two parts: a single-wire communication control state machine and a memory read / write control state machine. Their operation is time-division multiplexed: during slave code reception and decoding, the slave encoding module and memory control module are not working; during the memory control module's operation, the single-wire communication control state machine is not working; during slave code encoding and return, the slave decoding module and memory control module are not working. Based on the above workflow subdivision principle, a gated clock is used to disable the clock tree flipping in non-working states, reducing the dynamic power consumption of the digital control circuit and ensuring that the average power consumption of the digital circuit during communication encoding and decoding is <5μA.

[0032] 3. The encryption chip of this invention has only two pins and is powered by a built-in capacitor, requiring no other external components: Based on low-power design technology, proportional code level transmission and communication timing optimization, it solves the problem of excessive power consumption and the need for external energy storage capacitors to power the encryption and authentication function with a single chip. Only a small built-in capacitor is needed to meet the requirements of the encryption and authentication process. Attached Figure Description

[0033] Figure 1 This is a circuit block diagram of a low-power single-bus communication encryption chip provided by the present invention.

[0034] Figure 2 This is a voltage regulator circuit diagram provided by the present invention.

[0035] Figure 3 This is the bias circuit diagram provided by the present invention.

[0036] Figure 4 This is the power-on reset circuit diagram provided by the present invention.

[0037] Figure 5 This is a clock circuit diagram provided by the present invention.

[0038] Figure 6 This is a circuit diagram of the bias voltage generation provided by the present invention.

[0039] Figure 7 This is a digital control circuit diagram provided by the present invention.

[0040] Figure 8 This is a gated clock circuit diagram provided by the present invention.

[0041] Figure 9 This is a timing diagram of encrypted authentication communication provided by the present invention.

[0042] Figure 10 This is the timing diagram of the SYNC synchronization signal provided by the present invention.

[0043] Figure 11 This is a bit timing diagram for write operations provided by the present invention.

[0044] Figure 12 This is a read operation bit timing diagram provided by the present invention.

[0045] Figure 13 This is a circuit block diagram of the single-bus communication encryption and authentication system provided by the present invention. Detailed Implementation

[0046] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0047] like Figure 1 As shown, this embodiment of the invention provides a low-power single-bus communication encryption chip, comprising:

[0048] The interface circuit has its input / output terminals connected to the PA and PB ports; a full-wave rectifier circuit is used to achieve voltage conversion of DC pulse signals.

[0049] The interface circuit includes a voltage regulator circuit and a bias circuit. The power supply terminal of the interface circuit is connected to the voltage regulator circuit, and the power supply terminal of the voltage regulator circuit is connected to the bias circuit. The voltage regulator circuit adopts a voltage detection feedback type voltage adjustment circuit, and the bias circuit adopts a bias circuit that generates nA-level bias current.

[0050] The system includes a power-on reset circuit and a clock circuit. The power-on reset circuit generates a reset signal for the chip system upon power-on and sends it to the digital control circuit. The clock circuit generates a clock signal for the chip system and sends it to the digital control circuit. The power-on reset circuit is an AC reset circuit with a capacitor charging and discharging structure. The clock circuit is an oscillation circuit with a constant current source of mirror bias current for a capacitor charging and discharging structure.

[0051] The system includes a data decoding circuit and an encoding / modulation circuit. The data decoding circuit decodes the data received through the PA port and outputs demodulated data to the digital control circuit. The encoding / modulation circuit encodes and modulates the modulation data sent by the digital control circuit and outputs it to the PA port.

[0052] Digital control circuits are used to control the operating state of the chip system in order to realize encryption operations and memory read / write control;

[0053] An encryption algorithm circuit and a memory are provided. The encryption algorithm circuit performs encryption operations based on a key, a UID, and host information. The memory is used to store the key and UID information of the encryption algorithm circuit.

[0054] like Figure 2As shown, a voltage regulator circuit is designed to prevent the pulsating DC voltage after rectification from the interface circuit from exceeding the withstand voltage of the MOSFETs and causing damage to the devices. The voltage regulator circuit includes: PMOS transistors P1~P10, NMOS transistors N1~N5, transistor Q1, resistors R1~R2, and capacitors C1~C3; the source terminals of PMOS transistors P1~P3 are connected to the pulsating voltage T2; the drain and gate terminals of PMOS transistor P1 are connected to the gate terminal of PMOS transistor P2 and the drain terminal of NMOS transistor N3; the drain terminal of PMOS transistor P2 is connected to one end of resistor R1, the gate terminal of PMOS transistor P3, and the drain terminal of NMOS transistor N1; the drain terminal of PMOS transistor P3... Connect one end of capacitor C1 to output the operating power supply VDD. Connect the other end of capacitor C1 to the source of NMOS transistor N1 and ground. Connect the other end of resistor R1 to the source of NMOS transistors N2-N3 and ground. Connect the gate and drain of NMOS transistor N2 to the gate of NMOS transistor N3, the source of NMOS transistor N4, and the source of NMOS transistor N5. Connect the gate and drain of NMOS transistor N4 to the gate and drain of PMOS transistor P6. Connect the source of PMOS transistor P6 to NMOS transistor N5. The drain of PMOS transistor P5 and the gate of NMOS transistor N5 are connected to the gate of PMOS transistor P5, the source of PMOS transistor P8, the drain of PMOS transistor P7, and one end of capacitor C2. The source of PMOS transistor P5 is connected to the drain of PMOS transistor P4. The source of PMOS transistor P4 is connected to the sources of PMOS transistors P7 and PMOS transistor P10 and connected to the operating power supply VDD. The gate of PMOS transistor P4 is connected to the gate of NMOS transistor N1 and the control signal VDD_T2_C. TL, the gate terminals of PMOS transistors P7 and P10 are connected to the bias voltage VBP0, the drain terminal of PMOS transistor P10 is connected to one end of resistor R2 and capacitor C3, the gate terminals of PMOS transistors P8~P9 and the reference voltage VREF, the other end of resistor R2 is connected to the emitter of transistor Q1, the base and collector of transistor Q1 are connected to the other end of capacitors C2~C3 and the drain terminal of PMOS transistor P9 and grounded, and the source terminal of PMOS transistor P9 is connected to the drain terminal of PMOS transistor P8.

[0055] After the pulsating DC voltage T2 is generated by the interface circuit of the above full-wave rectifier circuit structure, the VDD voltage begins to rise, and VREF begins to build up. Capacitor C2 is charged through P7 transistor. When the VC voltage is less than 1.4V (2Vth, where Vth is the threshold voltage of N2 transistor + N5 transistor), the current of N2 transistor is provided by the P6-N5 transistor branch, and the VDD voltage stabilizes at 2.2V (3Vth). When the VC voltage is greater than 1.4V (2Vth), N5 transistor turns on, and the current of N2 transistor is provided by N5 transistor, forcing the VDD voltage to continue to rise, eventually stabilizing near the target voltage.

[0056] The power supply voltage VDD does not increase with the rectified pulsating voltage T2. This is because when VDD rises, the current of N2 increases, and the current IR1 flowing through resistor R1 after being mirrored by the current mirror formed by N2 and N3 also increases. The voltage drop VR across resistor R1 increases, which weakens the conduction of P3 driven by VDD, and the VDD voltage decreases. This negative feedback process stabilizes the VDD voltage at a fixed voltage value determined by VREF.

[0057] like Figure 3 As shown, the bias circuit includes: PMOS transistors PA1~PA4, NMOS transistors NA1~NA5, and resistor RA1; the source terminals of PMOS transistors PA1~PA4 are connected to the operating power supply VDD; the gate terminal of PMOS transistor PA1 is connected to the gate and drain terminals of PMOS transistor PA2, the gate terminal of PMOS transistor PA3, and the drain terminal of NMOS transistor NA3 to generate a bias voltage VBP0; the drain terminal of PMOS transistor PA1 is connected to the gate and drain terminals of NMOS transistor NA1, the gate terminals of NMOS transistors NA2~NA3, and P... The drain of MOSFET PA4 and the gate of PMOS transistor PA4 are connected to the drains of PMOS transistor PA3 and NMOS transistor NA4. The gates of NMOS transistors NA4 to NA5 are connected to the operating power supply VDD. The source of NMOS transistor NA4 is connected to the drain of NMOS transistor NA5. The source of NMOS transistor NA5 is connected to the source of NMOS transistor NA2 and one end of resistor RA1 and grounded. The other end of resistor RA1 is connected to the source of NMOS transistor NA3. The drain of NMOS transistor NA2 is connected to the source of NMOS transistor NA1.

[0058] After the operating power supply VDD is established, the bias circuit provides the basic bias current for each module of the analog circuit. Its structure is independent of the power supply. The startup circuit uses large-size inverting ratio transistors for transistors N4 and N5, and the bias resistor RA1 uses a large-size resistor with complementary temperature characteristics to meet the low-power design requirements.

[0059] like Figure 4As shown, the power-on reset circuit includes: PMOS transistors P11~P19, NMOS transistors N11~N13, inverter INV1, Schmitt trigger SMT1, delay unit DLA1, and capacitors C11~C12; the source terminal of PMOS transistor P11 is connected to the operating power supply VDD, the gate terminal of PMOS transistor P11 is connected to the output terminal of inverter INV1, and the input terminal of inverter INV1 is connected to the enable signal POR_FAST_ENH. The drain of P11 is connected to the source of PMOS transistor P12, the drain of PMOS transistor P12 is connected to the source of PMOS transistor P13, the drain of PMOS transistor P13 is connected to the source of PMOS transistor P14, the gates of PMOS transistors P12~P14 are connected to the gates of PMOS transistors P15~P16, the output of delay unit DLA1, one end of capacitor C12, and the reset signal RST_H, and the drain of PMOS transistor P14 is connected to PMOS transistor P16 and PMO... The drain terminals of S-MOSFET P18 and NMOS transistor N11, and the gate terminals of PMOS transistors P19 and NMOS transistor N13, the source terminals of PMOS transistors P15, PMOS transistors P17 and PMOS transistor P19, and the other ends of capacitors C11-C12 are connected to the operating power supply VDD. The drain terminal of PMOS transistor P15 is connected to the source terminal of PMOS transistor P16, and the gate terminal of PMOS transistor P17 is connected to the gate terminals of PMOS transistors P18 and NMOS transistors N11-N12. With bias voltage VBN0, the drain of PMOS transistor P17 is connected to the source of PMOS transistor P18, the drain of PMOS transistor P19 is connected to the drain of NMOS transistor N12, one end of capacitor C11, and the input of Schmitt trigger SMT1, the output of Schmitt trigger SMT1 is connected to the input of delay unit DLA1, the source of NMOS transistor N12 is connected to the drain of NMOS transistor N13, and the sources of NMOS transistors N11 and NMOS transistor N13 are grounded.

[0060] The power-on reset circuit provides a reset signal to other modules in the circuit, ensuring that the digital logic starts working after the voltage stabilizes. This structure has no DC reset point; the reset time varies with the power-on time (mainly determined by the bias current settling time), and the reset signal release is determined by the threshold voltage of the Schmitt trigger SMT1. The AC reset circuit has no DC path, and the static power consumption is almost zero after the reset is complete.

[0061] like Figure 5As shown, the clock circuit includes: PMOS transistors PM3~PM8, NMOS transistors NM4~NM7, AND gates AND1~AND2, NOT gates NOT1~NOT10, and capacitors CM1~CM2; the source terminals of PMOS transistors PM3~PM4 and PMOS transistors PM6~PM7 are connected to the operating power supply VDD, the gate terminals of PMOS transistors PM3~PM4 and PMOS transistors PM6~PM7 are connected to the bias voltage VBP1, the drain terminal of PMOS transistor PM3 is connected to the drain terminal of NMOS transistor NM4, and the input terminal of NOT gate NOT5; NMOS transistor NM4... The source terminal of NMOS transistor NM4 is grounded. The gate terminal of NMOS transistor NM4 is connected to the drain terminals of NMOS transistor NM5 and PMOS transistor PM5, as well as the grounded capacitor CM1. The source terminal of NMOS transistor NM5 is grounded. The gate terminal of NMOS transistor NM5 is connected to the input terminal of NOT gate NOT4 and the output terminal of NOT gate NOT3. The source terminal of PMOS transistor PM5 is connected to the drain terminal of PMOS transistor PM4. The gate terminal of PMOS transistor PM5 is connected to the substrate terminal SUB. The drain terminal of PMOS transistor PM6 is connected to the drain terminal of NMOS transistor NM6 and the input terminal of NOT gate NOT1. The source terminal of NMOS transistor NM6 is grounded. The gate of NMOS transistor NM6 is connected to the drain of NMOS transistor NM7 and PMOS transistor PM8, as well as to the grounded capacitor CM2. The source of NMOS transistor NM7 is grounded. The gate of NMOS transistor NM7 is connected to the output of NOT gate NOT4. The gate of PMOS transistor PM8 is connected to the substrate SUB. The source of PMOS transistor PM8 is connected to the drain of PMOS transistor PM7. The output of NOT gate NOT1 is connected to input one of AND gate AND1. Input two of AND gate AND1 is connected to the output of AND gate AND2 and the input of NOT gate NOT7. AND gate AND1... The output of NOT gate 1 is connected to the input of AND gate AND2 and NOT gate NOT2. The output of NOT gate NOT2 is connected to the input of NOT gate NOT3. The second input of AND gate AND2 is connected to the output of NOT gate NOT6. The input of NOT gate NOT6 is connected to the output of NOT gate NOT5. The output of NOT gate NOT7 is connected to the input of NOT gate NOT8. The output of NOT gate NOT8 is connected to the input of NOT gate NOT9. The output of NOT gate NOT9 is connected to the input of NOT gate NOT10. The output of NOT gate NOT10 outputs the oscillation clock OSC_OUT.

[0062] Preferably, each of the capacitors CM1 to CM2 is composed of multiple parallel-connected, grounded capacitors.

[0063] like Figure 6As shown, it also includes a bias voltage generating circuit, which includes: PMOS transistors PM1~PM2 and NMOS transistors NM1~NM3; the source terminals of PMOS transistors PM1~PM2 are connected to the operating power supply VDD, the gate terminal of PMOS transistor PM1 is connected to the bias voltage VBP0, the drain terminal of PMOS transistor PM1 is connected to the gate and drain terminals of NMOS transistor NM1, the gate terminal of NMOS transistor NM2, and the drain terminal of NMOS transistor NM3, the gate terminal of NMOS transistor NM3 is connected to the enable signal EN1, the source terminal of NMOS transistor NM3 is grounded, the source terminal of NMOS transistor NM1 is connected to the source terminal of NMOS transistor NM2, and the drain terminal of NMOS transistor NM2 is connected to the gate and drain terminals of PMOS transistor PM2 to generate the bias voltage VBP1.

[0064] The clock circuit generates the counting clock for the digital circuit. It uses a current source to charge and discharge the capacitor to produce a periodic clock signal. The upper and lower charging and discharging structures alternately generate set and reset signals for the RS flip-flops (composed of AND gates AND1~AND2 and NOT gates NOT1~NOT10). Through feedback, the charging and discharging state of the capacitor is changed, and the process repeats to finally form an oscillating clock output.

[0065] like Figure 7 As shown, the digital control circuit TOP_DIG includes:

[0066] The control module CODE_CTRL includes a single-wire communication control state machine and a memory read / write control state machine. The single-wire communication control state machine has a built-in decoding module and an encoding module. The decoding module is used to decrypt the demodulated data modin output by the data decoding circuit, and the encoding module is used to encrypt the data read from the memory and output the modulated data modout.

[0067] The reset synchronization module is used to input the chip system reset signal por_l (which is formed by inverting the reset signal RST_H) output by the power-on reset circuit, and output a low-level active reset signal rst_n to the control module.

[0068] The memory control module is connected to both the memory read / write control state machine and the memory.

[0069] like Figure 8As shown, the decoding module, the encoding module, and the memory read / write control state machine each have their register REG1 clocked by a gate-controlled clock module. The gate-controlled clock module includes a gated clock gclk; the output of the gated clock gclk is connected to the clock input of register REG1. The gated clock gclk includes a register REG2 and an AND gate; the input of register REG2 is connected to an enable signal EN2; the clock input of register REG2 is connected to a clock signal CLK and the first input of the AND gate; the second input of the AND gate is connected to the output of register REG2; and the output of the AND gate serves as the output of the gated clock gclk.

[0070] The digital control circuit of this invention mainly comprises two parts: a single-wire communication control state machine and a memory read / write control state machine. These two parts operate in a time-division multiplexing manner. During slave code reception and decoding, the slave encoding module and memory control module are inactive; during the operation of the memory control module, the single-wire communication control state machine is inactive; and during slave code encoding and return, the slave decoding module and memory control module are inactive. Based on this workflow segmentation principle, a gated clock is used to disable clock tree flipping in inactive states, reducing the dynamic power consumption of the digital control circuit and ensuring that the average power consumption of the digital circuit during communication encoding and decoding is <5μA.

[0071] This invention reduces clock tree flips and saves flip power by adding a gated clock (gclk). Simultaneously, by reducing the flipping behavior of register clock pins, the internal power consumption of the registers is also reduced. By using a gated clock to control clock flips according to the system workflow, when the decoding module, the encoding module, and the memory read / write control state machine are not operating, the clock input to the relevant register REG1 in each module is shut off, effectively reducing the power consumption of the digital control circuit.

[0072] like Figure 13 As shown, the present invention also provides a single-bus communication encryption authentication system, which employs a low-power single-bus communication encryption chip as described above, comprising:

[0073] The host side includes a main control MCU and a power supply circuit; the power supply circuit includes a battery and a PMOS transistor PM; the power supply terminal of the main control MCU is connected to the positive terminal of the battery and the source terminal of the PMOS transistor PM, the ground terminal of the main control MCU is connected to the negative terminal of the battery and ground connection point B, the GPIO1 terminal of the main control MCU is connected to the gate terminal of the PMOS transistor PM, the drain terminal of the PMOS transistor PM is connected to one end of the DC blocking capacitor C and the power supply connection point A, the GPIO2 terminal of the main control MCU is connected to the output terminal of the comparator CMP, the two input terminals of the comparator CMP are respectively connected to the differential output terminal of the low-pass filter LPF, and the input terminal of the low-pass filter LPF is connected to the other end of the DC blocking capacitor C;

[0074] The slave device includes a load RL and an encryption chip; one end of the load RL is connected to power connection point A' and PA port, and the other end of the load RL is connected to ground connection point B' and PB port.

[0075] The host MCU connects to the load RL and the encryption chip via a power supply circuit, and sends commands and data to the encryption chip. The encryption chip returns encrypted authentication data by modulating the load on the bus. The host receives the load-modulated data using a DC blocking-low-pass-comparison amplification scheme. This invention's encryption chip, by multiplexing the existing power connection point (A&A') and ground connection point (B&B') on the power supply circuit, enables load-carrying communication between the host and slave ends through only two connection points.

[0076] Bus communication timing is as follows Figure 9 As shown, process ① is the bus power-on process; process ② is the encryption chip's internal power-on reset process; processes ③ and ⑦ are the host code transmission process; process ④ is the encryption chip's memory data reading process; process ⑤ is the encryption chip's encryption calculation process; process ⑥ is the encryption chip's encoding and return code modulation output process; and process ⑧ is the encryption chip's memory writing process. After the bus is powered on, PA / PB is pulled high, the encryption chip's built-in capacitor is charged, and after power-on reset, the chip can receive host commands and start working; the host sends synchronization codes and instruction codes to communicate with the encryption chip, and the timing of the synchronization codes and instruction codes is as follows. Figure 10As shown, the duty cycle and timing of the proportional code ensure that the built-in capacitor C1 reliably powers the encryption chip during the communication phase. The encryption chip loads data from the memory according to the instructions and performs encryption operations. The result is sent to the host through load modulation. After successful authentication by the host, a synchronization code and instruction code are sent to write to the encryption chip's memory. In stages ②, ④, ⑤, and ⑧, the encryption chip is in its internal working state. At this time, the chip power consumption is relatively high, but communication with the host is not required, so the host pulls the bus level high to directly power the encryption chip. In stages ①, ③, ⑥, and ⑦, the encryption chip is in its interface working state. At this time, the chip power consumption is relatively low, and communication with the host is required, so power is supplied through the built-in capacitor. In summary, this communication timing and low-power design ensures stable power supply to the chip under different operating conditions.

[0077] When the host transmits communication codes, it sends digital 0 / 1 levels through a proportional code. The high level time of the proportional code must ensure that the charge stored in capacitor C1 inside the encryption chip can continuously power the system and keep it above the minimum operating voltage when it is at a low level. At other times, the host bus is pulled high to continuously supply power, ensuring that the encryption chip can continuously supply power during high-power operations.

[0078] The timing sequence of the ratio code for writing and reading 0 / 1 data during communication between the host and the encryption chip is as follows: Figures 10-12 As shown, Figure 10 For the SYNC synchronization signal timing, the low-level time is required to be greater than 27T (T is the period of the clock signal generated by the clock circuit), and the high-level time is 4T~25T;

[0079] Figure 11 This is the timing sequence for the write operation. Data is written after the SYNC signal is sent. A frame of data transmission begins on the falling edge of the SYNC signal. The low-level duration for writing 0 is 10T~14T, and the high-level duration is greater than 2T; the low-level duration for writing 1 is 2T~6T, and the high-level duration is greater than 10T.

[0080] Figure 12 This is the timing sequence for a read operation. When reading data, the host pulls the bus high and waits for 200T before the encryption chip replies with data. Specifically, for reading 0, the low-level time is 24T and the high-level time is 8T; for reading 1, the low-level time is 8T and the high-level time is 24T.

[0081] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A low-power single-bus communication encryption chip, characterized in that, include: An interface circuit, wherein the input / output terminals of the interface circuit are connected to the PA port and the PB port; The interface circuit includes a voltage regulator circuit and a bias circuit. The power supply terminal of the interface circuit is connected to the voltage regulator circuit, and the power supply terminal of the voltage regulator circuit is connected to the bias circuit. The voltage regulator circuit adopts a voltage detection feedback type voltage adjustment circuit, and the bias circuit adopts a bias circuit that generates nA-level bias current. The system includes a power-on reset circuit and a clock circuit. The power-on reset circuit generates a reset signal for the chip system upon power-on and sends it to the digital control circuit. The clock circuit generates a clock signal for the chip system and sends it to the digital control circuit. The power-on reset circuit is an AC reset circuit with a capacitor charging and discharging structure. The clock circuit is an oscillation circuit with a constant current source of mirror bias current for a capacitor charging and discharging structure. The system includes a data decoding circuit and an encoding / modulation circuit. The data decoding circuit decodes the data received through the PA port and outputs demodulated data to the digital control circuit. The encoding / modulation circuit encodes and modulates the modulation data sent by the digital control circuit and outputs it to the PA port. Digital control circuits are used to control the operating state of the chip system in order to realize encryption operations and memory read / write control; An encryption algorithm circuit and a memory are provided. The encryption algorithm circuit performs encryption operations based on a key, a UID, and host information. The memory is used to store the key and UID information of the encryption algorithm circuit.

2. The low-power single-bus communication encryption chip as described in claim 1, characterized in that, The voltage regulator circuit includes: PMOS transistors P1~P10, NMOS transistors N1~N5, transistor Q1, resistors R1~R2, and capacitors C1~C3; the source terminals of PMOS transistors P1~P3 are connected to a pulsating voltage T2; the drain and gate terminals of PMOS transistor P1 are connected to the gate terminal of PMOS transistor P2 and the drain terminal of NMOS transistor N3; the drain terminal of PMOS transistor P2 is connected to one end of resistor R1, the gate terminal of PMOS transistor P3, and the drain terminal of NMOS transistor N1; the drain terminal of PMOS transistor P3... Connect one end of capacitor C1 to output the operating power supply VDD. Connect the other end of capacitor C1 to the source of NMOS transistor N1 and ground. Connect the other end of resistor R1 to the source of NMOS transistors N2-N3 and ground. Connect the gate and drain of NMOS transistor N2 to the gate of NMOS transistor N3, the source of NMOS transistor N4, and the source of NMOS transistor N5. Connect the gate and drain of NMOS transistor N4 to the gate and drain of PMOS transistor P6. Connect the source of PMOS transistor P6 to NMOS transistor N5. The drain of PMOS transistor P5 and the gate of NMOS transistor N5 are connected to the gate of PMOS transistor P5, the source of PMOS transistor P8, the drain of PMOS transistor P7, and one end of capacitor C2. The source of PMOS transistor P5 is connected to the drain of PMOS transistor P4. The source of PMOS transistor P4 is connected to the sources of PMOS transistors P7 and PMOS transistor P10 and connected to the operating power supply VDD. The gate of PMOS transistor P4 is connected to the gate of NMOS transistor N1 and the control signal VDD_T2_C. TL, the gate terminals of PMOS transistors P7 and P10 are connected to the bias voltage VBP0, the drain terminal of PMOS transistor P10 is connected to one end of resistor R2 and capacitor C3, the gate terminals of PMOS transistors P8~P9 and the reference voltage VREF, the other end of resistor R2 is connected to the emitter of transistor Q1, the base and collector of transistor Q1 are connected to the other end of capacitors C2~C3 and the drain terminal of PMOS transistor P9 and grounded, and the source terminal of PMOS transistor P9 is connected to the drain terminal of PMOS transistor P8.

3. The low-power single-bus communication encryption chip as described in claim 2, characterized in that, The bias circuit includes: PMOS transistors PA1~PA4, NMOS transistors NA1~NA5, and resistor RA1; the source terminals of PMOS transistors PA1~PA4 are connected to the operating power supply VDD; the gate terminal of PMOS transistor PA1 is connected to the gate and drain terminals of PMOS transistor PA2, the gate terminal of PMOS transistor PA3, and the drain terminal of NMOS transistor NA3 to generate a bias voltage VBP0; the drain terminal of PMOS transistor PA1 is connected to the gate and drain terminals of NMOS transistor NA1, the gate terminals of NMOS transistors NA2~NA3, and PMOS transistor PA1. The drain of transistor PA4 is connected to the drain of PMOS transistor PA3 and NMOS transistor NA4. The gate of NMOS transistor PA4 is connected to the drain of PMOS transistor PA3 and NMOS transistor NA4. The gates of NMOS transistors NA4 to NA5 are connected to the operating power supply VDD. The source of NMOS transistor NA4 is connected to the drain of NMOS transistor NA5. The source of NMOS transistor NA5 is connected to the source of NMOS transistor NA2 and one end of resistor RA1 and grounded. The other end of resistor RA1 is connected to the source of NMOS transistor NA3. The drain of NMOS transistor NA2 is connected to the source of NMOS transistor NA1.

4. The low-power single-bus communication encryption chip as described in claim 1, characterized in that, The power-on reset circuit includes: PMOS transistors P11~P19, NMOS transistors N11~N13, inverter INV1, Schmitt trigger SMT1, delay unit DLA1, and capacitors C11~C12; the source terminal of PMOS transistor P11 is connected to the operating power supply VDD, the gate terminal of PMOS transistor P11 is connected to the output terminal of inverter INV1, and the input terminal of inverter INV1 is connected to the enable signal POR_FAST_ENH. The drain of P11 is connected to the source of PMOS transistor P12, the drain of PMOS transistor P12 is connected to the source of PMOS transistor P13, the drain of PMOS transistor P13 is connected to the source of PMOS transistor P14, the gates of PMOS transistors P12~P14 are connected to the gates of PMOS transistors P15~P16, the output of delay unit DLA1, one end of capacitor C12, and the reset signal RST_H, and the drain of PMOS transistor P14 is connected to PMOS transistor P16, PMOS... The drain terminals of transistors P18 and NMOS transistor N11, and the gate terminals of PMOS transistors P19 and NMOS transistor N13, the source terminals of PMOS transistors P15, PMOS transistors P17 and PMOS transistor P19, and the other ends of capacitors C11~C12 are connected to the operating power supply VDD. The drain terminal of PMOS transistor P15 is connected to the source terminal of PMOS transistor P16. The gate terminal of PMOS transistor P17 is connected to the gate terminals of PMOS transistors P18 and NMOS transistors N11~N12, as well as the bias terminal. Set the voltage VBN0, connect the drain of PMOS transistor P17 to the source of PMOS transistor P18, connect the drain of PMOS transistor P19 to the drain of NMOS transistor N12, one end of capacitor C11, and the input of Schmitt trigger SMT1, connect the output of Schmitt trigger SMT1 to the input of delay unit DLA1, connect the source of NMOS transistor N12 to the drain of NMOS transistor N13, and ground the sources of NMOS transistors N11 and NMOS transistor N13.

5. The low-power single-bus communication encryption chip as described in claim 1, characterized in that, The clock circuit includes: PMOS transistors PM3~PM8, NMOS transistors NM4~NM7, AND gates AND1~AND2, NOT gates NOT1~NOT10, and capacitors CM1~CM2; the source terminals of PMOS transistors PM3~PM4 and PM6~PM7 are connected to the operating power supply VDD, the gate terminals of PMOS transistors PM3~PM4 and PM6~PM7 are connected to the bias voltage VBP1, the drain terminal of PMOS transistor PM3 is connected to the drain terminal of NMOS transistor NM4, and the input terminal of NOT gate NOT5; the NMOS transistor NM4... The source terminal of NMOS transistor NM4 is grounded. The gate terminal of NMOS transistor NM4 is connected to the drain terminals of NMOS transistor NM5 and PMOS transistor PM5, as well as to the grounded capacitor CM1. The source terminal of NMOS transistor NM5 is grounded. The gate terminal of NMOS transistor NM5 is connected to the input terminal of NOT gate NOT4 and the output terminal of NOT gate NOT3. The source terminal of PMOS transistor PM5 is connected to the drain terminal of PMOS transistor PM4. The gate terminal of PMOS transistor PM5 is connected to the substrate terminal SUB. The drain terminal of PMOS transistor PM6 is connected to the drain terminal of NMOS transistor NM6 and the input terminal of NOT gate NOT1. The source terminal of NMOS transistor NM6 is grounded. The gate of NMOS transistor NM6 is connected to the drain of NMOS transistor NM7 and PMOS transistor PM8, as well as to the grounded capacitor CM2. The source of NMOS transistor NM7 is grounded. The gate of NMOS transistor NM7 is connected to the output of NOT gate NOT4. The gate of PMOS transistor PM8 is connected to the substrate SUB. The source of PMOS transistor PM8 is connected to the drain of PMOS transistor PM7. The output of NOT gate NOT1 is connected to input one of AND gate AND1. Input two of AND gate AND1 is connected to the output of AND gate AND2 and the input of NOT gate NOT7. The output is connected to the input of AND gate AND2 and NOT gate NOT2. The output of NOT gate NOT2 is connected to the input of NOT gate NOT3. The second input of AND gate AND2 is connected to the output of NOT gate NOT6. The input of NOT gate NOT6 is connected to the output of NOT gate NOT5. The output of NOT gate NOT7 is connected to the input of NOT gate NOT8. The output of NOT gate NOT8 is connected to the input of NOT gate NOT9. The output of NOT gate NOT9 is connected to the input of NOT gate NOT10. The output of NOT gate NOT10 outputs the oscillation clock OSC_OUT.

6. The low-power single-bus communication encryption chip as described in claim 5, characterized in that, The capacitors CM1 to CM2 are each composed of multiple parallel-connected, grounded capacitors.

7. A low-power single-bus communication encryption chip as described in claim 5, characterized in that, It also includes a bias voltage generating circuit, which includes: PMOS transistors PM1~PM2 and NMOS transistors NM1~NM3; the source terminals of PMOS transistors PM1~PM2 are connected to the operating power supply VDD, the gate terminal of PMOS transistor PM1 is connected to the bias voltage VBP0, the drain terminal of PMOS transistor PM1 is connected to the gate and drain terminals of NMOS transistor NM1, the gate terminal of NMOS transistor NM2, and the drain terminal of NMOS transistor NM3, the gate terminal of NMOS transistor NM3 is connected to the enable signal EN1, the source terminal of NMOS transistor NM3 is grounded, the source terminal of NMOS transistor NM1 is connected to the source terminal of NMOS transistor NM2, and the drain terminal of NMOS transistor NM2 is connected to the gate and drain terminals of PMOS transistor PM2 to generate the bias voltage VBP1.

8. The low-power single-bus communication encryption chip as described in claim 1, characterized in that, The digital control circuit includes: The control module includes a single-wire communication control state machine and a memory read / write control state machine; the single-wire communication control state machine has a built-in decoding module and an encoding module, the decoding module is used to decrypt the demodulated data output by the data decoding circuit, and the encoding module is used to encrypt the data read from the memory and output the modulated data. The reset synchronization module is used to input the chip system reset signal output by the power-on reset circuit and output a low-level active reset signal rst_n to the control module. The memory control module is connected to both the memory read / write control state machine and the memory.

9. A low-power single-bus communication encryption chip as described in claim 8, characterized in that, The decoding module, the encoding module, and the memory read / write control state machine each have their register REG1 clocked by a gate-controlled clock module. Each gate-controlled clock module includes a gated clock gclk. The output of gclk is connected to the clock input of register REG1. gclk includes register REG2 and an AND gate. The input of register REG2 is connected to an enable signal EN2. The clock input of register REG2 is connected to a clock signal CLK and the first input of the AND gate. The second input of the AND gate is connected to the output of register REG2. The output of the AND gate serves as the output of the gated clock gclk.

10. A single-bus communication encryption authentication system, employing a low-power single-bus communication encryption chip as described in any one of claims 1 to 9, characterized in that, include: The host side includes a main control MCU and a power supply circuit; the power supply circuit includes a battery and a PMOS transistor PM; the power supply terminal of the main control MCU is connected to the positive terminal of the battery and the source terminal of the PMOS transistor PM, the ground terminal of the main control MCU is connected to the negative terminal of the battery and ground connection point B, the GPIO1 terminal of the main control MCU is connected to the gate terminal of the PMOS transistor PM, the drain terminal of the PMOS transistor PM is connected to one end of the DC blocking capacitor C and the power supply connection point A, the GPIO2 terminal of the main control MCU is connected to the output terminal of the comparator CMP, the two input terminals of the comparator CMP are respectively connected to the differential output terminal of the low-pass filter LPF, and the input terminal of the low-pass filter LPF is connected to the other end of the DC blocking capacitor C; The slave device includes a load RL and an encryption chip; one end of the load RL is connected to power connection point A' and PA port, and the other end of the load RL is connected to ground connection point B' and PB port. During communication, the host sends low-level and high-level digital logic "0" and "1" via a proportional code. During the high-level period of the proportional code, the host charges the built-in capacitor of the encryption chip through the bus voltage. During the low-level period of the proportional code, the encryption chip discharges the charge stored in the built-in capacitor to maintain system operation. The charge injected into the built-in capacitor during the high-level period of the proportional code is always higher than the charge consumed by the encryption chip during the low-level period. This ensures that the voltage of the built-in capacitor during the low-level period is always higher than the minimum operating voltage of the encryption chip, thus guaranteeing continuous power supply. At other times, the host will pull the bus high to continuously supply power, ensuring continuous power supply during high-power operations inside the encryption chip.

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