A source-down mos device based on a planar mos process and a preparation method thereof

Abstract

The application discloses a source-down MOS device based on a planar MOS process and a preparation method, relates to the technical field of semiconductor devices, and comprises a semiconductor substrate, an active region and a gate region, the active region is formed on the surface of the semiconductor substrate, and the gate region is located above the active region; a drain and a source are arranged in the active region, the drain on one side is electrically connected to the front surface of a chip through a forward metal electrode, and the forward metal electrode is located in the gate region; the source on the other side is in communication with the semiconductor substrate through an electrode connecting area and forms a good ohmic contact, and a substrate metal electrode is arranged at the bottom of the semiconductor substrate. The application has the advantages of reasonable layout, compact structure, low process cost, reduced main groove and field plate groove mask steps compared with the heterostructure of Diodes, avoided stress and defects caused by groove filling, high integration, direct realization of source interconnection in the chip compared with the package-level source bottom of Infineon, support for multi-device stacking design, and saved pad and lead channel space.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and particularly relates to a source-down MOS device based on a planar MOS process and a preparation method thereof. BACKGROUND

[0002] MOS field effect transistor (MOSFET) is one of the most important power semiconductor devices in modern electronic devices, and plays a key role in power management, motor control, inverter and other applications. With the development of electronic devices towards miniaturization, high efficiency and high power density, higher requirements are put forward for the performance of MOSFET, especially in terms of on-resistance, switching speed and thermal management. The source-down structure as an innovative power MOSFET packaging and structure technology has attracted widespread attention in recent years.

[0003] The patent of Diodes Incorporated (such as US20210151596A) proposes a source-down configured field effect transistor, which realizes the source-down structure by setting a trench in the semiconductor chip and embedding conductive gate material and conductive field plate in the trench, but this scheme needs deep trench etching and filling, which requires higher equipment and process requirements. At the same time, a vertical field plate structure needs to be formed, which increases the manufacturing difficulty. The trench and field plate structure will increase the parasitic capacitance, which may affect the switching speed and frequency performance of the transistor. It is not compatible with the existing planar MOS process, and a new process flow and equipment need to be developed.

[0004] The source-down device of Infineon (such as OptiMOS TM series) adopts flip-chip technology to directly connect the source pad to the packaging substrate, which simplifies the chip structure, but is limited by the packaging parasitic parameters (such as lead inductance ~ 1.2nH). Its quality factor

FoM=Rds(on)·Qg

[0005] Therefore, how to provide a source-down MOS device and preparation method based on a planar MOS process, which adopts an embedded source interconnection structure to realize the source-down layout, and is compatible with the traditional planar MOS process, effectively reducing the packaging cost, has become a technical problem to be solved by the technical personnel in the field. SUMMARY

[0006] The purpose of the present application is to provide a source-down MOS device based on a planar MOS process, which solves the problems of deep trench etching, filling and other high difficulty and high cost required by the prior art.

[0007] To solve the above technical problems, the present application adopts the following technical solutions:

[0008] The present application is a source-down MOS device based on a planar MOS process, comprising a semiconductor substrate, an active region and a gate region, the active region is formed on the surface of the semiconductor substrate, and the gate region is located above the active region.

[0009] The active region is provided with a drain and a source, the drain on the upper side is electrically connected to the front surface of the chip through a forward metal electrode, and the forward metal electrode is located in the gate region; the source on the other side is in communication with the semiconductor substrate through an electrode connecting area and forms a good ohmic contact, and the electrode connecting area is located in a reverse type layer provided on the top of the semiconductor substrate; the bottom of the semiconductor substrate is provided with a substrate metal electrode for lead-out.

[0010] Preferably, the active region comprises the entire region composed of a reverse type layer and a drift layer, the electrode connecting area is epitaxially formed on the drift layer, and the reverse type layer is an isolation layer formed by epitaxy, diffusion or ion implantation.

[0011] Preferably, the semiconductor substrate adopts a single crystal semiconductor material, which is a heavily doped substrate layer, the reverse type layer is a highly doped isolation layer, and the drift layer is a lowly doped epitaxial layer.

[0012] Preferably, a plurality of well regions are provided on the drift layer, the source is located in the well region and corresponds to the position of the electrode connecting area below in one-to-one correspondence; the drain is located on the top of the drift layer and between any two adjacent sources.

[0013] Preferably, the gate region comprises a gate oxide layer, a gate and a gate insulating layer arranged in sequence, the gate oxide layer is located above the drift layer, the gate is located above the gate oxide layer and leaves a plurality of gate recesses corresponding to the drain and the source, the gate insulating layer is filled and covers the gate, the gate insulating layer is connected to completely close the gate recess corresponding to the source, the forward metal electrode is provided in the gate recess corresponding to the drain, and a second insulating layer is provided at the forward metal electrode.

[0014] Preferably, the material of the gate oxide layer is Thermal SiO2, and the thickness is designed to be 24 nm; the gate adopts polycrystalline silicon or a metal gate, and the metal gate is specifically Pt, Pd, NiSi or CoSi, and the thickness is designed to be 450 nm; the material of the gate insulating layer is SiO2 or SiOxNy, and the thickness is designed to be 1200 nm.

[0015] A method for manufacturing a source-down MOS device based on a planar MOS process, comprising the following steps:

[0016] Step one, manufacturing of the substrate, first, select P-type or N-type silicon wafer as the substrate material according to the manufacturing type, second, after the silicon wafer is selected, form a heavily doped substrate layer through doping process;

[0017] Step two, form a reverse type layer through epitaxy, diffusion or ion implantation, the reverse type layer is located above the semiconductor substrate, for realizing isolation of the semiconductor substrate and the drift layer;

[0018] Step three, form an electrode connection area through ion implantation, implant corresponding ions according to the product type to form multiple independent heavily doped electrode areas, which become the current channel for the source to communicate with the substrate;

[0019] Step four, form a drift layer through epitaxy, which is located between the source and the drain, for bearing high voltage;

[0020] Step five, form a well area through ion implantation or diffusion, which is located above the drift layer and corresponds to the electrode connection area one by one, providing a basis for forming the source area;

[0021] Step six, form a drain area through ion implantation, which is located at the top of the drift layer and between two adjacent well areas, form an independent highly doped area after ion implantation, for communicating with the positive metal electrode above;

[0022] Step seven, form a source area through ion implantation, which is located in the middle of the well area, form an independent highly doped area after ion implantation;

[0023] Step eight, form a gate oxide layer, which is an insulating medium between the gate and the active area, for preventing leakage;

[0024] Step nine, manufacture the gate, the gate is located above the gate oxide layer and corresponds to the drain and the source in the reserved multiple gate grooves;

[0025] Step ten, protect the gate through the first insulating layer;

[0026] Step eleven, form a positive metal electrode through the first layer of metallization;

[0027] Step twelve, protect the positive metal electrode through the second insulating layer;

[0028] Step thirteen, thin the back of the substrate;

[0029] Step fourteen, form a substrate metal electrode through back metallization.

[0030] Preferably, in step four, the drift layer is formed through a planar MOS process.

[0031] Preferably, in the step thirteen, the back surface of the substrate is thinned, and the thickness of the thinned substrate is 325-425 μm.

[0032] Compared with the prior art, the application has the beneficial technical effects:

[0033] The application discloses a source-down MOS device based on a planar MOS process, which comprises a semiconductor substrate, an active region and a gate region arranged on the semiconductor substrate in sequence, and the active region comprises an inversion layer and a drift layer.

[0034] 1) The source electrode is embedded in the device, which is different from traditional LDMOS devices, and the source electrode is located below the device, and through specific doping and structural design, an electrode connection area is arranged on the inversion layer to form a current channel, so that the source electrode and the substrate form a good ohmic contact, and the on-resistance is reduced; the drain electrode is located above the device, and a certain spacing is formed between the source electrode and the drain electrode to realize the voltage resistance function of the device.

[0035] 2) The gate region is arranged between the source region and the drain region, and is isolated from the semiconductor substrate through a gate oxide layer, and is used for controlling the conduction and cutoff of the device.

[0036] 3) Compatible with traditional planar MOS process: the drift layer, gate recess and doping steps of the existing MOS process are used, and only ion implantation and back metalization process operations need to be added, without complex heterostructures, so that the manufacturing cost is reduced.

[0037] 4) Double-side heat dissipation optimization: the back source electrode is in direct contact with the substrate metal electrode, and the drain electrode on the front surface is combined to form an upper and lower double-side heat dissipation structure, so that the heat management efficiency is significantly improved.

[0038] In general, the application has reasonable layout, compact structure and low process cost, compared with the heterostructure of Diodes, two mask steps of main grooves and field plate grooves are reduced, and stress and defects caused by groove filling are avoided; the integration degree is high, compared with the package-level source bottom of Infineon, the source electrode interconnection is directly realized in the chip, the multi-device stacking design is supported, and the space occupied by the pad and the lead channel is saved. BRIEF DESCRIPTION OF DRAWINGS

[0039] The application will be further described below in combination with the description of the accompanying drawings.

[0040] Figure 1 A schematic diagram of the source-down MOS device based on the planar MOS process is shown in the accompanying drawings.

[0041] Figure 2 Structure change diagram for steps 1-3 of the present application;

[0042] Figure 3 Structure change diagram for steps 4-7 of the present application;

[0043] Figure 4 Structure change diagram for steps 8-10 of the present application;

[0044] Figure 5 Structure change diagram for steps 11-14 of the present application;

[0045] Figure 6 Flow chart of the preparation method of the source-down MOS device of the present application.

[0046] BRIEF DESCRIPTION OF DRAWINGS 1, semiconductor substrate; 2, inversion layer; 3, electrode connection area; 4, drift layer; 5, well region; 6, drain; 7, source; 8, gate oxide layer; 9, gate; 10, gate insulating layer; 11, positive metal electrode; 12, second insulating layer; 13, substrate metal electrode. DETAILED DESCRIPTION

[0047] In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects more clearly understood, the present application will be further described in detail below in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application and not to limit the present application.

[0048] As shown in Figures 1-5 A source-down MOS device based on a planar MOS process, comprising a semiconductor substrate 1, an active region and a gate region, the active region is formed on the surface of the semiconductor substrate, and the gate region is located above the active region.

[0049] The active region is provided with a drain 6 and a source 7, the drain 6 located on the upper side is electrically connected to the front surface of the chip through a positive metal electrode 11, and the positive metal electrode 11 is located in the gate region; the source 7 located on the other side is in communication with the semiconductor substrate 1 through an electrode connection area 3 and forms a good ohmic contact, and the electrode connection area 3 is located in the inversion layer 2 provided on the top of the semiconductor substrate 1.

[0050] The bottom of the semiconductor substrate 1 is provided with a substrate metal electrode 13 for lead-out.

[0051] Specifically, the active region includes the entire region composed of the inversion layer 2 and the drift layer 4, the electrode connection area 3 epitaxially forms the drift layer 4, and the inversion layer 2 is an isolation layer formed by epitaxy, diffusion or ion implantation.

[0052] The semiconductor substrate 1 is made of single-crystal semiconductor material and is a heavily doped substrate layer. The inversion layer 2 is a highly doped isolation layer, and the drift layer 4 is a lightly doped epitaxial layer.

[0053] Specifically, the drift layer 4 is provided with multiple well regions 5, the source electrode 7 is located in the well region 5 and corresponds one-to-one with the position of the electrode connection region 3 below; the drain electrode 6 is located on the top of the drift layer 4 and is located between any two adjacent source electrodes 7.

[0054] Specifically, the gate region includes a gate oxide layer 8, a gate 9, and a gate insulating layer 10 arranged sequentially. The gate oxide layer 8 is located above the drift layer 4. The gate 9 is located above the gate oxide layer 8, and multiple gate grooves are reserved therefor corresponding to the drain 6 and the source 7. The gate insulating layer 10 fills and covers the gate 9. After the gate insulating layer 10 is connected, the gate groove corresponding to the source 7 is completely sealed. The positive metal electrode 11 is disposed in the gate groove corresponding to the drain 6. A second insulating layer 12 is disposed at the positive metal electrode 11. The second insulating layer 12 is located above the gate insulating layer 10. The main function of the second insulating layer 12 is to achieve electrical isolation and prevent short circuit between the drain and adjacent conductors (such as the source, gate, or substrate). It can also play an environmental protection role, blocking corrosion or leakage caused by moisture, pollutants, or ion migration. The thickness and number of layers of the positive metal electrode 11 and the second insulating layer 12 can be further set according to actual needs.

[0055] Specifically, the gate oxide layer 8 is made of thermal SiO2 with a thickness of 24 nm; the gate 9 is made of polysilicon or a metal gate, specifically Pt, Pd, NiSi, or CoSi, with a thickness of 450 nm; the gate insulating layer 10 is made of SiO2 or SiO2. x N y The thickness is designed to be 1200nm.

[0056] like Figure 6 As shown, a method for fabricating a source-down MOS device based on planar MOS technology as described above specifically includes the following steps:

[0057] Step 1: Substrate fabrication. A P-type or N-type silicon wafer is selected to fabricate the semiconductor substrate 1. Typically, a P-type substrate is used to fabricate NMOS, and an N-type substrate is used to fabricate PMOS. Simultaneously, after selecting the silicon wafer, a heavily doped substrate layer is formed through doping processes (CZ method, epitaxy, ion implantation, or diffusion), with a doping concentration reaching 10⁻⁶. 19 ~10 20 cm -3The substrate layer serves as a support for the inversion layer 2 and mainly functions to reduce resistance, support epitaxial growth and optimize device performance.

[0058] Step two: the inversion layer 2 is formed by epitaxy, diffusion or ion implantation and is located above the semiconductor substrate 1 to isolate the semiconductor substrate from the drift layer; since the heavily doped substrate layer has low resistance and cannot withstand high voltage, the inversion layer 2 can provide a high-resistance drift region to balance the on-resistance and withstand voltage.

[0059] Step three: the electrode connection region 3 is formed by ion implantation, and corresponding ions are implanted at specified positions of the inversion layer 2 to form multiple independent heavily doped electrode regions, which serve as current channels for the source 6 to communicate with the semiconductor substrate 1 and form a good ohmic contact therebetween;

[0060] Step four: the drift layer 4 is formed by epitaxy and is located between the source and the drain to withstand high voltage and optimize the on-resistance, and belongs to a pre-prepared low-doped (lightly doped) region with a specific doping concentration of about 10 14 ~10 15 cm -3 ; wherein the inversion layer 2 and the drift layer 4 together form an active region;

[0061] Step five: the well region 5 is formed by ion implantation or diffusion and is located above the drift layer 4 and corresponds to the positions of the electrode connection region 3 to provide a basis for the source region, and the doping concentration of the well region 5 can reach 10 16 ~10 17 cm -3 ;

[0062] Step six: the drain region 6 is formed by ion implantation and is located at the top of the drift layer and between two adjacent well regions, and an independent high-doped region is formed after ion implantation to communicate with the upper positive metal electrode;

[0063] Step seven: the source region 7 is formed by ion implantation and is located in the middle of the well region, and an independent high-doped region is formed after ion implantation; the specific doping concentration of the drain region 6 and the source region 7 can reach 10 19 ~10 20 cm -3 ;

[0064] Step eight: formation of the gate oxide layer as an insulating medium between the gate and the active region to prevent leakage; specifically, Thermal SiO2 (silicon dioxide generated by thermal oxidation process) is used with a thickness of 24 nm.

[0065] Step nine: gate preparation, the gate is located above the gate oxide layer and corresponds to the drain and source in the reserved multiple gate grooves; specifically, polycrystalline silicon or metal gate (such as TiN, TaN+W) is used;

[0066] Step ten, the first insulating layer protects the gate from damage in subsequent processes;

[0067] Step eleven, the first layer of metallization forms a positive metal electrode;

[0068] Step twelve, the second insulating layer protects the positive metal electrode, achieving front protection, one is passivation protection, preventing metal electrode oxidation, corrosion or mechanical damage, two is to achieve the role of dielectric isolation, reducing the parasitic capacitance between adjacent metal electrodes;

[0069] Step thirteen, the substrate is thinned on the back, mainly to reduce the thickness of the substrate, and then make the product overall thinner to meet the packaging requirements;

[0070] Step fourteen, back metallization forms a substrate metal electrode to provide a connection interface between the chip and the packaging substrate.

[0071] Specifically, in step four, the drift layer is formed by planar MOS process, which simplifies the manufacturing process and reduces the manufacturing cost.

[0072] Specifically, in step thirteen, the substrate is thinned on the back, and the thinned substrate thickness is 325-425μm, which can reduce thermal resistance and improve heat dissipation capacity, and at the same time, it can adapt to packaging requirements and realize the production of thin chip.

[0073] The source-down MOS device prepared by the application forms a double-sided heat dissipation channel by leading the source to the back of the chip and cooperating with the drain on the top. The source on the back of the chip can be in contact with the substrate metal electrode to form an efficient main heat dissipation path, wherein the substrate metal electrode is made of copper or aluminum, which is part of the electrical connection and also the main heat dissipation path. At the same time, the drain on the front can still be used as an auxiliary heat dissipation path. This double-sided heat dissipation design greatly improves the heat management efficiency, which is crucial to meet the development needs of modern electronic equipment miniaturization, high efficiency and high power density.

[0074] Specifically, taking PMOS (or NMOS) as an example, the detailed preparation process is as follows:

[0075] Step one, the preparation of the substrate, selecting an N-type (or P-type) silicon wafer, forming a heavily doped substrate layer by epitaxy of one of the doping processes, i.e. forming an N++ (or P++) substrate;

[0076] Step two, forming a P+ (or N+) inversion layer 2 by epitaxy, which completely covers the substrate layer;

[0077] Step three, implanting phosphorus (or boron) ions to form an N+ (or P+) electrode connection area 3;

[0078] Step four, epitaxial forming N- (or P-) drift layer 4, between the source and the drain, for bearing high voltage;

[0079] Step five, ion implantation or diffusion forming trap region, implanting corresponding ions in the designated position of drift layer 4 to form P+ (or N+) trap region;

[0080] Step six, ion implantation forming drain region, implanting phosphorus (or boron) ions in the top of drift layer 4 and between two adjacent trap regions 5 to form independent high doped region, namely N+ (or P+) drain region;

[0081] Step seven, ion implantation forming source region, implanting phosphorus (or boron) ions in trap region 5 to form high doped region, namely N+ (or P+) source region;

[0082] Step eight, forming gate oxide layer, using Thermal SiO2 material to make, thickness is 24nm;

[0083] Step nine, preparing gate, using polysilicon to make, reserving multiple gate recess grooves, the width of gate recess groove is 650nm;

[0084] Step ten, protecting gate by first insulating layer, using SiO2 or SiOxNy material to make, thickness is 1200nm;

[0085] Step eleven, forming forward metal electrode 11 by first layer metallization, through metal deposition into the gate recess groove corresponding to drain region;

[0086] Step twelve, protecting forward metal electrode by second insulating layer;

[0087] Step thirteen, thinning treatment of the back of the substrate;

[0088] Step fourteen, back metallization forming substrate metal electrode.

[0089] Specifically, in step four, drift layer is formed by plane MOS process.

[0090] Specifically, in step thirteen, the back of the substrate is thinned, and the thickness of the thinned substrate is 325μm-425μm.

[0091] The product prepared by the preparation method has a cell size of 8.8μm-11.6μm; specifically, the doping concentration of each region is reasonably set according to the actual performance requirement.

[0092] It is to be noted that, in the present text, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0093] The above-described embodiments are merely preferred ways of implementing the present application, and are not intended to limit the scope of the present application. Any modification and improvement made by those skilled in the art to the technical solutions of the present application without departing from the design spirit of the present application shall fall within the scope of protection of the present application.

Claims

1. A source-down MOS device based on planar MOS technology, characterized in that: It includes a semiconductor substrate (1), an active region and a gate region, wherein the active region is formed on the surface of the semiconductor substrate and the gate region is located above the active region; The active region is provided with a drain (6) and a source (7). The drain (6) located on the upper side is electrically connected to the front side of the chip through a positive metal electrode (11), which is located in the gate region. The source (7) located on the other side is connected to the semiconductor substrate (1) through an electrode connection region (3) and forms a good ohmic contact. The electrode connection region (3) is located in the inversion layer (2) provided on the top of the semiconductor substrate (1). The bottom of the semiconductor substrate (1) is provided with a substrate metal electrode (13) for lead-out.

2. The source-down MOS device based on planar MOS technology according to claim 1, characterized in that: The active region includes the entire region consisting of the inversion layer (2) and the drift layer (4), the electrode connection region (3) is epitaxially formed to form the drift layer (4), and the inversion layer (2) is an isolation layer formed by epitaxy, diffusion or ion implantation.

3. The source-down MOS device based on planar MOS technology according to claim 2, characterized in that: The semiconductor substrate (1) is made of single-crystal semiconductor material and is a heavily doped substrate layer. The inversion layer (2) is a highly doped isolation layer, and the drift layer (4) is a lightly doped epitaxial layer.

4. The source-down MOS device based on planar MOS technology according to claim 2, characterized in that: The drift layer (4) is provided with multiple well regions (5), the source electrode (7) is located in the well region (5) and corresponds one-to-one with the position of the electrode connection region (3) below; the drain electrode (6) is located on the top of the drift layer (4) and is located between any two adjacent source electrodes (7).

5. The source-down MOS device based on planar MOS technology according to claim 4, characterized in that: The gate region includes a gate oxide layer (8), a gate (9), and a gate insulating layer (10) arranged in sequence. The gate oxide layer (8) is located above the drift layer (4). The gate (9) is located above the gate oxide layer (8), and a plurality of gate grooves are reserved corresponding to the drain (6) and the source (7). The gate insulating layer (10) fills and covers the gate (9). After the gate insulating layer (10) is connected, the gate groove corresponding to the source (7) is completely closed. The positive metal electrode (11) is disposed in the gate groove corresponding to the drain (6), and a second insulating layer (12) is disposed at the positive metal electrode (11).

6. The source-down MOS device based on planar MOS technology according to claim 5, characterized in that: The gate oxide layer (8) is made of Thermal SiO2 and has a thickness of 24 nm; the gate (9) is made of polysilicon or metal, specifically Pt, Pd, NiSi or CoSi, and has a thickness of 450 nm; the gate insulating layer (10) is made of SiO2 or SiOxNy and has a thickness of 1200 nm.

7. A method for fabricating a source-down MOS device based on planar MOS technology as described in any one of claims 1-6, characterized in that: Includes the following steps: Step 1: Substrate fabrication. First, select a P-type or N-type silicon wafer as the substrate material according to the fabrication type. Second, after selecting the silicon wafer, form a heavily doped substrate layer through a doping process. Step 2: Epitaxy, diffusion or ion implantation to form an inversion layer. The inversion layer is located above the semiconductor substrate and is used to isolate the semiconductor substrate from the drift layer. Step 3: Ion implantation to form electrode connection regions. According to the product type, corresponding ions are implanted to form multiple independent heavily doped electrode regions, which become current channels for connecting the source and the substrate. Step 4: An epitaxial drift layer is formed between the source and drain electrodes to withstand high voltage. Step 5: Ion implantation or diffusion forms a trap region, located on the drift layer and with a position corresponding to the electrode connection region, providing a basis for source region formation; Step 6: Ion implantation forms a drain region, located at the top of the drift layer and between two adjacent well regions. After ion implantation, an independent highly doped region is formed, which is used to connect with the positive metal electrode above. Step 7: Ion implantation to form a source region, located in the middle of the trap region, forming an independent highly doped region after ion implantation; Step 8: Formation of the gate oxide layer, which serves as an insulating medium between the gate and the active region to prevent leakage. Step 9: Gate fabrication, wherein the gate is located above the gate oxide layer and the reserved gate recesses correspond to the drain and source. Step 10: The first insulating layer protects the gate. Step 11: First layer metallization to form a positive metal electrode; Step 12: The second insulating layer protects the positive metal electrode; Step 13: Thinning the back side of the substrate; Step 14: Metallize the back side to form the substrate metal electrode.

8. The preparation method according to claim 7, characterized in that: In step four, the drift layer is formed using a planar MOS process.

9. The preparation method according to claim 7, characterized in that: In step thirteen, the back side of the substrate is thinned, and the thickness of the thinned liner is 325μm to 425μm.

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