Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The invention provides a semiconductor device and a preparation method thereof, and electronic equipment, relates to the technical field of semiconductors, and aims to solve the problem that the performance of the device is affected due to the fact that the cellular size is difficult to reduce. The semiconductor device comprises a substrate, a first electrode and a second electrode which are located on the two sides of the substrate, and an epitaxial layer, a conductive well layer, a doped layer, a gate oxide layer and a gate which are located between the substrate and the first electrode. The epitaxial layer comprises two inclined planes which are oppositely arranged, the conductive well layer comprises two channel regions which are arranged at intervals and are in contact with the two inclined planes, and the doping layer comprises two doping parts which are in contact with the two channel regions respectively; the gate oxide layer at least covers the two channel regions; the semiconductor device is applied to a semiconductor power device, the cell size can be reduced, and the channel carrier mobility is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and an electronic device. Background Technology

[0002] Due to the superior physical and electrical properties of silicon carbide (SiC) semiconductor materials, such as a large bandgap, high critical breakdown field strength, high thermal conductivity, and high carrier saturation drift velocity, SiC semiconductor devices, such as SiC metal-oxide-semiconductor field-effect transistors (MOSFETs), are commonly used in high-temperature, high-frequency, and high-power devices, including SiC power devices. Currently, SiC power devices have broad application prospects in fields such as new energy vehicles, renewable energy, rail transportation, and smart grids. Summary of the Invention

[0003] The embodiments of this disclosure provide a semiconductor device and a method for fabricating the same, as well as an electronic device, aimed at solving the problem of how to reduce the cell size of a semiconductor device and improve the channel carrier mobility.

[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0005] On one hand, a semiconductor device is provided. The semiconductor device includes a substrate, a first electrode and a second electrode disposed on opposite sides of the substrate, an epitaxial layer, a conductive well layer, a doped layer, a gate oxide layer and a gate electrode sequentially disposed between the first electrode and the substrate along a first direction, wherein the first direction is the direction from the substrate to the first electrode.

[0006] The epitaxial layer includes a first part, a second part, and a third part arranged sequentially along the first direction; the second part includes a first inclined surface and a second inclined surface arranged opposite to each other along a second direction, the second direction being perpendicular to the first direction; the first inclined surface has a first acute angle with the plane where the substrate is located, and the second inclined surface has a second acute angle with the plane where the substrate is located.

[0007] The conductive well layer includes a first well portion and a second well portion spaced apart along the second direction, and the second and third portions of the epitaxial layer are disposed together between the first well portion and the second well portion; wherein, the first well portion includes a first channel region, the first channel region is in contact with the first inclined surface and has the same extension direction; the second well portion includes a second channel region, the second channel region is in contact with the second inclined surface and has the same extension direction.

[0008] The doped layer includes a first doped portion and a second doped portion, wherein the first doped portion is disposed on the side of the first channel region away from the second channel region and in contact with the first channel region, and the second doped portion is disposed on the side of the second channel region away from the first channel region and in contact with the second channel region.

[0009] The gate oxide layer covers at least the first channel region and the second channel region.

[0010] The semiconductor device provided in the above embodiments of this disclosure has a channel region extending obliquely relative to the plane of the substrate. While keeping the channel width constant, this effectively reduces the cell size of the semiconductor device and increases the cell density, thereby enabling the crystal plane corresponding to the channel region to achieve optimal channel carrier mobility. Furthermore, because the channel region extends obliquely, the contact area between the channel and the gate oxide layer is increased, resulting in a more uniform electric field distribution at the bottom of the gate oxide layer, reducing the gate oxide electric field, improving gate oxide reliability, and thus enhancing the reliability of the semiconductor device.

[0011] In some embodiments, the first acute angle is in the range of 10°-80°, and the second acute angle is in the range of 10°-80°.

[0012] In some embodiments, the dimensions of the first channel region along its extension direction are in the range of 0.1 μm to 2.0 μm, and the dimensions of the second channel region along its extension direction are in the range of 0.1 μm to 2.0 μm.

[0013] In some embodiments, the first part of the epitaxial layer includes at least a drift layer, and the third part includes a JFET region.

[0014] In some embodiments, at least the second part of the first, second, and third portions of the epitaxial layer includes a current spreading layer.

[0015] In some embodiments, the first part includes the drift layer and a portion of the current spreading layer near the drift layer, and the second part includes the remaining portion of the current spreading layer.

[0016] In some embodiments, the drift layer is an N-drift layer, the current spreading layer is an N+ current spreading layer, and the JFET region is an N JFET region; the conductive well layer is a P conductive well layer; the first doped portion includes a first N+ doped region and a first P+ doped region sequentially disposed along the direction from the second doped portion to the first doped portion, and the second doped portion includes a second N+ doped region and a second P+ doped region sequentially disposed along the direction from the first doped portion to the second doped portion.

[0017] In some embodiments, the epitaxial layer is made of silicon carbide.

[0018] On the other hand, a method for fabricating a semiconductor device is provided, comprising:

[0019] Provide substrate;

[0020] An initial epitaxial layer is formed on one side of the substrate;

[0021] The initial epitaxial layer is etched to give the initial epitaxial layer a first initial slope and a second initial slope disposed opposite to each other along a second direction. The first initial slope has a first acute angle with the plane where the substrate is located, and the second initial slope has a second acute angle with the plane where the substrate is located. The second direction is a direction parallel to the plane where the substrate is located.

[0022] Ion implantation is performed on the etched initial epitaxial layer to form an initial conductive well layer including a first initial well portion and a second initial well portion; the first initial well portion and the second initial well portion are spaced apart along the second direction; the first initial well portion includes a first channel region having the same extension direction as the first initial slope; the second initial well portion includes a second channel region having the same extension direction as the second initial slope; the portion of the initial epitaxial layer in which the first initial well portion and the second initial well portion are not formed forms an epitaxial layer;

[0023] Ion implantation is performed on the initial conductive well layer to form a first doped portion that contacts the first channel region and a second doped portion that contacts the second channel region in the first initial well portion and the second initial well portion, respectively, to obtain a doped layer; the portion of the first initial well portion in which the first doped portion is not formed is the first well portion, and the portion of the second initial well portion in which the second doped portion is not formed is the second well portion, and the first well portion and the second well portion constitute a conductive well layer;

[0024] A gate oxide layer and a gate electrode are sequentially formed on the side of the doped layer away from the substrate, wherein the gate oxide layer at least covers the first channel region and the second channel region;

[0025] A first electrode is formed on the side of the gate away from the substrate; and

[0026] A second electrode is formed on the other side of the substrate.

[0027] In some embodiments, an initial epitaxial layer is formed on one side of the substrate, comprising:

[0028] An initial film layer is obtained by epitaxial growth on one side of the substrate, and ion doping is performed simultaneously with the epitaxial growth to obtain a drift layer and an initial current spreading layer. The doping concentration of the portion of the initial film layer near the substrate is different from the doping concentration of the portion of the initial film layer away from the substrate. The initial epitaxial layer includes the drift layer and the initial current spreading layer.

[0029] In some embodiments, etching the initial epitaxial layer to give the initial epitaxial layer a first initial bevel and a second initial bevel disposed opposite each other along a second direction includes:

[0030] The initial current spreading layer is etched to form the first initial bevel and the second initial bevel on the surface of the initial current spreading layer.

[0031] In some embodiments, after ion implantation is performed on the etched initial epitaxial layer to form an initial conductive well layer including a first initial well portion and a second initial well portion, the fabrication method further includes:

[0032] Ion implantation is performed on the portion of the initial current spread layer located between the first initial well and the second initial well to obtain a JFET region; the portion of the initial current spread layer in which the JFET region is not formed is the current spread layer.

[0033] On the other hand, an electronic device is provided, including a semiconductor device.

[0034] It is understood that the beneficial effects of the semiconductor device fabrication method and electronic device provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor device described above, and will not be repeated here. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below.

[0036] Figure 1 This is a schematic diagram of the structure of an electronic device according to some embodiments;

[0037] Figure 2 Provided according to some embodiments Figure 1 A schematic diagram of the structure of a chip in an electronic device is shown.

[0038] Figure 3 This is a schematic diagram of the structure of a semiconductor device provided according to some examples;

[0039] Figure 4 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 1 ;

[0040] Figure 5 This is a schematic diagram of the structure of a semiconductor device according to some embodiments;

[0041] Figure 6 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 2 ;

[0042] Figures 7-21 This is a step diagram of a method for fabricating a semiconductor device according to some embodiments. Detailed Implementation

[0043] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0044] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0045] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0046] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0047] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0048] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0049] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0050] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0051] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0052] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0053] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and that “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0054] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0055] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0056] The technical terms used in the embodiments of this disclosure are explained below:

[0057] Semiconductor: A semiconductor is a material whose conductivity at room temperature is between that of a conductor and an insulator; semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities or defects, in which the concentration of electrons and holes is equal, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an intrinsic semiconductor. Among them, when the impurities doped into an impurity semiconductor can provide a certain concentration of charge carriers (such as holes or electrons), the impurity semiconductor doped with impurities that provide electrons (such as pentavalent phosphorus) is also called an electron-type semiconductor or an N (negative) type semiconductor, and the impurity semiconductor doped with impurities that provide holes (such as trivalent boron) is also called a hole-type semiconductor or a P (positive) type semiconductor, it can improve the conductivity of the intrinsic semiconductor. Generally, the higher the charge carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity. In the embodiments of this disclosure, this type of impurity semiconductor is also called a conductive semiconductor, for example, a conductive silicon carbide material doped with impurities such as nitrogen (N), boron (B), and aluminum (Al). Furthermore, when impurities doped into an impurity semiconductor can compensate for impurities, the donor electrons are just enough to fill the acceptor level, but cannot provide electrons and holes to the conduction and valence bands, resulting in a semiconductor material with a wide bandgap having a resistivity similar to that of an insulator. For example, in the embodiments of this disclosure, doping silicon carbide with transition metals achieves impurity compensation, thereby increasing the resistivity of the silicon carbide material. This type of impurity semiconductor is also called a semi-insulating semiconductor or a semi-insulator, or has semi-insulating characteristics.

[0058] Unless otherwise defined, all technical terms used herein have the same meaning as commonly known to those skilled in the art. In this disclosure, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple. Furthermore, in embodiments of this disclosure, the terms "first," "second," etc., do not limit the quantity or order.

[0059] Furthermore, in this disclosure, directional terms such as "upper" and "lower" are defined relative to the indicated placement of the components in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the placement of the components in the accompanying drawings.

[0060] It should be noted that in this disclosure, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this disclosure should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0061] It should be noted that the attached diagrams (e.g.) Figure 6 The 151 / 15 appearing in the figure indicates that both the first well portion 151 and the conductive well layer 15 can refer to the structure shown, and the first well portion 151 belongs to the conductive well layer 15. Other similar reference numerals appearing in the figures also follow the above description.

[0062] Due to its superior physical and electrical properties, such as large bandgap, high critical breakdown field strength, high thermal conductivity, and high carrier saturation drift velocity, silicon carbide (SiC) semiconductor material has become a crucial foundational material for the development of the third-generation semiconductor industry. Compared to traditional silicon-based devices, silicon carbide power devices, with their excellent high-voltage resistance, high-temperature resistance, and low-loss performance, are applied in fields such as new energy vehicles, renewable energy, rail transportation, and smart grids.

[0063] This disclosure provides an electronic device that can be applied to products or components with power conversion functions, such as photovoltaic inverters, power conversion systems and drive systems for electric vehicles, traction converters in rail transit, charging devices for mobile phones, and power adapters for laptops. The electronic device can also be different types of user equipment or terminal equipment, such as laptops, tablets, mobile phones, wearable devices, and in-vehicle equipment, or it can be a power amplifier device used in the aforementioned electronic devices. It should be understood that the electronic device 1 can also be a device or component with signal receiving / transmitting functions in equipment such as amplifiers, modulators, base stations, and radars. This disclosure does not impose any special limitations on the specific form of the electronic device 1 described above.

[0064] The following uses an electronic device with power conversion function as an example to illustrate some embodiments of this disclosure. However, the implementation of this disclosure is not limited to this, and any other display device can be considered as long as the same technical concept is applied.

[0065] Figure 1 This is a schematic diagram of the structure of an electronic device according to some embodiments. Figure 1 As shown, the electronic device 1000 includes, for example, a chip 100 and a circuit board 200, with the chip 100 disposed on the circuit board 200, and the circuit board 200 configured to supply power to the chip 100 and transmit signals.

[0066] Figure 2 Provided according to some embodiments Figure 1 The diagram shows a schematic representation of the structure of a chip in an electronic device. For example, such as... Figure 2 As shown, the chip 100 includes, for example, a semiconductor device 1 and a packaging substrate 2, and the semiconductor device 1 is coupled to the packaging substrate 2.

[0067] Here, semiconductor device 1 can be a silicon carbide (SiC) semiconductor device, such as a metal oxide semiconductor field effect transistor (MOSFET).

[0068] In some examples, the SiC MOSFET is an N-type SiC MOSFET or a P-type SiC MOSFET. The following example uses an N-type SiC MOSFET to introduce this semiconductor device.

[0069] Figure 3 This is a schematic diagram of the structure of a semiconductor device provided based on some examples. For example... Figure 3As shown, the cell structure of SiCMOSFET 1001 includes: an N+ substrate 001, an N-drift layer 002 sequentially disposed on one side of the N+ substrate 001, two P-well regions 003, an N+ region 004 and a P+ region 005 symmetrically disposed on the left and right sides, a gate oxide layer 006, a gate 007, a gate dielectric layer 008 and a source 009, and a drain 010 disposed on the other side of the N+ substrate 001. When the SiC MOSFET 1001 is working, a voltage is applied between the gate 007 and the source 009. An inversion layer is formed on the surface of the p-well region 003 below the gate oxide layer 006, forming an electron channel, namely the N-type channel 012. Electrons pass from the source 009 through the N+ region 004, the P-well region 003, the junction field-effect transistor (JFET) region 011 between the two P-well regions 003, and then through the N-drift layer 002 to the drain 010, thereby turning on the source 009 and the drain 010.

[0070] for Figure 3 The SiC MOSFET structure shown has an inversion layer parallel to the plane of the substrate, forming a planar channel. This limits the reduction of the cell pitch of the semiconductor device to some extent. In addition, the SiC / SiO2 interface state density of this structure is extremely high. Coulomb scattering at the interface will cause a decrease in the channel carrier mobility of the MOSFET, which will greatly affect the electrical performance of the semiconductor device. Furthermore, in the blocking state, due to the high breakdown voltage, an electric field concentration will occur at the bottom of the gate oxide layer 006, especially at the sharp corners where the gate oxide layer 006 connects to the P-well region 003, the N+ region 004, and the JFET region 011, which can easily lead to local breakdown and affect the reliability of the semiconductor device.

[0071] Based on this, the present disclosure provides a semiconductor device to solve the aforementioned technical problems. Figure 4 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 1 .like Figure 4 As shown, the cell structure of semiconductor device 1 includes: a substrate 11, a first electrode 12 and a second electrode 13 disposed on opposite sides of the substrate 11, and an epitaxial layer 14, a conductive well layer 15, a doped layer 16, a gate oxide layer 17 and a gate 18 disposed sequentially between the first electrode 12 and the substrate 11 along a first direction X.

[0072] The first direction X is the direction from the substrate 11 to the first electrode 12.

[0073] For example, substrate 11 can be a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, etc.

[0074] For example, the first electrode 12 is the source electrode and the second electrode 13 is the drain electrode.

[0075] like Figure 4 As shown, the epitaxial layer 14 includes a first part, a second part, and a third part sequentially disposed along a first direction X; the second part includes a first inclined surface 141 and a second inclined surface 142 disposed opposite to each other along a second direction Y, the second direction Y being perpendicular to the first direction X. The first inclined surface 141 has a first acute angle α1 with the plane containing the substrate 11, and the second inclined surface 142 has a second acute angle α2 with the plane containing the substrate 11.

[0076] For example, the first acute angle α1 is equal to the second acute angle α2, and the first inclined plane 141 and the second inclined plane 142 are two mirror-symmetric inclined planes.

[0077] like Figure 4 As shown, the conductive well layer 15 includes a first well portion 151 and a second well portion 152 spaced apart along the second direction Y, and the second and third portions of the epitaxial layer 14 are disposed between the first well portion 151 and the second well portion 152. For example, the longitudinal section of the second portion of the epitaxial layer 14 is an isosceles trapezoid, and the third portion is rectangular; the portions connecting the two have the same dimensions, i.e., the length of the rectangle (e.g., ...). Figure 4 The first direction shown has the same dimensions as the upper base of the isosceles trapezoid.

[0078] The first well portion 151 includes a first channel region 1511, which contacts the first inclined surface 141 and has the same extending direction. It is understood that the first well portion 151 may also include a first straight region, which is located on the side of the first channel region 1511 away from the second well portion 152 and contacts the first channel region 1511. The size of the first straight region along the first direction X is smaller than the size of the first channel region 1511 along the first direction X.

[0079] The second well portion 152 includes a second channel region 1521, which contacts the second inclined surface 142 and has the same extending direction. It is understood that the second well portion 152 may also include a second straight region, located on the side of the second channel region 1521 opposite to the first well portion 151 and in contact with the second channel region 1521, and the dimension of the second straight region along the first direction X is smaller than the dimension of the second channel region 1521 along the first direction X.

[0080] The doped layer 16 includes a first doped portion 161 and a second doped portion 162. The first doped portion 161 is disposed on the side of the first channel region 1511 away from the second channel region 1521 and contacts the first channel region 1511. The second doped portion 162 is disposed on the side of the second channel region 1521 away from the first channel region 1511 and contacts the second channel region 1521. It is understood that both the first doped portion 161 and the second doped portion 162 will contact the first electrode 12. For example, ohmic contacts can be formed between the first doped portion 161 and the second doped portion 162 and the first electrode 12, respectively. Figure 4 (Not shown in the image) to ensure the input and output of current.

[0081] A gate oxide layer 17 is disposed between the conductive well layer 15, the doped layer 16, the epitaxial layer 14, and the gate 18. For example, the gate oxide layer 17 may be disposed between the first channel region 1511 and the second channel region 1521 of the conductive well layer 15, the first doped portion 161 and the second doped portion 162 of the doped layer 16, and the epitaxial layer 14 and the gate 18. The gate oxide layer 17 at least covers the first channel region 1511 and the second channel region 1521, for example, it may cover the first channel region 1511 and the second channel region 1521, a third portion of the epitaxial layer 14, and portions of the first doped portion 161 and the second doped portion 162. The material of the gate oxide layer 17 includes, for example, insulating materials such as silicon oxide and hafnium oxide.

[0082] In the semiconductor device provided in this embodiment, when a voltage is applied between the gate 18 and the first electrode (e.g., source) 12, an inversion layer is formed on the surface of the conductive well layer 15 below the gate oxide layer 17, constituting an electron channel. That is, the first channel region 1511 and the second channel region 1521 serve as channels for electron flow, such that electrons on the left side of the semiconductor device pass sequentially from the first electrode (e.g., source) 12 through the first doped portion 161, the first channel region 1511, and the JFET region 19 between the first channel region 1511 and the second channel region 1521, and on the right side of the semiconductor device, electrons pass sequentially from the first electrode 12 through the second doped portion 162, the second channel region 1521, and the JFET region 19 between the first channel region 1511 and the second channel region 1521, and then from the JFET region 19 through the epitaxial layer 14 to the second electrode (e.g., drain) 13, thereby achieving conduction between the first electrode and the second electrode, and current flows from the second electrode to the first electrode.

[0083] Because the semiconductor device provided in this embodiment has a channel region that extends obliquely relative to the plane where the substrate 11 is located, compared to Figure 3The semiconductor device shown can effectively reduce the cell pitch and increase the cell density of the semiconductor device while keeping the channel width unchanged, so that the crystal plane corresponding to the channel region can achieve the optimal channel carrier mobility.

[0084] Meanwhile, with the same cell pitch, the increased channel length due to its oblique extension allows for better shielding of the electric field reaching the JFET region during reverse breakdown. This means the electric field at the bottom of the gate oxide layer 17 is dispersed, resulting in a more uniform electric field distribution. This reduces the gate oxide electric field, enhances breakdown voltage performance, and reduces the likelihood of localized breakdown. Furthermore, since the gate oxide layer above the channel and the gate oxide layer above the JFET region are located on different crystal planes, the corresponding crystal plane of the channel region exhibits higher channel carrier mobility, thereby improving gate oxide reliability and enhancing the overall reliability of the semiconductor device.

[0085] Figure 5 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. In some embodiments, Figure 5 This illustrates a semiconductor device with channels designed in an oblique distribution, such as... Figure 5 As shown, the cell structure of the active region of the SiC MOSFET 5, from bottom to top (first direction X in the figure), consists of a drain (not shown), an n++ substrate 51, an n-drift layer 52, two symmetrically arranged p-well layers 53, a p++ region 54 and an n++ region 55, and a source electrode (not shown). The p-well layers 53 are both curved upwards on opposite sides. Above the curved portion of the p-well layers 53 is a secondary epitaxial p-type layer 56 inclined towards the vertical central axis of the cell structure. An implanted n-layer 57 is located between the two secondary epitaxial p-type layers 56. Above the secondary epitaxial p-type layers 56 and the implanted n-layer 57 are, in sequence, an arched gate oxide layer 58, a polysilicon layer 59, and an isolation passivation layer (not shown in the figure). This MOSFET structure forms a sloping channel on the high-quality secondary epitaxial SiC surface to improve the quality of the MOS gate and channel mobility, and reduce the on-resistance of the device. However, the fabrication process of this MOSFET structure is very complex. It requires the formation of an n-drift layer through epitaxy, followed by the growth of a P-type layer through a secondary epitaxy method, and then thermal oxidation to form a MOS gate structure. This ensures that a channel can be formed when a voltage is applied to the gate, allowing electrons to pass through the channel to the drain and thus enabling the MOSFET to conduct.

[0086] Secondary epitaxy refers to a further epitaxial growth process performed on an already grown semiconductor material (primary epitaxy). Secondary epitaxy is not only complex and difficult to control, but it also introduces new defects to the interface, thus affecting the interface state density.

[0087] Compared to Figure 5 The semiconductor device shown in this embodiment does not require additional complex processes during its fabrication. It only requires patterning the epitaxial layer formed in the first epitaxial layer to give the patterned epitaxial layer a slanted side surface. This allows the surface of the P-well layer formed above the epitaxial layer that contacts the gate oxide layer to form a slanted channel region. The fabrication process is simple and easy to operate.

[0088] In some embodiments, reference Figure 4 As shown, the included first acute angle α1 and the included second acute angle α2 can be in the range of 10° to 80°. For example, the included first acute angle α1 and the included second acute angle α2 can be 10°, 20°, 30°, 50° or 80°, etc.

[0089] In some embodiments, reference Figure 4 As shown, the dimensions of the first channel region 1511 along its extension direction and the dimensions of the second channel region 1521 along its extension direction can be in the range of 0.1 μm to 2.0 μm. This arrangement ensures sufficient channel length. For example, the lengths of the first channel region 1511 and the second channel region 1521 can be 0.1 μm, 0.3 μm, 0.5 μm, 1.0 μm, 1.6 μm, or 2.0 μm, etc.

[0090] In some embodiments, the material of the epitaxial layer 14 may include silicon carbide (SiC). Silicon carbide has advantages such as a wide bandgap, high critical breakdown field strength, high saturated electron mobility, high melting point, and high thermal conductivity. Using silicon carbide as the epitaxial material can provide semiconductor devices with lower on-resistance and higher dielectric breakdown voltage, thus making it easier to meet the requirements of high-performance power devices. Of course, the material of the epitaxial layer 14 may also include nitride semiconductor materials such as gallium nitride, and this embodiment does not limit this.

[0091] It is understood that the materials of the substrate 11 and the epitaxial layer 14 can be the same or different. For example, the materials of the substrate 11 and the epitaxial layer 14 can both be silicon carbide.

[0092] In some embodiments, such as Figure 4 As shown, an interlayer dielectric layer 20 is further disposed between the gate 18 and the first electrode 12. For example, the interlayer dielectric layer 20 may be disposed between the gate 18, the gate oxide layer 17, the doped layer 16, and the first electrode 12. The material of the interlayer dielectric layer 20 may be an insulating material such as silicon oxide, silicon nitride, or hafnium oxide.

[0093] In some embodiments, such as Figure 4As shown, the epitaxial layer 14 is located between the substrate 11 and the conductive well layer 15, which is used to form a channel when the semiconductor device is in operation. The epitaxial layer 14 may have the same doping type as the substrate 11, for example, both are N-doped or both are P-doped.

[0094] Figure 6 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 2 In some examples, such as Figure 6 As shown, the epitaxial layer 14 may include a drift layer 1041, a current stretching layer (CSL) 1042, and a JFET region 19. In this case, in the first, second, and third portions of the epitaxial layer 14, the first portion includes the drift layer 1041, the second portion includes the current stretching layer 1042, and the third portion includes the JFET region 19. Alternatively, in other examples, the first portion includes a portion of the drift layer 1041 and the current stretching layer 1042, the second portion includes the remaining portion of the current stretching layer 1042, and the third portion includes the JFET region 19.

[0095] In other examples, epitaxial layer 14 may include drift layer 1041 and JFET region 19. In this case, in the first, second and third parts of epitaxial layer 14, the first and second parts include drift layer 1041, and the third part includes JFET region 19.

[0096] Here, the drift layer 1041, the current spreading layer 1042, and the JFET region 19 have the same doping type, for example, all are N-doped. For example, the doping concentration of the current spreading layer 1042 can be greater than the doping concentration of the drift layer 1041. Again, for example, the doping concentration of the JFET region 19 can be greater than the doping concentration of the current spreading layer 1042.

[0097] It should be noted that the current spreading layer 1042 is a highly conductive structure. The current spreading layer 1042 can widen the current path, allowing the current to be distributed more evenly to the working area of ​​the device, thereby improving the performance of the semiconductor device.

[0098] The following example uses an N-type MOSFET, combined with... Figure 6The semiconductor device provided in the embodiments of this disclosure will be described. The semiconductor device 1 may include an N+ substrate 11, an N epitaxial layer 14 (including an N- drift layer 1041, an N+ current spreading layer 1042, and an N JFET region 19) sequentially disposed along a first direction X, a P-conductive well layer 15, a doped layer 16, a gate oxide layer 17, and a gate 18. The P-conductive well layer 15 includes a first P-well portion 151 and a second P-well portion 152. The doped layer 16 includes a first doped portion 161 located above the first P-well portion 151 and a second doped portion 162 located above the second P-well portion 152. The first doped portion 161 includes a first N+ doped region 1611 near the first channel region 1511 and a first P+ doped region 1612 away from the first channel region 1511. The second doped portion 162 includes a second N+ doped region 1621 near the second channel region 1521 and a second P+ doped region 1622 away from the second channel region 1521. The gate oxide layer 17 covers at least the first trench region 1511 and the second trench region 1521.

[0099] In this embodiment, by designing the channel as a sloped channel, the cell pitch of the semiconductor device can be effectively reduced while maintaining the same channel width, thereby increasing the cell density and enabling the crystal plane corresponding to the channel region to achieve optimal channel carrier mobility. Simultaneously, the gate oxide electric field can be reduced, thus improving gate oxide reliability. Furthermore, the addition of the current spreading layer widens the current path, allowing the current to be evenly distributed across the operating region of the device, reducing current concentration effects, and thus improving the performance of the semiconductor device.

[0100] It is understood that the above description uses an N-channel MOSFET as an example, but this is only for illustrative purposes. The technical solutions described in the embodiments of this disclosure are also applicable to P-channel semiconductor devices. For example, a P-channel semiconductor device may have dopants of the opposite type to those in the N-channel semiconductor device examples. In some embodiments, the P-channel semiconductor device has the same structure and the same doping concentration as described in the examples of this disclosure, but with the opposite dopant type (e.g., P-regions instead of N-regions, N+ regions instead of P+ regions, etc.).

[0101] Figures 7-21 This is a step diagram illustrating a method for fabricating a semiconductor device according to some embodiments. For example... Figures 7-21 As shown, this disclosure provides a method for fabricating a semiconductor device, which can be used to fabricate the semiconductor device 1 provided in any of the above embodiments. The method includes the following steps.

[0102] S1: As Figure 7 As shown, a substrate 11 is provided.

[0103] For example, substrate 11 can be a silicon substrate or a silicon carbide substrate.

[0104] S2: As Figure 8 As shown, an initial epitaxial layer 140 is formed on one side of the substrate 11.

[0105] For example, in embodiments of this disclosure, an epitaxial growth process may be used to grow an initial epitaxial layer 140 on one side of a substrate 11.

[0106] For example, the materials forming the substrate 11 and the initial epitaxial layer can both include wide-bandgap semiconductor materials, such as silicon carbide. The substrate 11 and the initial epitaxial layer 140 have the same doping type, but the doping concentration of the initial epitaxial layer 140 is less than that of the substrate 11. For example, the substrate 11 is N-type heavily doped (N+) silicon carbide, and the initial epitaxial layer 140 is N-type lightly doped (N-) silicon carbide. Thus, the initial epitaxial layer 140 can be directly epitaxially grown on the substrate 11 without switching the doping type. The substrate 11 uses a high doping concentration (low resistance) to serve as a mechanical support and current path, while the initial epitaxial layer 140 uses a low doping concentration. In this way, the epitaxial layer 14 in the fabricated semiconductor device can withstand high voltage and form a wider depletion layer, thereby dispersing the electric field intensity, preventing breakdown, and improving the breakdown voltage capability of the semiconductor device. The doping concentration and growth thickness of the initial epitaxial layer 140 can be controlled according to the design parameters of the semiconductor device, such as the breakdown voltage.

[0107] S3: As Figure 9 As shown, a first mask is used to etch an initial epitaxial layer 140 so that the initial epitaxial layer 140 has a first initial inclined surface 1401 and a second initial inclined surface 1402 disposed opposite to each other along the second direction Y. The first initial inclined surface 1401 has a first acute angle α1 with the plane where the substrate 11 is located, and the second initial inclined surface has a second acute angle α2 with the plane where the substrate is located. The second direction Y is a direction parallel to the plane where the substrate 11 is located.

[0108] Here, the material of the first mask is not limited in the embodiments disclosed herein. For example, the first mask may be photoresist.

[0109] For example, the initial epitaxial layer 140 can be etched using ICP (Inductively Coupled Plasma Etching). For instance, etching gases such as SF6 / O2 can be used.

[0110] For example, the initial epitaxial layer 140 is made of SiC, and the first mask is made of photoresist. The first mask is used to protect the initial epitaxial layer 140. The area of ​​the initial epitaxial layer exposed by the first mask is etched. The etching depth and the angle of the first initial slope 1401 and the second initial slope 1402 (i.e., the first acute angle α1 and the second acute angle α2) can be controlled by controlling the morphology of the photoresist and the SiC / photoresist selectivity ratio.

[0111] For example, by controlling the morphology of the photoresist and the SiC / photoresist selectivity ratio, the first acute angle α1 and the second acute angle α2 are controlled within the range of 10°-80°, and the lengths of the first initial slope 1401 and the second initial slope 1402 are controlled within the range of 0.1μm to 2.0μm.

[0112] For example, the etching shape of SiC can be designed such that the first acute angle α1 and the second acute angle α are equal, and the lengths of the first initial inclined plane 1401 and the second initial inclined plane 1402 are also equal.

[0113] S4: As Figure 10 As shown, an ion implantation is performed on the etched initial epitaxial layer using a second mask to form an initial conductive well layer 150 including a first initial well portion 1510 and a second initial well portion 1520. The first initial well portion 1510 and the second initial well portion 1520 are spaced apart along a second direction Y. The first initial well portion 1510 includes a first channel region 1511, which has the same extension direction as the first initial slope 1401. The second initial well portion 1520 includes a second channel region 1521, which has the same extension direction as the second initial slope 1402. The portion of the initial epitaxial layer where the first initial well portion 1510 and the second initial well portion 1520 are not formed forms an epitaxial layer 14.

[0114] The second mask can be a dielectric material or a photoresist. For example, a mask layer (referred to as the first mask layer) can be first formed using SiO2. This first mask layer is then etched using a photomask, a fluorine-based gas such as CF4, and O2 to form a SiO2 mask pattern, thus forming the second mask. During the etching process, the morphology of the SiO2 mask pattern can be controlled by adjusting the SiO2 / photoresist etching selectivity ratio. Here, the thickness of the first mask layer must be sufficient to block the energy of ion implantation.

[0115] Then, the etched initial epitaxial layer is protected by a second mask. For example, the top surface 1403 between the first initial slope 1401 and the second initial slope 1402 of the etched initial epitaxial layer is masked so that ion implantation is performed on the portion of the etched initial epitaxial layer other than the top surface 1403.

[0116] For example, during the ion implantation process in step S4, the doping types of the first channel region 1511 and the second channel region 1521 are opposite to the doping types of the initial epitaxial layer 140. For instance, the initial epitaxial layer 140 is doped with N-type, while the first channel region 1511 and the second channel region 1521 are doped with P-type. This allows the final semiconductor device to form an inversion layer during operation, creating channels for electron flow.

[0117] For example, in step S4, the doping type is P-type, and the implanted ions can be P-type ions. For instance, doped materials containing trivalent elements such as Al or B can be selected for ion implantation. The depth and concentration of ion implantation are related to the design of the threshold voltage of the semiconductor device.

[0118] For example, the ion implantation depth ranges from 0.3 to 1.5 μm, and the doping concentration during the ion implantation process is in the range of 1E¹² cm⁻¹. -3 Up to 1E16cm -3 Within the range.

[0119] Here, since the shape of the initial epitaxial layer 140 after etching in step S3 is already determined, after ion implantation in step S4, a first channel region 1511 with the same extension direction as the first initial slope 1401, the same length, and the same first acute angle α1 can be formed, as well as a second channel region 1521 with the same extension direction as the second initial slope 1402, the same length, and the same second acute angle α2.

[0120] S5: As Figures 10 to 12 As shown, ion implantation is performed on the initial conductive well layer 150 to form a first doped portion 161 in the first initial well portion 1510 and a second doped portion 162 in the second initial well portion 1520, respectively, which contacts the first channel region 1511 and contacts the second channel region 1521, thus obtaining a doped layer 16; the portion of the first initial well portion 1510 where the first doped portion 161 is not formed is the first well portion 151, and the portion of the second initial well portion 1520 where the second doped portion 162 is not formed is the second well portion 152. The first well portion 151 and the second well portion 152 constitute the conductive well layer 15.

[0121] Step S5 above includes S51 and S52.

[0122] S51: As Figure 11As shown, using a third mask, ion implantation is performed on the first portion of the initial conductive well layer 150 that contacts the first channel region 1511 to form a first doped region 1611 that contacts the first channel region 1511, and ion implantation is performed on the second portion of the initial conductive well layer 150 that contacts the second channel region 1521 to form a second doped region 1621 that contacts the second channel region 1521.

[0123] The first doped region 1611 and the second doped region 1621 have the same doping type, and the doping type of the first doped region 1611 and the second doped region 1621 is opposite to the doping type of the first channel region 1511 and the second channel region 1521.

[0124] For example, in step S4, the implanted ions can be P-type ions, that is, the doping type of the first channel region 1511 and the second channel region 1521 is P-type. Then, in step S51, the implanted ions can be N-type ions, that is, the doping type of the first doped region 1611 and the second doped region 1621 is N-type.

[0125] Furthermore, the doping type of the first doped region 1611 and the second doped region 1621 is the same as the doping type of the initial epitaxial layer 140, and the doping concentration of the first doped region 1611 and the second doped region 1621 is greater than the doping concentration of the initial epitaxial layer 140.

[0126] For example, in step S2, the initial epitaxial layer 140 is lightly doped (N-) of N type; in step S51, the first doped region 1611 and the second doped region 1621 are heavily doped (N+) of N type.

[0127] For example, in the ion implantation process of step S51, the doping material is a doping material containing pentavalent elements such as N or P.

[0128] For example, the ion implantation depth is in the range of 0.1 μm to 1.0 μm, and the doping concentration during the ion implantation process is in the range of 1E12 cm⁻¹. -3 Up to 1E16cm -3 Within the range.

[0129] It should be noted that before step S51, the second mask can be removed using chemical solutions such as HF / HNO3, followed by an RCA cleaning process. Afterward, a second mask layer (which can be called the second mask layer) can be formed using SiO2, and then etched using a photomask, fluorine-based gases such as CF4, and O2 to form a SiO2 mask pattern, thus forming the third mask. During the etching process, the morphology of the SiO2 mask pattern can be controlled by adjusting the SiO2 / photoresist etching selectivity ratio. Here, the thickness of the formed second mask layer must be sufficient to block the energy of ion implantation (e.g., N+ ion implantation).

[0130] S52: As Figure 12 As shown, using a fourth mask, ion implantation is performed on the third portion of the initial conductive well layer 150 adjacent to the first doped region 1611 to form a third doped region 1612 in contact with the first doped region 1611, and ion implantation is performed on the fourth portion of the initial conductive well layer 150 adjacent to the second doped region 1621 to form a fourth doped region 1622 in contact with the second doped region 1621.

[0131] The third doped region 1612 and the fourth doped region 1622 have the same doping type, and the doping type of the third doped region 1612 and the fourth doped region 1622 is opposite to the doping type of the first doped region 1611 and the second doped region 1621.

[0132] For example, if the first doping region 1611 and the second doping region 1621 are N-type heavy doped (N+), then the third doping region 1612 and the fourth doping region 1622 are P-type heavy doped (P+).

[0133] For example, in the ion implantation process of step S52, the dopant material is a dopant material containing trivalent elements such as Al or B. For example, the ion implantation depth is in the range of 0.1 μm to 2.5 μm, and the doping concentration during the ion implantation process is 1E13 cm⁻¹. -3 Up to 1E18cm -3 Within the range.

[0134] It should be noted that before step S52, the third mask can be removed using chemical solutions such as HF / HNO3, followed by RCA cleaning. Afterward, a third mask layer (which can be called the third mask layer) can be formed using SiO2, and then etched using a photomask, fluorine-based gases such as CF4, and O2 to form a SiO2 mask pattern, thus forming the fourth mask. During etching, the morphology of the SiO2 mask pattern can be controlled by adjusting the SiO2 / photoresist etching selectivity ratio. Here, the thickness of the formed third mask layer must be sufficient to block the energy of ion implantation (e.g., P+ ion implantation).

[0135] In step S5, the first doped region 1611 and the third doped region 1612 constitute the first doped region 161, and the second doped region 1621 and the fourth doped region 1622 constitute the second doped region 162.

[0136] For example, the first doped region 1611 and the third doped region 1612 can respectively correspond to the first N+ doped region 1611 and the first P+ doped region 1612 in the above structural embodiment, and the second doped region 1621 and the fourth doped region 1622 can respectively correspond to the second N+ doped region 1621 and the second P+ doped region 1622 in the above structural embodiment.

[0137] S6: As Figure 13 As shown, a fifth mask is used to perform ion implantation on the portion corresponding to the top surface 1403 of the etched initial epitaxial layer to form a JFET region located between the first channel region 1511 and the second channel region 1521.

[0138] For example, during the ion implantation process in this step, the dopant is a dopant containing pentavalent elements such as N or P. For instance, the doping type of the formed JFET region is N-type heavily doped (N+).

[0139] For example, the ion implantation depth is in the range of 0.1 to 1.0 μm, and the doping concentration during the ion implantation process is in the range of 1E12cm. -3 Up to 1E16cm -3 Within the range.

[0140] It should be noted that before step S6, the fourth mask can be removed using chemical solutions such as HF / HNO3, followed by RCA cleaning. Afterward, a fourth mask layer (which can be called the fourth mask layer) can be formed using SiO2, and then etched using a photomask, fluorine-based gases such as CF4, and O2 to form a SiO2 mask pattern, thus forming the fifth mask. During etching, the morphology of the SiO2 mask pattern can be controlled by adjusting the SiO2 / photoresist etching selectivity ratio. Here, the thickness of the formed fourth mask layer must be sufficient to block the energy of ion implantation (e.g., N+ ion implantation).

[0141] S7: As Figure 14 As shown, a gate oxide film 170 is deposited on the side of the doped layer 16 away from the substrate 11, and the gate oxide film 170 covers the structures formed in the aforementioned steps S1-S6.

[0142] In semiconductor devices, the gate oxide layer needs to possess excellent insulation properties and stability, while also meeting the requirements for stable operation at high temperatures, high electric fields, and for extended periods. For example, the gate oxide film 170 can be made of SiO2.

[0143] For example, the thickness of the gate oxide film 170 can be in the range of 30nm-80nm.

[0144] For example, a gate oxide film 170 can be deposited using methods such as Chemical Vapor Deposition (CVD), Low Pressure Chemical Vapor Deposition (LPCVD), or Physical Vapor Deposition (PVD). For instance, the gate oxide film 170 can be formed via thermal oxidation or through LPCVD using tetraethoxysilane (TEOS), followed by high-temperature annealing. The annealing temperature can be in the range of 1100-1400℃, and the annealing atmosphere can be NO or N2. This post-oxidation annealing (POA) process can effectively eliminate interface state defects between SiC in the epitaxial layer and SiO2 in the gate oxide film.

[0145] For example, during the formation of the gate oxide film 170, the thickness of the portion of the gate oxide film 170 above the channel (i.e., the first channel region 1511 and the second channel region 1521) and the portion above the JFET region can be adjusted by controlling the process conditions during the LPCVD process using TEOS. For instance, the portion of the gate oxide film 170 above the channel is relatively thin to maintain good channel control performance; while the portion of the gate oxide film 170 above the JFET region is relatively thick, which can improve the breakdown voltage of this portion, thereby improving gate oxide reliability.

[0146] It should be noted that before step S7, the fifth mask can be removed using chemical solutions such as HF / HNO3, followed by the RCA (Radio Corporation of America Cleaning Process) cleaning process. The RCA cleaning process is a standard wet cleaning process developed by RCA. In some embodiments, after the RCA cleaning process, a sacrificial oxide layer is formed, for example, with a thickness in the range of 5 nm to 300 nm. This sacrificial oxide layer is then removed using chemical solutions such as HF / HNO3 to eliminate the damage to the SiC surface caused by the multiple implantations in the aforementioned steps, thereby improving the surface roughness of the SiC.

[0147] S8: As Figure 15 As shown, a gate layer 180 is formed on the side of the gate oxide film 170 away from the substrate 11.

[0148] For example, the material of the gate layer 180 is polycrystalline silicon. For instance, the thickness of the gate layer 180 is in the range of 100nm-800nm.

[0149] S9: such as Figure 16 As shown, the gate oxide film 170 and gate layer 180 formed in steps S7 and S8 are patterned to form a gate oxide layer 17 and gate 18 that at least cover the first channel region 1511 and the second channel region 1521.

[0150] For example, processes such as exposure, development, and etching are used to pattern the gate oxide film 170 and the gate layer 180.

[0151] It should be noted that before step S9, a layer of photoresist can be formed on the gate layer 180, and then the above-mentioned patterning process can be performed using a photomask, gases such as CF4, Cl2, and O2 to form the gate oxide layer 17 and the gate 18. During the etching process, the morphology of the gate oxide layer 17 and the gate 18 can be controlled by controlling the morphology of the photoresist.

[0152] S10: As Figure 17 As shown, an interlayer dielectric film 201 is formed on the side of the gate 18 away from the substrate 11, and the interlayer dielectric film 201 is patterned to form an interlayer dielectric layer 20 that at least covers the gate 18.

[0153] For example, the interlayer dielectric film 201 can be formed using plasma-enhanced chemical deposition (PECVD). Here, the patterning process can include processes such as exposure, development, and etching.

[0154] For example, the material of the interlayer dielectric thin film 201 can be insulating materials such as silicon dioxide, silicon nitride, and hafnium oxide.

[0155] For example, the material of the interlayer dielectric thin film 201 can be silicon dioxide, and the thickness can be 500 nm.

[0156] It should be noted that after the formation of the interlayer dielectric layer 20, such as Figure 17 As shown, source holes can also be formed on the interlayer dielectric layer 20 using photolithography and etching methods, exposing portions of the surfaces of the first doped portion 161 and the second doped portion 162. Then, nickel (Ni) is deposited within the source holes, i.e., Ni is deposited on the exposed surfaces of the first doped portion 161 and the second doped portion 162, and a source ohmic contact 211 is formed by rapid thermal annealing. The annealing temperature is, for example, in the range of 800-1100°C.

[0157] S11: As Figure 18 As shown, a first electrode 12 is deposited on the side of the interlayer dielectric layer 20 away from the substrate 11, and a second electrode 13 is formed on the other side of the substrate 11.

[0158] Here, the method for forming the first electrode 12 (e.g., source electrode) and the second electrode 13 (e.g., drain electrode) in this embodiment is not limited. They can be formed using methods known to those skilled in the art, such as metal deposition.

[0159] The semiconductor device formed according to the above steps has a channel region extending obliquely relative to the plane of the substrate. While keeping the channel width constant, the cell size of the semiconductor device can be effectively reduced, increasing the cell density and allowing the crystal plane corresponding to the channel region to achieve optimal channel carrier mobility. Furthermore, the oblique extension of the channel region increases the contact area between the channel and the gate oxide layer, thus making the bottom electric field distribution of the gate oxide layer more uniform, reducing the gate oxide electric field, and improving gate oxide reliability, thereby enhancing the reliability of the semiconductor device. Moreover, the semiconductor device fabrication method provided in this disclosure is simple, requiring no additional complex processes. It only involves patterning the initial epitaxial layer formed in a single epitaxial growth process, giving the patterned initial epitaxial layer oblique sides. This allows the surface of the P-well layer formed above the epitaxial layer, which contacts the gate oxide layer, to form an obliquely extending channel region. The fabrication process is simple, easy to operate, and low in cost.

[0160] In some embodiments, such as Figure 19 As shown, forming the initial epitaxial layer 140 in step S2 may include: forming an initial film layer on one side of the substrate 11 using an epitaxial growth process, and performing ion doping during epitaxial growth to obtain an initial current spreading layer 10420. The doping concentration of the portion of the initial film layer close to the substrate 11 is different from the doping concentration of the portion of the initial film layer far from the substrate 11. The initial epitaxial layer 140 includes the drift layer 1041 and the initial current spreading layer 10420.

[0161] For example, the doping concentrations of drift layer 1041 and initial current spreading layer 10420 are different. For instance, the doping concentration of drift layer 1041 is 1E14 cm⁻¹. -3 Up to 5E16cm -3 Within the range, while the doping concentration of the initial current extension layer 10420 is in the range of 1E16cm. -3 Up to 5E17cm -3 Within the range.

[0162] Based on this, such as Figure 20 As shown, etching the initial epitaxial layer 140 in step S3 is actually etching the initial current spreading layer 10420. For example, the initial current spreading layer 10420 is etched to form a first initial bevel 1401 and a second initial bevel 1402 on the surface of the initial current spreading layer 10420.

[0163] It is understandable that in step S6, ion implantation is performed on the portion corresponding to the top surface 1403 of the etched initial epitaxial layer, that is, ion implantation is performed on the top surface 1403 of the initial current extension layer 10420. For example... Figure 21 As shown, after obtaining the JFET region 19 through ion implantation, the initial current extension layer 10420 (as shown) Figure 20 As shown, this forms a current spreading layer 1042.

[0164] The fabrication method provided in this embodiment can form a current spreading layer 1042. The formation of the current spreading layer 1042 widens the current channel, allowing the current to be evenly distributed to the working area of ​​the device, thereby improving the performance of the semiconductor device.

[0165] It is understandable that, during the above preparation method, if the current spreading layer 1042 is formed, the corresponding figures for steps S4, S5, and steps S7 to S11 are ( Figures 10-12 ,as well as Figures 14 to 18 All of these can be used as a reference. Figure 6 Understanding the structure of the semiconductor device shown.

[0166] In some embodiments, the formed drift layer is an N-drift layer, the formed current spreading layer is an N+ current spreading layer, and the formed first well and second well are P-wells; the formed first doped region includes a first N+ doped region near the first channel region and a first P+ doped region away from the first channel region, and the formed second doped region includes a second N+ doped region near the second channel region and a second P+ doped region away from the second channel region.

[0167] It should be noted that the fabrication methods for P-channel MOSFET devices provided in the above embodiments are all illustrated using N-channel MOSFETs as an example. These fabrication methods are also applicable to P-channel MOSFETs. Simply changing the doping type in the above embodiments to the opposite type will yield a P-channel MOSFET, which will not be elaborated further here.

[0168] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; The first electrode and the second electrode are disposed on opposite sides of the substrate; as well as An epitaxial layer, a conductive well layer, a doped layer, a gate oxide layer, and a gate are sequentially disposed between the first electrode and the substrate along a first direction, wherein the first direction is the direction from the substrate to the first electrode; The epitaxial layer includes a first part, a second part, and a third part arranged sequentially along the first direction; the second part includes a first inclined surface and a second inclined surface arranged opposite to each other along a second direction, the second direction being perpendicular to the first direction; the first inclined surface has a first acute angle with the plane where the substrate is located, and the second inclined surface has a second acute angle with the plane where the substrate is located; The conductive well layer includes a first well portion and a second well portion spaced apart along the second direction, and the second and third portions of the epitaxial layer are disposed together between the first well portion and the second well portion; wherein, the first well portion includes a first channel region, the first channel region is in contact with the first inclined surface and has the same extension direction; the second well portion includes a second channel region, the second channel region is in contact with the second inclined surface and has the same extension direction. The doped layer includes a first doped portion and a second doped portion, wherein the first doped portion is disposed on the side of the first channel region away from the second channel region and in contact with the first channel region, and the second doped portion is disposed on the side of the second channel region away from the first channel region and in contact with the second channel region. The gate oxide layer covers at least the first channel region and the second channel region.

2. The semiconductor device according to claim 1, characterized in that, The first acute angle is within the range of 10°-80°, and the second acute angle is within the range of 10°-80°.

3. The semiconductor device according to claim 1, characterized in that, The dimensions of the first channel region along its extension direction are in the range of 0.1μm-2.0μm, and the dimensions of the second channel region along its extension direction are in the range of 0.1μm-2.0μm.

4. The semiconductor device according to claim 1, characterized in that, The first part of the epitaxial layer includes at least a drift layer, and the third part includes a JFET region.

5. The semiconductor device according to claim 4, characterized in that, Of the first, second, and third portions of the epitaxial layer, at least the second portion includes a current spreading layer.

6. The semiconductor device according to claim 5, characterized in that, The first part includes the drift layer and a portion of the current spreading layer near the drift layer, and the second part includes the remaining portion of the current spreading layer.

7. The semiconductor device according to claim 6, characterized in that, The drift layer is an N-drift layer, the current spreading layer is an N+ current spreading layer, and the JFET region is an N JFET region; The conductive well layer is a P-conductive well layer; The first doped region includes a first N+ doped region and a first P+ doped region sequentially disposed along the direction from the second doped region to the first doped region, and the second doped region includes a second N+ doped region and a second P+ doped region sequentially disposed along the direction from the first doped region to the second doped region.

8. The semiconductor device according to any one of claims 1-7, characterized in that, The material of the epitaxial layer is silicon carbide.

9. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; An initial epitaxial layer is formed on one side of the substrate; The initial epitaxial layer is etched to give the initial epitaxial layer a first initial slope and a second initial slope disposed opposite to each other along a second direction. The first initial slope has a first acute angle with the plane where the substrate is located, and the second initial slope has a second acute angle with the plane where the substrate is located. The second direction is a direction parallel to the plane where the substrate is located. Ion implantation is performed on the etched initial epitaxial layer to form an initial conductive well layer including a first initial well portion and a second initial well portion; The first initial well portion and the second initial well portion are spaced apart along the second direction; the first initial well portion includes a first channel region, which has the same extension direction as the first initial slope; the second initial well portion includes a second channel region, which has the same extension direction as the second initial slope; the portion of the initial epitaxial layer in which the first initial well portion and the second initial well portion are not formed forms an epitaxial layer; Ion implantation is performed on the initial conductive well layer to form a first doped portion that contacts the first channel region and a second doped portion that contacts the second channel region in the first initial well portion and the second initial well portion, respectively, to obtain a doped layer; the portion of the first initial well portion in which the first doped portion is not formed is the first well portion, and the portion of the second initial well portion in which the second doped portion is not formed is the second well portion, and the first well portion and the second well portion constitute a conductive well layer; A gate oxide layer and a gate electrode are sequentially formed on the side of the doped layer away from the substrate, wherein the gate oxide layer at least covers the first channel region and the second channel region; A first electrode is formed on the side of the gate away from the substrate; as well as A second electrode is formed on the other side of the substrate.

10. The preparation method according to claim 9, characterized in that, An initial epitaxial layer is formed on one side of the substrate, comprising: An initial film layer is obtained by epitaxial growth on one side of the substrate, and ion doping is performed simultaneously with the epitaxial growth to obtain a drift layer and an initial current spreading layer. The doping concentration of the portion of the initial film layer near the substrate is different from the doping concentration of the portion of the initial film layer away from the substrate. The initial epitaxial layer includes the drift layer and the initial current spreading layer.

11. The preparation method according to claim 10, characterized in that, The etching of the initial epitaxial layer to give the initial epitaxial layer a first initial slope and a second initial slope disposed opposite each other along a second direction includes: The initial current spreading layer is etched to form the first initial bevel and the second initial bevel on the surface of the initial current spreading layer.

12. The preparation method according to claim 11, characterized in that, After ion implantation of the etched initial epitaxial layer to form an initial conductive well layer including a first initial well portion and a second initial well portion, the fabrication method further includes: Ion implantation is performed on the portion of the initial current spread layer located between the first initial well and the second initial well to obtain a JFET region; the portion of the initial current spread layer in which the JFET region is not formed is the current spread layer.

13. An electronic device, characterized in that, The semiconductor device included in any one of claims 1-8.

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