Semiconductor device

Abstract

A semiconductor device (1, 2) is provided with: an insulating film (42) having an end portion (43) facing an active region (10A); a gate wiring (36) provided on the insulating film (42); and a gate lead-out section (38) that connects the gate electrode (32) and the gate wiring (36) and extends across an end section (43) of the upper insulating film (42). A boundary region (10B) of a semiconductor substrate (10) has a first semiconductor layer (14) of a first conductivity type and a second semiconductor layer (16) of a second conductivity type. The second semiconductor layer (16) has a contact section (18) that is in contact with the main electrode (24) at a position outside the gate wiring (36).

Description

Technical Field

[0001] The technology disclosed in this specification relates to semiconductor devices. Background Technology

[0002] A semiconductor device includes a semiconductor substrate divided into an active region, a peripheral breakdown voltage region surrounding the active region, and a boundary region located between the active region and the peripheral breakdown voltage region, surrounding the active region. A gate electrode is provided in the active region, and the current flowing in the active region is controlled according to the voltage applied to the gate electrode. A peripheral breakdown voltage structure, such as a guard ring, is provided in the peripheral breakdown voltage region. An insulating film is provided on the semiconductor substrate corresponding to the boundary region, and gate wiring is disposed on the insulating film. A gate lead-out extends from the gate electrode provided in the active region, and the gate lead-out extends across the end of the insulating film and connects to the gate wiring.

[0003] An example of such a semiconductor device is disclosed in Patent Document 1.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2023-022586 Summary of the Invention

[0007] Furthermore, the boundary region of the semiconductor substrate has an n-type semiconductor layer and a p-type semiconductor layer disposed on the n-type semiconductor layer. The n-type semiconductor layer is a semiconductor layer referred to as a drift layer or the like. The p-type semiconductor layer is the portion extending from a semiconductor layer disposed in the active region, referred to as a p-type body layer or p-type base layer or the like, toward the surrounding breakdown voltage region within the boundary region.

[0008] If a rapid voltage change occurs between the main electrodes, a displacement current flows through the capacitor used to charge and discharge the pn junction of the p-type and n-type semiconductor layers. For example, if the diode embedded in the semiconductor device is turned off, a rapid voltage change occurs between the main electrodes, causing a displacement current to flow. This displacement current flows laterally towards the active region in the p-type semiconductor layer, flowing into the portion of the p-type semiconductor layer that connects to the main electrodes. At this time, the displacement current passes through the p-type semiconductor layer located below the end of the insulating film. The potential of the p-type semiconductor layer located below the end of the insulating film rises based on the product of the displacement current and the resistance of the p-type semiconductor layer.

[0009] According to the inventors' research, when a displacement current flows, the electric field concentrates at the ends of the insulating film. This specification provides a semiconductor device that suppresses the electric field concentration caused by the displacement current.

[0010] One aspect of the semiconductor device disclosed herein may also include: a semiconductor substrate divided into an active region, a peripheral breakdown voltage region disposed around the active region, and a boundary region disposed between the active region and the peripheral breakdown voltage region and around the active region, and having a first main surface and a second main surface; a main electrode disposed on the first main surface of the semiconductor substrate; an insulating film disposed on the first main surface of the semiconductor substrate, at least disposed on a portion of the boundary region, and having an end facing the active region; a gate wiring disposed on the insulating film and disposed along the boundary region; and a gate lead-out portion connecting the gate wiring to the gate electrode disposed in the active region of the semiconductor substrate and extending across the end of the insulating film. The boundary region of the semiconductor substrate may also include: a first semiconductor layer of a first conductivity type; and a second semiconductor layer of a second conductivity type disposed on the first semiconductor layer, the surface of which is disposed at a position constituting the first main surface. The second semiconductor layer may also have a contact portion that contacts the main electrode at a position further outward than the gate wiring.

[0011] According to the aforementioned semiconductor device, a portion of the displacement current flowing in the second semiconductor layer branches into a contact located outside the gate wiring. Therefore, the displacement current flowing in the second semiconductor layer below the end of the insulating film is reduced, thus suppressing potential rise in that area. As a result, the electric field concentration at the end of the insulating film when the displacement current flows is mitigated. Attached Figure Description

[0012] Figure 1 This is a plan view of the semiconductor device according to the first embodiment. It is a diagram showing the positional relationship of the active region, boundary region and peripheral voltage-resistant region on the semiconductor substrate when viewed from above.

[0013] Figure 2 This is a cross-sectional view of the main part of the semiconductor device according to the first embodiment, schematically showing the... Figure 1 The figure showing the cross-sectional view of the trench grid corresponding to line II-II.

[0014] Figure 3 This is a cross-sectional view of the main part of the semiconductor device according to the first embodiment, schematically showing the... Figure 1 The figure corresponding to line III-III is a cross-sectional view that does not include the trench grid.

[0015] Figure 4 This is a cross-sectional view of the main part of the semiconductor device according to the first embodiment, schematically showing the... Figure 1 The diagram shows the sectional view corresponding to line IV-IV.

[0016] Figure 5This is an enlarged cross-sectional view of the main part of the semiconductor device according to the first embodiment, and is a schematic cross-sectional view showing the area near the tapering end of the field insulating film.

[0017] Figure 6 It means and Figure 4 A diagram showing the path of the displacement current at the corresponding cross-section.

[0018] Figure 7 This is a plan view of the semiconductor device according to the second embodiment. It is a diagram showing the positional relationship of the active region, boundary region and peripheral voltage-resistant region on the semiconductor substrate when viewed from above.

[0019] Figure 8 This is a cross-sectional view of the main part of the semiconductor device according to the second embodiment, schematically showing the relationship with... Figure 7 The diagram of the cross-sectional view corresponding to line VIII-VIII. Detailed Implementation

[0020] (First Implementation)

[0021] like Figure 1 As shown, the semiconductor device 1 of the first embodiment is formed using a semiconductor substrate 10. The material of the semiconductor substrate 10 is not particularly limited, and for example, it may be silicon carbide (SiC).

[0022] The semiconductor substrate 10 is formed of a rectangular plate and, when viewed from a direction orthogonal to the main surface of the semiconductor substrate 10 (hereinafter referred to as "top view"), is divided into an active region 10A, a boundary region 10B, and a peripheral voltage withstand region 10C. The active region 10A is located at the center of the semiconductor substrate 10 and is the region where a switching structure for controlling current is formed. The switching structure includes a gate structure as described later, and is not particularly limited; for example, it can be a MOSFET or a reverse-biased IGBT. The boundary region 10B is the region located between the active region 10A and the peripheral voltage withstand region 10C, surrounding the active region 10A. The peripheral voltage withstand region 10C is the region surrounding the active region 10A and the boundary region 10B, surrounding both the active region 10A and the boundary region 10B. A peripheral voltage withstand structure, such as a guard ring, is formed in the peripheral voltage withstand region 10C.

[0023] like Figures 2-4As shown, the semiconductor substrate 10 has an upper surface 10a and a lower surface 10b as its pair of main surfaces. A drain electrode 22 is provided on the lower surface 10b of the semiconductor substrate 10, and a source electrode 24 is provided on the upper surface 10a of the semiconductor substrate 10. The semiconductor device 1 is a switching element that controls the current flowing between the pair of main electrodes, namely the drain electrode 22 and the source electrode 24, and is a vertically oriented switching element configured such that the current flows longitudinally in the semiconductor substrate 10. The semiconductor substrate 10 has a high-concentration n-type semiconductor layer 12, a low-concentration n-type semiconductor layer 14, and a p-type semiconductor layer 16.

[0024] The high-concentration n-type semiconductor layer 12 is a semiconductor layer containing a high concentration of n-type impurities, also known as a drain layer. The high-concentration n-type semiconductor layer 12 is continuously disposed in the active region 10A, the boundary region 10B, and the peripheral breakdown voltage region 10C, and is located at a position exposed on the lower surface 10b of the semiconductor substrate 10.

[0025] The low-concentration n-type semiconductor layer 14 is a semiconductor layer containing n-type impurities at a lower concentration than that of the high-concentration n-type semiconductor layer 12, and is also referred to as a drift layer. The low-concentration n-type semiconductor layer 14 is continuously disposed in the active region 10A, the boundary region 10B, and the peripheral breakdown voltage region 10C. The low-concentration n-type semiconductor layer 14 is disposed in the boundary region 10B between the high-concentration n-type semiconductor layer 12 and the p-type semiconductor layer 16. Furthermore, the low-concentration n-type semiconductor layer 14 is an example of a first semiconductor layer.

[0026] The p-type semiconductor layer 16 is a semiconductor layer containing p-type impurities, and it is a portion extending from the p-type body layer or p-type base layer formed in the active region 10A of the semiconductor substrate 10 toward the peripheral breakdown region 10C within the boundary region 10B. The p-type semiconductor layer 16 is disposed on the low-concentration n-type semiconductor layer 14 in the boundary region 10B, and its surface is disposed at a position constituting the upper surface 10a of the semiconductor substrate 10. Furthermore, the p-type semiconductor layer 16 is an example of a second semiconductor layer.

[0027] The semiconductor device 1 also includes a trench gate 30, a field insulating film 42, and an interlayer insulating film 44. Alternatively, a planar gate structure may be provided instead of the trench gate 30.

[0028] Trench gates 30 are disposed in the active region 10A, and when viewed from above the semiconductor substrate 10, they extend in one direction from one end of the active region 10A to the other. Multiple trench gates 30 are provided in the active region 10A, and when viewed from above the semiconductor substrate 10, the multiple trench gates 30 are arranged in a striped pattern. However, the striped pattern is only one example; the multiple trench gates 30 can also be arranged in other layouts. In this embodiment, the area where the multiple trench gates 30 are disposed is the active region 10A, the area where the p-type semiconductor layer 16 is disposed, i.e., the area from the end of the trench gate 30 to the outer boundary of the p-type semiconductor layer 16, is the boundary region 10B, and the area further outward than the p-type semiconductor layer 16 is the peripheral breakdown voltage region 10C.

[0029] The trench gate 30 has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is insulated from the semiconductor substrate 10 through the gate insulating film 34 and from the source electrode 24 through the interlayer insulating film 44. The gate insulating film 34 extends beyond the field insulating film 42 to the upper surface 10a of the semiconductor substrate 10 corresponding to the peripheral withstand voltage region 10C.

[0030] A field insulating film 42 is disposed on at least a portion of the area corresponding to the boundary region 10B in the upper surface 10a of the semiconductor substrate 10. The field insulating film 42 has a tapered end 43 configured to taper at the front end. The tapered end 43 refers to the end of the field insulating film 42 near the active region 10A, and is thinner than the maximum film thickness of the field insulating film 42. In this example, the film thickness of the tapered end 43 gradually decreases towards the active region 10A, and the upper surface of the tapered end 43 is inclined towards the active region 10A. Alternatively, the tapered end 43 may be configured to have a film thickness that decreases in a stepped manner.

[0031] A gate wiring 36 is provided on the field insulating film 42. The gate wiring 36 extends from a gate pad (not shown) provided on the semiconductor substrate 10 and is disposed along the boundary region 10B on the field insulating film 42. The gate wiring 36 may be disposed around the active region 10A along the boundary region 10B, or it may be disposed along the boundary region 10B on a portion of the periphery of the active region 10A.

[0032] like Figure 2 As shown, a gate lead-out portion 38 extends from the end of the gate electrode 32. The gate lead-out portion 38 extends across the tapering end 43 of the upper field insulating film 42, connecting the gate electrode 32 to the gate wiring 36. In other words, the gate lead-out portion 38 is the wiring portion between the gate electrode 32 and the gate wiring 36. Figure 5As shown, if the thickness of the gate lead-out portion 38 is set to Tg, and the width of the tapered end portion 43 of the field insulating film 42, i.e., the width of the tapered end portion 43 in a cross-section perpendicular to the direction in which the front end of the field insulating film 42 extends when viewed from above the semiconductor substrate 10, is set to L, then the relationship Tg < L holds. If this relationship holds, it is possible to suppress the breakage of the gate lead-out portion 38 in the portion crossing the field insulating film 42.

[0033] like Figure 2 As shown, the interlayer insulating film 44 covers the gate electrode 32, the gate wiring 36, and the gate lead-out portion 38, insulating them from the source electrode 24. Figure 3 and Figure 4 As shown, an opening 46 is formed in the interlayer insulating film 44 to expose the upper surface 10a of the semiconductor substrate 10 corresponding to the active region 10A. The source electrode 24 is in contact with the upper surface 10a of the semiconductor substrate 10 through the opening 46 in the interlayer insulating film 44. The source electrode 24 extends from the active region 10A toward the peripheral withstand voltage region 10C on the interlayer insulating film 44 in the boundary region 10B.

[0034] like Figure 4 As shown, a through-hole 48 is formed that penetrates the interlayer insulating film 44, the gate insulating film 34, and the field insulating film 42. The through-hole 48 is formed in the boundary region 10B at a position further outward than the gate wiring 36, that is, closer to the peripheral withstand voltage region 10C than the gate wiring 36, exposing the p-type semiconductor layer 16. The portion of the p-type semiconductor layer 16 exposed in the through-hole 48 is called the contact portion 18. A source electrode 24 is filled in the through-hole 48, and the source electrode 24 is in contact with the contact portion 18 of the p-type semiconductor layer 16. Alternatively, the through-hole 48 can also be formed by penetrating the interlayer insulating film 44 and the gate insulating film 34 on the outside of the field insulating film 42.

[0035] Figure 1 The area where the contact portion 18 of the p-type semiconductor layer 16 is formed is indicated in gray. The contact portion 18 is disposed only at the corner of the boundary region 10B. The corner of the boundary region 10B is defined by at least one of the following: If the distance from the edge of the semiconductor substrate 10 (i.e., the chip end) to the active region 10A is defined as D1, then the portion of the boundary region 10B located within the range where the distance D1 is not the minimum can also be defined as a corner. In addition, as described above, the boundary region 10B is the area where the p-type semiconductor layer 16 is disposed. When viewed from above the semiconductor substrate 10, the p-type semiconductor layer 16 disposed around the rectangular active region 10A has a curved portion at its outer boundary. The portion of the boundary region 10B located inside the curved outer boundary of the outer boundary of the p-type semiconductor layer 16 can also be defined as a corner.

[0036] Next, refer to Figure 6The features of semiconductor device 1 will be described. Additionally, Figure 6 Equivalent to Figure 4 For clarity, reference numerals have been omitted from the accompanying drawings. When a sharp voltage change occurs between the drain and source electrodes, a displacement current flows through the capacitor used to charge and discharge the pn junction of the p-type semiconductor layer 16 and the low-density n-type semiconductor layer 14. For example, if the diode built into the semiconductor device 1 is turned off, a sharp voltage change occurs between the drain and source electrodes, and a displacement current flows.

[0037] Here, we consider a comparative example where the contact portion 18 is not provided in the p-type semiconductor layer 16. The displacement current flows laterally through the p-type semiconductor layer 16 toward the active region 10A, flowing into the portion of the p-type semiconductor layer 16 in contact with the source electrode 24 within the active region 10A. At this time, the displacement current passes through the p-type semiconductor layer 16 located below the tapered end 43 of the field insulating film 42. The potential of the p-type semiconductor layer 16 located below the tapered end 43 of the field insulating film 42 increases based on the product of the displacement current and the resistance of the p-type semiconductor layer 16. In semiconductor devices where the end of the field insulating film 42 is tapered, the electric field tends to concentrate at the tapered end 43 of the field insulating film 42 when the displacement current flows. Furthermore, while such electric field concentration is significant when the end of the field insulating film 42 is tapered, it can also occur when the end of the field insulating film 42 is not tapered.

[0038] On the other hand, in the semiconductor device 1 of this embodiment, a portion of the displacement current flowing through the p-type semiconductor layer 16 branches and flows into the contact portion 18 located outside the gate wiring 36. Therefore, the displacement current flowing in the p-type semiconductor layer 16 below the tapered end 43 of the field insulating film 42 is reduced, and thus the potential rise in that portion is suppressed. As a result, the electric field concentration at the tapered end 43 of the field insulating film 42 when the displacement current flows is mitigated. Therefore, the semiconductor device 1 can have high tolerance to abrupt voltage changes between the drain and source electrodes.

[0039] As described above, the contact portion 18 of the p-type semiconductor layer 16 is provided at the corner of the boundary region 10B. The corner of the boundary region 10B is a region where the displacement current flowing toward the active region 10A is concentrated and the current density is high, making it a problematic area for electric field concentration at the tapered end 43 of the field insulating film 42. In the semiconductor device 1, by forming the contact portion 18 of the p-type semiconductor layer 16 at the corner of the boundary region 10B, such electric field concentration can be effectively mitigated. Furthermore, the contact portion 18 of the p-type semiconductor layer 16 is only provided at the corner of the boundary region 10B and not at the straight portion of the boundary region 10B. Therefore, it is not necessary to make the width of the boundary region 10B wider just to form the contact portion, thus suppressing the increase in the area of ​​the semiconductor device 1.

[0040] Furthermore, when the semiconductor substrate 10 of the semiconductor device 1 is silicon carbide (SiC), the resistance of the p-type semiconductor layer 16 is high, and the potential of the p-type semiconductor layer 16 is prone to rise. Therefore, the technique of forming the contact portion 18 in the p-type semiconductor layer 16 is particularly useful when the material of the semiconductor substrate 10 is silicon carbide (SiC).

[0041] (Second Implementation)

[0042] Figure 7 and Figure 8 The semiconductor device 2 of the second embodiment is indicated. Furthermore, components common to the semiconductor device 1 of the first embodiment are marked with the same symbols, and their descriptions are omitted.

[0043] like Figure 7 As shown, in semiconductor device 2, when viewed from above, a portion of the boundary region 10B of the straight section extends outward, and the width of this portion is relatively wide. That is, in semiconductor device 2, when viewed from above, the outer boundary of a portion of the p-type semiconductor layer 16 of the straight section extends outward, and the width of this portion is relatively wide. In semiconductor device 2, a contact portion 19 is also formed in the wide portion of the p-type semiconductor layer 16.

[0044] For various reasons, it is sometimes desirable to form a portion of the p-type semiconductor layer 16 wider than other portions. In this case, the current density of the displacement current increases in the wider portion of the p-type semiconductor layer 16, and therefore, when the displacement current flows, the electric field tends to concentrate at the tapered end 43 of the field insulating film 42 located in the wider portion of the p-type semiconductor layer 16. In the semiconductor device 2, by also forming a contact portion 19 in the wider portion of the p-type semiconductor layer 16, such electric field concentration can be effectively mitigated.

Claims

1. A semiconductor device, characterized in that, have: A semiconductor substrate is divided into an active region, a peripheral breakdown voltage region arranged around the active region, and a boundary region arranged between the active region and the peripheral breakdown voltage region and around the active region, and has a first main surface and a second main surface. The main electrode is disposed on the first main surface of the semiconductor substrate; An insulating film is disposed on the first main surface of the semiconductor substrate and is at least configured in a portion of the boundary region, having an end facing the active region; Gate wiring is disposed on the insulating film and arranged along the boundary region; as well as A gate lead-out portion connects the gate wiring to the gate electrode disposed in the active region of the semiconductor substrate, and extends across the end of the insulating film. The boundary region of the semiconductor substrate includes: First semiconductor layer of first conductivity type; and A second semiconductor layer of a second conductivity type is disposed on the first semiconductor layer, and its surface is disposed at the position constituting the first main surface. The second semiconductor layer has a contact portion that is connected to the main electrode at a position further outward than the gate wiring.

2. The semiconductor device according to claim 1, characterized in that, When viewed from above, the contact portion is located only at the corner of the boundary region.

3. The semiconductor device according to claim 1, characterized in that, The end of the insulating film has a tapered end that tapers towards the active region.

4. The semiconductor device according to claim 3, characterized in that, The width of the tapered end of the insulating film is greater than the thickness of the gate lead.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The semiconductor substrate is silicon carbide.

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