Power semiconductor device and preparation method of power semiconductor device

Abstract

The invention provides a power semiconductor device and a preparation method of the power semiconductor device. The power semiconductor device comprises a substrate; the epitaxial layer is located on one side of the substrate; the gate structure is at least partially located in the epitaxial layer, and at least partial structure of the gate structure is hemispherical; the Schottky contact region is located in the epitaxial layer and is located between two adjacent gate structures; the source structure is located at one side of the epitaxial layer away from the substrate; the drain structure is located on one side of the substrate away from the epitaxial layer. The reliability of the power semiconductor device can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically, to a power semiconductor device and a method for fabricating the power semiconductor device. Background Technology

[0002] Power semiconductor devices have demonstrated significant advantages in applications such as new energy vehicles, photovoltaic inverters, and industrial power conversion. However, they face unique challenges in design and manufacturing, especially in trench-type devices, where many issues limit the overall performance and reliability of the devices.

[0003] To overcome the above problems, there is an urgent need for a highly reliable power semiconductor device.

[0004] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0005] The main objective of this application is to provide a power semiconductor device and a method for fabricating a power semiconductor device, so as to solve the problem of how to improve the reliability of power semiconductor devices in the prior art.

[0006] To achieve the above objectives, according to one aspect of this application, a power semiconductor device is provided, comprising: a substrate; an epitaxial layer located on one side of the substrate; a gate structure located at least partially within the epitaxial layer, wherein at least a portion of the gate structure is hemispherical in shape; a Schottky contact region located within the epitaxial layer and between two adjacent gate structures; a source structure located on the side of the epitaxial layer away from the substrate; and a drain structure located on the side of the substrate away from the epitaxial layer. Optionally, the power semiconductor device further includes: a first doped region located within the epitaxial layer and on both sides of the gate structure, wherein the doping type of the first doped region is different from the doping type of the substrate; a second doped region located within the epitaxial layer and on the side of the first doped region away from the gate structure, wherein the doping type of the second doped region is different from the doping type of the substrate; an active region located within the epitaxial layer, on both sides of the gate structure and on the side of the first doped region away from the substrate, wherein the doping type of the active region is different from the doping type of the first doped region; and a third doped region located within the epitaxial layer and on the side of the second doped region away from the gate structure, wherein the doping type of the third doped region is the same as the doping type of the substrate.

[0007] Optionally, the gate structure satisfies at least one of the following: the central angle of the cross section of the gate structure along the thickness direction of the substrate is 120~170°; the average radius of the cross section of the gate structure along the thickness direction of the substrate is a first width; the width of the surface of the gate structure away from the substrate is a second width; and the ratio of the first width to the second width is 0.5~1.5.

[0008] Optionally, the gate structure includes a gate oxide layer and a gate, the gate oxide layer being located between the gate and the epitaxial layer, wherein the gate is a trench gate.

[0009] Optionally, the gate structure is hemispherical in shape.

[0010] Optionally, the gate structure is divided into a first part and a second part along the thickness direction of the substrate, and the second part is hemispherical in shape.

[0011] Optionally, the gate structure has a polygonal or circular cross-sectional shape along the direction perpendicular to the substrate thickness, and the Schottky contact region has a polygonal or circular cross-sectional shape along the direction perpendicular to the substrate thickness.

[0012] To achieve the above objectives, according to one aspect of this application, a method for fabricating a power semiconductor device is provided, for fabricating any of the aforementioned power semiconductor devices. The method includes: providing a substrate; forming a first pre-epitaxial layer on one side of the substrate; processing the first pre-epitaxial layer to obtain a first pre-doped region, a second pre-doped region, and a pre-active region, wherein the remaining portion of the first pre-epitaxial layer forms a second pre-epitaxial layer, wherein the second pre-doped region is located on both sides of the first pre-doped region and the pre-active region, the pre-active region is located on the side of the first pre-doped region away from the substrate, the doping type of the first pre-doped region is different from the doping type of the substrate, the doping type of the second pre-doped region is different from the doping type of the substrate, and the doping type of the pre-active region is different from the doping type of the first pre-doped region; on the surface of the pre-active region away from the substrate and the first pre-doped region... On the surface of the second pre-doped region away from the substrate, a mask layer and a photoresist layer are formed sequentially. The photoresist layer, a portion of the mask layer, a portion of the pre-active region, a portion of the first pre-doped region, and a portion of the second pre-epitaxial layer are sequentially removed to form a trench. The remaining mask layer is then removed, leaving the remaining first pre-doped region to form a first doped region and the remaining pre-active region to form an active region. At least one of the bottom and side surfaces of the trench is curved. A gate structure is formed at least in the trench. The second pre-doped region is processed to obtain a third doped region and a Schottky contact region, wherein the Schottky contact region is located on the side of the third doped region away from the substrate. The remaining second pre-doped region forms a second doped region, resulting in an epitaxial layer. The doping type of the third doped region is the same as the doping type of the substrate. A source structure is formed on the side of the epitaxial layer away from the substrate. A drain structure is formed on the side of the substrate away from the epitaxial layer.

[0013] Optionally, a groove is formed by sequentially removing the photoresist layer, a portion of the mask layer, a portion of the prepared active region, a portion of the first prepared doped region, and a portion of the second prepared epitaxial layer, including: removing a portion of the photoresist layer to obtain a first prepared groove, wherein at least one of the bottom surface and the side surface of the first prepared groove is a curved surface, and the central angle of the curved surface of the first prepared groove is smaller than the central angle of the curved surface of the groove; removing a portion of the mask layer to obtain a second prepared groove, and removing the remaining photoresist layer, wherein at least one of the bottom surface and the side surface of the second prepared groove is a curved surface, the central angle of the curved surface of the second prepared groove is smaller than the central angle of the curved surface of the groove, and the central angle of the curved surface of the second prepared groove is larger than the central angle of the curved surface of the first prepared groove; sequentially removing a portion of the prepared active region, a portion of the first prepared doped region, and a portion of the second prepared epitaxial layer to obtain the groove, and removing the remaining mask layer.

[0014] Optionally, processing the second pre-doped region to obtain a third doped region and a Schottky contact region includes: removing a portion of the second pre-doped region to form a third pre-drilled trench, with the remaining second pre-doped region forming the third pre-doped region; processing the third pre-doped region to obtain the third doped region; and depositing a metal material in the third pre-drilled trench to obtain the Schottky contact region.

[0015] This application provides a power semiconductor device, including a substrate; an epitaxial layer located on one side of the substrate; a gate structure at least partially located within the epitaxial layer, the shape of which is hemispherical; a Schottky contact region located within the epitaxial layer and between two adjacent gate structures; a source structure located on the side of the epitaxial layer away from the substrate; and a drain structure located on the side of the substrate away from the epitaxial layer. This solution avoids the technical problems of uneven gate oxide quality and electric field concentration at the corners of the gate structure, which affect the reliability and withstand voltage of the device, caused by setting the shape of at least part of the gate structure to hemispherical. Furthermore, by setting the Schottky contact region and integrating the structure of a Schottky barrier diode, the reverse turn-off characteristics of the device are further optimized, switching losses are reduced, and the overall reliability of the power semiconductor device is optimized. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1A schematic diagram of the structure of a first power semiconductor device according to an embodiment of this application is shown;

[0018] Figure 2 A schematic diagram of the structure of a second power semiconductor device provided according to an embodiment of this application is shown;

[0019] Figure 3 The first type is shown Figure 1 Top view;

[0020] Figure 4 The second type is shown Figure 1 Top view;

[0021] Figure 5 A schematic diagram of the structure of a third power semiconductor device provided according to an embodiment of this application is shown;

[0022] Figure 6 A schematic flowchart of a method for fabricating a power semiconductor device according to an embodiment of this application is shown;

[0023] Figure 7 A schematic diagram of the fabrication process of a power semiconductor device according to an embodiment of this application is shown.

[0024] Figure 8 A schematic diagram of the structure corresponding to the formation process of the groove provided in an embodiment of this application is shown.

[0025] The above figures include the following reference numerals:

[0026] 10. Substrate; 11. Epitaxial layer; 12. Gate structure; 121. Gate oxide layer; 122. Gate; 13. First doped region; 14. Second doped region; 15. Active region; 16. Third doped region; 17. Schottky contact region; 18. Source structure; 19. Drain structure; 20. First ohmic contact region; 21. Second ohmic contact region; 22. Dielectric layer; 23. First pre-epitaxial layer; 24. Second pre-epitaxial layer; 25. First pre-doped region; 26. Second pre-doped region; 27. Pre-active region; 28. Mask layer; 29. ​​Photoresist layer; 40. Trench; 41. First pre-trench; 42. Second pre-trench. Detailed Implementation

[0027] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0028] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0030] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0031] Existing trench-type power semiconductor devices employ a rectangular trench structure, meaning the sidewalls and bottom of the trench are nearly right angles. This design results in uneven quality of the gate oxide layer across the trench sidewalls and bottom, affecting its reliability. Specifically, electric field concentration easily forms at the right-angle corners of the trench, which exacerbates stress in the gate oxide layer, leading to defects and reducing the device's breakdown voltage and long-term operational stability. Furthermore, during reverse turn-off, existing power semiconductor devices are prone to carrier injection into the drift layer during the body diode's freewheeling turn-off process, resulting in intensified bipolarization and increased switching losses, negatively impacting the device's switching speed and efficiency. This phenomenon is particularly pronounced under prolonged high-frequency, high-power operation, further affecting the overall performance and reliability of the device.

[0032] As described in the background section, the reliability of power semiconductor devices in the prior art is not ideal. To solve the above problems, embodiments of this application provide a power semiconductor device and a method for fabricating a power semiconductor device.

[0033] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0034] Figure 1 , Figure 2 as well as Figure 5 This is a schematic diagram of the structure of a first type of power semiconductor device provided according to an embodiment of this application. For example... Figure 1 , Figure 2 as well as Figure 5 As shown, it includes:

[0035] Substrate 10;

[0036] The substrate 10 can be made of silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, sapphire, etc.

[0037] Epitaxial layer 11 is located on one side of the substrate 10;

[0038] In practical applications, the epitaxial layer 11 can be a single-layer structure or a multi-layer structure. The doping type of the epitaxial layer 11 is the same as that of the substrate 10. Its thickness ranges from 5 to 10 μm, and the carrier concentration is 1e⁻¹. 12 -1e 16 cm -3 .

[0039] The gate structure 12 is at least partially located within the epitaxial layer 11, and the shape of at least a portion of the gate structure 12 is hemispherical.

[0040] like Figure 2 As shown, the gate structure 12 can be curved only on the bottom surface, which can increase the thickness of the gate structure 12 and thus improve the voltage withstand capability of the power semiconductor device; or, only the sides can be curved; or, as shown... Figure 1 As shown, the bottom and side surfaces of the gate structure 12 are both curved, forming a hemispherical structure, compared to Figure 2 The structure shown can further reduce the complexity of the manufacturing process. In practical applications, the gate structure 12 includes a gate oxide layer 121 and a gate 122. The gate 122 is located on the side of the gate oxide layer 121 away from the substrate 10. The gate oxide layer 121 can be made of oxide, and the gate 122 can be made of polysilicon. Figure 3 yes Figure 1 Top view, Figure 1 It is along Figure 3 The cross-sectional view obtained along the AA' direction, as shown below. Figure 3 As shown, the cross-sectional shape of the gate structure 12 along the thickness direction perpendicular to the substrate 10 can be circular. Figure 4 yes Figure 1 Another top view, Figure 1 It is along Figure 3The cross-sectional view obtained along the AA' direction, as shown below. Figure 4 As shown, the cross-sectional shape of the gate structure 12 along the thickness direction perpendicular to the substrate 10 can be polygonal.

[0041] Schottky contact region 17 is located within the epitaxial layer 11 and between two adjacent gate structures 12.

[0042] The depth of the aforementioned Schottky contact region 17 can be 0.01~0.1 μm, and the width of the aforementioned Schottky contact region 17 can be 0.1~1.0 μm. For example... Figure 3 and Figure 4 As shown, in one specific embodiment, the Schottky contact region 17 is equidistant from the adjacent gate structure 12.

[0043] The source structure 18 is located on the side of the epitaxial layer 11 away from the substrate 10;

[0044] The thickness of the aforementioned source structure 18 can be 4~8μm, and the material of the aforementioned source structure 18 can be one or more alloys of nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru), platinum (Pt), etc.

[0045] The drain structure 19 is located on the side of the substrate 10 away from the epitaxial layer 11.

[0046] The thickness of the drain structure 19 can be 1~3μm, and the material of the drain structure 19 can be one or more alloys of nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru), platinum (Pt).

[0047] This embodiment provides a power semiconductor device, including a substrate; an epitaxial layer located on one side of the substrate; a gate structure at least partially located within the epitaxial layer, the shape of which is hemispherical; a Schottky contact region located within the epitaxial layer and between two adjacent gate structures; a source structure located on the side of the epitaxial layer away from the substrate; and a drain structure located on the side of the substrate away from the epitaxial layer. This solution avoids the technical problems of uneven gate oxide quality and electric field concentration at the corners of the gate structure, which affect the reliability and withstand voltage of the device, caused by setting the shape of at least part of the gate structure to hemispherical. Furthermore, by setting the Schottky contact region and integrating the structure of a Schottky barrier diode, the reverse turn-off characteristics of the device are further optimized, switching losses are reduced, and the overall reliability of the power semiconductor device is optimized.

[0048] In some other embodiments, such as Figure 1, Figure 2 as well as Figure 5 As shown, the power semiconductor device further includes: a first doped region 13 located within the epitaxial layer 11 and on both sides of the gate structure 12, wherein the doping type of the first doped region 13 is different from the doping type of the substrate 10; a second doped region 14 located within the epitaxial layer 11 and on the side of the first doped region 13 away from the gate structure 12, wherein the doping type of the second doped region 14 is different from the doping type of the substrate 10; an active region 15 located within the epitaxial layer 11, on both sides of the gate structure 12 and on the side of the first doped region 13 away from the substrate 10, wherein the doping type of the active region 15 is different from the doping type of the first doped region 13; and a third doped region 16 located within the epitaxial layer 11 and on the side of the second doped region 14 away from the gate structure 12, wherein the doping type of the third doped region 16 is the same as the doping type of the substrate 10. In practical applications, this application does not limit the thickness and width of the first doped region 13, and those skilled in the art can set and adjust it according to actual conditions. The doping type of the second doped region 14 is the same as that of the first doped region 13. This application does not limit the thickness and width of the second doped region 14; those skilled in the art can set and adjust them according to actual conditions. The doping type of the active region 15 is different from both the first doped region 13 and the second doped region 14; the doping type of the active region 15 is the same as that of the substrate 10 and the epitaxial layer 11. The ion implantation concentration of the active region 15 can be 1e⁻¹. 17 ~1e 20 cm 3 The doping concentration of the third doped region 16 mentioned above can be 1e. 17 ~1e 20 cm 3 .

[0049] In other embodiments, such as Figure 1 As shown, the gate structure 12 satisfies at least one of the following: the central angle of the cross-section of the gate structure 12 along the thickness direction of the substrate 10 is 120~170°, wherein the cross-section is the cross-section of the gate structure 12 along the thickness direction of the substrate 10; the average radius of the cross-section of the gate structure 12 along the thickness direction of the substrate 10 is a first width, the width of the surface of the gate structure 12 away from the substrate 10 is a second width, and the ratio of the first width to the second width is 0.5~1.5.

[0050] The central angle of the gate structure is within the range of 120° to 170°, and the ratio of the first width to the second width is within the range of 0.5 to 1.5. This ensures that the depth of the gate structure is appropriate while preventing excessive manufacturing complexity from increasing costs. Specifically, the gate structure forms a fan-shaped structure. The average thickness of the gate structure along the thickness direction of the substrate is 0.4 to 0.8 μm; the average width of the gate structure along the thickness direction perpendicular to the substrate is 0.6 to 1.0 μm; and the average spacing between two adjacent gate structures is 0.5 to 1.5 μm. The average width of the gate structure being within the range of 0.6 to 1.0 μm and the average spacing between two adjacent gate structures being within the range of 0.5 to 1.5 μm ensures that the width of the gate structure is appropriate and prevents mutual interference between the gate structures.

[0051] In other embodiments, such as Figure 1 As shown, the gate structure 12 includes a gate oxide layer 121 and a gate 122. The gate oxide layer 121 is located between the gate 122 and the epitaxial layer 11, wherein the gate 122 is a trench gate. The gate structure 12 includes a gate oxide layer 121 and a gate 122. The gate oxide layer 121 and the gate 122 work together to not only control the flow of charge carriers, but also further ensure the stability and reliability of the device.

[0052] In some other embodiments, such as Figure 1 and Figure 5 As shown, the gate structure 12 is hemispherical. The fabrication process for this hemispherical gate structure 12 is simple and suitable for medium- and low-voltage power semiconductor devices.

[0053] In other embodiments, such as Figure 2 As shown, the gate structure 12 is divided into a first part and a second part along the thickness direction of the substrate 10, and the second part is hemispherical in shape. Compared with the spherical gate structure 12, the gate structure 12 with the above shape can further deepen the trench, thereby further improving the voltage withstand capability of the power semiconductor device, and thus making it more suitable for high voltage applications.

[0054] Specifically, the second part is located on the side closer to the substrate, the first part is located on the side of the second part away from the substrate, the thickness of the first part is in the range of 1~2.5μm, the center angle of the second part is 25~60°, and the width of the first part and the second part is in the range of 0.5~1.5μm.

[0055] In some other embodiments, such as Figure 1As shown, the Schottky contact region 17 satisfies at least one of the following: the average thickness of the Schottky contact region 17 along the thickness direction of the substrate 10 is 0.01~0.1μm; the average width of the Schottky contact region 17 along the thickness direction perpendicular to the substrate 10 is 0.1~1μm.

[0056] The average thickness of the Schottky contact area is in the range of 0.01~0.1μm, which can reduce thermal resistance while ensuring the performance of the Schottky contact area. The average width of the Schottky contact area is in the range of 0.1~1μm, which can avoid current concentration and localized heating, and also prevent excessive parasitic capacitance from affecting switching speed.

[0057] In other embodiments, such as Figure 1 , Figure 2 as well as Figure 5 As shown, the gate structure 12 has a polygonal or circular cross-sectional shape along the thickness direction perpendicular to the substrate 10, and the Schottky contact region 17 has a polygonal or circular cross-sectional shape along the thickness direction perpendicular to the substrate 10. The cross-sectional shapes of the gate structure 12 and the Schottky contact region 17 can further increase the Schottky contact area, thereby further improving device performance.

[0058] Specifically, the cross-sectional shape of the gate structure 12 along the thickness direction perpendicular to the substrate 10 can be as follows: Figure 3 The circle shown can also be as follows: Figure 4 The polygon shown. The cross-sectional shape of the Schottky contact region 17 along the thickness direction perpendicular to the substrate 10 can be as follows. Figure 3 The circle shown can also be as follows: Figure 4 The polygon shown.

[0059] like Figure 3 and 4 As shown, the Schottky contact region 17 and gate structure 12 can be arranged in a "4+1" configuration, that is, one Schottky contact region 17 is placed at the center position between four adjacent gate structures 12. The above arrangement of the Schottky contact region 17 and gate structure 12 can further reduce the cell size and improve compactness.

[0060] In another specific embodiment, such as Figure 1 As shown, the doping concentration of the second doped region 14 is greater than that of the first doped region 13. This configuration can further improve the performance of power semiconductor devices.

[0061] The doping concentration of the first doped region mentioned above can be 1e. 15 ~1e 17 cm 3 The doping concentration of the second doped region can be 1e.17 ~1e 20 cm 3 .

[0062] In the specific implementation process, such as Figure 1 As shown, the surface of the epitaxial layer 11 closest to the substrate 10 is the first surface, the surface of the gate structure 12 furthest from the substrate 10 is the second surface, and the surface of the epitaxial layer 11 furthest from the substrate 10 is the third surface. The minimum distance between the third surface and the first surface is less than the minimum distance between the second surface and the first surface. In other words, the height of the gate structure 12 is slightly higher than the upper surface of the epitaxial layer 11, which can further avoid leakage caused by incomplete etching of the edge areas during the trench etching process of the gate structure 12, thereby further improving the reliability of the power semiconductor device.

[0063] In practical applications, the minimum distance between the third surface and the first surface can be 0.1 μm, just as the minimum distance between the second surface and the first surface can be 0.1 μm.

[0064] In other embodiments, such as Figure 5 As shown, the power semiconductor device further includes at least one of the following: a first ohmic contact region 20 located between the drain structure 19 and the substrate 10; a second ohmic contact region 21 located between the Schottky contact region 17 and the source structure 18, between the second doped region 14 and the source structure 18, and between the active region 15 and the source structure 18; and a dielectric layer 22 located between the gate structure 12 and the source structure 18. The dielectric layer 22 is used to isolate the gate structure 12 and the source structure 18, providing good isolation, thereby further improving the reliability of the power semiconductor device.

[0065] The thickness of the dielectric layer can be 1.0~2.5μm, and the material of the dielectric layer can be a low dielectric constant material such as SiOF, TEOS, MSQ, BPSG, or a combination thereof.

[0066] In another specific embodiment, the minimum distance between the Schottky contact region and each of the adjacent gate structures is the same.

[0067] This application also provides a method for fabricating a power semiconductor device, used to fabricate any of the above-mentioned power semiconductor devices. Figure 6 This is a schematic flowchart illustrating a method for fabricating a power semiconductor device according to an embodiment of this application. Figure 6 As shown, the fabrication method of the above-mentioned power semiconductor device includes:

[0068] Step S301, provide a substrate;

[0069] The substrate material can be silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, sapphire, etc.

[0070] Step S302: A first pre-epitaxial layer 23 is formed on one side of the substrate 10, resulting in the following... Figure 7 The structure shown in (a);

[0071] In practical applications, epitaxial layers can be formed using methods such as Chemical Vapor Deposition (CVD), Metal-Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), Atomic Layer Deposition (ALD), and Physical Vapor Deposition (PVD). These epitaxial layers can be single-layer or multi-layer structures, and the doping type of the epitaxial layer is the same as that of the substrate.

[0072] Step S303: The first pre-epitaxy layer 23 is processed to obtain a first pre-doped region 25, a second pre-doped region 26, and a pre-active region 27. The remaining portion of the first pre-epitaxy layer 23 forms a second pre-epitaxy layer 24. The second pre-doped region 26 is located on both sides of the first pre-doped region 25 and the pre-active region 27. The pre-active region 27 is located on the side of the first pre-doped region 25 away from the substrate. The doping type of the first pre-doped region 25 is different from the doping type of the substrate. The doping type of the second pre-doped region 26 is different from the doping type of the substrate. The doping type of the pre-active region 27 is different from the doping type of the first pre-doped region 25. The result is as follows: Figure 7 The structure shown in (b);

[0073] The aforementioned first pre-doped region, second pre-doped region, and pre-active region can be formed by ion implantation or by etching followed by backfilling. This application does not limit the width and thickness of the aforementioned first pre-doped region, second pre-doped region, and pre-active region; those skilled in the art can set and adjust them according to actual conditions.

[0074] In step S304, a mask layer 28 and a photoresist layer 29 are sequentially formed on the surface of the pre-active region 27 away from the substrate 10 and the surface of the second pre-doped region 26 away from the substrate 10, to obtain the following: Figure 7 The structure shown in (c);

[0075] This application does not limit the materials and thickness of the above-mentioned mask layer and photoresist layer, and those skilled in the art can set and adjust them according to the actual situation.

[0076] Step S305: Sequentially remove the photoresist layer 29, a portion of the mask layer 28, a portion of the prepared active region 27, a portion of the first prepared doped region 25, and a portion of the second prepared epitaxial layer 24 to form a groove 40. Remove the remaining mask layer 28. The remaining first prepared doped region 25 forms the first doped region 13, and the remaining prepared active region 27 forms the active region 15. At least one of the bottom and side surfaces of the groove 40 is curved, resulting in... Figure 7 The structure shown in (d);

[0077] The aforementioned photoresist, mask layer, pre-active region, first pre-doped region, and second pre-epitaxial layer can be removed by etching. During the etching process of the photoresist and mask layer, the formation of the aforementioned grooves can be achieved by adjusting the center focus of the light source. After completing the above process steps, the structure surface is cleaned, a carbon film is deposited on the device surface, and then annealing is performed at a high temperature to activate the implanted ions and repair lattice damage during the implantation process. The annealing temperature is between 1700℃ and 1800℃, and the time is between 30 and 60 minutes.

[0078] Step S306, at least in the aforementioned groove 40, a gate structure 12 is formed to obtain the following: Figure 7 The structure shown in (e);

[0079] In practical applications, such as Figure 7 As shown in (e), the gate oxide layer 121 and the gate 122 can be sequentially deposited in the groove to obtain the gate structure 12 described above. The specific process flow is as follows: After annealing, a gate oxide layer is formed on the surface of the epitaxial layer by thermal oxidation, and then annealed in a nitrogen-containing atmosphere. The nitrogen-containing atmosphere helps to reduce interface state defects between the silicon carbide surface and the gate oxide layer. The thickness of the gate oxide layer is between 100 and 600 angstroms. The annealing temperature is between 1000°C and 1100°C, and the time is between 30 and 60 minutes.

[0080] Step S307: The second pre-doped region 26 is processed to obtain a third doped region 16 and a Schottky contact region 17, wherein the Schottky contact region 17 is located on the side of the third doped region 16 away from the substrate 10. The remaining second pre-doped region 26 forms a second doped region 14, resulting in an epitaxial layer 11. The doping type of the third doped region 16 is the same as the doping type of the substrate 10, resulting in... Figure 7 The structure shown in (f);

[0081] Step S308: A source structure 18 is formed on the side of the epitaxial layer 11 away from the substrate 10, resulting in... Figure 7 The structure shown in (g);

[0082] The material of the above-mentioned source structure can be one or more alloys of nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru), platinum (Pt), etc.

[0083] Step S309: A drain structure 19 is formed on the side of the substrate 10 away from the epitaxial layer 11, resulting in... Figure 1 The structure shown.

[0084] The material of the above-mentioned drain structure can be one or more alloys of nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru), platinum (Pt), etc.

[0085] This embodiment provides a method for fabricating a power semiconductor device. First, a substrate is provided; a first pre-epitaxial layer is formed on one side of the substrate; the pre-epitaxial layer is then processed to obtain a first pre-doped region, a second pre-doped region, and a pre-active region, with the remaining first pre-epitaxial layer forming a second pre-epitaxial layer; a mask layer and a photoresist layer are sequentially formed on the surface of the pre-active region away from the substrate and the surface of the second pre-doped region away from the substrate; then, the photoresist layer, a portion of the mask layer, a portion of the pre-active region, a portion of the first pre-doped region, and a portion of the second pre-epitaxial layer are sequentially removed to form a trench, and the remaining mask layer is removed, with the remaining first pre-doped region forming a first doped region and the remaining pre-active region forming an active region; a gate structure is formed at least in the trench; the second pre-doped region is then processed to obtain a third doped region and a Schottky contact region; finally, a source structure is formed on the side of the epitaxial layer away from the substrate; and a drain structure is formed on the side of the substrate away from the epitaxial layer. This solution avoids the technical problems of uneven gate oxide quality and electric field concentration at the corners of the gate structure affecting the reliability and withstand voltage of the device caused by the right angle between the sidewalls and bottom of the gate structure in the prior art, which is due to the curved bottom and the right angle between the gate structure sidewalls and bottom. At the same time, by setting the Schottky contact area and integrating the structure of the Schottky barrier diode, the reverse turn-off characteristics of the device are further optimized, the switching loss is reduced, and the overall reliability of the power semiconductor device is optimized.

[0086] In the specific implementation process, step S305 above can be achieved through the following steps:

[0087] Step S3051: Remove a portion of the photoresist layer 29 to obtain a first pre-grooved groove 41, wherein at least one of the bottom surface and side surface of the first pre-grooved groove 41 is a curved surface, and the central angle of the curved surface of the first pre-grooved groove 41 is smaller than the central angle of the curved surface of the groove, resulting in... Figure 8 The structure shown in (a);

[0088] Step S3052: Remove a portion of the mask layer 28 to obtain the second pre-reserved groove 42, and remove the remaining photoresist layer 29. At least one of the bottom and side surfaces of the second pre-reserved groove 42 is a curved surface. The central angle of the curved surface of the second pre-reserved groove 42 is smaller than the central angle of the curved surface of the groove, and the central angle of the curved surface of the second pre-reserved groove 42 is larger than the central angle of the curved surface of the first pre-reserved groove 41, resulting in... Figure 8 The structure shown in (b);

[0089] Step S3053: Sequentially remove a portion of the aforementioned prepared active region 27, a portion of the aforementioned first prepared doped region 25, and a portion of the aforementioned second prepared epitaxial layer 24 to obtain the aforementioned groove 40, and remove the remaining aforementioned mask layer 28 to obtain the following... Figure 7 The structure shown in (d).

[0090] The above-mentioned dry etching method for forming grooves can further improve the accuracy of gate groove formation compared to wet etching or other etching methods.

[0091] Step S307 above can also be achieved through the following steps: Step S2071, removing a portion of the second pre-doped region to form a third pre-doped groove, with the remaining second pre-doped region forming the third pre-doped region; Step S2072, processing the third pre-doped region to obtain the third doped region; Step S2073, depositing metal material in the third pre-doped groove to obtain the Schottky contact region. This method can further simplify the processing difficulty of the Schottky contact region and the third doped region.

[0092] The aforementioned third doped region can be formed by ion implantation.

[0093] As can be seen from the above description, the embodiments of the present invention achieve the following technical effects:

[0094] 1) The power semiconductor device of this application includes a substrate; an epitaxial layer located on one side of the substrate; a gate structure at least partially located within the epitaxial layer, wherein at least one of the bottom and side surfaces of the gate structure along the thickness direction of the substrate is curved; a first doped region located within the epitaxial layer and on both sides of the gate structure; a second doped region located within the epitaxial layer and on the side of the first doped region away from the gate structure; an active region located within the epitaxial layer, on both sides of the gate structure, and on the side of the first doped region away from the substrate; a third doped region located within the epitaxial layer and on the side of the second doped region away from the gate structure; a Schottky contact region located within the epitaxial layer and on the side of the third doped region away from the substrate; a source structure located on the side of the epitaxial layer away from the substrate; and a drain structure located on the side of the substrate away from the epitaxial layer. This solution avoids the technical problems of uneven gate oxide quality and electric field concentration at the corners of the gate structure affecting the reliability and withstand voltage of the device caused by the right angle between the sidewalls and bottom of the gate structure in the prior art, which is due to the curved bottom and the right angle between the gate structure sidewalls and bottom. At the same time, by setting the Schottky contact area and integrating the structure of the Schottky barrier diode, the reverse turn-off characteristics of the device are further optimized, the switching loss is reduced, and the overall reliability of the power semiconductor device is optimized.

[0095] 2) The method for fabricating a power semiconductor device according to this application includes: First, a substrate is provided; a first pre-epitaxial layer is formed on one side of the substrate; the pre-epitaxial layer is then processed to obtain a first pre-doped region, a second pre-doped region, and a pre-active region, with the remaining first pre-epitaxial layer forming a second pre-epitaxial layer; a mask layer and a photoresist layer are sequentially formed on the surface of the pre-active region away from the substrate and the surface of the second pre-doped region away from the substrate; then, the photoresist layer, a portion of the mask layer, a portion of the pre-active region, a portion of the first pre-doped region, and a portion of the second pre-epitaxial layer are sequentially removed to form a trench, and the remaining mask layer is removed, with the remaining first pre-doped region forming a first doped region and the remaining pre-active region forming an active region; a gate structure is formed at least in the trench; the second pre-doped region is then processed to obtain a third doped region and a Schottky contact region; finally, a source structure is formed on the side of the epitaxial layer away from the substrate; and a drain structure is formed on the side of the substrate away from the epitaxial layer. This solution avoids the technical problems of uneven gate oxide quality and electric field concentration at the corners of the gate structure affecting the reliability and withstand voltage of the device caused by the right angle between the sidewalls and bottom of the gate structure in the prior art, which is due to the curved bottom and the right angle between the gate structure sidewalls and bottom. At the same time, by setting the Schottky contact area and integrating the structure of the Schottky barrier diode, the reverse turn-off characteristics of the device are further optimized, the switching loss is reduced, and the overall reliability of the power semiconductor device is optimized.

[0096] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A power semiconductor device, characterized in that, include: Substrate; An epitaxial layer is located on one side of the substrate; A gate structure, at least partially located within the epitaxial layer, wherein at least a portion of the gate structure is hemispherical in shape; A Schottky contact region is located within the epitaxial layer and between two adjacent gate structures; The source structure is located on the side of the epitaxial layer away from the substrate; The drain structure is located on the side of the substrate away from the epitaxial layer.

2. The power semiconductor device according to claim 1, characterized in that, The power semiconductor device further includes: The first doped region is located within the epitaxial layer and on both sides of the gate structure. The doping type of the first doped region is different from the doping type of the substrate. The second doped region is located within the epitaxial layer and on the side of the first doped region away from the gate structure. The doping type of the second doped region is different from the doping type of the substrate. The active region is located within the epitaxial layer, on both sides of the gate structure, and on the side of the first doped region away from the substrate. The doping type of the active region is different from that of the first doped region. The third doped region is located within the epitaxial layer and on the side of the second doped region away from the gate structure, and the doping type of the third doped region is the same as the doping type of the substrate.

3. The power semiconductor device according to claim 1, characterized in that, The gate structure satisfies at least one of the following: The central angle of the cross-section of the gate structure along the thickness direction of the substrate is 120~170°; The average radius of the cross-section of the gate structure along the thickness direction of the substrate is the first width, and the width of the surface of the gate structure away from the substrate is the second width. The ratio of the first width to the second width is 0.5 to 1.

5.

4. The power semiconductor device according to claim 1, characterized in that, The gate structure includes a gate oxide layer and a gate, wherein the gate oxide layer is located between the gate and the epitaxial layer, and the gate is a trench gate.

5. The power semiconductor device according to claim 1, characterized in that, The gate structure is hemispherical in shape.

6. The power semiconductor device according to claim 1, characterized in that, The gate structure is divided into a first part and a second part along the thickness direction of the substrate, and the second part is hemispherical in shape.

7. The power semiconductor device according to claim 1, characterized in that, The gate structure has a polygonal or circular cross-sectional shape along the thickness direction perpendicular to the substrate, and the Schottky contact region has a polygonal or circular cross-sectional shape along the thickness direction perpendicular to the substrate.

8. A method for fabricating a power semiconductor device, characterized in that, The method for preparing the power semiconductor device according to any one of claims 1 to 7 comprises: Provide substrate; A first pre-epiaxial layer is formed on one side of the substrate; The first pre-epipolar layer is processed to obtain a first pre-doped region, a second pre-doped region, and a pre-active region. The remaining first pre-epipolar layer forms the second pre-epipolar layer. The second pre-doped region is located on both sides of the first pre-doped region and the pre-active region. The pre-active region is located on the side of the first pre-doped region away from the substrate. The doping type of the first pre-doped region is different from the doping type of the substrate. The doping type of the second pre-doped region is different from the doping type of the substrate. The doping type of the pre-active region is different from the doping type of the first pre-doped region. A mask layer and a photoresist layer are sequentially formed on the surface of the pre-active region away from the substrate and on the surface of the second pre-doped region away from the substrate; The photoresist layer, a portion of the mask layer, a portion of the pre-active region, a portion of the first pre-doped region, and a portion of the second pre-epitaxial layer are removed sequentially to form a groove. The remaining mask layer is then removed, the remaining first pre-doped region forms a first doped region, and the remaining pre-active region forms an active region. At least one of the bottom surface and side surface of the groove is a curved surface. A gate structure is formed at least in the groove; The second pre-doped region is processed to obtain a third doped region and a Schottky contact region, wherein the Schottky contact region is located on the side of the third doped region away from the substrate, and the remaining second pre-doped region forms a second doped region to obtain an epitaxial layer, wherein the doping type of the third doped region is the same as the doping type of the substrate. A source structure is formed on the side of the epitaxial layer away from the substrate; A drain structure is formed on the side of the substrate away from the epitaxial layer.

9. The method for fabricating a power semiconductor device according to claim 8, characterized in that, Sequentially removing the photoresist layer, a portion of the mask layer, a portion of the prepared active region, a portion of the first prepared doped region, and a portion of the second prepared epitaxial layer to form a groove, including: A portion of the photoresist layer is removed to obtain a first pre-groove, wherein at least one of the bottom surface and the side surface of the first pre-groove is a curved surface, and the central angle of the curved surface of the first pre-groove is smaller than the central angle of the curved surface of the groove. A portion of the mask layer is removed to obtain a second pre-groove, and the remaining photoresist layer is removed. The bottom surface and the side surface of the second pre-groove are at least curved surfaces. The central angle of the curved surface of the second pre-groove is smaller than the central angle of the curved surface of the groove, and the central angle of the curved surface of the second pre-groove is larger than the central angle of the curved surface of the first pre-groove. The groove is obtained by sequentially removing a portion of the prepared active region, a portion of the first prepared doped region, and a portion of the second prepared epitaxial layer, and then removing the remaining mask layer.

10. The method for fabricating a power semiconductor device according to claim 8, characterized in that, The second pre-doped region is processed to obtain a third doped region and a Schottky contact region, including: A portion of the second pre-doped region is removed to form a third pre-doped groove, and the remaining second pre-doped region forms the third pre-doped region; The third pre-doped region is processed to obtain the third doped region; Metal material is deposited in the third pre-reserved groove to obtain the Schottky contact area.

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