Semiconductor structure and preparation method thereof, and semiconductor device

Abstract

The invention relates to a semiconductor structure and a preparation method thereof, and a semiconductor device. The semiconductor structure comprises a lifting substrate; the interlayer dielectric layers and the gate grooves are located on the first surface of the substrate and are alternately arranged in the first direction parallel to the first surface; a dielectric lamination layer, a target work function layer, a protection layer, a barrier layer and a metal conductive layer which are sequentially arranged along a second direction deviating from the substrate are arranged in the gate trench; wherein the dielectric stack is located on the inner surface of the gate trench; the longitudinal section of the target work function layer is concave, and the top surface is lower than the plane where the opening of the gate trench is located; the protection layer is located on the upper surface of the target work function layer and the inner wall of the dielectric lamination layer, and the top surface of the protection layer is flush with the top surfaces of the barrier layer, the metal conductive layer and the interlayer dielectric layer. In the structure, the surface and the side wall of the work function layer are ensured to be provided with the protection layers for protecting the work function layer, and the protection layers are not directly exposed on the surface of the grid, so that Wet HF in the subsequent process does not damage the bottom work function layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a semiconductor structure, a preparation method thereof, and a semiconductor device. BACKGROUND

[0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly realized by continuously reducing the size of integrated circuit devices to improve its speed. In advanced chip manufacturing, a high dielectric parameter metal gate (HK-MG) process is widely used to improve chip performance, in which a plurality of work function metals can be selected to adjust the threshold voltage of the metal gate.

[0003] However, in the process of forming the metal gate, since the gate material is soft and active in nature, defects such as particle residues, scratches, and corrosion are easily generated in chemical mechanical polishing (CMP), which destroys the original morphology of the gate in subsequent processes, thereby affecting the performance of the device. SUMMARY

[0004] Therefore, it is necessary to provide a semiconductor structure, a preparation method thereof, and a semiconductor device to at least maintain the morphology of the gate in the subsequent polishing process to solve the technical problems in the prior art.

[0005] In a first aspect, the present application provides a semiconductor structure, comprising: a substrate; and an interlayer dielectric layer and a gate trench alternately arranged along a first direction parallel to a first surface of the substrate on the first surface of the substrate;

[0006] The gate trench comprises, in sequence along a second direction away from the substrate, a dielectric stack, a target work function layer, a protective layer, a barrier layer, and a metal conductive layer; wherein the dielectric stack is located on the inner surface of the gate trench; the longitudinal section of the target work function layer is in the shape of a concave character, and the top surface is lower than the plane where the gate trench opening is located; the protective layer is located on the upper surface of the target work function layer and the inner wall of the dielectric stack, and the top surface is flush with the top surfaces of the barrier layer, the metal conductive layer, and the interlayer dielectric layer.

[0007] In the semiconductor structure of the above-mentioned embodiments, the longitudinal section of the target work function layer is in the shape of a concave character, and the sidewall is lower than the sidewall of the gate trench. The protective layer covers the concave character structure of the work function and extends to the interface between the dielectric stack and the barrier layer, effectively avoiding the direct contact of the etching solution with the target work function layer when the etching solution penetrates along the defects or damage on the surface of the covering layer in the subsequent polishing process, and ensuring the integrity of the morphology of the target work function layer.

[0008] In some embodiments, the dielectric stack comprises: a first dielectric layer, a second dielectric layer;

[0009] The first dielectric layer is located on the bottom surface of the gate trench.

[0010] The second dielectric layer is located on the top surface of the first dielectric layer and the inner wall of the gate trench.

[0011] In some embodiments, the inner wall of the second dielectric layer is in contact with the outer wall of the target work function layer and the outer wall of the protective layer.

[0012] In some embodiments, the substrate includes a first active region and a second active region arranged along a first direction.

[0013] The second dielectric layer in the first active region is the same as or different from the second dielectric layer of the second active region.

[0014] In a second aspect, the present application provides a semiconductor structure preparation method, including: providing a substrate, the first surface of the substrate including alternatingly arranged interlayer dielectric layers and gate trenches along a first direction parallel to the first surface;

[0015] After the gate trench is formed with the dielectric stack, an initial work function layer with a preset excess thickness is formed to cover the dielectric stack; the thickness is used to represent the size along a second direction away from the substrate.

[0016] The target gas is used to remove part of the initial work function layer of the gate trench, so that part of the inner wall of the gate trench is exposed, and a target work function layer with a longitudinal section in the shape of a concave character is obtained.

[0017] A protective layer is formed to cover at least the upper surface of the target work function layer and the exposed inner wall.

[0018] In the preparation method in the above embodiments, part of the sidewall of the initial work function layer is removed by selective etching with the target gas to form a concave character structure, so as to ensure that the top surface of the target work function layer is lower than the plane where the gate trench opening is located. During the etching process, the dielectric stack acts as an etching stop layer to effectively protect the gate trench from damage.

[0019] The protective layer has excellent step coverage capability, completely wraps the concave structure, thereby blocking the penetration path of the subsequent etching solution, and ensuring the integrity of the target work function layer structure.

[0020] In some embodiments, the target gas is used to remove part of the initial work function layer, including:

[0021] The target gas including hydrogen fluoride and ammonia is used to remove the initial work function layer with a target thickness in the gate trench.

[0022] In some embodiments, the preset excess thickness is positively correlated with the target thickness.

[0023] In some embodiments, the dielectric stack includes a first dielectric layer and a second dielectric layer.

[0024] The first dielectric layer is located at the bottom of the gate trench;

[0025] The second dielectric layer is located on the top surface of the first dielectric layer and on the inner wall of the gate trench;

[0026] The substrate includes a first active region and a second active region arranged along a first direction;

[0027] The second dielectric layer in the first active region may be the same as or different from the second dielectric layer in the second active region.

[0028] In some embodiments, a barrier layer is formed that at least covers the inner surface of the protective layer, and a metallic conductive layer is formed that fills the remaining gaps in the gate trench.

[0029] Chemical mechanical polishing is performed on the semiconductor structure to form a metal gate.

[0030] Thirdly, this application also provides a semiconductor device, including the semiconductor structure as described in any of the above embodiments; or the semiconductor structure formed by the preparation method as described in any of the above embodiments.

[0031] In the semiconductor devices described above, key failure issues such as threshold voltage drift and gate leakage caused by physical damage or chemical corrosion of the target work function layer can be effectively avoided, reducing chip manufacturing defects from the source and providing a reliable guarantee for improving chip yield.

[0032] The semiconductor structure, its fabrication method, and the electronic device provided in this application have the following unexpected technical effects:

[0033] During the process, anisotropic etching is used to precisely shape the concave target work function layer. At the same time, conformal coating technology is used to form a continuous and sealed protective layer on the surface and sidewalls of the target work function layer, which isolates the erosion of etching solutions in subsequent CMP, wet cleaning and other processes, effectively ensuring the integrity of the target work function layer and thus significantly improving the chip yield. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1a This is a schematic diagram of the fabrication process of a semiconductor structure in related technologies;

[0036] Figure 1b for Figure 1a A schematic diagram of a partial cross-sectional electron microstructure of the middle gate;

[0037] Figure 2 A cross-sectional schematic view of a semiconductor structure provided in an embodiment of the present application;

[0038] Figure 3 A flowchart of a semiconductor structure preparation method provided in an embodiment of the present application;

[0039] Figure 4 A cross-sectional schematic view of a structure obtained after forming a gate trench in step S102 of a semiconductor structure preparation method provided in an embodiment of the present application;

[0040] Figure 5a A cross-sectional schematic view of a structure obtained after forming a dielectric stack in step S502 of a semiconductor structure preparation method provided in an embodiment of the present application;

[0041] Figure 5b A cross-sectional schematic view of a structure obtained after forming a dielectric stack in step S502 of a semiconductor structure preparation method provided in an embodiment of the present application; Figure 5a An enlarged structure schematic view of the dashed box in FIG. 10;

[0042] Figure 6 A cross-sectional schematic view of a structure obtained after forming an initial work function layer in step S504 of a semiconductor structure preparation method provided in an embodiment of the present application;

[0043] Figure 7 A cross-sectional schematic view of a structure obtained after forming a target work function layer in step S106 of a semiconductor structure preparation method provided in an embodiment of the present application;

[0044] Figure 8 A cross-sectional schematic view of a structure obtained after forming a protection layer in step S108 of a semiconductor structure preparation method provided in an embodiment of the present application;

[0045] Figure 9 A cross-sectional schematic view of a structure obtained after forming a dielectric stack in step S502 of a semiconductor structure preparation method provided in an embodiment of the present application; Figure 8 A cross-sectional schematic view of a structure obtained after forming a barrier layer and a metal conductive layer in step S504 of a semiconductor structure preparation method provided in an embodiment of the present application;

[0046] Figure 10 A comparison schematic view of a semiconductor structure provided in the present application and a semiconductor structure provided in the related art.

[0047] Legend of reference signs:

[0048] 10, substrate; 11, interlayer dielectric layer; 12, gate trench; 21, first dielectric layer; 22, second dielectric layer; 201, first dielectric material layer; 202, second dielectric material layer; 203, third dielectric material layer; 204, fourth dielectric material layer; 205, fifth dielectric material layer; 301, initial work function layer; 30, target work function layer; 40, protection layer; 50, barrier layer; 60, metal conductive layer. DETAILED DESCRIPTION

[0049] For the purposes of this application, the application will now be described in more detail, by way of example only, with reference to the accompanying drawings. The preferred embodiments of the application are shown in the drawings. However, the application can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0051] It will be understood that when an element or layer is referred to as being "on" or "adjacent" or "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first dopant type could be termed a second dopant type, and similarly, a second dopant type could be termed a first dopant type; a first dopant type and a second dopant type are different dopant types, for example, a first dopant type can be P-type and a second dopant type can be N-type, or a first dopant type can be N-type and a second dopant type can be P-type.

[0052] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0053] As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. As used herein, the term "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0054] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implantation occurs. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the application, unless otherwise defined herein.

[0055] As the process flow 800 illustrates, the process flow 800 can include a number of operations, some of which can be combined or performed in a different order than shown. Figure 1aAs shown, during the formation of the gate structure in the grinding process, the grinding particles and the grinding liquid residues are easy to adhere and gather on the top surface of the gate, forming particle contaminants. In the dry etching step of the high resistivity (HiR) process, the surface of the cover layer forms local stress concentration or uneven etching due to the particle residues, resulting in defects such as pinholes and cracks in the cover layer, which destroys the continuity of the cover layer, causing the work function layer below to be directly exposed. When entering the subsequent wet etching process, although the gate metal layers are filled normally, the etching solution will penetrate to the work function layer along the channels formed by the defects of the cover layer. Since the etching rate of the etching solution on the work function layer material is significantly higher than that of the metal layer, the solution will continue to corrode along the sidewall of the work function layer, eventually causing the bottom work function layer to be partially missing, forming a void, and the specific structure is as follows Figure 1b As shown, directly causing the device to have threshold voltage drift, gate leakage and other electrical performance failures, seriously affecting the chip yield and reliability.

[0056] Based on this, please refer to Figure 2 The semiconductor structure provided in the present application includes a substrate, and a first surface on the front surface and a back surface opposite to the front surface, i.e., a second surface. In the case of ignoring the flatness of the first surface and the second surface, a first direction parallel to the first surface is defined, and the direction towards the substrate includes a second direction perpendicular to the first surface of the substrate. In the embodiments of the present application, the first direction is defined as the Y-axis direction, and the second direction is defined as the Z-axis direction.

[0057] The semiconductor structure includes: a substrate 10; and an interlayer dielectric layer 11 and a gate trench 12 arranged alternately along the OY direction on the first surface 10a of the substrate 10;

[0058] The gate trench 12 includes, in sequence along the OZ direction, a dielectric stack, a target work function layer 30, a protective layer 40, a barrier layer 50 and a metal conductive layer 60; wherein the dielectric stack is located on the inner surface of the gate trench 12; the longitudinal section of the target work function layer 30 is in the shape of a concave character, and the top surface is lower than the plane where the opening of the gate trench 12 is located; the protective layer 40 is located on the upper surface of the target work function layer 30 and the inner wall of the dielectric stack, and the top surface is flush with the top surfaces of the barrier layer 50, the metal conductive layer 60 and the interlayer dielectric layer 11.

[0059] For example, the substrate 10 includes a first active area A and a second active area B arranged along the OY direction.

[0060] In the present embodiment, the first active area A is a P-type active area, and the second active area B is an N-type active area. Of course, other electrical or isolation structures can also be included in the active area, which is a known technology for metal gate processes, and the specific structure will not be described in detail.

[0061] Further, in some embodiments, the dielectric stack includes a first dielectric layer 21, a second dielectric layer 22; the first dielectric layer 21 is located on the bottom surface of the gate trench 12; the second dielectric layer 22 is located on the top surface of the first dielectric layer 21, and the inner wall of the gate trench 12;

[0062] For example, the inner wall of the first dielectric layer 21 is in contact with the outer wall of the target work function layer 30 and the outer wall of the protective layer 40.

[0063] For example, the second dielectric layer 22 in the first active region A is the same as or different from the second dielectric layer 22 of the second active region B.

[0064] The semiconductor structure in the above embodiments can be compared with the semiconductor structure in the related art. Figure 1a When compared with the semiconductor structure in the related art, it can be found that in the semiconductor structure provided in the present application, the protective layer completely covers the top surface of the target work function layer, so that the target work function layer is embedded in the metal gate. When the subsequent wet etching process is entered, even if the top surface of the gate covering layer has defects, and the etching solution penetrates to the surface of the protective layer along the defect channel, it cannot continue to erode downward due to the physical barrier and chemical inertness of the protective layer, thereby ensuring the structural integrity of the target work function layer inside the gate. Compared with the structure in which the target work function layer is partially exposed in the prior art, the penetration path of the etching solution is effectively blocked, the risk of missing the target work function layer is effectively reduced, and the reliability of the semiconductor structure is improved.

[0065] Please refer to Figures 3-9 On the other hand, the present application provides a preparation method of a semiconductor structure, which is used to prepare the semiconductor structure as shown in Figure 2 The method includes steps S102-S108.

[0066] Step S102: providing a substrate 10, the substrate 10 includes interlayer dielectric layers 11 and gate trenches 12 arranged alternately along the OY direction on the first surface 10a of the substrate 10.

[0067] Step S104: after forming the dielectric stack in the gate trench 12, an initial work function layer 301 with a preset excess thickness is formed to cover the dielectric stack; the thickness is used to represent the size along the OZ direction.

[0068] Step S106: using a target gas to remove part of the initial work function layer 301 in the gate trench, so that part of the side wall of the gate trench 12 is exposed, and a target work function layer 30 with a concave longitudinal section is obtained.

[0069] Step S108: forming a protective layer 40 covering at least the upper surface and the exposed inner wall of the target work function layer 30.

[0070] The semiconductor structure obtained after steps S102-S108 can be referred to Figure 9For the convenience of understanding the present application, Figures 4 to 9 is a schematic diagram of each step of an exemplary semiconductor structure preparation method provided by an embodiment of the present application, wherein, Figure 9 An example of the semiconductor structure prepared by the preparation method of the present application can have other suitable examples, which are not limited herein by the present application.

[0071] The semiconductor structure provided by the embodiments of the present application will be described in detail below. Figures 4 to 9 The semiconductor structure provided by the embodiments of the present application will be described in detail below.

[0072] Referring to Figure 4 , step S102 further comprises: forming an interlayer dielectric layer 11 on the top surface of the substrate 10 by a deposition process, and then performing a photolithography and etching process to form gate trenches 12 spaced along the OY direction in the interlayer dielectric layer 11.

[0073] Exemplarily, the substrate 10 includes a P-type first active region A and an N-type second active region B arranged along the OY direction.

[0074] Exemplarily, the substrate 10 includes a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer below a thin semiconductor layer as an active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor generally include a crystalline semiconductor material silicon, but can also include one or more other semiconductor materials, such as germanium, silicon-germanium alloy, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, etc.) or combinations thereof. Other device structures (not shown) such as isolation trench structures can be included in the substrate 10, and a person skilled in the art can select the substrate according to the type of transistor, and thus the type of substrate should not limit the protection scope of the present application. x As, Ga x Al 1-x N, In x Ga 1-x As, etc.) or combinations thereof. Other device structures (not shown) such as isolation trench structures can be included in the substrate 10, and a person skilled in the art can select the substrate according to the type of transistor, and thus the type of substrate should not limit the protection scope of the present application.

[0075] Exemplarily, the interlayer dielectric layer 11 is generally a dielectric material, including but not limited to silicon nitride (SiN), silicon oxide (SiO2), or silicon oxynitride (SiO x N y ) and the like.

[0076] Referring to Figure 5a and Figure 5b , step S104 further comprises:

[0077] Step S502: sequentially forming, by a deposition process, a first dielectric material layer 201 at the bottom of the gate trench 12, a second dielectric material layer 202, a third dielectric material layer 203 on the top surface of the first dielectric material layer 201, and a fourth dielectric material layer 204 covering the remaining inner wall of the gate trench 12 and the top surface of the third dielectric material layer 203. Then, a fifth dielectric material layer 205 is further formed in the gate trench 12 corresponding to the first active region A, to obtain a structure as shown in Figure 5a .

[0078] Specifically, as shown in Figure 5a , the first dielectric material layer 201, the second dielectric material layer 202 and the third dielectric material layer 203 collectively constitute the first dielectric layer 21; in the first active region A, the fourth dielectric material layer 204 and the fifth dielectric material layer 205 collectively constitute the second dielectric layer 22; while in the second active region B, the second dielectric layer 22 is solely constituted by the fourth dielectric material layer 204.

[0079] For example, the material of the first dielectric material layer 201 includes but is not limited to silicon oxide (SiO2), silicon oxynitride (SiON), hafnium-based oxide HfSiO, etc. x N y .

[0080] For example, the material of the second dielectric material layer 202 includes but is not limited to materials with high k dielectric constant, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), titanium oxide (TiO2) or silicon oxide (SiO2), etc.; the material of the barrier layer 50 includes but is not limited to silicon oxide (SiO2), doped oxide (such as phosphorus-silicon glass PSG, boron-phosphorus-silicon glass BPSG) or silicon nitride (SiN), etc., mainly used to increase the capacitance of the device and reduce power consumption, and the specific physical thickness can be determined according to the performance requirements of the device.

[0081] For example, the material of the third dielectric material layer 203, the fourth dielectric material layer 204 and the fifth dielectric material layer 205 includes but is not limited to metal nitride, such as titanium nitride (TiN) or tantalum nitride (TaN), etc.

[0082] Among them, the first dielectric material layer 201, the second dielectric material layer 202 and the third dielectric material layer 203 constitute the first dielectric layer 21, and the structure is as shown in Figure 5b .

[0083] In the above embodiment, TiN is used as the third dielectric material layer 203, and TaN is used as the fourth dielectric material layer 204, which together form a double diffusion barrier structure for preventing the diffusion of the work function layer material; TiN is used as the fifth dielectric material layer 205 to increase the work function of the P-type first active region A, adjust the threshold voltage, and improve the electrical characteristics of the device. The first dielectric layer 21 and the second dielectric layer 22 together form a dielectric stack.

[0084] Referring to Figure 6 , step S504: depositing an excess initial work function layer 301 in the gate trench 12 by a deposition method to obtain a structure as shown in Figure 6 .

[0085] For example, the preset excess is positively correlated with the target thickness, and the greater the target thickness to be removed, the greater the preset excess. In this embodiment, the preset excess is in the range of 1 nm-2 nm, for example, 1 nm, 1.5 nm, or 2 nm, etc.

[0086] In this embodiment, TiAl (titanium aluminum compound) is selected as the initial work function layer 301, which has a suitable work function value and can effectively adjust the threshold voltage of the device. Of course, the material selection of the initial work function layer is not limited to this, and other materials can also be selected as the initial work function layer. The key is that when the target gas is used for etching later, the etching rate of the initial work function layer material needs to be significantly higher than that of the fourth dielectric material layer 204 and the fifth dielectric material layer 205, so as to form a sufficient etching selection ratio, thereby effectively protecting the barrier layer structure below and on the side when removing part of the initial work function layer material, and avoiding adverse effects on the device performance. The matching design of such material selection and etching process provides a flexible process window for device manufacturing.

[0087] Referring to Figure 7 , step S106 further includes: using a target gas including hydrogen fluoride and ammonia to remove the initial work function layer 301 in the gate trench 12 by a target thickness to obtain a target work function layer 30 as shown in Figure 7 , and then annealing the substrate 10 to remove the by-products of the reaction and repair the interface defects.

[0088] The thickness is used to represent the size along the ZO direction (the opposite direction of OZ).

[0089] For example, under radio frequency (RF) power, the mixed gas of hydrogen fluoride (HF) and ammonia (NH3) dissociates and generates NH4F, which contains F -The etching rate of the group to the initial work function layer (such as TiAl) is significantly higher than that to the fourth dielectric material layer 204 (such as TaN) and the fifth dielectric material layer 205 (such as TiN), so that the part of the initial work function layer 301 with a height exceeding 40 nm on the side wall of the gate trench 12 can be selectively removed.

[0090] In the above embodiment, the annealing process for removing by-products can be completed in the same process chamber as the above process, thereby reducing the process cost. The excess initial work function layer in step S504 can ensure that the target work function layer still has a sufficient thickness at the bottom after etching to maintain the electrical performance.

[0091] Referring to Figure 8 , step S108 further includes: forming the protective layer 40 by using an atomic layer deposition (ALD) process.

[0092] For example, the material of the protective layer 40 includes but is not limited to metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN), or niobium nitride (NbN), etc. In this embodiment, TiN is used as the protective layer 40.

[0093] In the above embodiment, the protective layer prepared by the atomic layer deposition (ALD) process has excellent conformality and good step coverage, can completely wrap the surface and side wall of the target work function layer, and no surface is exposed on the gate surface, so that the etching solution cannot contact the target work function layer in the subsequent wet etching process, and the risk of corrosion of the bottom target work function layer is fundamentally avoided.

[0094] Meanwhile, the target work function layer with a concave-shaped longitudinal cross-section increases the opening size during the deposition of the metal conductive layer compared with the unetched structure, is more conducive to the filling of the subsequent gate metal, reduces the filling defects such as holes and gaps caused by high aspect ratio, and improves the quality of the metal gate.

[0095] Referring to Figure 9 , in some embodiments, after step S108, the method further includes:

[0096] forming a barrier layer 50 covering at least the inner surface of the protective layer 40, and a metal conductive layer 60 filling the remaining gap of the gate trench 12; and performing chemical mechanical polishing on the above structure to form a metal gate.

[0097] For example, the material of the barrier layer 50 is a composite layer of titanium nitride and titanium (TTN), which is mainly used to improve the capacitance value of the transistor and improve its driving current capability, and can also be used as a diffusion barrier layer to block the diffusion of the material forming the metal conductive layer 60 downward to the dielectric layer.

[0098] For example, the material of the metal conductive layer 60 includes, but is not limited to, at least one of aluminum (Al), copper (Cu), nickel (Ni), chromium (Cr), tungsten (W), titanium (Ti), tantalum (Ta), silver (Ag), gold (Au) and platinum (Pt). In this embodiment, the material of the metal conductive layer 60 is Al.

[0099] In some embodiments, the present application also provides a semiconductor device including the semiconductor structure as described in the above embodiments; or including the semiconductor structure prepared by the preparation method as mentioned in the above embodiments. Since the semiconductor device of the above embodiments and the semiconductor structure and the preparation method thereof provided by the present application are based on the same inventive concept, the semiconductor device using the semiconductor structure and the preparation method thereof has all the advantages of the semiconductor structure and the preparation method thereof provided by the present application, which will not be repeated here.

[0100] In the above embodiments, the unexpected technical effects of the present application are:

[0101] Figure 10 For the comparison between the semiconductor structure provided by the present application and the semiconductor structure provided by the related art, FIG. (a) is the semiconductor structure provided by the present application, Figure 10 FIG. (a) is the semiconductor structure provided by the present application, Figure 10 FIG. (b) is the semiconductor structure provided by the related art. By selecting TiAl or other suitable materials as the initial work function layer, the dielectric stack, and ensuring that the etching rate of the initial work function layer material is significantly higher than that of the fourth dielectric material layer and the fifth dielectric material layer, a sufficient etching selectivity ratio is formed, which effectively protects the side and lower barrier layer structure during the selective removal of part of the initial work function layer, avoiding performance degradation; the protection layer prepared by atomic layer deposition (ALD) can completely wrap the surface and sidewall of the target work function layer due to its excellent conformality and good step coverage, so that the target work function layer is embedded in the metal gate, which blocks the contact path between the etching solution and the target work function layer in the subsequent wet etching process, thereby avoiding the corrosion risk of the bottom target work function layer from the root, and ensuring the integrity of its structure and electrical performance.

[0102] In addition, the concave-shaped design of the longitudinal section of the target work function layer increases the opening size during the deposition of the metal conductive layer compared to the original structure without etching, effectively reduces the high aspect ratio limitation in the filling process, reduces defects such as voids and gaps, improves the filling quality and conductive continuity of the metal gate, and realizes the dual improvement of device reliability and preparation stability.

[0103] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features of the above embodiments are described, however, as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present application.

[0104] The above-described embodiments are merely illustrative of several embodiments of the present application, which are described in more detail and in a specific manner, but should not be construed as limiting the scope of the patent application. It should be noted that for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; And interlayer dielectric layers and gate trenches are alternately arranged on the first surface of the substrate along a first direction parallel to the first surface; The gate trench includes a dielectric stack, a target work function layer, a protective layer, a barrier layer, and a metal conductive layer arranged sequentially along a second direction away from the substrate; wherein, the dielectric stack is located on the inner surface of the gate trench; the longitudinal section of the target work function layer is U-shaped, and its top surface is lower than the plane where the gate trench opening is located; the protective layer is located on the upper surface of the target work function layer and the inner wall of the dielectric stack, and its top surface is flush with the top surfaces of the barrier layer, the metal conductive layer, and the interlayer dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that, The dielectric stack includes: a first dielectric layer and a second dielectric layer; The first dielectric layer is located on the bottom surface of the gate trench; The second dielectric layer is located on the top surface of the first dielectric layer and on the inner wall of the gate trench.

3. The semiconductor structure according to claim 2, characterized in that, The inner wall of the second dielectric layer is in contact with the outer wall of the target work function layer and the outer wall of the protective layer.

4. The semiconductor structure according to claim 2, characterized in that, The substrate includes a first active region and a second active region arranged along the first direction; The second dielectric layer in the first active region may be the same as or different from the second dielectric layer in the second active region.

5. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, wherein a first surface of the substrate includes an interlayer dielectric layer and gate trenches arranged alternately along a first direction parallel to the first surface; After forming a dielectric stack in the gate trench, an initial work function layer with a predetermined excess thickness is formed to cover the dielectric stack; the thickness is used to characterize the dimension along a second direction away from the substrate; The initial work function layer of the gate trench is partially removed by using a target gas, exposing the inner wall of the gate trench and obtaining a target work function layer with a concave cross-section. A protective layer is formed that at least covers the upper surface of the target work function layer and the exposed inner wall.

6. The preparation method according to claim 5, characterized in that, Removing a portion of the initial work function layer using a target gas includes: The initial work function layer of the target thickness in the gate trench is removed using a target gas including hydrogen fluoride and ammonia.

7. The preparation method according to claim 6, characterized in that, The preset excess positive correlation is related to the target thickness.

8. The preparation method according to claim 5, characterized in that, The dielectric stack includes: a first dielectric layer and a second dielectric layer; The first dielectric layer is located on the bottom surface of the gate trench; The second dielectric layer is located on the top surface of the first dielectric layer and on the inner wall of the gate trench; The substrate includes a first active region and a second active region arranged along the first direction; The second dielectric layer in the first active region may be the same as or different from the second dielectric layer in the second active region.

9. The preparation method according to any one of claims 5-8, characterized in that, Also includes: A barrier layer is formed that at least covers the inner surface of the protective layer, and a metallic conductive layer is formed that fills the remaining gaps in the gate trench; The semiconductor structure is subjected to chemical mechanical polishing to form a metal gate.

10. A semiconductor device, characterized in that, include: The semiconductor structure as described in any one of claims 1-4; or The semiconductor structure prepared by the preparation method according to any one of claims 5-9.

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