Manufacturing method of semiconductor device, semiconductor device and electronic equipment

Abstract

The invention provides a manufacturing method of a semiconductor device, the semiconductor device and electronic equipment. The manufacturing method comprises the following steps: removing the part of the side wall structure away from the replacement gate to form a second isolation layer, wherein the part of the interlayer dielectric structure away from the replacement gate extends out of the second isolation layer. And forming a second semiconductor layer by taking the interlayer dielectric structure as a mask, wherein the second semiconductor layer is positioned on the inner side of the interlayer dielectric structure. And removing the interlayer dielectric structure, and forming a third isolation layer on the peripheral side surface of the second semiconductor layer and the surface, back to the second isolation layer, of the second semiconductor layer. Therefore, the second semiconductor layer is formed by taking the interlayer dielectric structure as the mask plate, and the interlayer dielectric structure limits the formation position of the second semiconductor layer, so that the position of the formed second semiconductor layer is not deviated, and the yield of the semiconductor device is further improved. Moreover, the formation position of the second semiconductor layer is not limited by an additional mask, so that the self-alignment of the second semiconductor layer is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and particularly relates to a manufacturing method of a semiconductor device, a semiconductor device and an electronic device. BACKGROUND

[0002] Semiconductor devices are applied to smart phones, tablets, computers, automobiles, household appliances and many other types of electronic devices, and the semiconductor devices provide the above-mentioned electronic devices with computing and storage capabilities. The semiconductor devices include a large number of transistors and other electronic elements, and the more intensive electronic elements make the semiconductor devices have better performance, lower energy consumption and higher reliability.

[0003] A vertical transport field-effect transistor (VTFET) or a vertical field-effect transistor (VFET) refers to a transistor with a channel perpendicular to a substrate. When the transistor size is scaled down, the channel can utilize the vertical space, thereby reducing the contacted gate pitch (CGP) and the area occupied by a unit transistor, and further improving the distribution density of the transistors in the semiconductor device. In the manufacturing process of the VTFET or the VFET, a mask plate (photolithography plate) is used to define the relative positions of the source, the gate and the drain. According to the current manufacturing process, it is difficult to make the position of the mask plate completely accurate, which leads to a deviation (misalignment) of the positions of the formed source or drain, and thus reduces the performance and yield of the VTFET or the VFET.

[0004] Therefore, how to align the positions of the source or the drain to improve the yield of the VTFET or the VFET is a problem to be solved by those skilled in the art. SUMMARY

[0005] The present application provides a manufacturing method of a semiconductor device, a semiconductor device and an electronic device, and aims to solve the problem that the misalignment of the positions of the source or the drain leads to a low yield of the transistor in the prior art.

[0006] In a first aspect, embodiments of the present application provide a method for manufacturing a semiconductor device, the method comprising: providing a first substrate structure, forming the first substrate structure into a substrate, a channel and a semiconductor structure, the channel and the semiconductor structure being located on a surface of the substrate, and the semiconductor structure connecting a side surface of the channel; sequentially forming an isolation structure, a replacement gate, a sidewall structure and an interlayer dielectric structure on the semiconductor structure, the isolation structure being located on a surface of the semiconductor structure facing away from the substrate, the replacement gate being located on a surface of the isolation structure facing away from the semiconductor structure, the sidewall structure and the interlayer dielectric structure being located on a surface of the replacement gate facing away from the isolation structure, the isolation structure, the replacement gate and the sidewall structure surrounding a peripheral surface of the channel, and the interlayer dielectric structure surrounding a peripheral surface of the sidewall structure; removing a portion of the sidewall structure facing away from the replacement gate to form a second isolation layer, a portion of the interlayer dielectric structure facing away from the replacement gate extending out of the second isolation layer, and an end of the channel facing away from the substrate extending out of the second isolation layer; forming a second semiconductor layer on the second isolation layer using the interlayer dielectric structure as a mask, the second semiconductor layer covering the end of the channel extending out of the second isolation layer, and the second semiconductor layer being located inside the interlayer dielectric structure; removing the interlayer dielectric structure to expose a peripheral surface of the second semiconductor layer, forming a third isolation layer on the peripheral surface of the second semiconductor layer and a surface of the second semiconductor layer facing away from the second isolation layer; removing the replacement gate to expose a peripheral surface of the channel, forming a gate layer on the peripheral surface of the channel, and removing a portion of the isolation structure away from the gate layer to form a first isolation layer, the gate layer being connected to the second isolation layer and the first isolation layer respectively, and the first isolation layer surrounding the peripheral surface of the channel; and removing a portion of the semiconductor structure away from the gate layer to form a first semiconductor layer, the first semiconductor layer surrounding the peripheral surface of the channel.

[0007] In summary, the method for manufacturing a semiconductor device provided by embodiments of the present application forms a second semiconductor layer around an end of the channel facing away from the substrate using the interlayer dielectric structure as a mask, the interlayer dielectric structure limiting the position where the second semiconductor layer is formed, i.e. the second semiconductor layer can only be formed inside the interlayer dielectric structure, so that the position of the second semiconductor layer formed will not deviate, thereby improving the yield of the semiconductor device. Moreover, the second semiconductor layer is formed inside the interlayer dielectric structure without using another mask to limit the position where the second semiconductor layer is formed, achieving self-alignment of the second semiconductor layer.

[0008] In one embodiment, the forming the second semiconductor layer on the second isolation layer with the interlayer dielectric structure as a mask includes: forming a first sub-semiconductor on a surface of the channel opposite to the substrate with the interlayer dielectric structure as the mask; forming a crystal layer on a surface of the second isolation layer opposite to the replacement gate with the interlayer dielectric structure as the mask, the crystal layer connecting the peripheral surface of the channel and covering the first sub-semiconductor; and implanting ions into the crystal layer to form a second sub-semiconductor, the second sub-semiconductor connecting the peripheral surface of the channel and covering the first sub-semiconductor, the first sub-semiconductor and the second sub-semiconductor constituting the second semiconductor layer. The first sub-semiconductor directly contacts the channel, thereby reducing the contact resistance between the second semiconductor layer and the channel. In addition, the uniformity of the single crystal silicon is better, thereby making the current transmission more stable.

[0009] In one embodiment, the material of the first sub-semiconductor includes single crystal silicon, and the material of the second sub-semiconductor includes amorphous silicon or polycrystalline silicon. The conductivity of the single crystal silicon is better than that of the amorphous silicon and the polycrystalline silicon, and the first sub-semiconductor directly contacts the channel, thereby reducing the contact resistance between the second semiconductor layer and the channel. In addition, the uniformity of the single crystal silicon is better, thereby making the current transmission more stable.

[0010] In one embodiment, the removing the interlayer dielectric structure exposes the peripheral surface of the second semiconductor layer, and the forming the third isolation layer on the peripheral surface of the second semiconductor layer and a surface of the second semiconductor layer opposite to the second isolation layer includes: forming a second isolation portion on the surface of the second semiconductor layer opposite to the second isolation layer with the interlayer dielectric structure as the mask. The removing the interlayer dielectric structure exposes the peripheral surface of the second semiconductor layer. A first isolation portion is formed on the peripheral surface of the second semiconductor layer, the first isolation portion surrounding the peripheral surface of the second isolation portion and the peripheral surface of the second semiconductor layer, and the first isolation portion and the second isolation portion constitute the third isolation layer. The forming the second isolation portion with the interlayer dielectric structure as the mask limits the position where the second isolation portion is formed, i.e., the second isolation portion can only be formed on the inner side of the interlayer dielectric structure, thereby improving the alignment accuracy between the second isolation portion and the second semiconductor layer. In addition, no mask is additionally used to limit the position where the second isolation portion is formed, thereby realizing self-alignment of the second isolation portion.

[0011] In one embodiment, the removing the replacement gate exposes the peripheral side surface of the channel, and forming a gate layer on the peripheral side surface of the channel includes: removing the replacement gate, and the peripheral side surface of the channel is exposed. A dielectric structure is formed on the peripheral side surface of the channel, and the dielectric structure connects the peripheral side surface of the third isolation layer. A metal gate structure is formed on the surface of the dielectric structure facing away from the channel, and the metal gate structure connects the surface of the dielectric structure facing away from the third isolation layer, and the dielectric structure and the metal gate structure constitute a gate layer structure. The part of the gate layer structure that is misaligned with the third isolation layer is removed to form the gate layer, and the gate layer is connected to the peripheral side surface of the channel, the first isolation layer, and the second isolation layer, respectively. Therefore, by first forming the replacement gate to occupy the position of the gate layer, and then removing the replacement gate and forming the gate layer, the yield of the gate layer is avoided from being affected by the high-temperature environment for forming the second semiconductor layer.

[0012] In one embodiment, the second isolation layer, the channel, and the isolation structure form a ring-shaped first accommodation cavity, the first accommodation cavity has a ring-shaped opening, and the peripheral side surface of the channel exposes the opening of the first accommodation cavity. The first accommodation cavity allows the material of the dielectric structure to be better deposited between the second isolation layer and the isolation structure, avoids the dielectric structure between the second isolation layer and the isolation structure from having a cavity void, and is beneficial to improve the quality of the dielectric structure.

[0013] In one embodiment, the dielectric structure forms a ring-shaped second accommodation cavity between the second isolation layer and the isolation structure, the second accommodation cavity has a ring-shaped opening, and the side surface of the dielectric structure facing away from the channel exposes the opening of the second accommodation cavity. The second accommodation cavity allows the material of the metal gate structure to be better deposited into the second accommodation cavity surrounded by the dielectric structure, avoids the metal gate structure in the second accommodation cavity from having a cavity void, and is beneficial to improve the quality of the metal gate structure.

[0014] In one embodiment, the removing the portion of the gate layer structure and the third isolation layer to form the gate layer includes removing the portion of the metal gate structure away from the isolation structure to form a metal gate transition structure. A mask body is formed on the surface of the third isolation layer facing away from the isolation structure. The removing the portion of the dielectric structure and the third isolation layer to form a dielectric layer and the removing the portion of the metal gate transition structure and the third isolation layer to form a metal gate layer, the dielectric layer and the metal gate layer constitute the gate layer. In order to avoid removing the third isolation layer in the process of forming the gate layer from the gate layer structure, the portion of the metal gate structure away from the isolation structure is removed first, the position of the portion to be removed is reserved, and the third isolation layer is provided with a layer of dielectric structure for protection. In the process of forming the gate layer from the gate layer structure, the position of the portion to be removed can make the gate layer faster, and the dielectric structure can protect the third isolation layer from being removed.

[0015] In one embodiment, in the process of forming the isolation structure into the first isolation layer, the semiconductor structure of a first predetermined thickness is removed. The portion of the isolation structure and the gate layer is completely removed.

[0016] In one embodiment, in the process of forming the semiconductor structure into the first semiconductor layer, the substrate of a second predetermined thickness is removed. The portion of the semiconductor structure and the first isolation layer is completely removed.

[0017] In one embodiment, the sidewall structure is formed into the second isolation layer by an isotropic etching process. The thickness and morphology of the second isolation layer formed by the isotropic etching process can be effectively controlled.

[0018] In one embodiment, after the first semiconductor layer is formed, the method for manufacturing the semiconductor device further includes forming a second interlayer dielectric layer on the side surface of the first semiconductor layer, the side surface of the first isolation layer, the side surface of the gate layer, the side surface of the third isolation layer, and the surface of the third isolation layer facing away from the gate layer. The second interlayer dielectric layer insulates the side surface of the first semiconductor layer, the side surface of the gate layer, the side surface of the third isolation layer, and the surface of the third isolation layer facing away from the gate layer.

[0019] In one implementation, the method for manufacturing the semiconductor device further includes: forming a first accommodating hole, a second accommodating hole, and a third accommodating hole in the second interlayer dielectric layer, and forming a via hole through the third isolation layer in the third isolation layer, the first accommodating hole extending to the first semiconductor layer, the second accommodating hole extending to the via hole, the second semiconductor layer being exposed from the via hole, and the third accommodating hole extending to the gate layer. A first electrode is formed in the first accommodating hole, a second electrode is formed in the second accommodating hole and the via hole, and a third electrode is formed in the third accommodating hole. The first semiconductor layer is electrically connected to an external circuit through the first electrode, the second semiconductor layer is electrically connected to an external circuit through the second electrode, and the gate layer is electrically connected to an external circuit through the third electrode.

[0020] In a second aspect, the embodiments of the present application further provide a semiconductor device manufactured by the method for manufacturing the semiconductor device. The semiconductor device includes a substrate, a channel, a first semiconductor layer, a first isolation layer, a gate layer, a second isolation layer, a third isolation layer, and a second semiconductor layer. The channel is arranged on a surface of the substrate, and the first semiconductor layer, the first isolation layer, the gate layer, the second isolation layer, and the second semiconductor layer are sequentially arranged along a height direction of the channel. The first semiconductor layer, the first isolation layer, the gate layer, the second isolation layer, and the second semiconductor layer are connected to a side surface of the channel, the second semiconductor layer is further connected to a surface of the channel opposite to the surface of the substrate, and the third isolation layer covers the second semiconductor layer.

[0021] In summary, the semiconductor device is manufactured by the method for manufacturing the semiconductor device. The method for manufacturing the semiconductor device forms the second semiconductor layer by using the interlayer dielectric structure as a mask, and the interlayer dielectric structure limits the position of the second semiconductor layer, i.e., the second semiconductor layer can only be formed on the inner side of the interlayer dielectric structure, so that the position of the second semiconductor layer is not deviated, thereby improving the yield of the semiconductor device. Moreover, the second semiconductor layer is formed on the inner side of the interlayer dielectric structure, and no mask is used to limit the position of the second semiconductor layer, thereby realizing self-alignment of the second semiconductor layer.

[0022] In a third aspect, the embodiments of the present application further provide an electronic device, which comprises a circuit board and the semiconductor device described above, and the semiconductor device is manufactured by the manufacturing method of the semiconductor device described above. The semiconductor device comprises a substrate, a channel, a first semiconductor layer, a first isolation layer, a gate layer, a second isolation layer, a third isolation layer and a second semiconductor layer. The channel is arranged on a surface of the substrate, and the first semiconductor layer, the first isolation layer, the gate layer, the second isolation layer and the second semiconductor layer are sequentially arranged in a height direction of the channel. The first semiconductor layer, the first isolation layer, the gate layer, the second isolation layer and the second semiconductor layer are connected to a side surface of the channel, the second semiconductor layer is further connected to a surface of the channel which is opposite to the surface of the substrate, and the third isolation layer covers the second semiconductor layer. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background art, the drawings needed to be used in the embodiments of the present application or the background art will be described below.

[0024] FIG. 1 A top view structural schematic diagram of the semiconductor device disclosed by the embodiments of the present application;

[0025] FIG. 2 A sectional view structural schematic diagram of the semiconductor device shown in FIG. 1 along the direction II-II; FIG. 1

[0026] A sectional view structural schematic diagram of the semiconductor device shown in FIG. 1 along the direction III-III; FIG. 3 FIG. 1 An enlarged schematic diagram of structure IV in the semiconductor device shown in FIG. 1;

[0027] FIG. 4 FIG. 2 An enlarged schematic diagram of structure V in the semiconductor device shown in FIG. 1;

[0028] FIG. 5 A flowchart of the manufacturing method of the semiconductor device disclosed by the embodiments of the present application; FIG. 3

[0029] A flowchart of step S100 of the manufacturing method of the semiconductor device disclosed by the embodiments of the present application; FIG. 6

[0030] A sectional view structural schematic diagram of the structure corresponding to step S110 along the first direction; FIG. 7

[0031] A sectional view structural schematic diagram of the structure corresponding to step S120 along the first direction; FIG. 8 FIG. 7 A sectional view structural schematic diagram of the structure corresponding to step S130 along the first direction;

[0032] FIG. 9 ​​​For FIG. 7 The step S120 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction;

[0033] FIG. 10 For FIG. 7 The step S130 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction;

[0034] FIG. 11 For FIG. 7 The step S140 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction;

[0035] FIG. 12 For FIG. 7 The step S140 shown in the figure corresponds to the cross-sectional view of the structure formed along the second direction;

[0036] FIG. 13 The flow chart of the step S200 of the method for manufacturing the semiconductor device disclosed in the embodiment of the present application;

[0037] FIG. 14 For FIG. 13 The step S210 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction;

[0038] FIG. 15 For FIG. 13 The step S210 shown in the figure corresponds to the cross-sectional view of the structure formed along the second direction;

[0039] FIG. 16 For FIG. 13 The step S220 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction;

[0040] FIG. 17 For FIG. 13 The step S220 shown in the figure corresponds to the cross-sectional view of the structure formed along the second direction;

[0041] FIG. 18 For FIG. 13 The step S230 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction;

[0042] FIG. 19 For FIG. 13 The step S240 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction;

[0043] FIG. 20 The flow chart of the step S300 of the method for manufacturing the semiconductor device disclosed in the embodiment of the present application;

[0044] FIG. 21 For FIG. 19 The step S310 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction;

[0045] FIG. 22 For FIG. 19 The step S320 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction;

[0046] FIG. 23 For the flowchart of step S400 of the method for manufacturing the semiconductor device disclosed in the embodiment of the present application;

[0047] FIG. 24 For FIG. 23 The step S410 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction;

[0048] FIG. 25 For FIG. 23 The step S420 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction;

[0049] FIG. 26 For FIG. 23 The step S430 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction;

[0050] FIG. 27 For the flowchart of step S500 of the method for manufacturing the semiconductor device disclosed in the embodiment of the present application;

[0051] FIG. 28 For FIG. 27 The step S510 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction;

[0052] FIG. 29 For FIG. 27 The step S520 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction;

[0053] FIG. 30 For FIG. 27 The step S530 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction;

[0054] FIG. 31 For the flowchart of step S600 of the method for manufacturing the semiconductor device disclosed in the embodiment of the present application;

[0055] FIG. 32 For FIG. 31 The step S610 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction;

[0056] FIG. 33 For FIG. 31 The step S620 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction;

[0057] FIG. 34 For FIG. 31The step S630 shown corresponds to a schematic view of a cross section of the structure formed along the first direction;

[0058] FIG. 35 The step S640 of the method for manufacturing the semiconductor device disclosed in the embodiments of the present application is shown in a schematic flow chart;

[0059] FIG. 36 For FIG. 35 The step S641 shown corresponds to a schematic view of a cross section of the structure formed along the first direction;

[0060] FIG. 37 For FIG. 35 The step S642 shown corresponds to a schematic view of a cross section of the structure formed along the first direction;

[0061] FIG. 38 For FIG. 35 The step S643 shown corresponds to a schematic view of a cross section of the structure formed along the first direction;

[0062] FIG. 39 For FIG. 6 The step S700 shown corresponds to a schematic view of a cross section of the structure formed along the first direction;

[0063] FIG. 40 For FIG. 6 The step S800 shown corresponds to a schematic view of a cross section of the structure formed along the first direction;

[0064] FIG. 41 For FIG. 6 The step S900 shown corresponds to a schematic view of a cross section of the structure formed along the first direction;

[0065] FIG. 42 For FIG. 6 The step S900 shown corresponds to a schematic view of a cross section of the structure formed along the second direction. DETAILED DESCRIPTION

[0066] The electronic device can be a mobile phone, a tablet computer, a television, an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a smart wearable device (for example, a smart watch, a smart bracelet), a vehicle-mounted device, a smart home device, a smart city device, a terminal device, or the like. The embodiments of the present application do not specially limit the specific type of the electronic device. For the convenience of description, the following will be described by taking a mobile phone as an example.

[0067] The mobile phone can include a circuit board, a display screen, a battery, a camera, and the like. The circuit board can be integrated with a processor, an internal memory, a charging circuit, and the like. Of course, the mobile phone can also include other constituent devices, and the circuit board can also be integrated with other circuit structures, which are not limited by the embodiments of the present application.

[0068] The processor can include one or more processing units, for example: the processor can include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Different processing units can be independent devices or can be integrated into one or more processors.

[0069] The GPU is a microprocessor for image processing, connected to the display screen and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Thus, the mobile phone realizes the display function through the GPU, the display screen, and the application processor, etc.

[0070] The charging circuit of the mobile phone includes a power management circuit and a charging management circuit. The power management circuit is connected to the battery, the charging management circuit, and the processor. The charging management circuit can receive charging input from the charger to charge the battery. The charging management circuit can also supply power to the mobile phone through the power management circuit while charging the battery. The power management circuit receives input from the battery and / or the charging management module to supply power to the processor, the internal memory, the display screen, the camera, and the like.

[0071] The mobile phone can also realize the shooting function through the camera, the GPU, the display screen, and the application processor, etc.

[0072] The internal memory in the mobile phone can be used to store computer executable program codes, and the executable program codes include instructions. The processor executes various functional applications and data processing of the mobile phone by running the instructions stored in the internal memory.

[0073] The electronic device described above can include semiconductor devices and circuit boards, and the like. The semiconductor devices are electrically connected to the circuit board through pins, and the semiconductor devices can be electrically connected to external circuits through the circuit board to realize signal intercommunication.

[0074] Based on this, the embodiment of the present application provides a semiconductor device which can be applied to the electronic device described above. The semiconductor device can be a core logic chip, a static random access memory (SRAM), a memory selector, a microprocessor, or the like. The embodiment of the present application does not specially limit the specific type of the semiconductor device.

[0075] The semiconductor device described above can include a transistor and a packaging element, the transistor being packaged inside the packaging element, and the number of transistors in the semiconductor device can be one or more, and the embodiment of the present application does not specially limit the number of transistors in the semiconductor device. The vertical transistor disclosed in the embodiment of the present application will be further described in detail below with reference to the accompanying drawings.

[0076] Please refer to FIGS. 1-3 , FIG. 1 for the schematic top view of the semiconductor device disclosed in the embodiment of the present application, FIG. 2 for FIG. 1 the schematic cross-sectional view of the semiconductor device shown in FIG. 2 along the II-II direction, FIG. 3 for FIG. 1 the schematic cross-sectional view of the semiconductor device shown in FIG. 3 along the III-III direction.

[0077] The vertical transistor 1 includes a substrate 10, a channel 20, a first semiconductor layer 30, a first isolation layer 50, a gate layer 60, a second isolation layer 70, a third isolation layer 71, and a second semiconductor layer 80. The channel 20 is arranged on the surface of the substrate 10. The first semiconductor layer 30, the first isolation layer 50, the gate layer 60, the second isolation layer 70, and the second semiconductor layer 80 are sequentially stacked along the height direction of the channel 20, and the first semiconductor layer 30, the first isolation layer 50, the gate layer 60, the second isolation layer 70, and the second semiconductor layer 80 are all connected to the outer side surface of the channel 20, and the second semiconductor layer 80 is also connected to the surface of the channel 20 opposite to the substrate 10. The third isolation layer 71 covers the second semiconductor layer 80. The first isolation layer 50 is used to insulate the gate layer 60 from the first semiconductor layer 30, the second isolation layer 70 is used to insulate the second semiconductor layer 80 from the gate layer 60, the third isolation layer 71 is used to insulate the surface of the second semiconductor layer 80, and the gate layer 60 is used to control the current size between the first semiconductor layer 30 and the second semiconductor layer 80.

[0078] It should be noted that the first semiconductor layer 30 can be a source, and the second semiconductor layer 80 can be a drain; or the first semiconductor layer 30 can be a drain, and the second semiconductor layer 80 can be a source. The embodiment of the present application does not limit the specific type of the first semiconductor layer 30 and the second semiconductor layer 80. The vertical transistor 1 has two types of P-type transistors and N-type transistors. In the embodiment of the present application,FIG. 2 The two vertical transistors 1 on the left side of the middle are P-type transistors, FIG. 2 The two vertical transistors 1 on the right side of the middle are N-type transistors, FIG. 3 The vertical transistor 1 on the left side of the middle is a P-type transistor, FIG. 3 The vertical transistor 1 on the right side of the middle is an N-type transistor. Accordingly, the substrate 10 and the channel 20 of the P-type transistor are N-type semiconductors, and the first semiconductor layer 30 and the second semiconductor layer 80 of the P-type transistor are P-type semiconductors. The substrate 10 and the channel 20 of the N-type transistor are P-type semiconductors, and the first semiconductor layer 30 and the second semiconductor layer 80 of the N-type transistor are N-type semiconductors. For example, FIG. 2 With FIG. 3 In the middle, the first substrate 10a is an N-type semiconductor, and the second substrate 10b is a P-type semiconductor.

[0079] For the convenience of description, it is defined that FIG. 1 The width direction of the vertical transistor 1 shown is the X-axis direction, the length direction of the vertical transistor 1 is the Y-axis direction, and the height direction of the vertical transistor 1 is the Z-axis direction. The X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other. The "up", "down", and other orientation words mentioned in the embodiments of the present application are described according to the orientation shown in the drawings, that is, the positive direction of the Z-axis is "up" and "top", and the negative direction of the Z-axis is "down" and "bottom", which does not form a limitation on the vertical transistor 1 in the actual application scenario. FIG. 1 The "up", "down", and other orientation words mentioned in the embodiments of the present application are described according to the orientation shown in the drawings, that is, the positive direction of the Z-axis is "up" and "top", and the negative direction of the Z-axis is "down" and "bottom", which does not form a limitation on the vertical transistor 1 in the actual application scenario.

[0080] Please refer to FIGS. 2-5 , FIG. 4 For FIG. 2 The enlarged schematic view of structure IV in the semiconductor device shown, FIG. 5 For FIG. 3 The enlarged schematic view of structure V in the semiconductor device shown. In the present application, the layer structure of the P-type vertical transistor 1 is the same as that of the N-type vertical transistor 1, and the difference between the P-type vertical transistor 1 and the N-type vertical transistor 1 lies in the shape of the second semiconductor layer 80. The layer structure of the P-type vertical transistor 1 and the layer structure of the N-type vertical transistor 1 are the same in naming and labeling, and the difference in the shape of the second semiconductor layer 80 will be described in subsequent embodiments. The following embodiments take one vertical transistor 1 as an example.

[0081] The substrate 10 includes a protrusion 11 and a base 12, the protrusion 11 is disposed on the surface of the base 12 facing the Z-axis direction. The protrusion 11 includes a first side surface 11a, a second side surface 11b, a third side surface 11c and a fourth side surface 11d, the first side surface 11a, the second side surface 11b, the third side surface 11c and the fourth side surface 11d constitute the peripheral side surface of the protrusion 11. The first side surface 11a and the second side surface 11b are disposed opposite along the X-axis direction, the third side surface 11c and the fourth side surface 11d are disposed opposite along the Y-axis direction, the third side surface 11c is connected with the first side surface 11a and the second side surface 11b respectively, and the fourth side surface 11d is connected with the first side surface 11a and the second side surface 11b respectively. The fourth side surface 11d is an inclined surface, in the Z-axis direction, the fourth side surface 11d is inclined to the direction where the third side surface 11c is located. The protrusion 11 is used to provide a surface for forming other layer structures of the vertical transistor 1.

[0082] In some embodiments, the first side surface 11a, the second side surface 11b, the third side surface 11c and the fourth side surface 11d are all connected with the base 12.

[0083] The base 12 includes a fifth side surface 12a and a sixth side surface 12b, the fifth side surface 12a and the sixth side surface 12b are disposed opposite along the Y-axis direction. The sixth side surface 12b is an inclined surface, in the Z-axis direction, the sixth side surface 12b is inclined to the direction where the fifth side surface 12a is located. The fifth side surface 12a is aligned with the third side surface 11c, and the sixth side surface 12b is aligned with the fourth side surface 11d.

[0084] The channel 20 is disposed on the surface of the protrusion 11 opposite to the base 12, and the channel 20 extends to the Z-axis direction. The channel 20 includes a first connecting surface 20a, a second connecting surface 20b, a third connecting surface 20c and a fourth connecting surface 20d, the first connecting surface 20a, the second connecting surface 20b, the third connecting surface 20c and the fourth connecting surface 20d constitute the outer side surface of the channel 20. The first connecting surface 20a and the second connecting surface 20b are disposed opposite along the X-axis direction, the third connecting surface 20c and the fourth connecting surface 20d are disposed opposite along the Y-axis direction, the third connecting surface 20c is connected with the first connecting surface 20a and the second connecting surface 20b respectively, and the fourth connecting surface 20d is connected with the first connecting surface 20a and the second connecting surface 20b respectively. The fourth connecting surface 20d includes a first sub-connecting surface 20d1 and a second sub-connecting surface 20d2 connected with each other, the first sub-connecting surface 20d1 and the second sub-connecting surface 20d2 are sequentially disposed along the Z-axis direction, that is, in the Z-axis direction, the height of the second sub-connecting surface 20d2 is higher than that of the first sub-connecting surface 20d1. The first sub-connecting surface 20d1 is an inclined surface, in the Z-axis direction, the first sub-connecting surface 20d1 is inclined to the direction where the third connecting surface 20c is located.

[0085] In one embodiment, the first connection surface 20a, the second connection surface 20b, the third connection surface 20c and the fourth connection surface 20d are all connected with the protrusion 11. In the X-axis direction, the height of the second side surface 11b is higher than the height of the second connection surface 20b, the height of the second connection surface 20b is higher than the height of the first connection surface 20a, and the height of the first connection surface 20a is higher than the height of the first side surface 11a. That is, the orthographic projection of the first connection surface 20a and the second connection surface 20b in the Z-axis direction is between the orthographic projection of the first side surface 11a and the second side surface 11b in the Z-axis direction. In the Y-axis direction, the height of the fourth connection surface 20d is higher than the height of the third connection surface 20c, and the height of the third connection surface 20c is higher than the height of the third side surface 11c. The first sub-connection surface 20d1 is aligned with the fourth side surface 11d.

[0086] The first semiconductor layer 30 is disposed on the surface of the protrusion 11 in the Z-axis direction, that is, the first semiconductor layer 30 is disposed on the surface of the protrusion 11 facing away from the substrate 12. The first semiconductor layer 30 is connected with the first connection surface 20a, the second connection surface 20b and the third connection surface 20c of the channel 20, and the fourth connection surface 20d is exposed to the first semiconductor layer 30. The first semiconductor layer 30 includes a first surface 30a, a second surface 30b, a third surface 30c, a fourth surface 30d and a fifth surface 30e. The first surface 30a and the second surface 30b are disposed opposite to each other along the X-axis direction, the third surface 30c and the fourth surface 30d are disposed opposite to each other along the Y-axis direction, and the third surface 30c and the fifth surface 30e are disposed opposite to each other along the Y-axis direction, that is, the fourth surface 30d and the fifth surface 30e are in the same direction. The third surface 30c is connected with the first surface 30a and the second surface 30b respectively, the fourth surface 30d is connected with the first surface 30a, and the fifth surface 30e is connected with the second surface 30b. The fourth surface 30d and the fifth surface 30e are inclined surfaces, and in the Z-axis direction, the fourth surface 30d and the fifth surface 30e are both inclined to the direction in which the third surface 30c is directed.

[0087] In one embodiment, the first surface 30a, the second surface 30b, the third surface 30c, the fourth surface 30d and the fifth surface 30e are all connected with the protrusion 11. The first surface 30a is aligned with the first side surface 11a, the second surface 30b is aligned with the second side surface 11b, the third surface 30c is aligned with the third side surface 11c, and the fourth surface 30d and the fifth surface 30e are both aligned with the first sub-connection surface 20d1. The first sub-connection surface 20d1 exposes the fourth surface 30d and the fifth surface 30e, that is, the first sub-connection surface 20d1 is not connected with the first semiconductor layer 30.

[0088] The first isolation layer 50 is disposed on the surface of the first semiconductor layer 30 along the Z-axis direction, i.e., the first isolation layer 50 is disposed on the surface of the first semiconductor layer 30 facing away from the protrusion 11. The first isolation layer 50 is connected to the first connecting surface 20a, the second connecting surface 20b, the third connecting surface 20c, and the second sub-connecting surface 20d2 of the fourth connecting surface 20d of the channel 20. The first isolation layer 50 includes a first contact surface 50a, a second contact surface 50b, and a third contact surface 50c, which are the peripheral surfaces of the first isolation layer 50. The first contact surface 50a and the second contact surface 50b are disposed opposite to each other along the X-axis direction, and the third contact surface 50c is connected between the first contact surface 50a and the second contact surface 50b.

[0089] In one embodiment, the first contact surface 50a, the second contact surface 50b, and the third contact surface 50c are all connected to the first semiconductor layer 30. The first contact surface 50a is aligned with the first surface 30a, and the second contact surface 50b is aligned with the second surface 30b. In the Y-axis direction, the height of the third connecting surface 20c is greater than the height of the third contact surface 50c, and the height of the third contact surface 50c is greater than the height of the third surface 30c, i.e., the orthogonal projection of the third contact surface 50c in the Z-axis direction is located between the orthogonal projection of the third connecting surface 20c in the Z-axis direction and the orthogonal projection of the third surface 30c in the Z-axis direction.

[0090] The gate layer 60 is arranged on the surface of the first isolation layer 50 along the Z-axis direction, i.e. the gate layer 60 is arranged on the surface of the first isolation layer 50 facing away from the first semiconductor layer 30. The gate layer 60 is connected with the first connecting surface 20a, the second connecting surface 20b, the third connecting surface 20c and the second sub connecting surface 20d2 of the fourth connecting surface 20d of the channel 20. The gate layer 60 comprises a dielectric layer 61 and a metal gate layer 62. The dielectric layer 61 comprises a first dielectric part 611, a second dielectric part 612 and a third dielectric part 613. The opposite ends of the first dielectric part 611 are connected with the second dielectric part 612 and the third dielectric part 613 respectively. The second dielectric part 612, the first dielectric part 611 and the third dielectric part 613 are arranged on the surface of the first isolation layer 50 along the Z-axis direction in sequence. That is, the second dielectric part 612 is arranged on the surface of the first isolation layer 50 facing away from the first semiconductor layer 30, the first dielectric part 611 is arranged on the surface of the second dielectric part 612 facing away from the first isolation layer 50, and the third dielectric part 613 is arranged on the surface of the first dielectric part 611 facing away from the second dielectric part 612. The first dielectric part 611 is connected with the first connecting surface 20a, the second connecting surface 20b, the third connecting surface 20c and the second sub connecting surface 20d2 of the fourth connecting surface 20d. The second dielectric part 612 is connected with the first connecting surface 20a, the second connecting surface 20b, the third connecting surface 20c and the second sub connecting surface 20d2 of the fourth connecting surface 20d. The third dielectric part 613 is connected with the first connecting surface 20a, the second connecting surface 20b, the third connecting surface 20c and the second sub connecting surface 20d2 of the fourth connecting surface 20d. The side of the second dielectric part 612 facing away from the channel 20 and the side of the third dielectric part 613 facing away from the channel 20 both extend out of the first dielectric part 611. The metal gate layer 62 is arranged on the outer side of the first dielectric part 611 and the surface of the first dielectric part 611 and the third dielectric part 613 facing each other. That is, the metal gate layer 62 is arranged on the circumferential side of the first dielectric part 611 facing away from the channel 20, and the metal gate layer 62 is connected with the first dielectric part 611 and the second dielectric part 612 respectively.

[0091] The second dielectric portion 612 includes a first dielectric side 612a, a second dielectric side 612b, and a third dielectric side 612c, which constitute the peripheral sides of the second dielectric portion 612. The first dielectric side 612a and the second dielectric side 612b are disposed opposite to each other along the X-axis direction, and the third dielectric side 612c is connected between the first dielectric side 612a and the second dielectric side 612b. The third dielectric portion 613 includes a fourth dielectric side 613a, a fifth dielectric side 613b, a sixth dielectric side 613c, and a seventh dielectric side 613d, which constitute the peripheral sides of the third dielectric portion 613. The fourth dielectric side 613a and the fifth dielectric side 613b are disposed opposite to each other along the X-axis direction, and the sixth dielectric side 613c and the seventh dielectric side 613d are disposed opposite to each other along the Y-axis direction. The sixth dielectric side 613c is connected to the fourth dielectric side 613a and the fifth dielectric side 613b, respectively, and the seventh dielectric side 613d is connected to the fourth dielectric side 613a and the fifth dielectric side 613b, respectively. The metal gate layer 62 includes a first outer side 62a, a second outer side 62b, and a third outer side 62c, which constitute the peripheral sides of the metal gate layer 62. The first outer side 62a and the second outer side 62b are disposed opposite to each other along the X-axis direction, and the third outer side 62c is connected between the first outer side 62a and the second outer side 62b.

[0092] In one embodiment, the first dielectric side 612a, the second dielectric side 612b, and the third dielectric side 612c are all connected to the first isolation layer 50. The first outer side 62a, the second outer side 62b, and the third outer side 62c are all connected to the second dielectric portion 612. The fourth dielectric side 613a, the fifth dielectric side 613b, the sixth dielectric side 613c, and the seventh dielectric side 613d are all connected to the metal gate layer 62. The first dielectric side 612a, the fourth dielectric side 613a, and the first outer side 62a are all aligned with each other, the second dielectric side 612b, the fifth dielectric side 613b, and the second outer side 62b are all aligned with each other, and the third dielectric side 612c, the sixth dielectric side 613c, and the third outer side 62c are all aligned with each other.

[0093] The second isolation layer 70 is disposed on the surface of the gate layer 60 along the Z-axis direction, i.e., the surface of the gate layer 60 facing away from the first isolation layer 50, and the second isolation layer 70 is connected to the second sub-connection surface 20d2 of the first connection surface 20a, the second connection surface 20b, the third connection surface 20c, and the fourth connection surface 20d of the channel 20.

[0094] The second semiconductor layer 80 is disposed on the surface of the second isolation layer 70 along the Z-axis direction, i.e., the second semiconductor layer 80 is disposed on the surface of the second isolation layer 70 facing away from the gate layer 60. The second semiconductor layer 80 is connected to the first connecting surface 20a, the second connecting surface 20b, the third connecting surface 20c, the second sub-connecting surface 20d2 of the fourth connecting surface 20d, and the surface of the channel 20 facing away from the substrate 10. The second semiconductor layer 80 includes a first sub-semiconductor 81 and a second sub-semiconductor 82, and the second sub-semiconductor 82 covers the first sub-semiconductor 81. The first sub-semiconductor 81 is disposed on the surface of the channel 20 facing away from the substrate 10, and the second sub-semiconductor 82 is connected to the surface of the second isolation layer 70 facing away from the gate layer 60, the first connecting surface 20a, the second connecting surface 20b, the third connecting surface 20c, the second sub-connecting surface 20d2 of the fourth connecting surface 20d, and the surface of the first sub-semiconductor 81.

[0095] The third isolation layer 71 includes a first isolation portion 72 and a second isolation portion 73, and the first isolation portion 72 is disposed on the peripheral surface of the second isolation portion 73. The first isolation portion 72 surrounds the peripheral surface of the second isolation layer 70 and the peripheral surface of the second sub-semiconductor 82, and the second isolation portion 73 is disposed on the surface of the second sub-semiconductor 82 facing away from the second isolation layer 70. The third isolation layer 71 includes a first surface 71a, a second surface 71b, a third surface 71c, and a fourth surface 71d, which constitute the peripheral surface of the third isolation layer 71. The first surface 71a and the second surface 71b are disposed opposite to each other along the X-axis direction, and the third surface 71c and the fourth surface 71d are disposed opposite to each other along the Y-axis direction. The third surface 71c is connected to the first surface 71a and the second surface 71b, respectively, and the fourth surface 71d is connected to the first surface 71a and the second surface 71b, respectively.

[0096] In an embodiment, the first surface 71a, the second surface 71b, the third surface 71c, and the fourth surface 71d are all connected to the third dielectric portion 613. The first surface 71a is aligned with the fourth dielectric side surface 613a, the second surface 71b is aligned with the fifth dielectric side surface 613b, the third surface 71c is aligned with the sixth dielectric side surface 613c, and the fourth surface 71d is aligned with the seventh dielectric side surface 613d.

[0097] To better describe the relationship between the plurality of vertical transistors 1, the present application divides four vertical transistors 1 into one transistor unit and divides two vertical transistors 1 into one transistor module, i.e., one transistor unit includes two transistor modules, and the transistor module is a Complementary Metal Oxide Semiconductor (CMOS). In the present application, the number of transistor modules can be multiple. Please refer to FIG. 1The four vertical transistors 1 in one transistor unit are respectively a first vertical transistor 1a, a second vertical transistor 1b, a third vertical transistor 1c and a fourth vertical transistor 1d. The first vertical transistor 1a and the second vertical transistor 1b are P-type transistors, and the third vertical transistor 1c and the fourth vertical transistor 1d are N-type transistors. One transistor module includes the first vertical transistor 1a and the third vertical transistor 1c, or includes the second vertical transistor 1b and the fourth vertical transistor 1d.

[0098] In one transistor module, the first vertical transistor 1a and the second vertical transistor 1b are sequentially and spacedly arranged along the X-axis direction, the third vertical transistor 1c and the fourth vertical transistor 1d are sequentially and spacedly arranged along the X-axis direction, the first vertical transistor 1a and the third vertical transistor 1c are sequentially arranged along the Y-axis direction and connected to each other, and the second vertical transistor 1b and the fourth vertical transistor 1d are sequentially arranged along the Y-axis direction and connected to each other. That is, the first vertical transistor 1a, the second vertical transistor 1b, the third vertical transistor 1c and the fourth vertical transistor 1d are distributed in two rows and two columns.

[0099] In some embodiments, the first vertical transistor 1a and the second vertical transistor 1b share one substrate 10, and the third vertical transistor 1c and the fourth vertical transistor 1d share one substrate 10. In other embodiments, a plurality of vertical transistors can share one substrate 10. It should be noted that the plurality of vertical transistors 1 sharing one substrate 10 are P-type transistors or N-type transistors.

[0100] In some embodiments, the vertical transistors 1 arranged along the X-axis direction in one row are P-type transistors or N-type transistors, and the P-type transistors and the N-type transistors in the vertical transistors 1 arranged along the Y-axis direction in one column are sequentially and alternately arranged, that is, the vertical transistors 1 arranged along the Y-axis direction in one column are sequentially arranged in the order of P-type transistor, N-type transistor, P-type transistor, N-type transistor, …, P-type transistor, N-type transistor.

[0101] In one transistor module, the following is illustrated by the connection relationship and position relationship between the first vertical transistor 1a and the third vertical transistor 1c.

[0102] Please refer to FIGS. 2-5In an embodiment, the first side surface 11a of the protrusion 11 of the first vertical transistor 1a and the third vertical transistor 1c both face the X-axis reverse direction, and the second side surface 11b of the protrusion 11 of the first vertical transistor 1a and the third vertical transistor 1c both face the X-axis direction. The third side surface 11c of the protrusion 11 of the first vertical transistor 1a and the third vertical transistor 1c are arranged opposite to each other, and the fourth side surface 11d of the protrusion 11 of the first vertical transistor 1a and the third vertical transistor 1c are arranged opposite to each other. The direction of the X-axis reverse direction is opposite to the direction of the X-axis direction.

[0103] In an embodiment, the first connection surface 20a of the channel 20 of the first vertical transistor 1a and the third vertical transistor 1c both face the X-axis reverse direction, and the second connection surface 20b of the channel 20 of the first vertical transistor 1a and the third vertical transistor 1c both face the X-axis direction. The third connection surface 20c of the channel 20 of the first vertical transistor 1a and the third vertical transistor 1c are arranged opposite to each other, and the fourth connection surface 20d of the channel 20 of the first vertical transistor 1a and the third vertical transistor 1c are arranged opposite to each other, that is, the first sub-connection surface 20d1 of the channel 20 of the first vertical transistor 1a and the third vertical transistor 1c are arranged opposite to each other, and the second sub-connection surface 20d2 of the channel 20 of the first vertical transistor 1a and the third vertical transistor 1c are arranged opposite to each other.

[0104] In an embodiment, the first surface 30a of the first semiconductor layer 30 of the first vertical transistor 1a and the third vertical transistor 1c both face the X-axis reverse direction, and the second surface 30b of the first semiconductor layer 30 of the first vertical transistor 1a and the third vertical transistor 1c both face the X-axis direction. The third surface 30c of the first semiconductor layer 30 of the first vertical transistor 1a and the third vertical transistor 1c are arranged opposite to each other, and the fourth surface 30d of the first semiconductor layer 30 of the first vertical transistor 1a and the third vertical transistor 1c are arranged opposite to each other, and the fifth surface 30e of the first semiconductor layer 30 of the first vertical transistor 1a and the third vertical transistor 1c are arranged opposite to each other.

[0105] In an embodiment, the first contact surface 50a of the first isolation layer 50 of the first vertical transistor 1a and the third vertical transistor 1c both face the X-axis reverse direction, and the second contact surface 50b of the first isolation layer 50 of the first vertical transistor 1a and the third vertical transistor 1c both face the X-axis direction. The third contact surface 50c of the first isolation layer 50 of the first vertical transistor 1a and the third vertical transistor 1c are arranged opposite to each other, and the first isolation layer 50 of the first vertical transistor 1a and the third vertical transistor 1c are connected to each other on the side facing each other.

[0106] In the present application, the gate layer 60 of the first vertical transistor 1a and the third vertical transistor 1c is connected. Among them, the first dielectric part 611 of the first vertical transistor 1a and the third vertical transistor 1c is spaced from each other, the second dielectric part 612 of the first vertical transistor 1a and the third vertical transistor 1c is connected to each other, the third dielectric part 613 of the first vertical transistor 1a and the third vertical transistor 1c is spaced from each other, and the metal gate layer 62 of the first vertical transistor 1a and the third vertical transistor 1c is connected to each other.

[0107] Specifically, the first dielectric side surface 612a of the second dielectric part 612 of the first vertical transistor 1a and the third vertical transistor 1c is directed to the X-axis reverse direction, the second dielectric side surface 612b of the second dielectric part 612 of the first vertical transistor 1a and the third vertical transistor 1c is directed to the X-axis direction, the third dielectric side surface 612c of the second dielectric part 612 of the first vertical transistor 1a and the third vertical transistor 1c is arranged opposite, and the side of the second dielectric part 612 of the first vertical transistor 1a and the third vertical transistor 1c is connected. The fourth dielectric side surface 613a of the third dielectric part 613 of the first vertical transistor 1a and the third vertical transistor 1c is directed to the X-axis reverse direction, the fifth dielectric side surface 613b of the third dielectric part 613 of the first vertical transistor 1a and the third vertical transistor 1c is directed to the X-axis direction, the sixth dielectric side surface 613c of the third dielectric part 613 of the first vertical transistor 1a and the third vertical transistor 1c is arranged opposite, and the seventh dielectric side surface 613d of the third dielectric part 613 of the first vertical transistor 1a and the third vertical transistor 1c is arranged opposite. The first outer side surface 62a of the metal gate layer 62 of the first vertical transistor 1a and the third vertical transistor 1c is directed to the X-axis reverse direction, and the second outer side surface 62b of the metal gate layer 62 of the first vertical transistor 1a and the third vertical transistor 1c is directed to the X-axis direction. The third outer side surface 62c of the metal gate layer 62 of the first vertical transistor 1a and the third vertical transistor 1c is arranged opposite, and the side of the metal gate layer 62 of the first vertical transistor 1a and the third vertical transistor 1c is connected.

[0108] In an embodiment, the first face 71a of the third isolation layer 71 of the first vertical transistor 1a and the third vertical transistor 1c is directed to the X-axis reverse direction, and the second face 71b of the third isolation layer 71 of the first vertical transistor 1a and the third vertical transistor 1c is spaced and arranged to be directed to the X-axis direction. The third face 71c of the third isolation layer 71 of the first vertical transistor 1a and the third vertical transistor 1c is arranged opposite, and the fourth face 71d of the third isolation layer 71 of the first vertical transistor 1a and the third vertical transistor 1c is arranged opposite.

[0109] The shape of the first sub-semiconductor 81 of the first vertical transistor 1a is different from the shape of the first sub-semiconductor 81 of the third vertical transistor 1c. The cross section of the first sub-semiconductor 81 of the first vertical transistor 1a is polygonal, and the overall shape of the first sub-semiconductor 81 of the first vertical transistor 1a is similar to a "diamond" shape, i.e., the overall shape of the first sub-semiconductor 81 of the first vertical transistor 1a is polyhedral. The cross section of the first sub-semiconductor 81 of the third vertical transistor 1c is semicircular, and the overall shape of the first sub-semiconductor 81 of the third vertical transistor 1c is semispherical. Accordingly, the shape of the inner side surface of the second sub-semiconductor 82 of the first vertical transistor 1a connected to the first sub-semiconductor 81 is also different from the shape of the inner side surface of the second sub-semiconductor 82 of the third vertical transistor 1c connected to the first sub-semiconductor 81.

[0110] The connection relationship between the second vertical transistor 1b and the fourth vertical transistor 1d is the same as the connection relationship between the first vertical transistor 1a and the third vertical transistor 1c described above, please refer to, and will not be repeated here. The positional relationship between the second vertical transistor 1b and the fourth vertical transistor 1d is the same as the positional relationship between the first vertical transistor 1a and the third vertical transistor 1c described above, please refer to, and will not be repeated here.

[0111] In this application, the substrate 10 can be a bulk silicon (Bulk Silicon) or an SOI wafer. The material of the channel 20 includes silicon (Si), silicon germanium (SiGe), or germanium (Ge). The material of the first isolation layer 50 includes at least one of silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbon nitride (SiCN), and silicon carbon oxynitride (SiCNO). The material of the dielectric layer 61 includes at least one of silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), yttrium oxide (Y2O3), and aluminum oxide (Al2O3). The material of the second isolation layer 70 includes at least one of silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbon nitride (SiCN), and silicon carbon oxynitride (SiCNO). x x y x x y ​​​​​at least one of silicon oxide (SiO), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon oxycarbide nitride (SiOCN), silicon carbonitride (SiCN), and silicon oxycarbide nitride (SiCNO). The first sub-semiconductor 81 of the first vertical transistor 1a and the second vertical transistor 1b (the first sub-semiconductor 81 whose overall shape is a polyhedron as mentioned above) is boron (B) doped silicon germanium (SiGe). The first sub-semiconductor 81 of the third vertical transistor 1c and the fourth vertical transistor 1d (the first sub-semiconductor 81 whose overall shape is a hemisphere as mentioned above) is phosphorus (P) doped silicon (Si). The first semiconductor 30 of the first vertical transistor 1a and the second vertical transistor 1b is also boron (B) doped silicon germanium (SiGe). The first semiconductor 30 of the third vertical transistor 1c and the fourth vertical transistor 1d is phosphorus (P) doped silicon (Si).

[0112] It should be noted that the material of the first sub-semiconductor 81 includes single crystal silicon, and the material of the second sub-semiconductor 82 includes amorphous silicon or polycrystalline silicon. The conductivity of single crystal silicon is better than that of amorphous silicon and polycrystalline silicon. Therefore, the first sub-semiconductor 81 is directly in contact with the channel 20, which can reduce the contact resistance between the second semiconductor layer 80 and the channel 20. Moreover, single crystal silicon has better uniformity, which makes the current transmission more stable.

[0113] The semiconductor device further includes a first electrode 110, a second electrode 120, a third electrode 130, and an interlayer dielectric layer 140. The first electrode 110 is connected with the first semiconductor layer 30, and the first electrode 110 is electrically connected with the first semiconductor layer 30. The second electrode 120 is connected with the second semiconductor layer 80, and the second electrode 120 is electrically connected with the second semiconductor layer 80. The third electrode 130 is connected with the gate layer 60, and the third electrode 130 is electrically connected with the gate layer 60. The interlayer dielectric layer 140 is connected with the side surface of the vertical transistor 1, the side surface of the first electrode 110, the side surface of the second electrode 120, and the side surface of the third electrode 130, respectively.

[0114] Specifically, the first electrode 110 includes a first sub-electrode 111 and a second sub-electrode 112 connected to each other, the first sub-electrode 111 is disposed on a surface of the first semiconductor layer 30 facing away from the substrate 10, and the second sub-electrode 112 is disposed on a surface of the first sub-electrode 111 facing away from the first semiconductor layer 30. The second isolation portion 73 is provided with a via hole penetrating the second isolation portion 73, the depth direction of the via hole is parallel to the Z-axis direction, and a surface of the second sub-semiconductor 82 facing away from the second isolation layer 70 is exposed to the via hole. The second electrode 120 includes a third sub-electrode 121 and a fourth sub-electrode 122 connected to each other, a part of the third sub-electrode 121 is accommodated in the via hole, and the third sub-electrode 121 is connected to the surface of the second sub-semiconductor 82 exposed to the via hole. The fourth sub-electrode 122 is disposed on a surface of the third sub-electrode 121 facing away from the second semiconductor layer 80. The third electrode 130 is disposed between the third isolation layer 71 of the first vertical transistor 1a and the third isolation layer 71 of the third vertical transistor 1c, and the third electrode 130 is connected to the connection between the metal gate layer 62 of the first vertical transistor 1a and the metal gate layer 62 of the third vertical transistor 1c, that is, the third electrode 130 is connected to the metal gate layer 62 of the first vertical transistor 1a and the metal gate layer 62 of the third vertical transistor 1c, respectively. Similarly, the other third electrode 130 is connected to the metal gate layer 62 of the second vertical transistor 1b and the metal gate layer 62 of the fourth vertical transistor 1d, respectively.

[0115] The number of the first electrodes 110 is changed according to the number of the vertical transistors 1, so that each vertical transistor 1 is provided with one first electrode 110. The number of the second electrodes 120 is changed according to the number of the vertical transistors 1, so that each vertical transistor 1 is provided with one second electrode 120. The number of the third electrodes 130 is changed according to the number of the transistor modules, so that each transistor module is provided with one third electrode 130.

[0116] The interlayer dielectric layer 140 is disposed on the peripheral side surface of each substrate 10, the peripheral side surface of each first semiconductor layer 30, the peripheral side surface of each first isolation layer 50, the peripheral side surface of each gate layer 60, the peripheral side surface of each third isolation layer 71, the peripheral side surface of each first electrode 110, the peripheral side surface of each second electrode 120, and the peripheral side surface of each third electrode 130. The end surface of the second sub-electrode 112 facing away from the first sub-electrode 111 exposes the interlayer dielectric layer 140, the end surface of the fourth sub-electrode 122 facing away from the third sub-electrode 121 exposes the interlayer dielectric layer 140, and the end surface of the third electrode 130 facing away from the gate layer 60 exposes the interlayer dielectric layer 140. The interlayer dielectric layer 140 is used to insulate the surface of the vertical transistor 1, the surface of the first electrode 110, the surface of the second electrode 120, and the surface of the third electrode 130.

[0117] Based on the same inventive concept, the application further provides a semiconductor device manufacturing method. The semiconductor device manufacturing method is used for manufacturing the semiconductor device described above. The same parts of the semiconductor device manufacturing method as the semiconductor device are described in the description of the semiconductor device, and are not described here again. Please refer to the description of the semiconductor device and FIGS. 1-5 the same, which are not described here again. Please refer to FIG. 6 , FIG. 12 , FIG. 19 , FIG. 22 , FIG. 26 , FIG. 30 , FIG. 34 and FIG. 38 . The semiconductor device manufacturing method comprises the following steps.

[0118] S100, providing a first substrate structure 210, forming the substrate 10, the channel 20 and the semiconductor structure 230 from the first substrate structure 210, the channel 20 and the semiconductor structure 230 are located on a surface of the substrate 10, and the semiconductor structure 230 is connected to the side surface of the channel 20.

[0119] S200, sequentially forming the isolation structure 250, the replacement gate 320, the sidewall structure 270 and the interlayer dielectric structure 340 on the semiconductor structure 230, the isolation structure 250 is located on the surface of the semiconductor structure 230 facing away from the substrate 10, the replacement gate 320 is located on the surface of the isolation structure 250 facing away from the semiconductor structure 230, the sidewall structure 270 and the interlayer dielectric structure 340 are located on the surface of the replacement gate 320 facing away from the isolation structure 250, the isolation structure 250 and the replacement gate 320 are arranged around the circumferential surface of the channel 20, the sidewall structure 270 is arranged around the circumferential surface of the channel 20, and the interlayer dielectric structure 340 is arranged around the circumferential surface of the sidewall structure 270.

[0120] S300, removing part of the sidewall structure 270 away from the replacement gate 320 to form a second isolation layer 70, part of the interlayer dielectric structure 340 away from the replacement gate 320 protrudes from the second isolation layer 70, and one end of the channel 20 away from the substrate 10 protrudes from the second isolation layer 70.

[0121] S400, forming a second semiconductor layer 80 on the second isolation layer 70 using the interlayer dielectric structure 340 as a mask, the second semiconductor layer 80 covers one end of the channel 20 protruding from the second isolation layer 70, and the second semiconductor layer 80 is located inside the interlayer dielectric structure 340.

[0122] S500, removing the interlayer dielectric structure 340 so that the circumferential surface of the second semiconductor layer 80 is exposed, and forming a third isolation layer 71 on the circumferential surface of the second semiconductor layer 80 and the surface of the second semiconductor layer 80 facing away from the second isolation layer 70.

[0123] S600, removing the replacement gate 320 to expose the peripheral side of the channel 20, forming a gate layer 60 on the peripheral side of the channel 20, and removing a portion of the isolation structure 250 and the gate layer 60 to form a first isolation layer 50, the gate layer 60 being connected to the second isolation layer 70 and the first isolation layer 50 respectively, and the first isolation layer 50 surrounding the peripheral side of the channel 20.

[0124] S700, removing a portion of the semiconductor structure 230 and the gate layer to form a first semiconductor layer 30, the first semiconductor layer 30 surrounding the peripheral side of the channel 20.

[0125] It can be understood that the manufacturing method of the semiconductor device forms the second semiconductor layer 80 by using the interlayer dielectric structure 340 as a mask plate, and the interlayer dielectric structure 340 limits the position where the second semiconductor layer 80 is formed, i.e. the second semiconductor layer 80 can only be formed on the inner side of the interlayer dielectric structure 340, so that the position of the formed second semiconductor layer 80 will not deviate, thereby improving the yield of the vertical transistor 1. Moreover, the second semiconductor layer 80 is formed on the inner side of the interlayer dielectric structure 340, without using a mask plate to limit the position where the second semiconductor layer 80 is formed, thereby realizing self-alignment of the second semiconductor layer 80.

[0126] Please refer to FIG. 7 , FIG. 7 The flowchart of step S100 of the manufacturing method of the semiconductor device disclosed in the embodiment of the present application, step S100 includes the following steps.

[0127] S110, forming a shallow trench isolation 240 on the peripheral side of the first substrate structure 210.

[0128] Specifically, please refer to FIG. 8 , FIG. 8 for FIG. 7 The cross-sectional view of the structure formed by step S110 shown in FIG. 1 corresponds to the II-II direction shown in the embodiment of the present application. The structure formed by step S110 of the manufacturing method of the semiconductor device disclosed in the embodiment of the present application is shown in the schematic view. The shallow trench isolation 240 is formed on the peripheral side of the first substrate structure 210 by etching process and filling process, the height of the shallow trench isolation 240 is lower than the height of the first substrate structure 210, the shallow trench isolation 240 separates the first substrate structure 210 from other first substrate structures 210, thereby insulating the first substrate structure 210 from other first substrate structures 210.

[0129] It should be noted that FIG. 8The illustration only shows the shallow trench isolation 240 located on one side of the first substrate structure 210; in reality, the shallow trench isolation 240 surrounds the periphery of the first substrate structure 210. The semiconductor device fabrication method is illustrated using the formation of two vertical transistors as an example. In fact, the semiconductor device fabrication method disclosed in this application can simultaneously form hundreds, thousands, tens of thousands, millions, or even more transistors.

[0130] S120, a mask structure 310 is formed on the surface of the first substrate structure 210.

[0131] Specifically, please refer to FIG. 9 , FIG. 9 for FIG. 7 The diagram shows a cross-sectional view of the structure formed in step S120 along the first direction. A mask structure 310 is formed on the surface of the first substrate structure 210 by a deposition process.

[0132] In this embodiment, two spaced mask structures 310 are formed on a first substrate structure 210. In other embodiments, a greater number of mask structures 310 may be formed on a first substrate structure 210.

[0133] S130, the first substrate structure 210 is formed into a second substrate structure 211 and a first sub-channel 21, the first sub-channel 21 is located on the surface of the second substrate structure 211, and the mask structure 310 is located on the surface of the first sub-channel 21 facing away from the second substrate structure 211.

[0134] Specifically, please refer to FIG. 10 , FIG. 10 for FIG. 7 The diagram shows a cross-sectional view of the structure formed in step S130 along the first direction. FIG. 10 Arrow S indicates the etching direction. The first substrate structure 210 is etched into a second substrate structure 211 and a first sub-channel 21 using an etching process. The first sub-channel 21 is located on the surface of the second substrate structure 211, and a mask structure 310 is located on the surface of the first sub-channel 21 facing away from the second substrate structure 211. The thickness of the second substrate structure 211 is less than the thickness of the first substrate structure 210. Due to the shielding effect of the mask structure 310, the first substrate structure 210 below the mask structure 310 is not etched, thus forming the first sub-channel 21.

[0135] S140, The second substrate structure 211 is formed into a semiconductor structure 230, the substrate 10 and the second sub-channel 22, the semiconductor structure 230 and the second sub-channel 22 are located on the surface of the substrate 10, the semiconductor structure 230 is connected to the side of the second sub-channel 22, the first sub-channel 21 is located on the surface of the second sub-channel 22 opposite to the substrate 10, the first sub-channel 21 and the second sub-channel 22 constitute the channel 20.

[0136] Specifically, please refer to FIG. 11 and FIG. 12 , FIG. 11 for FIG. 7 The diagram shows a cross-sectional view of the structure formed in step S140 along the first direction. FIG. 12 for FIG. 7 The schematic cross-sectional view of the structure formed in step S140 shown is along the second direction, wherein the second direction is... FIG. 1 The direction corresponding to III-III is shown. The second substrate structure 211 is formed into a semiconductor structure 230, a substrate 10, and a second sub-channel 22 using an ion implantation process. The sum of the thicknesses of the semiconductor structure 230 and the substrate 10 is equal to the thickness of the second substrate structure 211. Due to the obstruction of the mask structure 310, the second substrate structure 211 below the first sub-channel 21 is not implanted with ions, thus forming the second sub-channel 22. In other embodiments, the second substrate structure 211 can be directly etched into the substrate 10 and the second sub-channel 22 using an etching process, and then the semiconductor structure 230 can be formed on the substrate 10 using an epitaxial growth process.

[0137] In one embodiment, the semiconductor structure 230 connects the first connection surface 20a, the second connection surface 20b and the third connection surface 20c of the channel 20, and the shallow trench isolation 240 connects the first sub-connection surface 20d1.

[0138] In this embodiment, a semiconductor structure 230 may be connected to the sides of two channels 20. In other embodiments, a semiconductor structure 230 may be connected to the sides of more channels 20.

[0139] Please see FIG. 13 , FIG. 13 This is a flowchart illustrating step S200 of the semiconductor device fabrication method disclosed in the embodiments of this application. Step S200 includes the following steps.

[0140] S210. An isolation structure 250 is formed on the surface of the semiconductor structure 230 opposite to the substrate 10. The isolation structure 250 connects to the peripheral side surface of the channel 20.

[0141] Specifically, please refer to FIG. 14 and FIG. 15 , FIG. 14 for FIG. 13 The diagram shows a cross-sectional view of the structure formed in step S210 along the first direction. FIG. 15 for FIG. 13The step S210 shown corresponds to a schematic view of a cross section of the structure formed along the second direction. The isolation structure 250 is formed on the surface of the semiconductor structure 230 opposite to the substrate 10 by a deposition process and an etching process, the isolation structure 250 connects the first connecting surface 20a, the second connecting surface 20b, the third connecting surface 20c and the second sub connecting surface 20d2 of the fourth connecting surface 20d of the channel 20, and the isolation structure 250 also covers the shallow trench isolation 240.

[0142] In the embodiment of the present application, one isolation structure 250 can connect the peripheral side surfaces of four channels 20, and in other embodiments, one isolation structure 250 can also connect the peripheral side surfaces of a larger number of channels 20.

[0143] S220, forming a replacement gate 320 on the surface of the isolation structure 250 opposite to the semiconductor structure 230, the replacement gate 320 connects the peripheral side surfaces of the channel 20.

[0144] Specifically, please refer to FIG. 16 and FIG. 17 , FIG. 16 for FIG. 13 The step S220 shown corresponds to a schematic view of a cross section of the structure formed along the first direction, FIG. 17 for FIG. 13 The step S220 shown corresponds to a schematic view of a cross section of the structure formed along the second direction. The replacement gate 320 is formed on the surface of the isolation structure 250 opposite to the semiconductor structure 230 by a deposition process, the isolation structure 250 connects the first connecting surface 20a, the second connecting surface 20b, the third connecting surface 20c and the second sub connecting surface 20d2 of the fourth connecting surface 20d of the channel 20. In the subsequent manufacturing process, the thickness of the gate electrode layer 60 corresponds to the thickness of the replacement gate 320, so it is necessary to strictly control the flatness and thickness of the replacement gate 320. After the replacement gate 320 is formed, the surface of the replacement gate 320 is polished by a chemical mechanical polishing (CMP) process. After the chemical mechanical polishing process, the replacement gate 320 is etched to a specified height by an etching process.

[0145] In the embodiment of the present application, one replacement gate 320 can connect the peripheral side surfaces of four channels 20, and in other embodiments, one replacement gate 320 can also connect the peripheral side surfaces of a larger number of channels 20.

[0146] S230, forming a side wall structure 270 on the surface of the replacement gate 320 opposite to the isolation structure 250, the side wall structure 270 connects the peripheral side surfaces of the channel 20 and the peripheral side surfaces of the mask structure 310.

[0147] Specifically, please refer to FIG. 18 , FIG. 18 for FIG. 13The step S230 shown corresponds to a schematic view of a cross section of the structure formed along the first direction. The sidewall structure 270 is formed on the surface of the replacement gate 320 opposite to the isolation structure 250 by a deposition process and an etching process. Part of the replacement gate 320 is not shielded by the sidewall structure 270, and the sidewall structure 270 connects the first connecting surface 20a, the second connecting surface 20b, the third connecting surface 20c, and the second sub-connecting surface 20d2 of the fourth connecting surface 20d of the channel 20, and the peripheral side surface of the mask structure 310.

[0148] In the embodiments of the present application, one sidewall structure 270 connects the peripheral side surface of one channel 20 and the peripheral side surface of one mask structure 310.

[0149] It should be noted that the isolation structure can be formed on the surface of the replacement gate 320 opposite to the isolation structure 250 by a deposition process, and the isolation structure simultaneously connects the peripheral side surfaces of multiple channels 20 and the peripheral side surfaces of multiple mask structures 310, and then the multiple spaced sidewall structures 270 are formed by an etching process.

[0150] S240, an interlayer dielectric structure 340 is formed on the surface of the replacement gate 320 opposite to the isolation structure 250, and the interlayer dielectric structure 340 connects the peripheral side surface of the sidewall structure 270.

[0151] Specifically, please refer to FIG. 19 , FIG. 19 for FIG. 13 The step S240 shown corresponds to a schematic view of a cross section of the structure formed along the first direction. The interlayer dielectric structure 340 is formed on the surface of the replacement gate 320 exposed by the sidewall structure 270 by a deposition process, and the interlayer dielectric structure 340 connects the peripheral side surface of the sidewall structure 270. After the interlayer dielectric structure 340 is formed, the surface of the interlayer dielectric structure 340 opposite to the replacement gate 320 is polished by a chemical mechanical polishing process.

[0152] In the embodiments of the present application, one interlayer dielectric structure 340 connects the peripheral side surfaces of four sidewall structures 270, and in other embodiments, one interlayer dielectric structure 340 can also connect the peripheral side surfaces of a larger number of sidewall structures 270.

[0153] Please refer to FIG. 20 , FIG. 20 for a flowchart of the step S300 of the method for manufacturing the semiconductor device disclosed in the embodiments of the present application, and the step S300 includes the following steps.

[0154] S310, removing the mask structure 310.

[0155] Specifically, please refer to FIG. 21 , FIG. 21 for FIG. 19The step S310 shown corresponds to a schematic view of a cross section of the structure formed along the first direction. The mask structure 310 is removed so that the end of the channel 20 facing away from the substrate 10 is exposed.

[0156] S320, the part of the side wall structure 270 facing away from the replacement gate 320 is removed to form a second isolation layer 70, and the end of the channel 20 facing away from the substrate 10 protrudes out of the second isolation layer 70.

[0157] Specifically, refer to FIG. 22 , FIG. 22 for FIG. 19 The step S320 shown corresponds to a schematic view of a cross section of the structure formed along the first direction. The side wall structure 270 is isotropically etched by a reactive ion etching, and the etching process removes the part of the side wall structure 270 facing away from the replacement gate 320 to form the second isolation layer 70, the second isolation layer 70 connects the peripheral side surface of the channel 20, and the end of the channel 20 facing away from the substrate 10 protrudes out of the second isolation layer 70. The surface of the second isolation layer 70 facing away from the replacement gate 320 is arc-shaped.

[0158] It can be understood that the thickness and topography of the second isolation layer 70 formed can be effectively controlled by the isotropic etching process, so that the surface of the second isolation layer 70 facing away from the replacement gate 320 is arc-shaped. By removing the part of the side wall structure 270 facing away from the replacement gate 320, a space for forming the second semiconductor layer 80 is left, thereby controlling the position, size and topography of the second semiconductor layer 80.

[0159] Refer to FIG. 23 , FIG. 23 for

[0160] S410, a first sub-semiconductor 81 is formed on the surface of the channel 20 facing away from the substrate 10 with the interlayer dielectric structure 340 as a mask.

[0161] Specifically, refer to FIG. 24 , FIG. 24 for FIG. 23 The step S410 shown corresponds to a schematic view of a cross section of the structure formed along the first direction. The first sub-semiconductor 81 is formed on the channel 20 by an epitaxial growth process, the first sub-semiconductor 81 covers the surface of the channel 20 facing away from the substrate 10, and the first sub-semiconductor 81 is spaced apart from the second isolation layer 70 and the interlayer dielectric structure 340, respectively.

[0162] S420, a crystal layer 350 is formed on the surface of the second isolation layer 70 facing away from the replacement gate 320 with the interlayer dielectric structure 340 as a mask, the crystal layer 350 connects the peripheral side surface of the channel 20 and covers the first sub-semiconductor 81.

[0163] Specifically, refer to FIG. 25 , FIG. 25 for FIG. 23 the cross-sectional schematic view of the structure formed along the first direction corresponding to step S420. The crystal layer 350 is formed on the second isolation layer 70 by a deposition process, and the crystal layer 350 connects the peripheral side surface of the first sub-semiconductor 81, the surface of the first sub-semiconductor 81 facing away from the channel 20, the surface of the second isolation layer 70 facing away from the replacement gate 320, the inner side surface of the interlayer dielectric structure 340, and the peripheral side surface of the channel 20. After forming the crystal layer 350, the surface of the crystal layer 350 facing away from the second isolation layer 70 is polished by a chemical mechanical polishing process. After polishing the surface of the crystal layer 350 facing away from the second isolation layer 70, the crystal layer 350 is etched to a predetermined thickness by an etching process.

[0164] S430, ions are injected into the crystal layer 350 to form the second sub-semiconductor 82, and the first sub-semiconductor 81 and the second sub-semiconductor 82 constitute the second semiconductor layer 80.

[0165] Specifically, refer to FIG. 26 , FIG. 26 for FIG. 23 the cross-sectional schematic view of the structure formed along the first direction corresponding to step S430. The crystal layer 350 is formed into the second sub-semiconductor 82 by ion implantation. The second sub-semiconductor 82 connects the peripheral side surface of the first sub-semiconductor 81, the surface of the first sub-semiconductor 81 facing away from the channel 20, the surface of the second isolation layer 70 facing away from the replacement gate 320, the peripheral side surface of the channel 20, and the inner side surface of the interlayer dielectric structure 340.

[0166] It should be noted that the second semiconductor layer 80 is connected to the end surface of the channel 20 facing away from the substrate 10 and the peripheral side surface of the channel 20, respectively, which increases the contact area between the second semiconductor layer 80 and the channel 20, reduces the contact resistance between the second semiconductor layer 80 and the channel 20, and reduces the risk of the second semiconductor layer 80 bending and falling off after the replacement gate 320 is removed.

[0167] Refer to FIG. 27 , FIG. 27 for the flowchart of step S500 of the method for manufacturing the semiconductor device disclosed in the embodiments of the present application, and step S500 includes the following steps.

[0168] S510, the second isolation portion 73 is formed on the surface of the second sub-semiconductor 82 facing away from the second isolation layer 70 with the interlayer dielectric structure 340 as a mask.

[0169] Specifically, refer to FIG. 28 , FIG. 28 for FIG. 27The step S510 shown corresponds to a schematic view of a cross section of the structure formed along the first direction. The second isolation portion 73 is formed on the surface of the second sub-semiconductor 82 opposite to the second isolation layer 70 by a deposition process, and the second isolation portion 73 connects the inner side of the interlayer dielectric structure 340. After the second isolation portion 73 is formed, the surface of the second isolation portion 73 opposite to the second isolation layer 70 is polished by a chemical mechanical polishing process.

[0170] It can be understood that the second isolation portion 73 is formed by taking the interlayer dielectric structure 340 as a mask, and the interlayer dielectric structure 340 limits the position where the second isolation portion 73 is formed, i.e. the second isolation portion 73 can only be formed on the inner side of the interlayer dielectric structure 340, thereby improving the alignment accuracy between the second isolation portion 73 and the second sub-semiconductor 80. Moreover, no mask is additionally used to limit the position where the second isolation portion 73 is formed, thereby realizing self-alignment of the second isolation portion 73.

[0171] S520, the interlayer dielectric structure 340 is removed, and the peripheral side surface of the second sub-semiconductor 80 is exposed.

[0172] Specifically, refer to FIG. 29 , FIG. 29 for FIG. 27 The step S520 shown corresponds to a schematic view of a cross section of the structure formed along the first direction. The interlayer dielectric structure 340 is removed, and the peripheral side surface of the second isolation layer 70, the peripheral side surface of the second sub-semiconductor 82 and the peripheral side surface of the second isolation portion 73 are exposed.

[0173] S530, the first isolation portion 72 is formed on the peripheral side surface of the second isolation layer 70, the peripheral side surface of the second sub-semiconductor 82 and the peripheral side surface of the second isolation portion 73, and the first isolation portion 72 and the second isolation portion 73 constitute the third isolation layer 71.

[0174] Specifically, refer to FIG. 30 , FIG. 30 for FIG. 27 The step S530 shown corresponds to a schematic view of a cross section of the structure formed along the first direction. The first isolation portion 72 is formed on the surface of the replacement gate 320 opposite to the isolation structure 250 by a deposition process, and the first isolation portion 72 connects the peripheral side surface of the second isolation layer 70, the peripheral side surface of the second sub-semiconductor 82 and the peripheral side surface of the second isolation portion 73. After the first isolation portion 72 is formed, the surface of the first isolation portion 72 opposite to the replacement gate 320 is aligned with the surface of the second isolation portion 73 opposite to the second isolation layer 70 by an etching process.

[0175] refer to FIG. 31 , FIG. 31 for a flowchart of the step S600 of the method for manufacturing the semiconductor device disclosed in the embodiments of the present application, and the step S600 includes the following steps.

[0176] S610, removing the replacement gate 320, exposing the peripheral side of the channel 20.

[0177] In detail, referring to FIG. 32 , FIG. 32 for FIG. 31 the step S610 corresponds to the cross-sectional view of the structure formed along the first direction. The removal of the replacement gate 320 exposes the surface of the isolation structure 250 facing away from the semiconductor structure 230 and the peripheral side of the channel 20.

[0178] It can be understood that after the removal of the replacement gate 320, the second isolation layer 70, the channel 20 and the isolation structure 250 form a ring-shaped first accommodation cavity Q1, and the first accommodation cavity Q1 has a ring-shaped opening, and the peripheral side of the channel 20 exposes the opening of the first accommodation cavity Q1. The first accommodation cavity Q1 allows the material of the dielectric structure 360 to be better deposited between the second isolation layer 70 and the isolation structure 250, avoiding the occurrence of cavity pores in the dielectric structure 360 between the second isolation layer 70 and the isolation structure 250, and facilitating the improvement of the quality of the dielectric structure 360. FIG. 32 In particular, the cross section of the first accommodation cavity Q1 is in the shape of a "C".

[0179] S620, forming a dielectric structure 360 on the surface of the isolation structure 250 facing away from the semiconductor structure 230, the peripheral side of the channel 20 and the peripheral side of the first isolation part 72.

[0180] In detail, referring to FIG. 33 , FIG. 33 for FIG. 31 the step S620 corresponds to the cross-sectional view of the structure formed along the first direction. The dielectric structure 360 is formed by a deposition process, and the dielectric structure 360 connects the surface of the isolation structure 250 facing away from the semiconductor structure 230, the peripheral side of the channel 20, the surface of the first isolation part 72 facing the semiconductor structure 230, the peripheral side of the first isolation part 72 and the surface of the second isolation part 73 facing away from the semiconductor structure 230.

[0181] It can be understood that the dielectric structure 360 forms a ring-shaped second accommodation cavity Q2 between the second isolation layer 70 and the isolation structure 250, and the second accommodation cavity Q2 has a ring-shaped opening, and the side of the dielectric structure 360 facing away from the channel 20 exposes the opening of the second accommodation cavity Q2. In subsequent processes, the second accommodation cavity Q2 allows the material of the metal gate structure 370 to be better deposited into the second accommodation cavity Q2 formed by the dielectric structure 360, avoiding the occurrence of cavity pores in the metal gate structure 370 in the region surrounded by the dielectric structure 360, and facilitating the improvement of the quality of the metal gate structure 370. FIG. 33 In particular, the cross section of the second accommodation cavity Q2 is in the shape of a "C".

[0182] In this embodiment, a dielectric structure 360 ​​can connect the exposed surfaces of four channels 20 and the exposed surfaces of four second isolation layers 70. In other embodiments, a dielectric structure 360 ​​can connect an even greater number of exposed surfaces of channels 20 and an even greater number of exposed surfaces of second isolation layers 70.

[0183] Among them, part of the material of the metal grid structure 370 is a work function metal, which includes copper, iron, aluminum, zinc, silver, platinum, etc.

[0184] S630, a metal gate structure 370 is formed on the surface of the dielectric structure 360 ​​facing away from the isolation structure 250. The metal gate structure 370 connects the surface of the dielectric structure 360 ​​facing away from the channel 20, the surface of the dielectric structure 360 ​​facing away from the second isolation layer 70, and the surface of the dielectric structure 360 ​​facing away from the first isolation portion 72. The metal gate structure 370 and the dielectric structure 360 ​​constitute a gate layer structure.

[0185] Specifically, please refer to FIG. 34 , FIG. 34 for FIG. 31 The diagram shows a cross-sectional view of the structure formed in step S630 along the first direction. A metal gate structure 370 is formed by a deposition process. The metal gate structure 370 connects the surfaces of the dielectric structure 360 ​​facing away from the isolation structure 250, the dielectric structure 360 ​​facing away from the channel 20, the dielectric structure 360 ​​facing away from the second isolation layer 70, the dielectric structure 360 ​​facing away from the first isolation portion 72, and the dielectric structure 360 ​​facing away from the second isolation portion 73. After forming the metal gate structure 370, the dielectric structure 360 ​​and the metal gate structure 370 on the surface of the second isolation portion 73 facing away from the second isolation layer 70 can be removed, exposing the second isolation portion 73. After forming the metal gate structure 370, its surface can be smoothed by chemical mechanical polishing.

[0186] S640, Remove the portion of the gate layer structure that is offset from the third isolation layer 71 to form a gate layer 60, the gate layer 60 being connected to the peripheral side of the channel 20 and the surface of the second isolation layer 70 facing away from the second semiconductor layer 80.

[0187] Understandably, in related technologies, the gate layer is formed first, followed by the second semiconductor layer, which requires a high-temperature environment. Because the gate layer is not heat-resistant, the crystal uniformity of the gate layer decreases during the formation of the second semiconductor layer, leading to leakage, reduced reliability, and low yield. Forming the second semiconductor layer at a lower temperature results in an uneven surface appearance. The technical solution of this application avoids the aforementioned temperature constraints by forming the second semiconductor layer 80 first and then the gate layer 60, thus improving the reliability of the gate layer 60.

[0188] FIG. 6 shows a flowchart of step S640 of the method for manufacturing the semiconductor device according to the embodiment of the present application. Step S640 includes the following steps. FIG. 35 FIG. 35 FIG. 7 shows a flowchart of step S640 of the method for manufacturing the semiconductor device according to the embodiment of the present application. Step S640 includes the following steps.

[0189] S641, removing the part of the metal gate structure 370 away from the isolation structure 250 to form a metal gate transition structure 371.

[0190] Specifically, referring to FIG. 6, step S640 includes the following steps. FIG. 36 FIG. 36 For FIG. 35 FIG. 7 shows a cross-sectional view of the structure formed in step S641 along the first direction. The part of the metal gate structure 370 away from the isolation structure 250 is removed by etching process to form the metal gate transition structure 371, and the height of the surface of the metal gate transition structure 371 away from the isolation structure 250 is lower than that of the metal gate structure 370.

[0191] It can be understood that, in order to avoid removing the third isolation layer 71 in the process of forming the gate layer structure into the gate layer 60, the part of the metal gate structure 370 away from the isolation structure 250 is removed first to reserve the position of the part to be removed and to make the third isolation layer 71 have a layer of dielectric structure 360 for protection. In the process of forming the gate layer structure into the gate layer 60, the reserved position of the part to be removed can make the gate layer 60 be formed faster, and the dielectric structure 360 can protect the third isolation layer 71 from being removed.

[0192] It can also be understood that, in the process of etching the metal gate structure 370, no mask is used to limit the position of the part of the metal gate structure 370 to be etched, but the metal gate structure 370 between two adjacent third isolation layers 71 is etched by the shielding of the third isolation layer 71 to achieve self-aligned etching. Due to the shielding of the third isolation layer 71, the dielectric structure 360 below the third isolation layer 71 and the metal gate transition structure 371 will not be etched, which ensures that the on-state voltage (Vt) of the vertical transistor will not be shifted. Moreover, by selectively etching the metal gate structure 370, the third isolation layer 71 and the second semiconductor layer 80 will not be etched, which avoids the short circuit of the vertical transistor 1 caused by the etching of the third isolation layer 71 and the open circuit of the vertical transistor 1 caused by the etching of the second semiconductor layer 80.

[0193] S642, forming a mask body 380 on the surface of the third isolation layer 71 away from the isolation structure 250.

[0194] Specifically, referring to FIG. 6, step S640 includes the following steps. FIG. 37 FIG. 37 For​​​​FIG. 35 The step S642 shown corresponds to a schematic view of a cross section of the structure formed along the first direction. The mask body 380 is formed on the first isolation portion 72 and on the second isolation portion 73 by a photolithography process, and the mask body 380 does not shield the dielectric structure 360 and the metal gate transition structure 371 between the two adjacent second isolation layers 70. The mask body 380 includes a hard mask and a soft mask which are stacked.

[0195] S643, the dielectric structure 360 is removed from the portion misaligned with the third isolation layer 71 to form the dielectric layer 61, the metal gate transition structure 371 is removed from the portion misaligned with the third isolation layer 71 to form the metal gate layer 62, and the isolation structure 250 is formed into the first isolation layer 50. The dielectric layer 61 and the metal gate layer 62 are both located between the third isolation layer 71 and the first isolation layer 50. The dielectric layer 61 is connected to the circumferential side surface of the channel 20, and the metal gate layer 62 is connected to the circumferential side surface of the dielectric layer 61. The dielectric layer 61 and the metal gate layer 62 constitute the gate layer 60. The gate layer 60 is located corresponding to the position of the third isolation layer 71, and the first isolation layer 50 is located corresponding to the position of the gate layer 60.

[0196] Specifically, referring to FIG. 38 , FIG. 38 for FIG. 35 The step S643 shown corresponds to a schematic view of a cross section of the structure formed along the first direction. The dielectric structure 360 is removed from the portion misaligned with the third isolation layer 71 by a photolithography process, and the dielectric structure 360 under the third isolation layer 71 is retained to form the dielectric layer 61. The metal gate transition structure 371 is removed from the portion misaligned with the third isolation layer 71 by a photolithography process, and the metal gate transition structure 371 under the third isolation layer 71 is retained to form the metal gate layer 62. The isolation structure 250 is removed from the portion misaligned with the gate layer 60 by a photolithography process, and the isolation structure 250 under the third isolation layer 71 is retained to form the first isolation layer 50. The first isolation layer 50 is connected to the surface of the semiconductor structure 230 facing away from the substrate 10, the circumferential side surface of the channel 20, and the surface of the gate layer 60 facing away from the second semiconductor layer 80.

[0197] It should be noted that the mask body 380 serves as a mask plate for the photolithography process in step S630, and the dielectric layer 61, the metal gate layer 62, and the first isolation layer 50 are formed by one photolithography process. To ensure that the portion of the isolation structure 250 misaligned with the third isolation layer 71 is completely removed, the semiconductor structure 230 can be etched downward by a photolithography process, that is, the portion of the semiconductor structure 230 exposing the first isolation layer 50 can be etched downward by a first preset thickness. The first preset thickness can be 1 nm, 1.5 nm, 10 nm, 21 nm, or other values, which are not limited in the present application.

[0198] It is also understood that the technical solution of forming the gate layer 60 disclosed in the present application can reduce the number of multiple exposures of the self-aligned double imaging technology, reduce the process complexity, and improve the yield of the formed semiconductor device.

[0199] Please refer to FIG. 39 , FIG. 39 For FIG. 6 The step S700 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction.

[0200] The semiconductor structure 230 is removed by etching process, and the part of the semiconductor structure 230 under the gate layer 60 is reserved to form the first semiconductor layer 30, and the first semiconductor layer 30 surrounds the side surface of the channel 20. In order to ensure that the part of the semiconductor structure 230 which is staggered with the first isolation layer 50 is completely removed, the substrate 10 is etched downward to form the protrusion 11 and the base 12 of the substrate 10, that is, the part of the substrate 10 which exposes the first isolation layer 50 is etched downward by a second preset thickness. The second preset thickness can be 1nm, 1.5nm, 10nm, 21nm, or other values, which are not limited in the present application. The shallow trench isolation 240 is etched to the height of the base 12 to form the first interlayer dielectric layer 241, that is, the upper surface of the first interlayer dielectric layer 241 is aligned with the upper surface of the base 12.

[0201] The material of the first semiconductor layer 30 is consistent with the material of the semiconductor structure 230 formed therefrom. For example, the material of the first semiconductor 30 is boron (B) doped silicon germanium (SiGe), and the material of the semiconductor structure 230 formed therefrom is also boron (B) doped silicon germanium (SiGe). For another example, the material of the first semiconductor 30 is phosphorus (P) doped silicon (Si), and the material of the semiconductor structure 230 formed therefrom is also phosphorus (P) doped silicon (Si).

[0202] It should be noted that in the heat treatment process, the doping elements of the semiconductor structure 230 will diffuse into the second sub-channel 22, and the width between the two sides of the second sub-channel 22 is very small. Therefore, the channel of the vertical transistor 1 of the present application is actually the first sub-channel 21.

[0203] In the present application, please refer to FIG. 6 and FIG. 40 , FIG. 40 For FIG. 6 The step S800 shown in the figure corresponds to the cross-sectional view of the structure formed along the first direction. After forming the first semiconductor layer 30, the semiconductor device manufacturing method further comprises:

[0204] S800, a second interlayer dielectric layer 242 is formed on the circumferential side surface of the first semiconductor layer 30, the circumferential side surface of the first isolation layer 50, the circumferential side surface of the gate layer 60, the circumferential side surface of the third isolation layer 71, and the surface of the third isolation layer 71 facing away from the gate layer 60, and the first interlayer dielectric layer 241 and the second interlayer dielectric layer 242 constitute the interlayer dielectric layer 140.

[0205] Specifically, the second interlayer dielectric layer 242 is formed by a deposition process, and the second interlayer dielectric layer 242 connects the first interlayer dielectric layer 241, the circumferential side surface of the protrusion 11, the circumferential side surface of the first semiconductor layer 30, the circumferential side surface of the first isolation layer 50, the circumferential side surface of the gate layer 60, the circumferential side surface of the third isolation layer 71, and the surface of the third isolation layer 71 facing away from the gate layer 60.

[0206] In this application, please refer to FIG. 6 , FIG. 41 and FIG. 42 , please refer to FIG. 41 , FIG. 41 for FIG. 6 the step S900 corresponds to the cross-sectional view of the structure formed along the first direction. Please refer to FIG. 42 , FIG. 42 for FIG. 6 the step S900 corresponds to the cross-sectional view of the structure formed along the second direction.

[0207] S900, a first accommodating hole 140a, a second accommodating hole 140b, a third accommodating hole 140c are opened in the second interlayer dielectric layer 242, and a via hole penetrating the second isolation portion 73 is opened in the second isolation portion 73, the first accommodating hole 140a extends to the first semiconductor layer 30, the second accommodating hole 140b extends to the via hole, the second semiconductor 80 is exposed from the via hole, and the third accommodating hole 140c extends to the metal gate layer 62 of the gate layer 60.

[0208] Specifically, the first accommodating hole 140a is located on the side of the first semiconductor layer 30 facing away from the substrate 10, the second accommodating hole 140b is located on the side of the second isolation layer 70 facing away from the gate layer 60, and the third accommodating hole 140c is located on the side of the gate layer 60 facing away from the first isolation layer 50.

[0209] S1000, a first electrode 110 is formed in the first accommodating hole 140a, a second electrode 120 is formed in the second accommodating hole 140b and the via hole, and a third electrode 130 is formed in the third accommodating hole 140c.

[0210] Specifically, please refer to FIG. 2 and FIG. 3The first electrode 110 is connected with the first semiconductor layer 30 so that the first electrode 110 is electrically connected with the first semiconductor layer 30. The second electrode 120 is connected with the second semiconductor layer 80 so that the second electrode 120 is electrically connected with the second semiconductor layer 80. The third electrode 130 is connected with the metal gate layer 62 of the gate layer 60 so that the third electrode 130 is electrically connected with the metal gate layer 62. The first accommodating hole 140a, the second accommodating hole 140b and the third accommodating hole 140c can be interconnection line through holes.

[0211] The vertical transistor 1 formed by the manufacturing method of the semiconductor device disclosed above can achieve complete symmetry of left and right, and there is no misalignment caused by photolithography. Moreover, the manufacturing method of the semiconductor device only needs two times of photolithography process, reduces the number of photolithography process and the misalignment of layer structure caused by photolithography process, reduces the process complexity, improves the manufacturability and yield of the vertical transistor 1, and further improves the yield of the semiconductor device.

[0212] The manufacturing method of the semiconductor device disclosed above can also be used to form N-type MOS tube, P-type MOS tube, vertical nanowire transistor, vertical nanosheet transistor, junctionless transistor and inversion mode transistor.

[0213] It should be understood that the application of the present application is not limited to the above examples, and those skilled in the art can make improvements or changes according to the above description, and all these improvements and changes shall belong to the protection scope of the appended claims of the present application. Those skilled in the art can understand that all or part of the processes of the above embodiments can be implemented, and equivalent changes made according to the claims of the present application still belong to the scope covered by the present application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method for manufacturing the semiconductor device comprises: providing a first substrate structure, forming the first substrate structure into a substrate, a channel and a semiconductor structure, the channel and the semiconductor structure are located on a surface of the substrate, and the semiconductor structure is connected to a side surface of the channel; sequentially forming an isolation structure, a replacement gate, a sidewall structure and an interlayer dielectric structure on the semiconductor structure, the isolation structure is located on a surface of the semiconductor structure facing away from the substrate, the replacement gate is located on a surface of the isolation structure facing away from the semiconductor structure, the sidewall structure and the interlayer dielectric structure are located on a surface of the replacement gate facing away from the isolation structure, the isolation structure, the replacement gate and the sidewall structure surround a circumferential surface of the channel, and the interlayer dielectric structure surrounds a circumferential surface of the sidewall structure; removing a part of the sidewall structure away from the replacement gate to form a second isolation layer, a part of the interlayer dielectric structure facing away from the replacement gate protrudes from the second isolation layer, and an end of the channel facing away from the substrate protrudes from the second isolation layer; forming a second semiconductor layer on the second isolation layer by taking the interlayer dielectric structure as a mask, the second semiconductor layer covers an end of the channel protruding from the second isolation layer, and the second semiconductor layer is located on an inner side of the interlayer dielectric structure; removing the interlayer dielectric structure so that a circumferential surface of the second semiconductor layer is exposed, and forming a third isolation layer on the circumferential surface of the second semiconductor layer and a surface of the second semiconductor layer facing away from the second isolation layer; removing the replacement gate so that a circumferential surface of the channel is exposed, forming a gate layer on the circumferential surface of the channel, and removing a part of the isolation structure away from the gate layer to form a first isolation layer, the gate layer is connected to the second isolation layer and the first isolation layer respectively, and the first isolation layer surrounds the circumferential surface of the channel; removing a part of the semiconductor structure away from the gate layer to form a first semiconductor layer, and the first semiconductor layer surrounds the circumferential surface of the channel.

2. The method of manufacturing a semiconductor device according to Claim 1, wherein The method for forming the second semiconductor layer on the second isolation layer by taking the interlayer dielectric structure as a mask comprises: forming a first sub-semiconductor on a surface of the channel facing away from the substrate by taking the interlayer dielectric structure as the mask; forming a crystal layer on a surface of the second isolation layer facing away from the replacement gate by taking the interlayer dielectric structure as the mask, the crystal layer is connected to the circumferential surface of the channel and covers the first sub-semiconductor; injecting ions into the crystal layer to form a second sub-semiconductor, the second sub-semiconductor is connected to the circumferential surface of the channel and covers the first sub-semiconductor, and the first sub-semiconductor and the second sub-semiconductor constitute the second semiconductor layer.

3. The method of manufacturing a semiconductor device according to Claim 2, wherein The material of the first sub-semiconductor comprises monocrystalline silicon, and the material of the second sub-semiconductor comprises amorphous silicon or polycrystalline silicon.

4. The method of manufacturing a semiconductor device according to Claim 1, wherein The method for removing the interlayer dielectric structure so that the circumferential surface of the second semiconductor layer is exposed and forming the third isolation layer on the circumferential surface of the second semiconductor layer and a surface of the second semiconductor layer facing away from the second isolation layer comprises: forming a second isolation portion on a surface of the second semiconductor layer opposite to the second isolation layer by taking the interlayer dielectric structure as the mask plate; removing the interlayer dielectric structure, so that a peripheral side surface of the second semiconductor is exposed; forming a first isolation portion on the peripheral side surface of the second semiconductor, the first isolation portion surrounding a peripheral side surface of the second isolation portion and a peripheral side surface of the second semiconductor layer, and the first isolation portion and the second isolation portion constituting the third isolation layer.

5. The method of manufacturing a semiconductor device according to Claim 1, wherein The removing the replacement gate so that the peripheral side surface of the channel is exposed and forming a gate layer on the peripheral side surface of the channel includes: removing the replacement gate, so that the peripheral side surface of the channel is exposed; forming a dielectric structure on the peripheral side surface of the channel, the dielectric structure connecting a peripheral side surface of the third isolation layer; forming a metal gate structure on a surface of the dielectric structure opposite to the channel, the metal gate structure connecting a surface of the dielectric structure opposite to the third isolation layer, and the dielectric structure and the metal gate structure constituting a gate layer structure; removing a portion of the gate layer structure that is misaligned with the third isolation layer to form the gate layer, the gate layer connecting the peripheral side surface of the channel, the first isolation layer, and the second isolation layer, respectively.

6. The method of manufacturing a semiconductor device according to Claim 5, wherein The second isolation layer, the channel, and the isolation structure surround a ring-shaped first accommodation cavity, the first accommodation cavity has a ring-shaped opening, and the peripheral side surface of the channel exposes the opening of the first accommodation cavity.

7. The method of producing a semiconductor device according to Claim 5, wherein The dielectric structure surrounds a ring-shaped second accommodation cavity between the second isolation layer and the isolation structure, the second accommodation cavity has a ring-shaped opening, and a side surface of the dielectric structure opposite to the channel exposes the opening of the second accommodation cavity.

8. The method of producing a semiconductor device according to Claim 5, wherein The removing a portion of the gate layer structure that is misaligned with the third isolation layer to form the gate layer includes: removing a portion of the metal gate structure away from the isolation structure to form a metal gate transition structure; forming a mask body on a surface of the third isolation layer opposite to the isolation structure; removing a portion of the dielectric structure that is misaligned with the third isolation layer to form a dielectric layer and removing a portion of the metal gate transition structure that is misaligned with the third isolation layer to form a metal gate layer, the dielectric layer connecting the peripheral side surface of the channel, the metal gate layer connecting a peripheral side surface of the dielectric layer, and the dielectric layer and the metal gate layer constituting the gate layer.

9. The method of producing a semiconductor device according to any one of claims 1 to 8, wherein In a process of forming the first isolation layer from the isolation structure, a first preset thickness of the semiconductor structure is removed.

10. The method of producing a semiconductor device according to any one of claims 1 to 8, wherein In a process of forming the first semiconductor layer from the semiconductor structure, a second preset thickness of the substrate is removed.

11. The method of producing a semiconductor device according to any one of claims 1 to 8, wherein The side wall structure is formed into the second isolation layer through an isotropic etching process.

12. The method of producing a semiconductor device according to any one of claims 1 to 8, wherein After the first semiconductor layer is formed, the semiconductor device manufacturing method further includes: forming a second interlayer dielectric layer on a peripheral side surface of the first semiconductor layer, a peripheral side surface of the first isolation layer, a peripheral side surface of the gate layer, a peripheral side surface of the third isolation layer, and a surface of the third isolation layer opposite to the gate layer.

13. The method of producing a semiconductor device according to Claim 12, wherein The semiconductor device manufacturing method further includes: A first accommodating hole, a second accommodating hole and a third accommodating hole are opened in the second interlayer dielectric layer, and a via hole is opened in the third isolation layer, the first accommodating hole extends to the first semiconductor layer, the second accommodating hole extends to the via hole, the second semiconductor layer is exposed from the via hole, and the third accommodating hole extends to the gate layer; A first electrode is formed in the first accommodating hole, a second electrode is formed in the second accommodating hole and the via hole, and a third electrode is formed in the third accommodating hole.

14. A semiconductor device, characterized by comprising: The semiconductor device is manufactured by the manufacturing method of the semiconductor device according to any one of claims 1-13, and comprises a substrate, a channel, a first semiconductor layer, a first isolation layer, a gate layer, a second isolation layer, a third isolation layer and a second semiconductor layer, the channel is arranged on the surface of the substrate, the first semiconductor layer, the first isolation layer, the gate layer, the second isolation layer and the second semiconductor layer are sequentially arranged along the height direction of the channel, the first semiconductor layer, the first isolation layer, the gate layer, the second isolation layer and the second semiconductor layer are connected to the side surface of the channel, the second semiconductor layer is also connected to the surface of the channel opposite to the substrate, and the third isolation layer covers the second semiconductor layer.

15. An electronic device, comprising: The electronic device comprises a circuit board and the semiconductor device according to claim 14, and the semiconductor device is electrically connected to the circuit board.

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