Semiconductor structure and method of manufacturing the same

Abstract

The application relates to the technical field of integrated circuits, in particular to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; sequentially forming a pseudo-gate material layer and a mask layer on one side of the substrate, the mask layer comprising a first mask part and a second mask part; patterning the pseudo-gate material layer based on the mask layer to form a pseudo-gate structure, the pseudo-gate structure comprising a first pseudo-gate structure and a second pseudo-gate structure, the first pseudo-gate structure being formed based on the first mask part, the second pseudo-gate structure being formed based on the second mask part, and the width of the first pseudo-gate structure being smaller than the width of the second pseudo-gate structure; forming a groove in the second mask part; forming a first side wall on the sidewall of the first pseudo-gate structure, the sidewall of the second pseudo-gate structure and the sidewall of the groove; and removing at least part of the mask layer and the groove and the first side wall on the sidewall of the groove. By forming the groove in the second mask part, the topography of the second mask part is close to that of the first mask part.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] The semiconductor fabrication process involves multiple etching steps. In each etching step, the surface film of the semiconductor is consumed. However, the consumption of the surface film is not uniform, resulting in height differences in the surface film and consequently affecting the fabrication of other structures. Summary of the Invention

[0003] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the semiconductor problems in the prior art.

[0004] To achieve the above objectives, a method for fabricating a semiconductor structure is provided, comprising:

[0005] Provide substrate;

[0006] A dummy gate material layer and a mask layer are sequentially formed on one side of the substrate, the mask layer including a first mask portion and a second mask portion;

[0007] The pseudo-gate material layer is patterned based on the mask layer to form a pseudo-gate structure. The pseudo-gate structure includes a first pseudo-gate structure and a second pseudo-gate structure. The first pseudo-gate structure is formed based on the first mask portion, and the second pseudo-gate structure is formed based on the second mask portion. The width of the first pseudo-gate structure is smaller than the width of the second pseudo-gate structure.

[0008] A groove is formed within the second mask portion;

[0009] A first sidewall is formed on the sidewall of the first pseudo-gate structure, the sidewall of the second pseudo-gate structure, and the sidewall of the trench.

[0010] Remove at least a portion of the mask layer, and remove the trench and the first sidewall located on the sidewall of the trench.

[0011] In one embodiment, the depth of the trench is less than the thickness of the second mask portion.

[0012] In one embodiment, the trench forms a plurality of second mask patterns within the second mask portion, the size of the second mask pattern projected onto the substrate being the same as the size of the first mask portion projected onto the substrate.

[0013] In one embodiment, forming a trench within the second mask portion includes:

[0014] A patterned photoresist layer is formed covering the pseudo-gate structure, the first mask portion, and the second mask portion;

[0015] Based on the patterned photoresist layer, the second mask portion is etched to form the trench;

[0016] Remove the patterned photoresist layer.

[0017] In one embodiment, forming a first sidewall on the first pseudo-gate structure sidewall, the second pseudo-gate structure sidewall, and the trench sidewall includes:

[0018] A first sub-sidewall material layer is formed on the structural surface after the trench is formed;

[0019] Remove the first sub-sidewall material layer located on the upper surface of the substrate and the upper surface of the mask layer to form the first sub-sidewall on the sidewall of the first pseudo-gate structure, the sidewall of the second pseudo-gate structure, and the trench sidewall;

[0020] A second sub-sidewall material layer is formed on the structural surface after the formation of the first sub-sidewall;

[0021] Remove the second sub-sidewall material layer located on the upper surface of the substrate and the upper surface of the mask layer to form a second sub-sidewall on the sidewall of the first sub-sidewall.

[0022] In one embodiment, the mask layer includes a first mask functional layer and a second mask functional layer, the first mask functional layer being located on the side of the second mask functional layer away from the substrate, and the trench being located within the first mask functional layer.

[0023] In one embodiment, removing at least a portion of the first mask portion and the second mask portion, and removing the trench and the first sidewall located on the trench sidewall, includes:

[0024] Remove the first mask functional layer;

[0025] or,

[0026] Remove the first mask functional layer and the second mask functional layer.

[0027] In one embodiment, after forming the first sidewall on the first pseudo-gate structure sidewall, the second pseudo-gate structure sidewall, and the trench sidewall, the process includes:

[0028] A second sidewall material layer is formed on the structural surface after the first sidewall is formed;

[0029] A filling medium material layer is formed on the surface of the second sidewall material layer;

[0030] Removing at least a portion of the mask portion to remove the trench and the first sidewall of the trench sidewall includes:

[0031] The filling medium material layer, the second sidewall material layer, and at least a portion of the mask portion are planarized. After planarization, the remaining second sidewall material layer forms the second sidewall, and the remaining filling medium material layer forms the filling layer.

[0032] In one embodiment, the planarization process of the filling medium material layer, the second sidewall material layer, and at least a portion of the mask portion includes:

[0033] Remove the first pseudo-gate structure and the second pseudo-gate structure;

[0034] Conductive material is filled into the removal regions of the first pseudo-gate structure and the second pseudo-gate structure to form a gate structure.

[0035] On the other hand, a semiconductor structure is also provided, including a semiconductor structure obtained using a semiconductor structure preparation method provided by any of the foregoing embodiments and combinations thereof.

[0036] The semiconductor structure and fabrication method described in this specification have the following advantages: By forming a trench within the second mask portion, the morphology of the second mask portion is made close to that of the first mask portion. Subsequently, during the formation of the first sidewall, the consumption of etching gas on the first and second mask portions tends to be consistent, which avoids the generation of height differences between the first and second mask portions. This, in turn, facilitates the subsequent formation of other structures. By forming a trench within the second mask portion, this specification eliminates the need for multiple processes to eliminate this height difference, thereby reducing the cost of semiconductor fabrication and improving its efficiency. Moreover, the trench may contain some material from the first sidewall; by removing the trench, this specification allows for the rapid and simultaneous removal of this material from the first sidewall within the trench, thus not affecting the fabrication of subsequent structures. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of a substrate used in related technologies;

[0039] Figure 2Schematic diagrams of the first and second pseudo-gate structures in related technologies;

[0040] Figure 3 This is a schematic diagram illustrating the height difference between the first and second mask layers in a related technology.

[0041] Figure 4 This is a schematic diagram of photoresist layer formation in related technologies;

[0042] Figure 5 This is a schematic diagram of the formation of a dielectric layer in related technologies;

[0043] Figure 6 This is a schematic diagram of dielectric layer removal in related technologies;

[0044] Figure 7 A schematic diagram illustrating the removal of the first and second mask layers in related technologies;

[0045] Figure 8 A schematic diagram illustrating the removal of another first and second mask layers in related technologies;

[0046] Figure 9 A schematic diagram illustrating the formation of the grinding stop layer and grinding media layer in related technologies;

[0047] Figure 10 This is a schematic diagram of the removal of the grinding media layer in related technologies;

[0048] Figure 11 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0049] Figure 12 This is a schematic diagram of a substrate provided in one embodiment;

[0050] Figure 13 This is a schematic diagram of a first pseudo-gate structure and a second pseudo-gate structure provided in one embodiment;

[0051] Figure 14 This is a schematic diagram of a trench provided in one embodiment;

[0052] Figure 15 This is a schematic diagram of the first sub-sidewall material layer provided in one embodiment;

[0053] Figure 16 This is a schematic diagram of the first sub-sidewall provided in one embodiment;

[0054] Figure 17 This is a schematic diagram of the second sub-sidewall material layer provided in one embodiment;

[0055] Figure 18 This is a schematic diagram of the second sub-sidewall provided in one embodiment;

[0056] Figure 19 This is a schematic diagram of the second sidewall material layer provided in one embodiment;

[0057] Figure 20 This is a schematic diagram of a filling medium material layer provided in one embodiment;

[0058] Figure 21 This is a schematic diagram of the filling layer provided in one embodiment;

[0059] Figure 22 This is a schematic diagram of the second mask pattern provided in one embodiment;

[0060] Figure 23 This is a schematic diagram of a photoresist layer provided in one embodiment;

[0061] Figure 24 This is a schematic diagram of a patterned photoresist layer provided in one embodiment;

[0062] Figure 25 This is a schematic diagram of trench etching provided in one embodiment.

[0063] Explanation of reference numerals in the attached figures: Semiconductor structure - 100; Substrate - 110; Dummy gate material layer - 120; First dummy gate structure - 121; Second dummy gate structure - 122; Mask layer - 130; Initial mask layer - 1300; First mask portion - 131; Second mask portion - 132; Second mask pattern - 1320; First mask functional layer - 133; Second mask functional layer - 134; First sidewall - 140; First sub-sidewall - 141; First sub-sidewall material layer - 1410; Second sub-sidewall - 142; Second sub-sidewall material layer - 1420; Patterned photoresist layer - 150; Photoresist layer - 1500; Second sidewall - 160; Second sidewall material layer - 1600; Fill layer - 170; Filling dielectric material layer - 1700; Trench - 200.

[0064] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood. Detailed Implementation

[0065] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0067] In each embodiment, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in each embodiment according to the specific circumstances.

[0068] It should be understood that when an element or layer is referred to as "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," or "directly connected to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this embodiment, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion.

[0069] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0070] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0071] Embodiments of this specification are described herein with reference to cross-sectional views that serve as schematic representations of ideal embodiments (and intermediate structures). Variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, embodiments of this specification should not be limited to the specific shapes of the regions shown herein, but should include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of embodiments of this specification.

[0072] In related technologies, semiconductor structures can form dummy gate structures of varying sizes. For example, please refer to... Figure 1 A dummy gate material layer 120 and a mask material layer 12 can be sequentially formed on the substrate 110 of the semiconductor structure. Please refer to [further details]. Figure 2 The mask material layer 12 and the dummy gate material layer 120 can be etched sequentially to form a first dummy gate structure 121 with a smaller width and a second dummy gate structure 122 with a larger width. Simultaneously, a first mask layer 12A is formed on the top surface of the first dummy gate structure 121, and a second mask layer 12B is formed on the top surface of the second dummy gate structure 122. (See also...) Figure 3 In semiconductor manufacturing processes, sidewalls 13 are often used to surround a dummy gate structure. The sidewalls 13 can comprise multiple layers. During the formation of each layer, a sidewall material layer is typically formed over the entire surface, and then a portion of the sidewall material layer is removed to form the sidewall 13. During this process, it was found that the consumption of the first mask layer 12A and the second mask layer 12B is different; the consumption of the first mask layer 12A is higher, while the consumption of the second mask layer 12B is lower. This results in a height difference between the remaining first mask layer 12A and the second mask layer 12B (e.g.,...). Figure 3 (As shown at point A), this is detrimental to the subsequent formation of other structures. Therefore, it is necessary to eliminate this height difference. After research, it is believed that this height difference can be eliminated by gradually removing the first mask layer 12A and the second mask layer 12B. For example, please refer to... Figure 4 and Figure 5A protective layer 14, a dielectric layer 15, and a photoresist layer 16 covering each structure can be formed sequentially. The photoresist layer 16 may have openings. Based on the photoresist layer 16, the dielectric layer 15 is etched to form an opening in the dielectric layer 15 exposing the second dummy gate structure 122, and then the photoresist layer 16 is removed. Please refer to [further details to be added]. Figure 6 The remaining dielectric layer 15 is etched until it is flush with the first dummy gate structure 121. Next, please refer to... Figure 7 , Figure 8 The first mask layer 12A, the second mask layer 12B, and the remaining protective layer 14 and dielectric layer 15 can be removed, leaving the remaining first dummy gate structure 121 and second dummy gate structure 122 flush. Then, please refer to... Figure 9 This can form a polishing stop layer 17 and a polishing medium layer 18 covering the first dummy gate structure 121 and the second dummy gate structure 122. (See also...) Figure 10 The sidewalls 13, polishing stop layer 17, and polishing dielectric layer 18 above the first dummy gate structure 121 and the second dummy gate structure 122 are removed by chemical mechanical polishing or other methods. However, this method involves many steps and is costly, resulting in low semiconductor fabrication efficiency. Therefore, a method for fabricating a semiconductor structure according to one or more of the following embodiments is provided.

[0073] Please see Figure 11 This embodiment provides a method for fabricating a semiconductor structure 100. Figures 12 to 21 This is a schematic diagram of an intermediate result obtained in the fabrication method of the semiconductor structure 100. The fabrication method of the semiconductor structure 100 includes:

[0074] Step S100: Provide substrate 110.

[0075] Step S200: A pseudo gate material layer 120 and a mask layer 130 are sequentially formed on one side of the substrate 110. The mask layer 130 includes a first mask portion 131 and a second mask portion 132.

[0076] Step S300: Pattern the pseudo gate material layer 120 based on the mask layer 130 to form a pseudo gate structure. The pseudo gate structure includes a first pseudo gate structure 121 and a second pseudo gate structure 122. The first pseudo gate structure 121 is formed based on the first mask portion 131, and the second pseudo gate is formed based on the second mask portion 132. The width of the first pseudo gate structure 121 is smaller than the width of the second pseudo gate structure 122.

[0077] Step S400: A groove 200 is formed in the second mask portion 132.

[0078] Step S500: A first sidewall 140 is formed on the sidewall of the first pseudo-gate structure 121, the sidewall of the second pseudo-gate structure 122, and the sidewall of the trench 200.

[0079] Step S700: Remove at least the mask layer 130, and remove the trench 200 and the first sidewall 140 located on the sidewall of the trench 200.

[0080] In step S100, the substrate 110 may be constructed of a semiconductor material, an insulating material, or any combination thereof. For example, the material of the substrate 110 may include silicon, silicon germanium, silicon carbide, etc. Alternatively, the substrate 110 may also include a layered substrate of silicon-on-insulator or silicon-germanium-on-insulator, etc.

[0081] In step S200, please refer to Figure 12 As an example, a dummy gate material layer 120 and an initial mask layer 1300 can be sequentially formed on one side of the substrate 110. See also... Figure 13 Then, the initial mask layer 1300 is patterned to form a mask layer 130. The mask layer 130 includes a first mask portion 131 and a second mask portion 132, wherein the width of the first mask portion 131 is smaller than the width of the second mask portion 132.

[0082] The material of the dummy gate material layer 120 can include at least polysilicon. Of course, the dummy gate material layer 120 can also include other film layers, thereby forming a multilayer structure.

[0083] In step S300, please refer to Figure 13 A pseudo-gate structure can be formed by patterning a pseudo-gate material layer 120 based on a mask layer 130. A substrate 110 can be exposed between adjacent pseudo-gate structures. The pseudo-gate structure includes a first pseudo-gate structure 121 and a second pseudo-gate structure 122. The first pseudo-gate structure 121 is formed based on a first mask portion 131, and the second pseudo-gate structure 122 is formed based on a second mask portion 132. Furthermore, the width of the first pseudo-gate structure 121 is smaller than the width of the second pseudo-gate structure 122. This embodiment does not limit the specific width of the first pseudo-gate structure 121 and the specific width of the second pseudo-gate structure 122.

[0084] In step S400, please refer to Figure 14 The second pseudo-gate structure 122 can be etched only to form the trench 200. During this process, the trench 200 can extend along mutually perpendicular X and Y directions. This embodiment does not impose specific limitations on the depth, width, or length of the trench 200. As an example, the second pseudo-gate structure 122 with the trench 200 can be formed using wet etching or dry etching. For example, dry etching can include any one of reactive ion etching, inductively coupled plasma etching, or high-concentration plasma etching.

[0085] In one possible example, the depth of trench 200 is less than the thickness of the second mask portion 132. It is understood that when etching the second mask portion 132, trench 200 does not penetrate the second mask portion 132. For example, the thickness of the second mask portion 132 can be 200 Å-300 Å, and the depth of trench 200 can be 100 Å-150 Å. See also... Figure 22 In another possible example, the trench 200 forms a plurality of second mask patterns 1320 within the second mask portion 132, the size of the orthographic projection of the second mask pattern 1320 onto the substrate 110 being close to the size of the orthographic projection of the first mask portion 131 onto the substrate 110. In this case, the width or length of the second mask pattern 1320 is close to the width or length of the first mask portion 131.

[0086] For example, the size of the orthographic projection of the second mask pattern 1320 onto the substrate 110 is close to the size of the orthographic projection of the first mask portion 131 onto the substrate 110, which can be: the size of the orthographic projection of the second mask pattern 1320 onto the substrate 110 is 90% to 110% of the size of the orthographic projection of the first mask portion 131 onto the substrate 110. Specifically, the width of the orthographic projection of the second mask pattern 1320 onto the substrate 110 can be 90% to 110% of the width of the orthographic projection of the first mask portion 131 onto the substrate 110. And / or, the length of the orthographic projection of the second mask pattern 1320 onto the substrate 110 can be 90% to 110% of the length of the orthographic projection of the first mask portion 131 onto the substrate 110.

[0087] In step S500, please refer to Figures 15 to 18 A first sidewall 140 can be formed on the sidewalls of the first pseudo-gate structure 121, the second pseudo-gate structure 122, and the trench 200. As an example, the material of the first sidewall 140 may include silicon oxide, silicon nitride, etc. Further details can be found in [reference needed]. Figure 14 and Figure 18 During the formation of the first sidewall 140, the first mask portion 131 and the second mask portion 132 are consumed by etching gas, resulting in a reduction in the thickness of the first mask portion 131 and the second mask portion 132. Moreover, the amount of thickness reduction of the first mask portion 131 and the second mask portion 132 can be similar.

[0088] In step S700, please refer to Figures 19 to 21 At least a portion of the first mask portion 131 and at least a portion of the second mask portion 132 can be removed by chemical mechanical grinding or mechanical grinding, and at least the trench 200 and the first sidewall 140 located on the sidewall of the trench 200 are removed.

[0089] In this embodiment, by forming a trench 200 within the second mask portion 132, the morphology of the second mask portion 132 is made similar to that of the first mask portion 131. Subsequently, during the formation of the first sidewall 140, the consumption of etching gas on the first mask portion 131 and the second mask portion 132 tends to be consistent, which reduces the height difference between the first mask portion 131 and the second mask portion 132. This, in turn, facilitates the subsequent formation of other structures. By forming the trench 200 within the second mask portion 132, this embodiment eliminates the need for multiple processes to eliminate this height difference, thereby reducing the cost of semiconductor fabrication and improving its efficiency. Furthermore, the trench 200 may contain some material from the first sidewall 140; by removing the trench 200, this embodiment can quickly and simultaneously remove this material from the first sidewall 140 within the trench 200, thus not affecting the fabrication of subsequent structures.

[0090] In one embodiment, step S400 includes:

[0091] Step S410: Form a patterned photoresist layer 150 covering the pseudo gate structure, the first mask portion 131, and the second mask portion 132.

[0092] Step S420: Based on the patterned photoresist layer 150, etch the second mask portion 132 to form a trench 200.

[0093] Step S430: Remove the patterned photoresist layer 150.

[0094] In steps S410 to S430, please refer to Figures 23 to 25 A second mask portion 132 with trenches 200 can be formed by a patterned photoresist layer 150. For example, a photoresist layer 1500 can be formed over the entire surface first, and then etched to form a patterned photoresist layer 150 with multiple openings. The openings expose the second mask portion 132. Subsequently, the second mask portion 132 can be etched based on the patterned photoresist layer 150 to form the trenches 200.

[0095] In this embodiment, the patterned photoresist layer 150 allows for the rapid and accurate formation of the second mask portion 132 with trenches 200. Furthermore, by covering the dummy gate structure and the first mask portion 131 with the patterned photoresist layer 150, the patterned photoresist layer 150 protects the dummy gate structure and the first mask portion 131 from damage during the etching of the second mask portion 132. Simultaneously, compared to the aforementioned related technologies, this embodiment does not require the formation of the photoresist layer 16, thus not increasing the overall number of photomask operations.

[0096] In one embodiment, see Figures 15 to 18 Step S500 includes:

[0097] Step S510: Form a first sub-sidewall material layer 1410 on the structural surface after the trench 200 is formed.

[0098] Step S520: Remove the first sub-sidewall material layer 1410 located on the upper surface of the substrate 110 and the upper surface of the mask layer 130 to form the first sub-sidewall 141 on the sidewall of the first pseudo gate structure 121, the sidewall of the second pseudo gate structure 122, and the sidewall of the trench 200.

[0099] Step S530: Form a second sub-sidewall material layer 1420 on the structural surface after the formation of the first sub-sidewall 141.

[0100] Step S540: Remove the second sub-sidewall material layer 1420 located on the upper surface of the substrate 110 and the upper surface of the mask layer 130 to form a second sub-sidewall 142 on the sidewall of the first sub-sidewall 141.

[0101] In steps S510 to S540, the first sidewall 140 may include a first sub-sidewall 141 and a second sub-sidewall 142. The first sub-sidewall 141 and the second sub-sidewall 142 can be formed in a similar manner, i.e., both can be formed by first forming a material layer over the entire surface, and then removing a portion of the material layer by methods such as gas etching. This embodiment exemplarily illustrates the process of forming the first sub-sidewall 141 and the second sub-sidewall 142. It is understood that the first sidewall 140 may include the first sub-sidewall 141 and the second sub-sidewall 142, and may also include a third sub-sidewall and a fourth sub-sidewall, etc. This embodiment does not limit the specific number of film layers included in the first sidewall 140. Moreover, the third and fourth sub-sidewalls can also be formed in a similar manner.

[0102] In this embodiment, a removal step is involved in both the formation of the first sub-sidewall 141 and the second sub-sidewall 142. In this embodiment, a trench 200 is formed within the second mask portion 132, thereby making the morphology of the second mask portion 132 approximate that of the first mask portion 131. During the formation of the first sub-sidewall 141 and the second sub-sidewall 142, the consumption of etching gas on the first mask portion 131 and the second mask portion 132 tends to be consistent, thereby avoiding height differences between the first mask portion 131 and the second mask portion 132.

[0103] In one embodiment, see Figure 12 The initial mask layer 1300 may include a first mask functional layer 133 and a second mask functional layer 134, with the first mask functional layer 133 located on the side of the second mask functional layer 134 away from the substrate 110. It can be understood that both the first mask portion 131 and the second mask portion 132 include a portion of the first mask functional layer 133 and a portion of the second mask functional layer 134. See also... Figure 14The trench 200 is located within the first mask functional layer 133 of the second mask portion 132, that is, the trench 200 does not extend to the second mask functional layer 134.

[0104] Accordingly, step S700 includes:

[0105] Step S710: Remove the first mask functional layer 133, or remove the first mask functional layer 133 and the second mask functional layer 134.

[0106] In one possible example, when removing mask layer 130, only the first mask functional layer 133 may be removed, exposing the second mask functional layer 134. In another example, when removing mask layer 130, both the first mask functional layer 133 and the second mask functional layer 134 may be removed, exposing the first pseudo-gate structure 121 and the second pseudo-gate structure 122.

[0107] In this embodiment, the mask layer 130 may include a first mask functional layer 133 and a second mask functional layer 134, thereby ensuring that the trench 200 does not extend to the second pseudo gate structure 122, thus protecting the second pseudo gate structure 122 from damage.

[0108] In one embodiment, see Figures 19 to 21 After step S500, the following steps are included:

[0109] Step S600: Form a second sidewall material layer 1600 on the structural surface after the formation of the first sidewall 140.

[0110] Step S610: Form a filling medium material layer 1700 on the surface of the second sidewall material layer 1600.

[0111] Accordingly, step S700 includes:

[0112] Step S710: The filling medium material layer 1700, the second sidewall material layer 1600 and at least part of the mask portion are planarized, and after the planarization, the remaining second sidewall material layer 1600 forms the second sidewall 160, and the remaining filling medium material layer 1700 forms the filling layer 170.

[0113] In steps S600 to S710, please refer to Figure 19 The second sidewall material layer 1600 can serve as an etching stop layer. The second sidewall material layer 1600 can be formed over the entire surface. Please refer to [further details]. Figure 20 The filling dielectric material layer 1700 can then be formed. The material of the filling dielectric material layer 1700 may include silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0114] The filling dielectric material layer 1700 can fill the gaps between adjacent first dummy gate structures 121 and second dummy gate structures 122. Then, please refer to... Figure 21 The filler material layer 1700, the second sidewall material layer 1600, and at least a portion of the mask portion can be planarized by chemical mechanical polishing or mechanical polishing. Furthermore, the remaining second sidewall material layer 1600 forms the second sidewall 160, and the remaining filler material layer 1700 forms the filler layer 170. At this time, both the first sidewall 140 and the second sidewall 160 surround the first dummy gate structure 121 and the second dummy gate structure 122.

[0115] In another possible example, the planarization process can be performed stepwise on the filling dielectric material layer 1700, the second sidewall material layer 1600, and at least part of the mask portion. For example, the first step is to thin the filling dielectric material layer 1700, the second step is to etch down to the second sidewall material layer 1600, and the third step is to grind down to expose the second mask functional layer 134 or the pseudo-gate structure.

[0116] In this embodiment, by sequentially forming a second sidewall material layer 1600 and a filling medium material layer 1700, it is beneficial to planarize at least a portion of the mask portion, thereby removing the trench 200.

[0117] In one embodiment, step S700 is followed by:

[0118] Step S800: Remove the first pseudo-gate structure 121 and the second pseudo-gate structure 122.

[0119] Step S810: Fill the removal regions of the first pseudo-gate structure 121 and the second pseudo-gate structure 122 with conductive material to form a gate structure.

[0120] In steps S800 to S810, after removing the first dummy gate structure 121 and the second dummy gate structure 122, the remaining structure may include at least a filling layer 170, a first sidewall 140, and a second sidewall 160. Then, conductive material can be used to fill the areas where the first dummy gate structure 121 and the second dummy gate structure 122 were removed to form a gate structure.

[0121] Conductive materials can include metallic materials such as cobalt, nickel, titanium, tungsten, tantalum titanate, copper, and aluminum. Conductive materials can also be alloy materials, materials containing conductive metals, etc.

[0122] In this embodiment, by removing the first pseudo-gate structure 121 and the second pseudo-gate structure 122, the conductive material can be quickly filled into the areas where the first pseudo-gate structure 121 and the second pseudo-gate structure 122 have been removed, thereby rapidly fabricating the gate structure.

[0123] It should be understood that, although Figure 11 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 11 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0124] Based on the same inventive concept, a semiconductor structure 100 is provided in one embodiment. The semiconductor structure 100 is obtained by any or a combination of the foregoing embodiments.

[0125] In this embodiment, by forming a trench 200 within the second mask portion 132, the morphology of the second mask portion 132 is made close to that of the first mask portion 131. Subsequently, during the formation of the first sidewall 140, the consumption of etching gas on the first mask portion 131 and the second mask portion 132 tends to be consistent, which can reduce the height difference between the first mask portion 131 and the second mask portion 132. This, in turn, facilitates the rapid fabrication of other structures. By forming a trench 200 within the second mask portion 132, this embodiment eliminates the need for multiple processes to eliminate this height difference, thereby reducing the cost of semiconductor fabrication and improving the efficiency of semiconductor fabrication. Moreover, the trench 200 may contain some material of the first sidewall 140. In this embodiment, by removing the trench 200, some material of the first sidewall 140 within the trench 200 can be quickly and simultaneously removed simultaneously, thus not affecting the fabrication of subsequent structures.

[0126] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the phrase "this embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment.

[0127] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0128] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims. The above descriptions are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural transformations made based on the inventive concept of this application and the content of the specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A dummy gate material layer and a mask layer are sequentially formed on one side of the substrate, the mask layer including a first mask portion and a second mask portion; The pseudo-gate material layer is patterned based on the mask layer to form a pseudo-gate structure. The pseudo-gate structure includes a first pseudo-gate structure and a second pseudo-gate structure. The first pseudo-gate structure is formed based on the first mask portion, and the second pseudo-gate structure is formed based on the second mask portion. The width of the first pseudo-gate structure is smaller than the width of the second pseudo-gate structure. A groove is formed within the second mask portion; A first sidewall is formed on the sidewall of the first pseudo-gate structure, the sidewall of the second pseudo-gate structure, and the sidewall of the trench; Remove at least a portion of the mask layer, and remove the trench and the first sidewall located on the sidewall of the trench; The depth of the trench is less than the thickness of the second mask portion.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The trench divides the surface of the second mask portion into a plurality of second mask patterns, the size of the second mask pattern projected onto the substrate being close to the size of the first mask portion projected onto the substrate.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of a trench within the second mask portion includes: A patterned photoresist layer is formed covering the pseudo-gate structure, the first mask portion, and the second mask portion; Based on the patterned photoresist layer, the second mask portion is etched to form the trench; Remove the patterned photoresist layer.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of a first sidewall on the sidewalls of the first pseudo-gate structure, the second pseudo-gate structure, and the trench sidewall includes: A first sub-sidewall material layer is formed on the structural surface after the trench is formed; Remove the first sub-sidewall material layer located on the upper surface of the substrate and the upper surface of the mask layer to form the first sub-sidewall on the sidewall of the first pseudo-gate structure, the sidewall of the second pseudo-gate structure, and the trench sidewall; A second sub-sidewall material layer is formed on the structural surface after the formation of the first sub-sidewall; Remove the second sub-sidewall material layer located on the upper surface of the substrate and the upper surface of the mask layer to form a second sub-sidewall on the sidewall of the first sub-sidewall.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, Both the first mask portion and the second mask portion include a first mask functional layer and a second mask functional layer. The first mask functional layer is located on the side of the second mask functional layer away from the substrate, and the trench is located within the first mask functional layer of the second mask portion.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The removal of at least a portion of the mask layer, and the removal of the trench and the first sidewall located on the trench sidewall, includes: Remove the first mask functional layer; or, Remove the first mask functional layer and the second mask functional layer.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, After forming the first sidewall on the sidewalls of the first pseudo-gate structure, the second pseudo-gate structure, and the trench sidewall, the process includes: A second sidewall material layer is formed on the structural surface after the first sidewall is formed; A filling medium material layer is formed on the surface of the second sidewall material layer; Removing at least a portion of the mask layer, and removing the trench and the first sidewall located on the trench sidewall, includes: The filling medium material layer, the second sidewall material layer, the first mask portion, and the second mask portion are planarized. After the planarization process, the remaining second sidewall material layer forms the second sidewall, and the remaining filling medium material layer forms the filling layer.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, After planarizing the filling medium material layer, the second sidewall material layer, the first mask portion, and the second mask portion, the process includes: Remove the first pseudo-gate structure and the second pseudo-gate structure; Conductive material is filled into the removal regions of the first pseudo-gate structure and the second pseudo-gate structure to form a gate structure.

9. A semiconductor structure, characterized in that, The semiconductor structure is prepared using the semiconductor structure preparation method as described in any one of claims 1-8.

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