Register management method and device, electronic equipment and storage medium

Abstract

The present disclosure relates to a register management method and device, electronic equipment and storage medium, the method comprising: allocating a common on-chip storage space for registers of a plurality of processing units in a processing device; setting a write flag corresponding to the register of each processing unit in an array of the processing device; in response to executing a first command, reading register data of a target register from off-chip storage space and storing to the on-chip storage space, and setting the write flag corresponding to the target register in the array as valid; in response to executing a second command, determining the valid target write flag from the array, reading the register data corresponding to the target write flag from the on-chip storage space, and writing to the target register of the processing unit indicated by the target write flag. The embodiments of the present disclosure can improve the running efficiency of the processing device.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a register management method and apparatus, electronic device and storage medium. Background Technology

[0002] Processor chips, such as graphics processing units (GPUs), play an increasingly important role in graphics and general computing scenarios due to their highly parallel processing capabilities. A processor chip may include multiple processing units, and it needs to efficiently manage the local registers of each processing unit to support parallel computing.

[0003] However, in related technologies, each processing unit is often managed separately with the assistance of software. The register data of different processing units is first stored in memory, and then the data is read back and sent to different processing units through different command packets. The flexibility and resource utilization of this implementation method need to be further improved. Summary of the Invention

[0004] This disclosure presents a register management method and apparatus, electronic device and storage medium.

[0005] According to one aspect of this disclosure, a register management method is provided, comprising: in a processing device, allocating a shared on-chip storage space for registers of a plurality of processing units in the processing device; setting a write flag in an array of the processing device corresponding to a register of each processing unit, the write flag being valid to indicate that register data required by the register of the corresponding processing unit has been written to the on-chip storage space; wherein, there is a correspondence between the position of the write flag in the array and the storage address of the on-chip storage space; in response to executing a first command, reading register data of a target register from off-chip storage space and storing it in the on-chip storage space, and setting the write flag in the array corresponding to the target register to be valid; in response to executing a second command, determining a valid target write flag from the array, reading register data corresponding to the target write flag from the on-chip storage space, and writing it to the target register of the processing unit indicated by the target write flag.

[0006] In one possible implementation, the array includes multiple regions, each corresponding to a register of a processing unit; each region includes multiple rows and multiple columns of write flags, each row of write flags corresponding to a different base address in the on-chip memory space, and each column of write flags corresponding to a different offset address in the on-chip memory space; the base address and the offset address are used to determine the storage address of the register data.

[0007] In one possible implementation, reading register data corresponding to the target write flag from the on-chip storage space and writing it to the target register of the processing unit indicated by the target write flag includes: obtaining the base address and the offset address corresponding to the target write flag; determining the target storage address of the register data corresponding to the target write flag in the on-chip storage space based on the base address and the offset address; reading the register data corresponding to the target write flag from the location indicated by the target storage address in the on-chip storage space and writing it to the target register of the processing unit indicated by the target write flag.

[0008] In one possible implementation, each processing unit corresponds to a set of encoded information, which corresponds to a region in the array. Reading register data corresponding to the target write flag from the on-chip storage space and writing it to the target register of the processing unit indicated by the target write flag includes: reading the register data corresponding to the target write flag from the on-chip storage space according to the target write flag; sending the register data and the encoded information corresponding to the region to which the target write flag belongs to each processing unit, so that each processing unit writes the register data to its own register if the received encoded information is the same as its own encoded information, and sends the register data and the encoded information to the processing unit indicated by the encoded information if the received encoded information is different from its own encoded information.

[0009] In one possible implementation, setting the write flag corresponding to the target register in the array to be valid includes: obtaining the storage address of the register data of the target register in the on-chip storage space; determining the target position of the write flag corresponding to the target register in the array according to the correspondence between the position of the write flag in the array and the storage address of the on-chip storage space; and setting the write flag at the target position to be valid.

[0010] In one possible implementation, the method further includes: in response to the fact that the register data corresponding to all valid target write flags in the array has been sent to the registers in the processing unit, changing the valid target write flag to an invalid write flag.

[0011] In one possible implementation, the first command includes a read command in graphics processing, and the second command includes a draw command in graphics processing.

[0012] According to one aspect of this disclosure, a register management apparatus is provided, comprising: an allocation module for allocating shared on-chip storage space for registers of multiple processing units in a processing device; a setting module for setting a write flag corresponding to a register of each processing unit in an array of the processing device, wherein the write flag being valid indicates that register data required by the register of the corresponding processing unit has been written to the on-chip storage space; wherein the positions of the write flags in the array correspond to the storage addresses of the on-chip storage space; a first response module for reading register data of a target register from off-chip storage space and storing it in the on-chip storage space in response to executing a first command, and setting the write flag corresponding to the target register in the array to be valid; and a second response module for determining a valid target write flag from the array in response to executing a second command, reading register data corresponding to the target write flag from the on-chip storage space, and writing it to the target register of the processing unit indicated by the target write flag.

[0013] In one possible implementation, the array includes multiple regions, each corresponding to a register of a processing unit; each region includes multiple rows and multiple columns of write flags, each row of write flags corresponding to a different base address in the on-chip memory space, and each column of write flags corresponding to a different offset address in the on-chip memory space; the base address and the offset address are used to determine the storage address of the register data.

[0014] In one possible implementation, the second response module is configured to: obtain the base address and the offset address corresponding to the target write flag; determine the target storage address of the register data corresponding to the target write flag in the on-chip storage space based on the base address and the offset address; read the register data corresponding to the target write flag from the location indicated by the target storage address in the on-chip storage space, and write it to the target register of the processing unit indicated by the target write flag.

[0015] In one possible implementation, where each processing unit corresponds to a set of encoded information, and the encoded information corresponds to a region in the array, the second response module is configured to: read register data corresponding to the target write flag from the on-chip storage space according to the target write flag; send the register data and the encoded information corresponding to the region to which the target write flag belongs to each processing unit, so that each processing unit writes the register data into its own register if the received encoded information is the same as its own encoded information, and sends the register data and the encoded information to the processing unit indicated by the encoded information if the received encoded information is different from its own encoded information.

[0016] In one possible implementation, the first response module is configured to: obtain the storage address of the register data of the target register in the on-chip storage space; determine the target position of the write flag corresponding to the target register in the array according to the correspondence between the position of the write flag in the array and the storage address of the on-chip storage space; and set the write flag at the target position to be valid.

[0017] In one possible implementation, the apparatus further includes a third response module for: changing a valid target write flag to an invalid write flag in response to the fact that the register data corresponding to all valid target write flags in the array has been sent to the registers in the processing unit.

[0018] In one possible implementation, the first command includes a read command in graphics processing, and the second command includes a draw command in graphics processing.

[0019] According to one aspect of this disclosure, an electronic device is provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to perform the method described above.

[0020] According to one aspect of this disclosure, a computer-readable storage medium is provided that stores computer program instructions thereon, which, when executed by a processor, implement the above-described method.

[0021] In this embodiment of the disclosure, a shared on-chip storage space can be allocated for the registers of multiple processing units in the processing device; a write flag corresponding to the register of each processing unit is set in the array of the processing device, the write flag being valid to indicate that the register data required by the register of the corresponding processing unit has been written to the on-chip storage space; wherein, there is a correspondence between the position of the write flag in the array and the storage address of the on-chip storage space; in response to executing a first command, register data of a target register is read from off-chip storage space and stored in the on-chip storage space, and the write flag corresponding to the target register in the array is set to valid; in response to executing a second command, a valid target write flag is determined from the array, register data corresponding to the target write flag is read from the on-chip storage space and written to the target register of the processing unit indicated by the target write flag.

[0022] In this way, the register management method of this disclosure embodiment can use a hardware array to set valid target write flags for each register data written to the on-chip memory space. This allows subsequent traversal of the target write flags in the array to read the register data corresponding to the target write flag from the on-chip memory space and to the target register within the processing unit indicated by the target write flag. This eliminates the need to develop different commands for each processing unit. A single command (e.g., a first command) shared by multiple processing units can be used to continuously store the register data required by each processing unit in the on-chip memory. Then, a single command (a second command) shared by multiple processing units is executed to traverse the hardware array. Hardware scheduling using the array completes the read operations for register data of different processing units. The timing of register data being sent to the registers within each processing unit is entirely scheduled by the hardware array, reducing real-time software monitoring and improving the operating efficiency of the processing device. Furthermore, the register groups of multiple processing units can share the same on-chip memory space, effectively managing the registers of different processing units with a single on-chip memory space, saving hardware resources. Furthermore, hardware arrays can be used to record changed register data, so that only the changed register data is sent each time, instead of sending all register data once, thus avoiding duplicate transmission of register data, increasing the utilization rate of the processing pipeline, and improving the efficiency of the processing equipment.

[0023] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0025] Figure 1 A flowchart illustrating a register management method according to an embodiment of the present disclosure is shown.

[0026] Figure 2 A schematic diagram of a processing apparatus according to an embodiment of the present disclosure is shown.

[0027] Figure 3 A schematic diagram of an array according to an embodiment of the present disclosure is shown.

[0028] Figure 4 A block diagram of a register management apparatus according to an embodiment of the present disclosure is shown.

[0029] Figure 5 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0030] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0031] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0032] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0033] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0034] Figure 1 A flowchart illustrating a register management method according to an embodiment of this disclosure is shown, such as... Figure 1As shown, the register management method includes:

[0035] In step S11, in the processing device, a shared on-chip storage space is allocated for the registers of multiple processing units in the processing device;

[0036] In step S12, a write flag corresponding to the register of each processing unit is set in the array of the processing device. The write flag is effective in indicating that the register data required by the register of the corresponding processing unit has been written to the on-chip memory space. The position of the write flag in the array has a corresponding relationship with the storage address of the on-chip memory space.

[0037] In step S13, in response to executing the first command, register data of the target register is read from the off-chip storage space and stored in the on-chip storage space, and the write flag corresponding to the target register in the array is set to valid;

[0038] In step S14, in response to executing the second command, a valid target write flag is determined from the array, register data corresponding to the target write flag is read from the on-chip storage space, and written to the target register of the processing unit indicated by the target write flag.

[0039] In one possible implementation, the method can be executed by a controller in a processing device.

[0040] For example, the controller may be a logic circuit embedded in the processing device; the controller may also be software or program code running in the processing device, which may be implemented by a hardware co-description language, assembly language, high-level language (e.g., C, C++, etc.) or scripting language; the embodiments of this disclosure do not limit the form of the controller.

[0041] For example, the processing device may be a board integrating multiple processors, or a processor integrating multiple computing cores. The processor may include a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a General-Purpose Computing on Graphics Processing Units (GPGPU), a Tensor Processing Unit (TPU), a Neural Network Processing Unit (NPU), etc., and the embodiments of this disclosure do not impose specific limitations on this.

[0042] In one possible implementation, the processing device includes, in addition to the controller, multiple processing units, on-chip memory, and arrays. The different processing units can be processing units sharing the same computing core within the processing device, or processing units with different computing cores within the processing device. Each processing unit includes a register set, which consists of at least one register.

[0043] The register, as a component within the processing unit, offers higher read / write speeds compared to on-chip memory. It is a high-speed storage component with limited capacity and can be used to temporarily store register data such as instructions, data, and addresses, for example, for generating, modifying, or controlling element data of graphics. The register can be composed of latches or flip-flops; the embodiments of this disclosure do not limit the specific circuit structure of the register.

[0044] On-chip memory, also known as RAM, is a memory shared by multiple processing units within a processing device. On-chip memory can be random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), etc. The embodiments disclosed herein do not limit the type of on-chip memory.

[0045] Arrays are also embedded logic circuits in the processing device, such as flip-flops, used to mark register data. For example, when on-chip memory accepts written register data, a write flag can be recorded in the array for the written register data, making the write flag valid; or, for example, when register data is read from on-chip memory into a register in the corresponding processing unit, the write flag recorded for that register data can be cleared in the array, changing the write flag from valid to invalid.

[0046] In one possible implementation, in step S11, the controller may allocate a shared on-chip memory space for the register groups within all processing units in the on-chip memory; wherein, the size of the on-chip memory space may be determined according to the number of processing units and the size of the register groups within each processing device, and the embodiments of this disclosure do not limit the specific size of the allocated on-chip memory space.

[0047] In step S11, a shared on-chip storage space is allocated for the register groups within each processing unit. In step S12, a write flag corresponding to the registers of each processing unit is set in the array of the processing device. The write flag is valid to indicate that the register data required by the registers of the corresponding processing unit has been written to the on-chip storage space, and the write flag is invalid to indicate that the register data required by the registers of the corresponding processing unit has not been written to the on-chip storage space. The position of the write flag in the array has a corresponding relationship with the storage address of the on-chip storage space, so that the storage address of the corresponding register data in the on-chip storage space can be found based on the write flag.

[0048] Thus, when the processing device needs to render a frame or a scene, in step S13, the controller can execute the first command to read back the target register data to be used by each processing unit from the off-chip video memory and write it into the allocated on-chip storage space.

[0049] The first command, for example, includes a read command or a command related to read commands in graphics processing, used to read register data from off-chip video memory into on-chip memory. Off-chip video memory refers to memory located outside the processing device chip, specifically designed to provide data storage for the processing device. The read / write speed of off-chip video memory is slower than that of on-chip memory.

[0050] At the same time, the write flag is set to valid at the location in the array corresponding to the data written to the register in the on-chip memory space, indicating that a write has been made. Since different regions in the array correspond to different processing units, the controller can subsequently traverse the array to determine the processing unit to which each register data belongs.

[0051] In step S13, an array is used to record valid write flags for each target register data. In step S14, when the controller executes the second command, it can traverse the write flags in the array to determine the valid target write flags, calculate the target storage address of the register data corresponding to each target write flag in the on-chip storage space, and read the register data corresponding to each target write flag from the on-chip storage space according to the target storage address, and put it into the register group in the processing unit indicated by each target write flag. The second command may include, for example, drawing commands in graphics processing or commands related to drawing commands, a series of instructions or functions used to generate, modify, or control graphic elements.

[0052] Compared with related technical solutions, each processing unit needs to be managed separately with the assistance of software. Different read commands are executed for different processing units to store the register data of different processing units into the on-chip memory. Then, the register data is read back and sent to different processing units through different command packets.

[0053] It is known that existing technical solutions lack flexibility in register management, requiring the development of different commands for each processing unit, resulting in excessive software involvement. Furthermore, the timing of register data transmission to the registers within each processing unit is scheduled by software code, and the process from software code to hardware execution inevitably consumes time, reducing the operating efficiency of the processing device. In the embodiments of this disclosure, however, it is not necessary to develop different commands for each processing unit. A single command shared by multiple processing units (e.g., a first command) can be used to continuously store the register data required by each processing unit in on-chip memory. Then, the shared command (a second command) is executed, traversing the array (which is essentially hardware) and using hardware scheduling to complete the read operations of register data for different processing units. The timing of register data transmission to the registers within each processing unit is entirely hardware-scheduled, reducing real-time software monitoring and improving the operating efficiency of the processing device.

[0054] Furthermore, related technologies require allocating separate storage spaces for different processing units to manage their registers, resulting in a waste of hardware resources. In the embodiments of this disclosure, however, the register groups of multiple processing units can share the same on-chip storage space, effectively managing the registers of different processing units with a single on-chip storage space, thus saving hardware resources.

[0055] Furthermore, since the relevant technical solutions rely on software assistance and each processing unit manages its own data, when the processing device renders consecutive frames, all register data needs to be sent for each frame. Moreover, register data is repeatedly sent to each processing unit during each rendering, resulting in duplicate data transmission. This repetitive operation reduces the efficiency of the processing device. In the embodiments disclosed in this disclosure, the registers of different processing units are divided into different groups, and a hardware array is used to record the changed register data. This allows only the changed register data to be sent each time, avoiding the need to send all register data, thus preventing duplicate transmission, increasing the utilization rate of the processing device pipeline, and improving the efficiency of the processing device.

[0056] Figure 2 A schematic diagram of a processing apparatus according to an embodiment of the present disclosure is shown, such as Figure 2 As shown, the processing device includes N+1 processing units (e.g., processing units 0 to N), a controller, on-chip memory, and an array; wherein, processing unit 0 includes register group 0, processing unit 1 includes register group 1, and so on, with processing unit N including register group N.

[0057] The following is based on Figure 2 The register management method of this disclosure will be illustrated by way of example.

[0058] like Figure 2 As shown, different encoding information can be assigned to different processing units. For example, encoding information 0 can be assigned to processing unit 0, encoding information 1 can be assigned to processing unit 1, and so on, with encoding information N assigned to processing unit N. It should be understood that the encoding information is used to distinguish different processing units and can be one or a combination of numbers, symbols, and letters. The embodiments of this disclosure do not limit the specific form of the encoding information.

[0059] The controller can allocate a shared on-chip memory space for register groups 0 to N in the N+1 processing units, so that each processing unit will be allocated an address space.

[0060] When the processing device needs to render a frame or a scene, the controller can execute a first command (including a read command) to read back all the register data to be used by N+1 processing units from the off-chip video memory and write it to the allocated on-chip memory space. At the same time, the write flag is set to valid at the position in the array corresponding to the register data written in the on-chip memory space, indicating that it has been written.

[0061] In one possible implementation, the array includes multiple regions, each corresponding to a register of a processing unit; each region includes multiple rows and multiple columns of write flags, each row of write flags corresponding to a different base address in the on-chip memory space, and each column of write flags corresponding to a different offset address in the on-chip memory space; the base address and the offset address are used to determine the storage address of the register data.

[0062] Figure 3 A schematic diagram of an array according to an embodiment of the present disclosure is shown, such as Figure 3 As shown, each processing unit corresponds to a set of encoded information, which corresponds to a region in the array. Different rows of the array correspond to different base addresses, different columns of the array correspond to different offset addresses, and the encoded information of different processing units corresponds to different regions in the array. Here, the identifier "1" indicates that the write flag is valid, and the identifier "0" indicates that the write flag is invalid. It should be understood that this embodiment of the present disclosure uses the identifier "1" indicating that the write flag is valid and the identifier "0" indicating that the write flag is invalid as an example; it is also possible for the identifier "0" to indicate that the write flag is valid and the identifier "1" to indicate that the write flag is invalid. This embodiment of the present disclosure does not limit this.

[0063] For example, the base address of the first row in the array is 0, the base address of the second row is 8, the base address of the third row is 16, and so on, with the base address of the last row being 16N+8; the offset address of the first column in the array is 0, the offset address of the second column is 1, and so on, with the offset address of the last column being 7; the first two rows of the array correspond to the encoded information 0, the third and fourth rows correspond to the encoded information 1, and the last two rows correspond to the encoded information N. It should be understood that... Figure 3 The array in this disclosure is only an example. The embodiments of this disclosure do not impose specific restrictions on the number of rows and columns of the array, the base address corresponding to each row, the offset address corresponding to each column, and the encoding information corresponding to different regions. These can be set according to the actual application scenario.

[0064] In one possible implementation, setting the write flag corresponding to the target register in the array to be valid includes: obtaining the storage address of the register data of the target register in the on-chip storage space; determining the target position of the write flag corresponding to the target register in the array according to the correspondence between the position of the write flag in the array and the storage address of the on-chip storage space; and setting the write flag at the target position to be valid.

[0065] Because there is a correspondence between the positions of write flags in the array and their storage addresses in the on-chip memory, whenever the storage address of the target register's data in the on-chip memory is obtained, the target position of the write flag corresponding to that target register can be determined in the array, and the write flag at that target position can be set to valid. In this way, it is possible to precisely mark which registers' data has been updated in the shared on-chip memory, which helps improve data consistency and access efficiency.

[0066] In one possible implementation, reading register data corresponding to the target write flag from the on-chip storage space and writing it to the target register of the processing unit indicated by the target write flag includes: when the controller processes the second command, obtaining the base address and the offset address corresponding to the target write flag by traversing the write flags in the array; determining the target storage address of the register data corresponding to the target write flag in the on-chip storage space based on the base address and the offset address; reading the register data corresponding to the target write flag from the position indicated by the target storage address in the on-chip storage space and writing it to the target register of the processing unit indicated by the target write flag.

[0067] For example, when the controller iterates to the first row and first column of the array, it can detect whether the target write flag "1" exists at that position in the array; such as Figure 3The presence of a target write flag "1" in the first row and first column of the array indicates that this location corresponds to a register data in the on-chip storage space. Considering that the base address of the first row is 0 and the offset address of the first column is 0, the target storage address of the register data corresponding to this target write flag in the on-chip storage space is 0+0=0. The controller can read the register data from the location indicated by the target storage address 0 in the on-chip storage space, so that the read register data can be written into the target register in the processing unit 0 according to the encoding information 0 corresponding to this location in the array.

[0068] Similarly, when the controller iterates to the first row and second column of the array, it can detect whether the target write flag "1" exists at that position in the array; for example... Figure 3 The presence of a target write flag "1" in the first row and second column of the array indicates that this location corresponds to a register data in the on-chip storage space. Considering that the base address of the first row is 0 and the offset address of the second column is 1, the target storage address of the register data corresponding to this target write flag in the on-chip storage space is 0+1=1. The controller can read the register data from the location indicated by the target storage address 1 in the on-chip storage space, so that the read register data can be written into the target register in the processing unit 0 according to the encoding information 0 corresponding to this location in the array.

[0069] It should be understood that during the controller's traversal of the array, if the target write flag "1" is not detected in a certain row or column, the controller can continue to traverse the next element in the array until all elements in the array have been traversed.

[0070] In this way, hardware scheduling using arrays allows for the completion of register data read operations for different processing units. The timing of register data transmission to registers within each processing unit is entirely hardware-scheduled, reducing the need for real-time software monitoring and improving the operational efficiency of the processing equipment. Furthermore, dividing the registers of different processing units into different groups allows the use of hardware arrays to record changed register data. This enables the transmission of only the changed register data at a time, avoiding the need to transmit all register data at once, thus increasing the utilization rate of the processing equipment pipeline and improving the overall efficiency of the processing equipment.

[0071] In one possible implementation, reading register data corresponding to the target write flag from the on-chip storage space and writing it to the target register of the processing unit indicated by the target write flag includes: reading register data corresponding to the target write flag from the on-chip storage space according to the target write flag; sending the register data and the encoding information corresponding to the region to which the target write flag belongs to each processing unit, so that each processing unit writes the register data into its own register when the received encoding information is the same as its own encoding information, and sends the register data and the encoding information to the processing unit indicated by the encoding information when the received encoding information is different from its own encoding information.

[0072] In this way, when the controller processes the second command (such as a drawing command), it can calculate the target storage address by traversing the target write flags, read the register data of the corresponding processing unit according to the target storage address, and then send the encoding information and some register data used to distinguish the processing units to each processing unit. Each processing unit can store the corresponding register data into the local target register according to the encoding information.

[0073] For example, such as Figure 3 As shown, for the target write flag "1" in the first row and first column of the array, the controller can read register data from the location indicated by target storage address 0 in the on-chip storage space and send the register data and encoding information 0 to each processing unit. If the controller sends the register data and encoding information 0 to processing unit 0, and processing unit 0 detects that the encoding information 0 is the same as its own encoding information 0, it can store the register data in its own target register. If the controller sends the register data and encoding information 0 to other processing units, and other processing units detect that the encoding information 0 is different from their own encoding information, they will forward the register data and encoding information 0 to the processing unit 0 indicated by the encoding information 0.

[0074] By writing flags and encoded information to the target, the register data can be accurately transmitted, and the register data can be directed to the target processing unit.

[0075] In one possible implementation, in response to the fact that the register data corresponding to all valid target write flags in the array has been sent to the registers in the processing unit, the valid target write flag is changed to an invalid write flag.

[0076] For example, after all the register data for the target write flags has been sent, the valid target write flags in the array can be changed to invalid, and the valid target write flags can be set again when register data is written to the on-chip memory space next time.

[0077] Once the controller confirms that the register data corresponding to all target write flags has been delivered to the target register, it can change the status of the write flags from valid to invalid. This mechanism enables dynamic cyclic management and efficient reuse of limited target write flag resources, ensuring that each write operation has a clear active cycle definition, thereby supporting the processing device to continuously and efficiently perform register data write operations.

[0078] In summary, the register management method of this disclosure can utilize a hardware array to record valid target write flags for each register data written to the on-chip memory space. This allows for subsequent traversal of the target write flags in the array, reading the register data corresponding to the target write flag from the on-chip memory space, and storing it in the register of the processing unit indicated by the target write flag. This eliminates the need to develop different commands for each processing unit. A single command (e.g., a first command) shared by multiple processing units can be used to continuously store the register data required by each processing unit in the on-chip memory. Then, a single command (a second command) shared by multiple processing units is executed to traverse the hardware array. Hardware scheduling using the array allows for the completion of read operations for register data from different processing units. The timing of register data transmission to the registers in each processing unit is entirely scheduled by the hardware array, reducing real-time software monitoring and improving the operating efficiency of the processing device. Furthermore, the register groups of multiple processing units can share the same on-chip memory space, effectively managing the registers of different processing units with a single on-chip memory space, saving hardware resources. Furthermore, hardware arrays can be used to record changed register data, so that only the changed register data is sent each time, instead of sending all register data once, thus avoiding duplicate transmission of register data, increasing the utilization rate of the processing pipeline, and improving the efficiency of the processing equipment.

[0079] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0080] In addition, this disclosure also provides processors, graphics cards and electronic devices, computer-readable storage media, and programs, all of which can be used to implement any of the register management methods provided in this disclosure. The corresponding technical solutions and descriptions are described in the corresponding records in the method section and will not be repeated here.

[0081] Figure 4 A block diagram of a register management apparatus according to an embodiment of the present disclosure is shown, such as Figure 4 As shown, the device includes:

[0082] Allocation module 41 is used to allocate shared on-chip storage space for registers of multiple processing units in the processing device.

[0083] Setting module 42 is used to set a write flag corresponding to the register of each processing unit in the array of the processing device. The write flag is effective in indicating that the register data required by the register of the corresponding processing unit has been written to the on-chip memory space. The position of the write flag in the array has a corresponding relationship with the storage address of the on-chip memory space.

[0084] The first response module 43 is configured to, in response to executing the first command, read register data of the target register from the off-chip storage space and store it in the on-chip storage space, and set the write flag corresponding to the target register in the array to be valid;

[0085] The second response module 44 is configured to, in response to executing the second command, determine a valid target write flag from the array, read register data corresponding to the target write flag from the on-chip storage space, and write it to the target register of the processing unit indicated by the target write flag.

[0086] In one possible implementation, the array includes multiple regions, each corresponding to a register of a processing unit; each region includes multiple rows and multiple columns of write flags, each row of write flags corresponding to a different base address in the on-chip memory space, and each column of write flags corresponding to a different offset address in the on-chip memory space; the base address and the offset address are used to determine the storage address of the register data.

[0087] In one possible implementation, the second response module 44 is configured to: obtain the base address and the offset address corresponding to the target write flag; determine the target storage address of the register data corresponding to the target write flag in the on-chip storage space based on the base address and the offset address; read the register data corresponding to the target write flag from the location indicated by the target storage address in the on-chip storage space, and write it to the target register of the processing unit indicated by the target write flag.

[0088] In one possible implementation, where each processing unit corresponds to a set of encoded information, and the encoded information corresponds to a region in the array, the second response module 44 is configured to: read register data corresponding to the target write flag from the on-chip storage space according to the target write flag; send the register data and the encoded information corresponding to the region to which the target write flag belongs to each processing unit, so that each processing unit writes the register data into its own register when the received encoded information is the same as its own encoded information, and sends the register data and the encoded information to the processing unit indicated by the encoded information when the received encoded information is different from its own encoded information.

[0089] In one possible implementation, the first response module is configured to: obtain the storage address of the register data of the target register in the on-chip storage space; determine the target position of the write flag corresponding to the target register in the array according to the correspondence between the position of the write flag in the array and the storage address of the on-chip storage space; and set the write flag at the target position to be valid.

[0090] In one possible implementation, the apparatus further includes a third response module for: changing a valid target write flag to an invalid write flag in response to the fact that the register data corresponding to all valid target write flags in the array has been sent to the registers in the processing unit.

[0091] In one possible implementation, the first command includes a read command in graphics processing, and the second command includes a draw command in graphics processing.

[0092] This method is specifically technically related to the internal structure of computer systems and can solve technical problems of how to improve hardware computing efficiency or execution performance (including reducing data storage, reducing data transmission, and increasing hardware processing speed), thereby achieving technical effects that improve the internal performance of computer systems in accordance with natural laws.

[0093] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0094] This disclosure also proposes a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the above-described method. The computer-readable storage medium can be volatile or non-volatile.

[0095] This disclosure also proposes an electronic device, including: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to execute the above-described method.

[0096] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0097] Electronic devices can be provided as terminals, servers, or other forms of devices. Examples include user equipment (UE), mobile devices, user terminals, terminals, cellular phones, cordless phones, personal digital assistants (PDAs), handheld devices, computing devices, in-vehicle devices, wearable devices, etc., and the embodiments disclosed herein do not limit this.

[0098] Figure 5 A block diagram of an electronic device 1900 according to an embodiment of the present disclosure is shown. For example, the electronic device 1900 may be provided as a server or a terminal device. (Refer to...) Figure 5 The electronic device 1900 includes a processing component 1922, which further includes one or more such as Figure 2 The processor shown, and the memory resources represented by memory 1932, are used to store instructions, such as application programs, that can be executed by processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, processing component 1922 is configured to execute instructions to perform the methods described above.

[0099] Electronic device 1900 may also include a power supply component 1926 configured to perform power management of electronic device 1900, a wired or wireless network interface 1950 configured to connect electronic device 1900 to a network, and an input / output (I / O) interface 1958. Electronic device 1900 can operate on an operating system stored in memory 1932, such as a Microsoft Server operating system (Windows Server). TM Apple's graphical user interface-based operating system (Mac OSX) TM ), a multi-user, multi-process computer operating system (Unix) TM Linux is a free and open-source Unix-like operating system. TM ), an open-source Unix-like operating system (FreeBSD) TM (or similar.)

[0100] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of an electronic device 1900 to perform the above-described method.

[0101] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0102] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, (but not limited to) electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0103] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0104] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0105] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0106] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0107] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0108] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0109] The computer program product can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0110] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0111] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0112] If the technical solution of this application involves personal information, the product using this technical solution has clearly informed the user of the personal information processing rules and obtained the user's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using this technical solution has obtained the user's separate consent before processing the sensitive personal information, and also meets the requirement of "express consent". For example, at personal information collection devices such as cameras, clear and prominent signs are set up to inform users that they have entered the scope of personal information collection and that personal information will be collected. If an individual voluntarily enters the collection scope, it is deemed that they have agreed to the collection of their personal information; or on the personal information processing device, with clear signs / information informing users of the personal information processing rules, authorization is obtained from the individual through pop-up information or by asking the individual to upload their personal information; wherein, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the types of personal information processed.

[0113] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A register management method, characterized in that, The method includes: In the processing device, shared on-chip storage space is allocated for the registers of multiple processing units in the processing device; Write flags are set in the array of the processing devices to correspond to the registers of each processing unit. The write flags are effective in indicating that the register data required by the registers of the corresponding processing unit has been written to the on-chip memory space. There is a correspondence between the position of the write flags in the array and the storage address of the on-chip memory space. In response to executing the first command, register data of the target register is read from the off-chip storage space and stored in the on-chip storage space, and the write flag corresponding to the target register in the array is set to valid; In response to executing the second command, a valid target write flag is determined from the array, register data corresponding to the target write flag is read from the on-chip storage space, and written to the target register of the processing unit indicated by the target write flag.

2. The method according to claim 1, characterized in that, The array includes multiple regions, each region corresponding to a register of a processing unit; Each region includes multiple rows and columns of write flags. Each row of write flags corresponds to a different base address in the on-chip storage space, and each column of write flags corresponds to a different offset address in the on-chip storage space. The base address and the offset address are used to determine the storage address of the register data.

3. The method according to claim 2, characterized in that, Reading register data corresponding to the target write flag from the on-chip storage space and writing it to the target register of the processing unit indicated by the target write flag includes: Obtain the base address and the offset address corresponding to the target write flag; Based on the base address and the offset address, determine the target storage address of the register data corresponding to the target write flag in the on-chip storage space; Read the register data corresponding to the target write flag from the location indicated by the target storage address in the on-chip storage space, and write it to the target register of the processing unit indicated by the target write flag.

4. The method according to claim 1, characterized in that, Each processing unit corresponds to a piece of encoded information, and the encoded information corresponds to a region in the array. Reading register data corresponding to the target write flag from the on-chip storage space and writing it to the target register of the processing unit indicated by the target write flag includes: Read the register data corresponding to the target write flag from the on-chip memory space according to the target write flag; The register data and the encoded information corresponding to the region to which the target write flag belongs are sent to each processing unit, so that each processing unit writes the register data into its own register when the received encoded information is the same as its own encoded information, and sends the register data and the encoded information to the processing unit indicated by the encoded information when the received encoded information is different from its own encoded information.

5. The method according to claim 1, characterized in that, Setting the write flag in the array corresponding to the target register to be valid includes: Obtain the storage address of the target register's register data in the on-chip storage space; Based on the correspondence between the position of the write flag in the array and the storage address of the on-chip memory space, determine the target position of the write flag in the array corresponding to the target register; Set the write flag at the target location to valid.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: in response to the fact that the register data corresponding to all valid target write flags in the array has been sent to the registers in the processing unit, changing the valid target write flag to the invalid write flag.

7. The method according to any one of claims 1 to 5, characterized in that, The first command includes a read command in graphics processing, and the second command includes a draw command in graphics processing.

8. A register management device, characterized in that, include: An allocation module is used to allocate shared on-chip storage space for registers of multiple processing units in the processing device. A setting module is configured to set a write flag corresponding to the register of each processing unit in the array of the processing device. The write flag is effective in indicating that the register data required by the register of the corresponding processing unit has been written to the on-chip memory space. The positions of the write flags in the array correspond to the storage addresses of the on-chip memory space. The first response module is configured to, in response to the execution of the first command, read the register data of the target register from the off-chip storage space and store it in the on-chip storage space, and set the write flag corresponding to the target register in the array to be valid; The second response module is used to respond to the execution of the second command by determining a valid target write flag from the array, reading the register data corresponding to the target write flag from the on-chip storage space, and writing it to the target register of the processing unit indicated by the target write flag.

9. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1 to 7.

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