Data caching method and device, electronic equipment, storage medium and program product

Abstract

The invention relates to a data caching method and device, electronic equipment, a storage medium and a program product. The method comprises the following steps: receiving first message data sent by sending end equipment through a PCIe bus and determining a first message type of the first message data; if the first message type is one of multiple preset message types, determining an idle first cache unit from a target cache space; the target cache space is a cache space shared by message data of multiple preset message types; storing the first message data into a first cache unit; the space size of the target cache space is determined according to the reference credit cache size corresponding to the message data of each preset message type; the reference credit cache size corresponding to the message data of the preset message type represents the cache space size required when the transmission links between the receiving end equipment and the sending end equipment transmit the message data of the preset message type. By adopting the method, the cache space utilization rate of the receiving end equipment can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data storage, and in particular to a data caching method and device, electronic equipment, storage medium and program product. BACKGROUND

[0002] PCIe is a high-bandwidth, low-latency interface standard, and is widely used in various computer systems. In order to ensure that the data sent by the sending device does not exceed the receiving capacity of the receiving device, PCIe bus gives a set of flow control (FC) methods to improve the data transmission efficiency of PCIe bus. In this method, the receiving end informs the sending end of the size of the remaining buffer space for each type of message data of the receiving end, so that the sending end can know whether the receiving end can receive the message data to be sent through this mechanism before sending.

[0003] In related technologies, the receiving end corresponds to a reserved buffer space size for each type of message data, which is used to buffer each type of message data. However, in actual situations, due to uneven distribution of link transceiver packet types, the buffer space corresponding to each type of message data will only be full in extreme cases, so in most cases, other buffer spaces will be idle, which will result in low overall utilization of the receiving end's total buffer space and cause a large amount of memory resource redundancy and waste. SUMMARY

[0004] Therefore, it is necessary to provide a data caching method, device, electronic equipment, storage medium and program product capable of improving the utilization rate of the receiving end device's buffer space to solve the above technical problems.

[0005] In a first aspect, the present application provides a data caching method. The method is used for a receiving end device, and includes:

[0006] receiving first message data sent by a sending end device through a PCIe bus, and determining a first message type of the first message data;

[0007] if the first message type is one of a plurality of preset message types, determining an idle first buffer unit from a target buffer space; the target buffer space is a buffer space shared by message data of the plurality of preset message types;

[0008] storing the first message data into the first buffer unit;

[0009] The space size of the target cache space is determined according to reference credit cache sizes respectively corresponding to message data of each preset message type. The reference credit cache size corresponding to the message data of the preset message type represents a required cache space size in a case where a transmission link between the receiving end device and the sending end device transmits the message data of the preset message type.

[0010] In one of the embodiments, the method further includes: obtaining a maximum reference credit cache from the reference credit caches respectively corresponding to the message data of each preset message type; and taking the maximum reference credit cache as the space size of the target cache space.

[0011] In one of the embodiments, the determining of the idle first cache unit from the target cache space includes: determining the first cache unit from the target cache space according to the first message type.

[0012] In one of the embodiments, the determining of the first cache unit from the target cache space according to the first message type includes: determining a first tail pointer corresponding to the first message type; wherein different preset message types correspond to different tail pointers, and each tail pointer points to an idle cache unit that can store message data of a corresponding preset message type; and taking a cache unit pointed to by the first tail pointer as the first cache unit.

[0013] In one of the embodiments, the method further includes: after storing the first message data into the first cache unit, determining an idle second cache unit from the target cache space; and updating the first tail pointer to point to the second cache unit.

[0014] In one of the embodiments, the determining of the idle second cache unit from the target cache space includes: sequentially traversing other cache units in the target cache space except the first cache unit until the idle second cache unit is determined from the other cache units.

[0015] In one of the embodiments, the sequentially traversing of the other cache units in the target cache space except the first cache unit until the idle second cache unit is determined from the other cache units includes: in the process of sequentially traversing the other cache units, obtaining a flag value of a flag bit of each cache unit traversed, the flag value being used to indicate whether the corresponding cache unit is idle; and if the flag value of the flag bit of the currently traversed cache unit indicates idle, taking the currently traversed cache unit as the second cache unit.

[0016] In one of the embodiments, the flag value is further used to indicate a message type of message data occupying the corresponding cache unit when the corresponding cache unit is not idle.

[0017] In one embodiment, the method further includes: after storing the first message data into the first cache unit, updating the flag value of the first cache unit; wherein the updated flag value is used to indicate that the first cache unit is not idle and the first cache unit is occupied by message data of the first message type.

[0018] In one embodiment, the flag bit is constructed using a one-hot encoding method.

[0019] In one embodiment, the method further includes: in response to a read operation of message data for a second message type, determining a first header pointer corresponding to the second message type; wherein different preset message types correspond to different header pointers, and each header pointer points to a third buffer unit storing the second message data to be read corresponding to the second message type; and reading the second message data from the third buffer unit pointed to by the first header pointer.

[0020] In one embodiment, the method further includes: after reading the second message data, sequentially traversing the other cache units in the target cache space except for the third cache unit, until the fourth cache unit storing the message data of the second message type is determined; and updating the first head pointer to point to the fourth cache unit.

[0021] In one embodiment, the method further includes: periodically counting the number of free cache units in the target cache space; determining the size of the remaining credit cache space based on the size of the free cache units; and notifying the sending device of the size of the remaining credit cache space.

[0022] In one embodiment, the size of each cache unit in the target cache space is determined according to the amount of data corresponding to the message data of each preset message type.

[0023] In one embodiment, the size of each cache unit in the target cache space is two bytes.

[0024] In one embodiment, the cache units in the target cache space are arranged in a ring-shaped continuous distribution to form a ring-shaped target cache space.

[0025] In one embodiment, before receiving the first message data sent by the sending device, the method further includes: determining the reference credit buffer size corresponding to the message data of each preset message type; sending each reference credit buffer size to the sending device; wherein, each reference credit buffer size is used for the sending device to determine the amount of data to send for each preset message type.

[0026] In one embodiment, the message data of various preset message types includes at least PH message data, PD message data, NPH message data, NPD message data, CPLH message data, and CPLD message data.

[0027] Secondly, this application also provides a data caching device for a receiving end device; the device includes:

[0028] The data receiving module is used to receive the first message data sent by the sending device through the PCIe bus and determine the first message type of the first message data;

[0029] The unit determination module is used to determine an idle first cache unit from the target cache space if the first message type is one of a variety of preset message types; the target cache space is a cache space shared by message data of a variety of preset message types.

[0030] The data storage module is used to store the first message data into the first buffer unit;

[0031] The size of the target cache space is determined based on the reference credit cache size corresponding to the message data of each preset message type. The reference credit cache size corresponding to the message data of the preset message type represents the cache space required when the transmission links between the receiving device and the sending device both transmit message data of the preset message type.

[0032] In one embodiment, the device further includes a space determination module, configured to: obtain the maximum reference credit cache among the reference credit cache sizes corresponding to the message data of each preset message type; and use the maximum reference credit cache as the space size of the target cache space.

[0033] In one embodiment, the unit determination module is specifically used to: determine a first cache unit from the target cache space based on the first message type.

[0034] In one embodiment, the unit determination module is specifically used to: determine the first tail pointer corresponding to the first message type; wherein, different preset message types correspond to different tail pointers, and each tail pointer points to an idle buffer unit that can store message data of the corresponding preset message type; and the buffer unit pointed to by the first tail pointer is used as the first buffer unit.

[0035] In one embodiment, the device further includes a tail pointer update module, configured to: after storing the first message data into the first cache unit, determine a free second cache unit from the target cache space; and update the first tail pointer to point to the second cache unit.

[0036] In one embodiment, the tail pointer update module is specifically used to: sequentially traverse the other cache units in the target cache space except for the first cache unit, until a free second cache unit is determined from the other cache units.

[0037] In one embodiment, the tail pointer update module is specifically used to: obtain the flag value of the flag bit of each cache unit being traversed in sequence during the process of traversing other cache units. The flag value is used to indicate whether the corresponding cache unit is free. If the flag value of the flag bit of the currently traversed cache unit indicates that it is free, then the currently traversed cache unit is used as the second cache unit.

[0038] In one embodiment, the flag value is also used to indicate the message type of the message data occupying the corresponding cache unit when the corresponding cache unit is not idle.

[0039] In one embodiment, the apparatus further includes a flag update module, configured to: update the flag value of the first cache unit after storing the first message data into the first cache unit; wherein the updated flag value is used to indicate that the first cache unit is not idle and that the first cache unit is occupied by message data of the first message type.

[0040] In one embodiment, the flag bit is constructed using a one-hot encoding method.

[0041] In one embodiment, the device further includes a reading module, configured to: determine a first header pointer corresponding to the second message type in response to a reading operation of message data for the second message type; wherein different preset message types correspond to different header pointers, and each header pointer points to a third buffer unit storing the second message data to be read corresponding to the second message type; and read the second message data from the third buffer unit pointed to by the first header pointer.

[0042] In one embodiment, the device further includes a pointer update module, configured to: after reading the second message data, sequentially traverse the other cache units in the target cache space except for the third cache unit, until the fourth cache unit storing the message data of the second message type is determined; and update the first head pointer to point to the fourth cache unit.

[0043] In one embodiment, the device further includes a statistics module for: periodically counting the number of free cache units in the target cache space; determining the size of the remaining credit cache space based on the size of the free cache units; and notifying the sending device of the size of the remaining credit cache space.

[0044] In one embodiment, the size of each cache unit in the target cache space is determined according to the amount of data corresponding to the message data of each preset message type.

[0045] In one embodiment, the size of each cache unit in the target cache space is two bytes.

[0046] In one embodiment, the cache units in the target cache space are arranged in a ring-shaped continuous distribution to form a ring-shaped target cache space.

[0047] In one embodiment, the device further includes a synchronization module, configured to: determine the reference credit buffer size corresponding to the message data of each preset message type before receiving the first message data sent by the sending device; and send each reference credit buffer size to the sending device; wherein each reference credit buffer size is used for the sending device to determine the amount of data to send the message data of each preset message type.

[0048] In one embodiment, the message data of various preset message types includes at least PH message data, PD message data, NPH message data, NPD message data, CPLH message data, and CPLD message data.

[0049] Thirdly, this application also provides an electronic device, including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the method described in any of the first aspects above.

[0050] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any one of the first aspects above.

[0051] Fifthly, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the method described in any one of the first aspects above.

[0052] The aforementioned data caching method, apparatus, electronic device, storage medium, and program product involve a receiving device receiving first message data sent by a sending device via a PCIe bus and determining the first message type of the first message data. If the first message type is one of multiple preset message types, an idle first cache unit is determined from the target cache space shared by the message data of the multiple preset message types. The first message data is then stored in the first cache unit. The size of the target cache space is determined based on the reference credit cache size corresponding to the message data of each preset message type. The reference credit cache size corresponding to the message data of each preset message type represents the cache space size required when the transmission links between the receiving device and the sending device both transmit message data of the preset message type. In this way, since the size of the target cache space is determined according to the reference credit cache size corresponding to the message data of each preset message type, in extreme cases, when the link transmits message data of the same message type, the transmitted message data can be successfully stored. In other cases, all message data transmitted by the link can be stored in this shared cache space. Compared with setting a corresponding cache space for each message type, this effectively improves the utilization rate of cache space and avoids redundant waste of memory resources. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a diagram illustrating the application environment of a data caching method in one embodiment.

[0055] Figure 2 This is a flowchart illustrating a data caching method in one embodiment;

[0056] Figure 3 This is a schematic diagram of the PCIe architecture in one embodiment;

[0057] Figure 4 This is a schematic diagram of the PCIe path in one embodiment;

[0058] Figure 5 This is a schematic diagram of the process for notifying the remaining credit cache space size in one embodiment;

[0059] Figure 6 This is a schematic diagram of a circular target cache space in one embodiment;

[0060] Figure 7This is a schematic diagram of the tail pointer distribution in one embodiment;

[0061] Figure 8 This is a schematic diagram of the process of reading message data in one embodiment;

[0062] Figure 9 This is a schematic diagram of the head pointer distribution in one embodiment;

[0063] Figure 10 This is a structural block diagram of a data caching device in one embodiment;

[0064] Figure 11 This is a diagram of the internal structure of an electronic device in one embodiment. Detailed Implementation

[0065] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that many specific details are set forth in the following description in order to provide a full understanding of this application, but this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0067] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, first data may be referred to as second data, and similarly, second data may be referred to as first data. Both first data and second data are data, but they are not the same data.

[0068] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0069] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0070] As modern computer systems increasingly demand higher performance and lower power consumption, PCIe, as a high-bandwidth, low-latency interface standard, is widely used in various computer systems.

[0071] In earlier versions of PCIe, the sending end did not know whether the receiving end could receive the corresponding TLP (Transaction Layer Packets) at the current moment. Therefore, the sending end could only attempt to send. However, during this process, multiple waiting cycles might be inserted due to reasons such as the receiving device not being ready, or even retries might occur. With the evolution of the PCIe bus, including the increased demands for data rates and transmission bandwidth, these problems have severely impacted the bus's bandwidth performance.

[0072] In related technologies, the receiving end informs the sending end of the remaining buffer space for various types of message data. Therefore, the sending end can know whether the receiving end can receive the message data to be sent before sending. The receiving end reserves a corresponding buffer space for each type of message data. However, in reality, due to the uneven distribution of data packet types in the link, the buffer space for each type of message data is only filled in extreme cases. Therefore, in most cases, other buffer spaces are inevitably idle, leading to low overall utilization of the receiving end's buffer space and resulting in a significant waste of redundant memory resources.

[0073] In view of this, embodiments of this application provide a data caching method that can improve the utilization rate of the cache space at the receiving end and avoid causing a large amount of redundant waste of memory resources.

[0074] The data caching method provided in this application embodiment can be applied to, for example... Figure 1In the application environment shown, the sending device 101 communicates with the receiving device 102 via a PCIe bus. Both the sending device 101 and the receiving device 102 are PCIe devices. The sending device 101 and the receiving device 102 can be electronic devices; or they can be processing components within an electronic device, such as the sending device 101 being a central processing unit (CPU) and the receiving device 102 being a graphics card. This is not a complete example. Electronic devices can be, but are not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices, etc., and are not a complete example. The sending device 101 sends first message data to the receiving device 102 via the PCIe bus. The receiving device receives the first message data and determines the first message type. If the first message type is one of several preset message types, it determines an available first cache unit from the target cache space and stores the first message data in the first cache unit.

[0075] In one embodiment, such as Figure 2 As shown, a data caching method is provided. This embodiment illustrates the application of this method to a receiving device 102. In this embodiment, the method includes the following steps:

[0076] Step 201: Receive the first message data sent by the sending device through the PCIe bus, and determine the first message type of the first message data.

[0077] In an optional embodiment of this application, the first message data can be a TLP data packet. TLP types are divided into three categories: P (Posted Request) messages, NP (Non-Posted Request) messages, and CPL (Completion) messages.

[0078] Optionally, the receiving device parses the first message data, extracts the identifier field from the parsing result, and determines the message type of the first message data by looking up the identifier field in a table, thus obtaining the first message type.

[0079] Step 202: If the first message type is one of a variety of preset message types, then determine the free first cache unit from the target cache space.

[0080] In optional embodiments of this application, various preset message types are, for example, various TLP types.

[0081] The target cache space is a shared cache space for message data of multiple preset message types. Therefore, when it is determined that the first message type is one of the multiple preset message types, the first message data can be stored in the target cache space. Specifically, it can be stored in the first cache unit.

[0082] The target cache space is divided into multiple cache units. A free cache unit can be selected as the first cache unit. Optionally, all cache units have the same size.

[0083] In this embodiment of the application, the size of the target cache space is determined according to the reference credit cache size corresponding to the message data of each preset message type.

[0084] The reference credit buffer size corresponding to the message data of the preset message type represents the buffer space required when the transmission link between the receiving device and the sending device transmits message data of the preset message type.

[0085] In other words, the reference credit cache size for each preset message type is determined based on the PCIe path latency. For example, Figure 3 The diagram illustrates an existing PCIe architecture, where device A is the sending device and device B is the receiving device. P, NP, and CPL messages are all TPL type message data. Based on this, such as... Figure 4 The diagram illustrates a PCIe path, where latency comprises three main components: the internal latency of the sending device, the path latency between the sending and receiving devices, and the internal latency of the receiving device. Typically, to ensure PCIe transmission and reception performance, various message types must be able to be transmitted continuously back-to-back. Therefore, when calculating the reference credit buffer size for each preset message type, the PCIe receiver must ensure that the amount of message data that the reference credit buffer can hold covers at least the entire transmission link; that is, at least for the entire path's latency time, it must guarantee that the sending end can transmit data uninterruptedly. Under this basic principle, resources need to be reserved to account for a path consisting entirely of messages of a certain type.

[0086] Based on this, the embodiments of this application determine the maximum credit cache space required for each preset message type according to the PCIe path delay, which serves as the reference credit cache size for the message data of each preset message type. Then, the target cache space size is determined according to the reference credit cache size. In this way, while the message data of each preset message type share the cache space, it can be ensured that even in extreme cases, when the amount of data transmitted in the path delay is the largest, the receiving device can still receive and store these message data.

[0087] Step 203: Store the first message data into the first buffer unit.

[0088] In the aforementioned data caching method, the receiving device receives first message data sent by the sending device via the PCIe bus and determines the first message type of the first message data. If the first message type is one of multiple preset message types, an idle first cache unit is determined from the target cache space shared by the message data of the multiple preset message types. The first message data is then stored in the first cache unit. The size of the target cache space is determined based on the reference credit cache size corresponding to the message data of each preset message type. The reference credit cache size corresponding to the message data of the preset message type represents the cache space size required when the transmission link between the receiving device and the sending device transmits message data of the preset message type. Thus, since the size of the target cache space is determined based on the reference credit cache size corresponding to the message data of each preset message type, in extreme cases where the link transmits message data of the same message type, the transmitted message data can be successfully stored. In other cases, all message data transmitted by the link can be stored in this shared cache space. Compared to setting a corresponding cache space for each message type, this effectively improves cache space utilization and avoids redundant waste of memory resources.

[0089] As mentioned above, in order to ensure that the data sent by the PCIe bus transmitting device does not exceed the receiving device's receiving capacity, and to avoid triggering data retransmissions that reduce data output efficiency or data overflow that leads to data loss, the PCIe protocol provides a flow control (FC) method to improve the data transmission efficiency of the PCIe bus.

[0090] PCIe bus flow control uses a credit-based principle, coordinated by the transaction layer and data link layer. Flow Control DLLPs are sent between the data link layers of the two ports. During initialization, the receiver informs the sender of the size of the credit buffer space. Before sending, the sender can use the flow control mechanism to determine whether the receiver can receive the message data to be sent.

[0091] In this embodiment of the application, before receiving the first message data sent by the sending device, the method further includes: determining the reference credit buffer size corresponding to the message data of each preset message type, and sending each reference credit buffer size to the sending device.

[0092] The size of each reference credit buffer is used by the sending device to determine the amount of data to send for each preset message type.

[0093] In other words, this allows the sending device to still send message data based on the size of each reference credit buffer during initial transmission, ensuring that the initial data transmission and reception between the sending and receiving devices proceed normally.

[0094] In this way, the initialization algorithm can be used without modification, ensuring that the initial transmission process proceeds normally.

[0095] Understandably, the receiving device can send the size of each reference credit buffer via Flow Control DLLPs.

[0096] As mentioned above, the message data can be TLP message data.

[0097] Specifically, each message type is further divided into header field types and data field types based on whether it stores the message header field or the message data field. That is, the P type is specifically divided into PH (Posted request Header) for the message header field and PD (Posted request Data) for the data field; similarly, the NP type is divided into NPH and NPD, and the CPL type is divided into CPLH and CPLD.

[0098] Therefore, in the optional embodiments of this application, the message data of various preset message types include at least PH message data, PD message data, NPH message data, NPD message data, CPLH message data, and CPLD message data.

[0099] Furthermore, in this embodiment of the application, during the subsequent continuous data transmission between the two parties, the receiving end needs to periodically notify the sending end of its own buffer space size, so that the sending end device can use this as a reference to send message data.

[0100] In one embodiment, such as Figure 5 A flowchart illustrating the notification of remaining credit cache space size is shown, and the method further includes:

[0101] Step 501: Periodically count the number of free cache units in the target cache space.

[0102] Step 502: Determine the remaining credit cache space size based on the size of the free cache units.

[0103] Optionally, during each statistical process, if the space size of each cache unit is the same, the receiving device can count the number of idle cache units and obtain the space size of each cache unit that has been recorded in advance. The two are multiplied together to obtain the space size of the remaining credit cache space.

[0104] Optionally, when the space size of each cache unit is different, the receiving device pre-records the correspondence between the space size and the sequence number of each cache unit. During each statistical process, the sequence number of the idle cache unit is counted, the corresponding space size is obtained according to the sequence number, and the space sizes of each space are added together to obtain the space size of the remaining credit cache space.

[0105] The remaining credit cache space can also be determined in other ways, which are not fully illustrated here.

[0106] Step 503: Notify the sending device of the remaining credit cache space size.

[0107] Alternatively, similarly, the size of the remaining credit cache space can be sent to the receiving end via Flow Control DLLPs.

[0108] In this way, during normal operation, the sending device can use the Flow Control mechanism to know whether the receiving device can receive the message data to be sent before sending, thus ensuring the reliability of the data transmission process.

[0109] The following explains how to determine the target cache space and the size of the cache unit.

[0110] In one embodiment, the method further includes: obtaining the maximum reference credit cache size among the reference credit cache sizes corresponding to the message data of each preset message type; and using the maximum reference credit cache size as the target cache space size.

[0111] In other words, the sizes of each reference credit cache are compared to obtain the maximum value, i.e., the maximum reference credit cache, and thus the size of the target cache space is determined. The target cache space of the receiving end is configured accordingly.

[0112] Taking the TPL message of various preset message types as an example, assuming a total path delay of 1µs and a link width of X8 and a Gen5 rate (ignoring losses, etc.), the reference credit buffer size corresponding to the message data in the data field is 1000ns * 8 * 4B = 32KB. Here, the data volume of the message data in the data field is in 4DW granularity. When each header only sends 3DW of data, the required space is 32KB. However, considering the actual sending of Gen6 data larger than 3DW, a header may have 15DW. To ensure that this message data can be received, the required space is 160KB. Therefore, the maximum required space is 160KB, that is, the target buffer space size in this example is 160KB.

[0113] In this way, the maximum value among the buffer sizes calculated to meet the coverage path delay of various types of message data is selected, ensuring that data transmitted through the link can be successfully received and stored even in extreme cases.

[0114] In one possible implementation, the target cache space is evenly distributed according to the number of cache units to obtain the cache space for each cache unit.

[0115] In addition, in order to maximize the utilization of the target cache space, in another possible implementation, the size of each cache unit in the target cache space is determined according to the amount of data corresponding to the message data of each preset message type.

[0116] In an optional embodiment of this application, the size of each cache unit in the target cache space is determined according to the greatest common divisor of the data volume corresponding to the message data of each preset message type.

[0117] For example, in the example above, there are data volumes of 3DW, 4DW, and 15DW. The greatest common divisor is DW, which is two bytes.

[0118] Therefore, optionally, the size of each cache unit in the target cache space is two bytes.

[0119] This ensures that each cache unit is fully filled when used, with no remaining space, maximizing the use of cache space in each cache unit and further avoiding wasted cache space.

[0120] In one alternative implementation, the cache units in the target cache space are distributed in a ring-shaped continuous manner, forming a ring-shaped target cache space.

[0121] For example, cache units are arranged sequentially, each with a corresponding index, and these units are arranged in a circular pattern according to their indexes to form the target cache space. Optionally, the cache addresses of two adjacent cache units are contiguous. For example, ... Figure 6 A schematic diagram of a ring-shaped target cache space is shown.

[0122] This allows data to be stored in contiguous memory blocks, resulting in high access efficiency. It is especially suitable for scenarios requiring fast read and write speeds (such as real-time data processing), eliminating the need for complex memory operations and facilitating system resource planning and optimization.

[0123] In another alternative implementation, the cache units in the target cache space are arranged in a continuous stripe pattern to form the target cache space.

[0124] That is, the first cache space and the last cache space are not adjacent.

[0125] This increases the flexibility of the receiving device in configuring the target buffer space format.

[0126] The process of storing the first message data is explained below.

[0127] In one embodiment, determining a free first cache unit from a target cache space includes: determining a first cache unit from the target cache space based on a first message type.

[0128] Here, the first cache unit refers to the cache unit currently available for storing the first message data. The location of the cache unit currently available for storing the corresponding message data may be different for different preset message types. Therefore, in order to improve the efficiency of determining the first cache unit, the first cache unit can be determined from the target cache space according to the first message type.

[0129] In one embodiment, determining a first cache unit from a target cache space based on a first message type includes: determining a first tail pointer corresponding to the first message type, and using the cache unit pointed to by the first tail pointer as the first cache unit.

[0130] Different preset message types correspond to different tail pointers, and each tail pointer points to a free buffer unit that can store message data of the corresponding preset message type. Taking a circular buffer unit as an example... Figure 7 A schematic diagram of the tail pointer distribution is shown, which includes cache units with serial numbers starting from 0 and N.

[0131] In an optional embodiment of this application, the tail pointer can point to the tail address of the cache unit, or it can point to the sequence number of the cache unit. This is sufficient to determine the cache unit.

[0132] In an optional embodiment of this application, the first cache unit is a single cache unit.

[0133] Alternatively, the first cache unit may comprise a contiguous set of free cache units starting from the first cache unit pointed to by the first tail pointer. The total cache space of these contiguous free cache units is equal to the data size of the first message, thus ensuring that the first message data is successfully stored. For example, if the cache unit size is DW and the first message data size is 3DW, three cache units are required. When the first tail pointer points to cache unit 10, the determined first cache unit includes cache unit 10, cache unit 11, and cache unit 12.

[0134] Optionally, in one possible implementation, after receiving the first message data, the required number of buffer units K is determined based on the data volume of the first message data. Then, starting from the buffer unit pointed to by the first tail pointer, K consecutive free buffer units are determined as the first buffer units. It is understood that the sequence numbers of the multiple first buffer units may not be consecutive, but they are consecutive among all free buffer units. For example, in the above example, if buffer unit 12 is occupied, then the determined consecutive free first buffer units include buffer unit 10, buffer unit 11, and buffer unit 13.

[0135] Optionally, there may be a situation where two tail pointers point to the same cache unit. In this case, when the cache unit is occupied, both tail pointers are updated to point to the next free cache unit.

[0136] In one embodiment, the method further includes: after storing the first message data into the first buffer unit, determining a free second buffer unit from the target buffer space, and updating the first tail pointer to point to the second buffer unit.

[0137] In this way, when the first message type is received again, the second buffer unit can be quickly determined directly based on the updated first tail pointer. Here, the second buffer unit can be a single, free buffer unit.

[0138] In one embodiment, determining a free second cache unit from the target cache space includes: sequentially traversing the other cache units in the target cache space except for the first cache unit until a free second cache unit is determined from the other cache units.

[0139] Taking a circular target cache space as an example, the sequential traversal can be clockwise or counterclockwise. Taking a striped target cache space as an example, the sequential traversal can be from beginning to end or from end to beginning.

[0140] In one embodiment, sequentially traversing other cache units in the target cache space except for the first cache unit until a free second cache unit is determined from the other cache units includes: obtaining the flag value of the flag bit of each traversed cache unit during the sequential traversal of other cache units; if the flag value of the flag bit of the currently traversed cache unit indicates that it is free, then the currently traversed cache unit is taken as the second cache unit.

[0141] The flag value indicates whether the corresponding cache unit is idle. This allows for quick determination of the storage status of each cache unit based on the flag value, improving data storage efficiency.

[0142] In another embodiment, determining a first cache unit from the target cache space according to a first message type includes: determining a first tail pointer corresponding to the first message type; sequentially traversing other cache units after the cache unit pointed to by the first tail pointer until a free cache unit is determined as the first cache unit.

[0143] Different preset message types correspond to different tail pointers, and each tail pointer points to a buffer unit that stores the message data of the corresponding preset message type that was previously received, for example, pointing to the position of the last data block in that buffer unit. That is, the first tail pointer points to the buffer unit that stores the message data of the first message type that was previously received.

[0144] Accordingly, after storing the first message data into the first buffer unit, the first tail pointer is updated to point to the first buffer unit.

[0145] For example, update the first tail pointer to point to the last data block of the first cache unit.

[0146] This allows for flexible use of the tail pointer and ensures that message data is written efficiently.

[0147] In one embodiment, the flag value is used not only to indicate whether the corresponding buffer unit is idle, but also to indicate the type of message data occupying the corresponding buffer unit when the corresponding buffer unit is not idle.

[0148] Optionally, the flag bits are constructed using one-hot encoding. For example, a 6-bit flag bit.

[0149] For example, a flag of "000000" represents empty (the cache unit is free); the value of each of the other bits is '1', indicating that it is occupied by a certain type of TLP, for example:

[0150] 000000: Empty, not used;

[0151] 000001: PH (Posted Header) is occupied;

[0152] 000010: PD (Posted Data) in use;

[0153] 000100: NPH (Non-Posted Header) occupied;

[0154] 001000: NPD (Non-Posted Data) occupies;

[0155] 010000: CplH (Completion Header) is occupied;

[0156] 100000: CplD (Completion Data) is occupied.

[0157] In this way, the flag bits enable the receiving device to efficiently identify the storage status of each cache unit, which facilitates data storage and subsequent data retrieval.

[0158] In one embodiment, the method further includes: updating the flag value of the first cache unit after storing the first message data into the first cache unit.

[0159] The updated flag value is used to indicate that the first buffer unit is not idle and that the first buffer unit is occupied by message data of the first message type.

[0160] For example, if the first message data is PH message data, then after the first buffer unit writes the first message data, the flag value of its flag bit is updated from "000000" to "000001".

[0161] In one embodiment, such as Figure 8 The flowchart illustrating the process of reading message data is shown. The method also includes:

[0162] Step 801: In response to the read operation of message data for the second message type, determine the first header pointer corresponding to the second message type.

[0163] Different preset message types correspond to different header pointers, and each header pointer points to a third buffer unit that stores the second message data to be read corresponding to the second message type. Taking a circular buffer unit as an example... Figure 9 A schematic diagram of the head pointer distribution is shown.

[0164] Step 802: Read the second message data from the third buffer unit pointed to by the first head pointer.

[0165] In one embodiment, the method further includes:

[0166] After reading the second message data, the other cache units in the target cache space except for the third cache unit are traversed in sequence until the fourth cache unit storing the message data of the second message type is determined, and the first head pointer is updated to point to the fourth cache unit.

[0167] Optionally, as described above, the fourth buffer unit can be determined by the flag value of the flag bit to determine whether other buffer units are buffer units storing message data of the second message type.

[0168] Optionally, the head pointer can point to a cache unit, for example, the starting address of that cache unit, or its index. This is sufficient to identify the cache unit.

[0169] In this way, when reading message data of the second message type next time, the location of the data to be read can be quickly determined according to the direction of the first head pointer.

[0170] In one embodiment, the method further includes: after reading the second message data, updating the flag value of the third buffer unit.

[0171] The updated flag value is used to indicate that the third cache unit is idle.

[0172] For example, if the second message data is NPH message data, then after the second message data in the third buffer unit is read, the flag value of its flag bit is updated from "000100" to "000000".

[0173] This allows the receiving device to accurately count the currently available buffer units based on the flag value, thereby accurately informing the sending device of the remaining credit buffer space and ensuring that subsequent data is successfully received and stored by the receiving device.

[0174] In one embodiment, the sender stops sending message data when the remaining credit cache space in the target cache space is zero.

[0175] In one embodiment, when the remaining credit cache space of the target cache space changes from zero to non-zero (that is, from all cache units being occupied to at least one cache unit having its message data read and then being released), the current remaining credit cache space size is sent to the sending device so that the sending device can continue to send message data.

[0176] In one embodiment, when the first tail pointer points to a buffer unit storing the previously received message data of the first message type, if the buffer unit pointed to by the head pointer of the same preset message type is located at the next position of the buffer unit pointed to by the tail pointer in the traversal direction, it means that the target buffer space is full of data of that preset message type. At this time, no more data of the same type is written, ensuring that the tail pointer will not exceed the head pointer. In this embodiment, only the head and tail pointers of the same type are compared. The head and tail pointers of different types have no dependency relationship and can be used interchangeably.

[0177] In one embodiment, it can be understood that when the head pointer and tail pointer corresponding to the same preset message type point to the same buffer unit, it means that the target buffer space does not store message data of that type. For example, during the initialization phase.

[0178] For ease of understanding, the data caching method provided in this application will be described below with a complete embodiment.

[0179] Retrieve the maximum reference credit cache size from the reference credit cache sizes corresponding to the message data of each preset message type; use the maximum reference credit cache size as the target cache space size. Each cache unit in the target cache space is two bytes in size. The cache units in the target cache space are arranged in a circular, continuous pattern, forming a circular target cache space.

[0180] The size of each reference credit buffer is sent to the sending device; wherein, the size of each reference credit buffer is used by the sending device to determine the amount of data to be sent for each preset message type.

[0181] The system receives first message data sent by the transmitting device via the PCIe bus and determines the first message type. It then determines the first tail pointer corresponding to the first message type; different preset message types correspond to different tail pointers, each pointing to a buffer unit that stores the previously received message data of the corresponding preset message type. The system sequentially traverses the buffer units following the one pointed to by the first tail pointer until a free buffer unit is identified, which is then used as the first buffer unit. After storing the first message data in the first buffer unit, the first tail pointer is updated to point to the first buffer unit. Alternatively, determine the first tail pointer corresponding to the first message type; wherein different preset message types correspond to different tail pointers, and each tail pointer points to a free buffer unit that can store message data of the corresponding preset message type; use the buffer unit pointed to by the first tail pointer as the first buffer unit; after storing the first message data into the first buffer unit, sequentially traverse other buffer units in the target buffer space except for the first buffer unit until a free second buffer unit is determined from the other buffer units; update the first tail pointer to point to the second buffer unit; during the sequential traversal of other buffer units, obtain the flag value of the flag bit of each traversed buffer unit, the flag value is used to indicate whether the corresponding buffer unit is free; if the flag value of the flag bit of the currently traversed buffer unit indicates that it is free, then use the currently traversed buffer unit as the second buffer unit; after storing the first message data into the first buffer unit, update the flag value of the first buffer unit to indicate that the first buffer unit is not free and the first buffer unit is occupied by message data of the first message type.

[0182] Periodically count the number of free cache units in the target cache space; determine the size of the remaining credit cache space based on the size of the free cache units; and notify the sending device of the size of the remaining credit cache space.

[0183] In response to a read operation of message data for the second message type, a first header pointer corresponding to the second message type is determined; different preset message types correspond to different header pointers, and each header pointer points to a third buffer unit that stores the second message data to be read corresponding to the second message type; after reading the second message data from the third buffer unit pointed to by the first header pointer, the other buffer units in the target buffer space except the third buffer unit are traversed in sequence until the fourth buffer unit that stores the message data of the second message type is determined; the first header pointer is updated to point to the fourth buffer unit.

[0184] This method integrates PH, PD, NPH, NPD, CPLH, and CplD caches, sharing a single credit cache space. By proposing a novel shared cache size and its calculation method, it aims to improve the utilization of the receiver's data cache and reduce the number of redundant caches.

[0185] This method is highly versatile and can significantly reduce the number of caches. Continuing with the aforementioned 1µs path latency example: Simplifying the scenario and disregarding overhead, reserving resources only for the largest cache size among the six cache types, 160KB / ((160KB+32)*3) = 30%; due to the added flag bit in the shared logic and additional control logic (considering a 20% overhead), calculated as (32+6) / 32 *1.2 = 1.425, after adding the shared resource overhead to the 30% figure, 30% * 1.425 = 42.75%. Therefore, compared to the traditional Credit resource reservation method, this method can significantly reduce the size of the PCIe receiver's Creditbuffer cache, even considering the additional overhead, still resulting in a resource saving benefit of over 50%.

[0186] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0187] Based on the same inventive concept, this application also provides a data caching device for implementing the data caching method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more data caching device embodiments provided below can be found in the limitations of the data caching method described above, and will not be repeated here.

[0188] In one embodiment, such as Figure 10 As shown, a data caching device 1000 is provided, including: a data receiving module, a unit determining module, and a data storage module, wherein:

[0189] The data receiving module 1001 is used to receive first message data sent by the sending device through the PCIe bus and determine the first message type of the first message data;

[0190] The unit determination module 1002 is used to determine an idle first cache unit from the target cache space if the first message type is one of a variety of preset message types; the target cache space is a cache space shared by message data of a variety of preset message types.

[0191] Data storage module 1003 is used to store the first message data into the first buffer unit;

[0192] The size of the target cache space is determined based on the reference credit cache size corresponding to the message data of each preset message type. The reference credit cache size corresponding to the message data of the preset message type represents the cache space required when the transmission links between the receiving device and the sending device both transmit message data of the preset message type.

[0193] In one embodiment, the device further includes a space determination module, configured to: obtain the maximum reference credit cache among the reference credit cache sizes corresponding to the message data of each preset message type; and use the maximum reference credit cache as the space size of the target cache space.

[0194] In one embodiment, the unit determination module is specifically used to: determine a first cache unit from the target cache space based on the first message type.

[0195] In one embodiment, the unit determination module is specifically used to: determine the first tail pointer corresponding to the first message type; wherein, different preset message types correspond to different tail pointers, and each tail pointer points to an idle buffer unit that can store message data of the corresponding preset message type; and the buffer unit pointed to by the first tail pointer is used as the first buffer unit.

[0196] In one embodiment, the device further includes a tail pointer update module, configured to: after storing the first message data into the first cache unit, determine a free second cache unit from the target cache space; and update the first tail pointer to point to the second cache unit.

[0197] In one embodiment, the tail pointer update module is specifically used to: sequentially traverse the other cache units in the target cache space except for the first cache unit, until a free second cache unit is determined from the other cache units.

[0198] In one embodiment, the tail pointer update module is specifically used to: obtain the flag value of the flag bit of each cache unit being traversed in sequence during the process of traversing other cache units. The flag value is used to indicate whether the corresponding cache unit is free. If the flag value of the flag bit of the currently traversed cache unit indicates that it is free, then the currently traversed cache unit is used as the second cache unit.

[0199] In one embodiment, the flag value is also used to indicate the message type of the message data occupying the corresponding cache unit when the corresponding cache unit is not idle.

[0200] In one embodiment, the apparatus further includes a flag update module, configured to: update the flag value of the first cache unit after storing the first message data into the first cache unit; wherein the updated flag value is used to indicate that the first cache unit is not idle and that the first cache unit is occupied by message data of the first message type.

[0201] In one embodiment, the flag bit is constructed using a one-hot encoding method.

[0202] In one embodiment, the device further includes a reading module, configured to: determine a first header pointer corresponding to the second message type in response to a reading operation of message data for the second message type; wherein different preset message types correspond to different header pointers, and each header pointer points to a third buffer unit storing the second message data to be read corresponding to the second message type; and read the second message data from the third buffer unit pointed to by the first header pointer.

[0203] In one embodiment, the device further includes a pointer update module, configured to: after reading the second message data, sequentially traverse the other cache units in the target cache space except for the third cache unit, until the fourth cache unit storing the message data of the second message type is determined; and update the first head pointer to point to the fourth cache unit.

[0204] In one embodiment, the device further includes a statistics module for: periodically counting the number of free cache units in the target cache space; determining the size of the remaining credit cache space based on the size of the free cache units; and notifying the sending device of the size of the remaining credit cache space.

[0205] In one embodiment, the size of each cache unit in the target cache space is determined according to the amount of data corresponding to the message data of each preset message type.

[0206] In one embodiment, the size of each cache unit in the target cache space is two bytes.

[0207] In one embodiment, the cache units in the target cache space are arranged in a ring-shaped continuous distribution to form a ring-shaped target cache space.

[0208] In one embodiment, the device further includes a synchronization module, configured to: determine the reference credit buffer size corresponding to the message data of each preset message type before receiving the first message data sent by the sending device; and send each reference credit buffer size to the sending device; wherein each reference credit buffer size is used for the sending device to determine the amount of data to send the message data of each preset message type.

[0209] In one embodiment, the message data of various preset message types includes at least PH message data, PD message data, NPH message data, NPD message data, CPLH message data, and CPLD message data.

[0210] Each module in the aforementioned data caching device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of the electronic device in hardware form or independent of it, or stored in the memory of the electronic device in software form, so that the processor can call and execute the operations corresponding to each module.

[0211] In one exemplary embodiment, an electronic device is provided, the internal structure of which can be as shown in the figure. Figure 11As shown, this electronic device includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage medium. The input / output interface is used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a data caching method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the electronic device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the electronic device, or external keyboards, touchpads, or mice, etc.

[0212] Those skilled in the art will understand that Figure 11 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the electronic device to which the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0213] In one embodiment, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0214] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0215] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0216] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0217] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0218] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A data caching method, characterized in that, For use in a receiving device; the method includes: Receive the first message data sent by the sending device through the PCIe bus, and determine the first message type of the first message data; If the first message type is one of a variety of preset message types, then a free first cache unit is determined from the target cache space; the target cache space is a cache space shared by message data of the various preset message types. Store the first message data into the first cache unit; The size of the target cache space is determined based on the reference credit cache size corresponding to the message data of each preset message type. The reference credit cache size corresponding to the message data of each preset message type represents the cache space required when the transmission links between the receiving device and the sending device both transmit message data of the preset message type.

2. The method according to claim 1, characterized in that, The method further includes: Obtain the maximum reference credit cache size from the reference credit cache sizes corresponding to the message data of each preset message type; The maximum reference credit cache is used as the size of the target cache space.

3. The method according to claim 1, characterized in that, The step of determining the first free cache unit from the target cache space includes: The first cache unit is determined from the target cache space based on the first message type.

4. The method according to claim 3, characterized in that, The step of determining the first cache unit from the target cache space according to the first message type includes: Determine the first tail pointer corresponding to the first message type; wherein, different preset message types correspond to different tail pointers, and each tail pointer points to a buffer unit that stores the message data of the previously received corresponding preset message type; The process proceeds sequentially through the cache units following the first cache unit pointed to by the first tail pointer until a free cache unit is identified, which is then used as the first cache unit.

5. The method according to claim 4, characterized in that, The method further includes: After storing the first message data in the first cache unit, the first tail pointer is updated to point to the first cache unit.

6. The method according to claim 3, characterized in that, The step of determining the first cache unit from the target cache space according to the first message type includes: Determine the first tail pointer corresponding to the first message type; wherein, different preset message types correspond to different tail pointers, and each tail pointer points to a free buffer unit that can store message data of the corresponding preset message type; The cache unit pointed to by the first tail pointer is used as the first cache unit.

7. The method according to claim 6, characterized in that, The method further includes: After storing the first message data into the first cache unit, a free second cache unit is determined from the target cache space; Update the first tail pointer to point to the second cache unit.

8. The method according to claim 7, characterized in that, The step of determining a free second cache unit from the target cache space includes: The process proceeds sequentially through all cache units in the target cache space except for the first cache unit until a free second cache unit is identified from among the other cache units.

9. The method according to claim 8, characterized in that, The step of sequentially traversing the other cache units in the target cache space besides the first cache unit until a free second cache unit is determined from the other cache units includes: During the sequential traversal of the other cache units, the flag value of the flag bit of each traversed cache unit is obtained, and the flag value is used to indicate whether the corresponding cache unit is idle. If the flag value of the currently traversed cache unit indicates that it is free, then the currently traversed cache unit will be used as the second cache unit.

10. The method according to claim 9, characterized in that, The flag value is also used to indicate the message type of the message data occupying the corresponding cache unit when the corresponding cache unit is not idle.

11. The method according to claim 10, characterized in that, The method further includes: After storing the first message data into the first cache unit, update the flag value of the first cache unit; The updated flag value is used to indicate that the first cache unit is not idle and that the first cache unit is occupied by message data of the first message type.

12. The method according to claim 9, characterized in that, The flag bits are constructed using a one-hot encoding method.

13. The method according to any one of claims 1 to 12, characterized in that, The method further includes: In response to a read operation of message data for a second message type, a first header pointer corresponding to the second message type is determined; wherein, different preset message types correspond to different header pointers, and each header pointer points to a third buffer unit storing the second message data to be read corresponding to the second message type; Read the second message data from the third buffer unit pointed to by the first head pointer.

14. The method according to claim 13, characterized in that, The method further includes: After reading the second message data, the other cache units in the target cache space, except for the third cache unit, are traversed in sequence until the fourth cache unit storing the message data of the second message type is determined. Update the first head pointer to point to the fourth cache unit.

15. The method according to any one of claims 1 to 12, characterized in that, The method further includes: Periodically count the free cache units in the target cache space; Determine the remaining credit cache space size based on the size of the free cache units; The sending device is notified of the remaining credit cache space size.

16. The method according to any one of claims 1 to 12, characterized in that, The size of each cache unit in the target cache space is determined according to the amount of data corresponding to the message data of each preset message type.

17. The method according to claim 16, characterized in that, The size of each cache unit in the target cache space is two bytes.

18. The method according to any one of claims 1 to 12, characterized in that, The cache units in the target cache space are arranged in a ring-shaped continuous distribution, forming the ring-shaped target cache space.

19. The method according to any one of claims 1 to 12, characterized in that, Before receiving the first message data sent by the sending device, the method further includes: Determine the reference credit cache size corresponding to the message data of each of the preset message types; The size of each of the aforementioned reference credit caches is sent to the sending device; The reference credit buffer size is used by the sending device to determine the amount of data to send for each of the preset message types.

20. A data caching device, characterized in that, For receiving end equipment; the device includes: The data receiving module is used to receive first message data sent by the sending device through the PCIe bus, and to determine the first message type of the first message data; The unit determination module is used to determine an idle first cache unit from the target cache space if the first message type is one of a variety of preset message types; the target cache space is a cache space shared by message data of the various preset message types. The data storage module is used to store the first message data into the first cache unit; The size of the target cache space is determined based on the reference credit cache size corresponding to the message data of each preset message type. The reference credit cache size corresponding to the message data of each preset message type represents the cache space required when the transmission links between the receiving device and the sending device both transmit message data of the preset message type.

21. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 19.

22. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 19.

23. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 19.

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