Computing power scheduling method and device, communication equipment, medium and product

Abstract

The invention provides a computing power scheduling method and device, communication equipment, a medium and a product, and the method comprises the steps: carrying out the data preprocessing and topology awareness of a computing task, and obtaining a computing graph of the computing task; performing sub-graph division on the calculation graph to obtain calculation sub-graphs, and packaging the calculation sub-graphs into schedulable units; the calculation benefit of the schedulable unit is obtained by determining the execution delay, the power consumption and the heterogeneous coefficient of the calculation nodes which distribute the schedulable unit to different areas; constructing a task scheduling model meeting a service level target according to a maximum and minimum algorithm and the calculation benefit; the optimal allocation of the schedulable units on the computing nodes is determined through the task scheduling model, the schedulable units are scheduled to the computing nodes in parallel according to the optimal allocation, large computing tasks can be scheduled to a proper area according to delay and power consumption, the problem of hardware resource heterogeneity in the scheduling process can be solved, and the scheduling efficiency is improved. And the total power consumption of the whole task is reduced through refined scheduling.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of data processing, and in particular to a computing power scheduling method and device, a communication device, a medium and a product. BACKGROUND

[0002] In recent years, with the promotion of the national "East Number West Algorithm" project, cross-regional resource scheduling systems have received widespread attention and play a key role in achieving optimal resource allocation, improving energy efficiency, and promoting regional collaboration. Currently, the cross-domain computing power scheduling scheme is directly aimed at the entire task, matching the most suitable region for computing. Moreover, the current cross-regional resource scheduling system is still in the early stages of exploration. There are significant differences in application load between regions, and the mainstream application request and call link is dynamic and complex, with complex task interaction and correlation. Cross-domain task scheduling will cause unstable performance of the application and its chain reaction, leading to potential Service Level Agreement (SLA) constraint violation risks. SUMMARY

[0003] The first aspect of the present disclosure proposes a computing power scheduling method, which comprises: data preprocessing and topology perception of a computing task to obtain a computing graph of the computing task; subgraph division of the computing graph to obtain a computing subgraph, and packaging the computing subgraph into a schedulable unit; obtaining the computing benefit of the schedulable unit by determining the delay, power consumption and heterogeneous coefficient of the schedulable unit when distributed to different regional computing nodes for execution; constructing a task scheduling model that meets the service level target according to the max-min algorithm and the computing benefit, wherein the task scheduling model is used to optimize the distribution of the schedulable unit on the computing nodes by calculating the optimal computing benefit, and the execution time of the schedulable unit meets the preset time window; determining the optimal distribution of the schedulable unit on the computing nodes through the task scheduling model, and scheduling the schedulable unit to the computing nodes in parallel according to the optimal distribution.

[0004] In some embodiments of the present disclosure, the preprocessing and topology awareness of the computing task, and obtaining the topology graph of the computing task include: respectively measuring each operator of the computing task to obtain the computing parameters of each operator, the computing parameters including at least one of computing time, communication volume, required computing power resource, and rated power consumption; numbering all the operators, adding a first entry and a second entry in each operator based on the calling link between the operators, the first entry being a superior operator communicating with the operator, and the second entry being a subordinate operator of the operator; constructing a topology graph according to the first entry and the second entry of all the operators, wherein the vertex of the topology graph represents the operator, the edge of the topology graph represents the calling relationship between the operators, and the weight of the edge represents the data transmission volume between the operators; taking the computing parameters of each operator as the feature data of each vertex in the topology graph to obtain a topology graph with attribute features, and determining the topology graph with attribute features as the computation graph of the computing task.

[0005] In some embodiments of the present disclosure, the subgraph division of the computation graph to obtain the computation subgraph, and the packing of the computation subgraph into a schedulable unit include: determining a critical path in the computation graph according to a critical path algorithm; predicting at least one of the required power consumption, computing power and network delay of the operators included in each subgraph in the computation graph according to historical data to obtain a prediction result; dividing the computation graph into computation subgraphs based on the critical path and the prediction result; and packing the computation subgraphs into schedulable units by quantifying the communication volume and resource utilization between the operators.

[0006] In some embodiments of the present disclosure, the method further includes: performing unsupervised clustering based on the prediction result and the schedulable unit to obtain the sensitivity of the schedulable unit; and assigning a resource sensitivity coefficient to the schedulable unit according to the sensitivity, wherein the resource sensitivity coefficient is used to assist in calculating the delay, power consumption and heterogeneity coefficient of the schedulable unit when the schedulable unit is allocated to different regional computing nodes for execution.

[0007] In some embodiments of the present disclosure, by determining the delay, power consumption and heterogeneity coefficient of the schedulable unit allocated to the computing nodes in different regions, the computing benefit of the schedulable unit is obtained, including: performing merging on the call graph of the schedulable unit, and merging the functions with data transmission greater than a preset value in the schedulable unit execution process into a new subgraph; determining the transmission delay of the subgraph executing on the computing node according to the network delay, execution time and first product, and determining the delay computing benefit of the schedulable unit based on the transmission delay, wherein the first product is the product of the cold start delay and the cold start number; determining the total cost of the subgraph executing on the computing node according to the product of the execution cost difference per unit time between the central processing unit and the graphics processing unit of the computing node and the execution time, and confirming the power consumption computing benefit of the schedulable unit based on the total cost; determining the variation coefficient of the central processing unit and the graphics processing unit according to the performance indicators of the central processing unit and the graphics processing unit, and determining the heterogeneous computing benefit of the schedulable unit based on the variation coefficient; and confirming the computing benefit of the schedulable unit based on the delay computing benefit, the power consumption computing benefit and the heterogeneous computing benefit.

[0008] In some embodiments of the present disclosure, determining the variation coefficient of the central processing unit and the graphics processing unit according to the performance indicators of the central processing unit and the graphics processing unit includes: collecting the performance indicators of the central processing unit and the graphics processing unit of each computing node; determining the computing power of the central processing unit and the graphics processing unit of each computing node according to the performance indicators; determining the average value and the standard deviation of the computing power of the central processing unit and the graphics processing unit according to the computing power of the central processing unit and the graphics processing unit and the number of computing nodes; and determining the variation coefficient of the central processing unit and the graphics processing unit according to the ratio of the average value to the standard deviation.

[0009] The second aspect embodiment of the present disclosure proposes a computing power scheduling device, which comprises: an acquisition module configured to perform data preprocessing and topology perception on a computing task, and to acquire a computing graph of the computing task; a subgraph division model configured to divide the computing graph to obtain a computing subgraph, and to pack the computing subgraph into a schedulable unit; a calculation module configured to obtain the computing benefit of the schedulable unit by determining the delay, power consumption and heterogeneity coefficient of the schedulable unit allocated to the computing nodes in different regions; an optimization module configured to construct a task scheduling model meeting a service level objective according to a maximum-minimum algorithm and the computing benefit, wherein the task scheduling model is used to optimize the allocation of the schedulable unit on the computing nodes by calculating the optimal computing benefit, and the execution time of the schedulable unit meets a preset time window; and a parallel scheduling module configured to determine the optimal allocation of the schedulable unit on the computing nodes by the task scheduling model, and to schedule the schedulable unit to the computing nodes in parallel according to the optimal allocation.

[0010] A third aspect embodiment of the present disclosure provides a communication device, comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the first aspect embodiment of the present disclosure.

[0011] A fourth aspect embodiment of the present disclosure provides a non-transitory computer readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to perform the method described in the first aspect embodiment of the present disclosure.

[0012] A fifth aspect embodiment of the present disclosure provides a computer program product, comprising a computer program, wherein the computer program, when executed by a processor, implements the method described in the first aspect embodiment of the present disclosure.

[0013] In summary, the computing power scheduling method provided by the present disclosure includes data preprocessing and topology perception of a computing task to obtain a computing graph of the computing task; subgraph division of the computing graph to obtain a computing subgraph, and packaging the computing subgraph into a schedulable unit; obtaining computing benefits of the schedulable unit by determining the delay, power consumption and heterogeneous coefficient of the schedulable unit when being executed by computing nodes in different regions; constructing a task scheduling model meeting a service level objective according to a max-min algorithm and the computing benefits, wherein the task scheduling model is used to optimize the allocation of the schedulable unit on the computing nodes by calculating optimal computing benefits, and the execution time of the schedulable unit meets a preset time window; determining the optimal allocation of the schedulable unit on the computing nodes through the task scheduling model, and scheduling the schedulable unit to the computing nodes in parallel according to the optimal allocation, which can schedule large computing tasks to appropriate regions according to the delay and power consumption, and solve the heterogeneous problem of hardware resources in the scheduling process, and fine scheduling reduces the overall power consumption of the entire task.

[0014] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure, and do not constitute an undue limitation on the present disclosure.

[0016] Figure 1 A flowchart of a computing power scheduling method provided by an embodiment of the present disclosure;

[0017] Figure 2 A flowchart of a computing power scheduling method provided by an embodiment of the present disclosure;

[0018] Figure 3 A flowchart example of a computing power scheduling method provided for an embodiment of the present disclosure is shown in FIG. 1.

[0019] Figure 4 A structural schematic diagram of a computing power scheduling device provided for an embodiment of the present disclosure is shown in FIG. 2.

[0020] Figure 5 A hardware composition structural schematic diagram of a communication device provided for an embodiment of the present disclosure is shown in FIG. 3. DETAILED DESCRIPTION

[0021] Embodiments of the present disclosure are described in detail below, examples of which are shown in the accompanying drawings, in which the same or similar reference numbers represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, and cannot be understood as a limitation of the present disclosure.

[0022] First, the technical problems to be solved by the technical solutions of the present disclosure and related technologies are described in detail.

[0023] In recent years, with the promotion of the national "East Number West Algorithm" project, cross-regional resource scheduling systems have received widespread attention and play a key role in achieving resource optimization, improving energy efficiency, and promoting regional cooperation. First, cross-regional resource scheduling systems help achieve optimal resource allocation, and second, cross-regional resource scheduling systems can promote sustainable development of energy and environmental protection. Through systematic resource management and optimization, better use and development of clean energy and renewable energy can be achieved. In addition, cross-regional resource scheduling systems can also promote regional cooperation and development. There are differences in resource endowments and industrial structures between different regions, and through the introduction of cross-regional resource scheduling systems, resources and advantages can be complementary. The current cross-domain computing power scheduling scheme is directly aimed at the entire task, and the task is directly matched to the most suitable region for calculation.

[0024] The cross-regional resource scheduling system is still in the early exploration stage at this stage. There are large differences in application load between regions, and the main application request and call link is dynamic and complex, and the cross-domain task scheduling will cause the performance of the application to be unstable and its chain reaction, leading to potential SLA constraint violation risks.

[0025] To solve the above problems, the present disclosure proposes a computing power scheduling scheme, which uses the link between computing units to construct a topology graph structure by quantifying the computing time, communication volume, and computing power resources, and predicted power consumption of the perception operator level parameters, and comprehensively delays, power consumption, and heterogeneous scheduling strategies to ensure parallel scheduling of tasks. It can be applied to the case of heterogeneous cross-domain hardware resources, meet the SLA requirements, and solve the problems of cross-regional task scheduling in related technologies.

[0026] The present disclosure will be described in further detail below with reference to the drawings and specific embodiments.

[0027] Figure 1 A flowchart of a computing power scheduling method provided by an embodiment of the present disclosure.

[0028] As shown in the figure, the computing power scheduling method provided by the embodiment of the present disclosure includes the following steps 101-105: Figure 1

[0029] Step 101, data preprocessing and topology perception are performed on the computing task to obtain a computation graph of the computing task.

[0030] In some embodiments of the present disclosure, the computing task specifically refers to a large computing task, especially a computing task with complex task requirements and hardware limitations in cross-domain resource scheduling, such as the currently widely used online inference task.

[0031] In some embodiments of the present disclosure, data preprocessing includes abstracting computing task data and calculating the computing time, communication volume, required computing power resources, and rated power consumption of each computing step of the computing task.

[0032] In some embodiments of the present disclosure, there is a call link between the operators (or computing units) of the computing task, and the topology perception is used to accurately depict and model the characteristics to obtain the computation graph of the computing task.

[0033] In some embodiments of the present disclosure, topology perception includes understanding the connection and dependency relationship between operators, and constructing a call topology graph of the computing task according to the connection and dependency relationship between operators, and taking the call topology graph as the computation graph.

[0034] Step 102, subgraph division is performed on the computation graph to obtain a computation subgraph, and the computation subgraph is packaged as a schedulable unit.

[0035] In some embodiments of the present disclosure, the subgraph division method is determined according to the specific type of the task, which can be a critical path algorithm, a machine learning algorithm, a deep learning method based on a graph neural network, etc., and the present disclosure is not limited thereto.

[0036] In some embodiments of the present disclosure, an unsupervised clustering algorithm based on a graph attention network divides the computation graph into multiple computation subgraphs.

[0037] In some embodiments of the present disclosure, by quantifying the communication volume and resource utilization between operators, each subgraph is packaged as a schedulable unit, which helps to improve computing efficiency and reduce communication overhead under limited hardware resources, and to achieve low latency and high throughput. ​

[0038] In step 103, the computational efficiency of the schedulable unit is obtained by determining the delay, power consumption and heterogeneity coefficient of the computing nodes in different regions to which the schedulable unit is allocated.

[0039] In some embodiments of the present disclosure, the computational efficiency (CE) refers to the performance improvement or effective output that a system can obtain while consuming resources (such as time, memory, computing power, etc.) when performing a computing task. The goal of computational efficiency is to maximize the execution efficiency of a computing task by optimizing resource usage, thereby reducing redundancy, reducing costs and improving response speed.

[0040] In step 104, a task scheduling model that meets the service level objective is constructed according to the max-min algorithm and the computational efficiency.

[0041] The task scheduling model is used to optimize the allocation of the schedulable unit on the computing nodes by calculating the optimal computational efficiency, and the execution time of the schedulable unit meets the preset time window.

[0042] In some embodiments of the present disclosure, the service level objective (SLO) refers to a specific and quantifiable service performance indicator specified in the SLA. It clearly defines the service quality standards that the service provider should achieve within a specific time period.

[0043] In some embodiments of the present disclosure, the task scheduling model represents the optimal CE obtained by allocating a plurality of schedulable units to a plurality of computing nodes for execution.

[0044] In step 105, the optimal allocation of the schedulable unit on the computing nodes is determined through the task scheduling model, and the schedulable unit is scheduled in parallel to the computing nodes according to the optimal allocation.

[0045] In some embodiments of the present disclosure, based on the task scheduling model, it can be determined which computing node in each region each schedulable unit will be scheduled to, so that the divided schedulable units can be scheduled in parallel to the computing nodes in multiple regions.

[0046] In some embodiments of the present disclosure, the computing nodes include cloud computing centers, etc., and the regions can be across long-distance geographical regions, heterogeneous data centers, data centers with different design methods, etc.

[0047] In summary, the embodiments provided by the present disclosure include data preprocessing and topology awareness of a computing task, obtaining a computation graph of the computing task; subgraph division of the computation graph to obtain a computation subgraph, and packaging the computation subgraph into a schedulable unit; obtaining the computing benefit of the schedulable unit by determining the delay, power consumption and heterogeneous coefficient of the schedulable unit when being executed by different regional computing nodes; constructing a task scheduling model meeting a service level objective according to a max-min algorithm and the computing benefit, wherein the task scheduling model is used to optimize the allocation of the schedulable unit on the computing nodes by calculating the optimal computing benefit, and the execution time of the schedulable unit meets a preset time window; determining the optimal allocation of the schedulable unit on the computing nodes through the task scheduling model, and scheduling the schedulable unit to the computing nodes in parallel according to the optimal allocation, which can schedule large computing tasks to appropriate regions according to the delay and power consumption, and solve the heterogeneous problem of hardware resources in the scheduling process, and fine scheduling reduces the overall power consumption of the entire task.

[0048] Based on Figure 1 As shown in the embodiments of the present disclosure, as Figure 2 As shown, Figure 2 Another flowchart of the computing power scheduling method provided by the embodiments of the present disclosure is shown.

[0049] The computing power scheduling method provided by the embodiments of the present disclosure includes the following steps:

[0050] Step 201, data preprocessing and topology awareness of a computing task, obtaining a computation graph of the computing task.

[0051] In some embodiments of the present disclosure, preprocessing and topology awareness of a computing task, obtaining a topology structure graph of the computing task includes: respectively measuring each operator of the computing task to obtain the computing parameters of each operator, the computing parameters including at least one of the computing time, the communication volume, the required computing power resource, and the rated power consumption; numbering all operators, adding a first entry and a second entry in each operator based on the calling link between operators, the first entry being the superior operator communicating with the operator, and the second entry being the subordinate operator of the operator; constructing a topology structure graph according to the first entry and the second entry of all operators, wherein the vertex of the topology structure graph represents the operator, the edge of the topology structure graph represents the calling relationship between the operators, and the weight of the edge represents the data transmission volume between the operators; taking the computing parameters of each operator as the feature data of each vertex in the topology structure graph to obtain a topology structure graph with attribute features, and determining the topology structure graph with attribute features as the computation graph of the computing task.

[0052] In some embodiments of the present disclosure, the computing task data is abstracted, and each computing step of the computing task is measured to measure the computing parameters such as the computing time, the communication volume, the required computing power resource, and the rated power consumption of each computing step, i.e., the operator level.

[0053] In some embodiments of the present disclosure, all operators are numbered, two entries are added in each operator, one entry is the superior operator in communication with the present operator, and one entry is the subordinate operator in communication with the present operator, a directed acyclic graph (DAG) is constructed according to the above two data entries to represent the calling topology of the computing task, represented as G=(V, E), where V represents the vertex set and E represents the edge set, the vertex set V represents the operators of the computing task, the edge set E represents the calling relationship between the operators, and w is used to represent the weight of the edge, that is, the data transmission amount between the operators. The quantized operator level computing time, communication amount and computing power resources, predicted power consumption and other parameters are all taken as the feature data of each vertex in the vertex set V, and the topology structure graph with attribute features obtained is taken as the computation graph of the computing task.

[0054] In step 202, the computation graph is subgraph-divided to obtain a computation subgraph, and the computation subgraph is packed into a schedulable unit.

[0055] In some embodiments of the present disclosure, subgraph-dividing the computation graph to obtain a computation subgraph and packing the computation subgraph into a schedulable unit include: determining a critical path in the computation graph according to a critical path algorithm; predicting at least one of power consumption, computing power and network delay required by the operators contained in each subgraph in the computation graph according to historical data to obtain a prediction result; dividing the computation graph into computation subgraphs based on the critical path and the prediction result; and packing the computation subgraph into a schedulable unit by quantizing the communication amount and resource utilization between the operators.

[0056] In some embodiments of the present disclosure, the subgraph division method can be determined according to the specific type of the task, which can be a critical path algorithm, a machine learning algorithm, or a deep learning method based on a graph neural network.

[0057] In some embodiments of the present disclosure, as shown in Figure 3 According to the attention weight of the node in the graph, it can be determined which nodes should be divided into the same subgraph. The critical path in the computation graph is determined according to the critical path algorithm, and the attribute features of the operators contained in the subgraph are predicted by the computation graph attribute machine learning algorithm, including the possible required power consumption, computing power and network delay.

[0058] In some embodiments of the present disclosure, the computation subgraphs with larger weights are merged, that is, the subgraphs with weights greater than a preset threshold are merged, for example, the influence of the power consumption of two subgraphs is much greater than that of other attributes, the two subgraphs are merged into one subgraph, and the subgraph attribute features are recalculated, which can form an efficient calling topology structure, thereby maximizing the overall throughput while meeting the SLO.

[0059] In some embodiments of the present disclosure, the method further comprises: obtaining the sensitivity of the schedulable unit based on the prediction result and the unsupervised clustering of the schedulable unit; and assigning a resource sensitivity coefficient to the schedulable unit according to the sensitivity, wherein the resource sensitivity coefficient is used to assist in calculating the delay, power consumption and heterogeneity coefficient of the execution of the schedulable unit on the computing nodes in different regions.

[0060] In some embodiments of the present disclosure, the sensitivity of the schedulable unit is obtained based on the above-mentioned prediction and the unsupervised clustering of the quantized schedulable unit, and a resource sensitivity coefficient is assigned to each schedulable unit according to the sensitivity. The resource sensitivity coefficient can be used to determine whether the corresponding computing subgraph of the schedulable unit is a network delay sensitive, computing power sensitive or power consumption sensitive schedulable unit.

[0061] It should be noted that based on the above method, the dynamically changing call link and the complex task interaction mode of the complex association can be abstracted into a schedulable unit, the network efficiency and energy efficiency of cross-region scheduling are improved, and important foundation is provided for the construction and optimization of the cross-region resource scheduling system.

[0062] Step 203, merging the call graph of the schedulable unit, and merging the functions with a data transmission amount greater than a preset value in the execution process of the schedulable unit into a new subgraph.

[0063] In some embodiments of the present disclosure, the functions that need to transmit a large amount of intermediate data in the execution process are preliminarily merged into new subgraphs by merging the call subgraph and the pipeline model.

[0064] Step 204, determining the transmission delay of the execution of the subgraph on the computing node according to the network delay, the execution time and the first product, and determining the delay calculation benefit of the schedulable unit based on the transmission delay, wherein the first product is the product of the cold start delay and the cold start times.

[0065] In some embodiments of the present disclosure, the new subgraph is further abstracted into a DAG. A G=(V,E) is constructed, and the weight of the edge represents the transmission delay latency q The delay of the execution of the computing task on the computing node is determined by the following formula 1:

[0066]

[0067] wherein, respectively represent the network delay, the execution time and the cold start delay multiplied by the cold start times, q represents a computing node in a plurality of different regions, and k represents a computing subgraph of a computing task. When V jWhen the value of the product of the unit execution cost difference and the execution time is 0, it indicates that there is a computing task in the hot start stage on the computing node in this region, and the recovery of the elastic resource is considered, so that the resource changes with the load to adapt to more general situations, for example, there is a load flow pattern, including the scene of flow burst and flow flat. From the delay consideration, the allocation strategy is to obtain the optimal computing benefit by minimizing the delay of the computing node executing the task.

[0068] In step 205, the total cost of executing the sub-graph on the computing node is determined according to the product of the unit time execution cost difference between the central processor and the graphics processor of the computing node and the execution time, and the power consumption computing benefit of the schedulable unit is confirmed based on the total cost.

[0069] In some embodiments of the present disclosure, the total cost is determined by multiplying the unit execution cost difference by the sum of the execution time and the node utilization, and the specific calculation is shown in formula 2:

[0070]

[0071] Wherein, is the unit time execution cost difference between the CPU and the GPU, and the cost difference is determined by subtracting the power consumption cost of the operation side from the price cost of the user side, and k represents a computing sub-graph of the computing task.

[0072] In some embodiments of the present disclosure, for a complex computing task (such as online inference), the overall execution time of all sub-computing graphs should meet the SLO, and the formula is as follows:

[0073]

[0074] Wherein, the parallel coefficient p i represents the parallelism of the sub-graph k i . From the power consumption consideration, the allocation strategy is to minimize the cost by minimizing the utilization of the node in the low-price high-energy-consumption area under the premise of meeting the SLO and the resource elasticity demand, so as to obtain the optimal computing benefit.

[0075] In step 206, the coefficients of variation of the central processor and the graphics processor are determined according to the performance indicators of the central processor and the graphics processor, and the heterogeneous computing benefit of the schedulable unit is determined based on the coefficients of variation.

[0076] In some embodiments of the present disclosure, the determination of the coefficient of variation of the central processing unit and the graphics processing unit according to the performance indicators of the central processing unit and the graphics processing unit comprises: collecting the performance indicators of the central processing unit and the graphics processing unit of each computing node; determining the computing power of the central processing unit and the graphics processing unit of each computing node according to the performance indicators; determining the average value and the standard deviation of the computing power of the central processing unit and the graphics processing unit according to the computing power of the central processing unit and the graphics processing unit and the number of computing nodes; and determining the coefficient of variation of the central processing unit and the graphics processing unit according to the ratio of the average value to the standard deviation.

[0077] It should be noted that there are differences in hardware resource micro-architecture and processor generations between regions, which leads to differences in computing resource allocation and estimation bias in the scheduling process. The execution cost per unit time of the CPU and GPU is used to charge the user, however, due to the differences in hardware performance and network transmission overhead, the execution time may have significant differences between different regions. Therefore, the present disclosure designs an influence factor I to quantitatively analyze the bias.

[0078] In some embodiments of the present disclosure, the CPU and GPU are standardized and calibrated, the CPU and GPU performance indicators of each node in the cluster are collected, and the computing power level distribution of the region is calculated. The computing power level of the cluster can be represented by a normal distribution N(μ,σ 2 ), where μ is the average value of the computing power level, σ is the standard deviation of the computing power level, and X ~ N(μ,σ 2 ). By testing or measuring the computing power in the cluster, the computing power data of all nodes can be obtained, and then μ and σ can be calculated to determine the computing power level of the entire cluster, wherein the cluster is a set of computing nodes.

[0079] In some embodiments of the present disclosure, the average value and the standard deviation of the CPU and GPU computing power level in the cluster are calculated by and , wherein n is the number of nodes, is the CPU computing power level of the i th node. Based on this, performance optimization, resource scheduling and other operations can be further performed on the cluster to improve the computing power level of the cluster.

[0080] Further, in some embodiments of the present disclosure, the coefficient of variation of the CPU and GPU is calculated by , wherein the coefficient of variation c and the coefficient of variation g represent the coefficient of variation of the CPU and GPU computing power level, respectively. The larger the coefficient of variation value, the greater the difference in computing power in the cluster.

[0081] In some embodiments of this disclosure, the coefficient of variation can be used to determine the allocation strategy for CPUs and GPUs. Resource types with higher coefficients of variation have greater dispersion and may require more flexible allocation strategies. For example, the allocation strategy may include allocating more resources to resource types with higher coefficients of variation to ensure a more balanced resource utilization across nodes. Specifically, assuming a total resource amount of T for CPUs and GPUs is desired, the allocation quantity for CPUs and GPUs can be determined according to the coefficients of variation of CPUs and GPUs using the following formulas 4 and 5:

[0082]

[0083] It should be noted that the above-mentioned handling methods for differences in hardware resource microarchitecture and processor generations between regions are not only applicable to situations where there are significant differences in CPU and GPU computing power levels. In practical applications, the influencing factors can be adjusted. This allows for the adaptation to more complex task requirements and hardware limitations, enabling the determination of resource allocation strategies to meet SLA requirements.

[0084] Step 207: Determine the computational efficiency of schedulable units based on latency computation efficiency, power consumption computation efficiency, and heterogeneous computation efficiency.

[0085] In some embodiments of this disclosure, based on the delay calculation benefit CE 延迟 Power consumption calculation efficiency CE 功耗 Heterogeneous computing benefits CE 异构系数 The final benefit CE is calculated using the following formula:

[0086] CE = Normalization(∑αCE) i ); i = {delay, power consumption, heterogeneity coefficient} Formula 6

[0087] In some embodiments of this disclosure, a comprehensive allocation strategy considering latency, power consumption, and heterogeneity coefficients is adopted. Under the premise of satisfying SLO, the computational efficiency is optimized by optimizing latency, power consumption, and heterogeneity coefficients to obtain the optimal allocation strategy.

[0088] In some embodiments of this disclosure, a module-based optimization algorithm is employed, such as... Figure 3 As shown, submodules 1, 2, and 3 are used to schedule computing power based on latency, power consumption, and heterogeneity, respectively. This can solve the problem of heterogeneous hardware resources during the scheduling process, and at the same time reduce the overall power consumption of the entire task through fine-grained scheduling.

[0089] Step 208: Based on the minimization algorithm and computational efficiency, construct a task scheduling model that meets the service level objectives.

[0090] The task scheduling model is used to optimize the allocation of the schedulable unit on the computing node by calculating the optimal computing efficiency, and the execution time of the schedulable unit meets a preset time window.

[0091] In step 209, the optimal allocation of the schedulable unit on the computing node is determined by the task scheduling model, and the schedulable unit is scheduled to the computing node in parallel according to the optimal allocation.

[0092] In some embodiments of the present disclosure, in order to improve the computing efficiency, parallel scheduling is adopted, specifically, a parallel scheduling module is added to the system, and the multiple schedulable units are changed from serial computing to parallel computing.

[0093] In some embodiments of the present disclosure, the delay of the sub-computing graph is represented as t max = max (t1, …, t R ), where t max represents the highest delay in all subgraphs, R represents the number of subgraphs, and the completion time of all computing subgraphs is

[0094] In some embodiments of the present disclosure, according to the max-min algorithm and the computing efficiency, the task scheduling model is constructed as follows:

[0095] F(g, l) = max 1≤i≤l {min{F(g-1, i), CE(i, l)}} Formula 7

[0096] The task scheduling model represents the optimal CE obtained by decomposing l computing units into g subgraphs, which is limited to the computing time of each subgraph falling between the earliest start time and the latest end time. The CE function is determined by steps 204-207 described above, that is, the CE function is determined by the allocation strategy considering delay, power consumption and heterogeneity. The computing unit refers to the basic module for computing, including the computing node, and can also be a smaller particle in the node such as GPU / CPU core. The task scheduling model is used to optimize the CE considering delay, power consumption and heterogeneity, to obtain the best subgraph partition corresponding to the optimal CE, that is, the best task allocation. The optimized CE can reduce the computing time, reduce the resource consumption, and improve the overall efficiency of the system.

[0097] In some embodiments of the present disclosure, the best subgraph computing sequence satisfying the SLO is derived, and the calculation formula is as follows:

[0098] P(L) = max 1≤g≤N {F(g, L)} Formula 8

[0099] In some embodiments of this disclosure, the task scheduling model satisfies the SLO constraint, where SLO can be floating, for example, S = (1 + δ)SLO, where δ is a custom variable floating value. The algorithm's time complexity is O(n log n).

[0100]

[0101] Where M is a function that quantifies the computational cost of a subgraph, and M(1,L) represents the computational cost of 1 to L subgraphs.

[0102] In some embodiments of this disclosure, a task scheduling model can be used to determine which region's computing node each schedulable unit will be scheduled to, so that the divided schedulable units can be scheduled in parallel to computing nodes in multiple regions.

[0103] In some embodiments of this disclosure, computing nodes include cloud computing centers, etc., and the regions can span long-distance geographical areas, or be heterogeneous data centers, data centers with different design methods, etc.

[0104] In summary, the solution provided in this disclosure constructs a topology graph structure using links between computing units by quantifying parameters such as computation time, communication volume, computing resources, and expected power consumption at the perception operator level. It then uses a graph attention network to subdivide the topology graph and allocate resource sensitivity coefficients. Based on a module-based optimization algorithm, it performs a process for parallel task scheduling that ensures computational latency. This solution is applicable to heterogeneous hardware resources across domains, meets SLA requirements, and solves the problems of cross-regional task scheduling in related technologies.

[0105] This disclosure also provides a computing power scheduling device, such as... Figure 4 As shown. Figure 4 This is a schematic diagram of the computing power scheduling device provided in an embodiment of the present disclosure. The computing power scheduling device 300 includes:

[0106] The acquisition module 310 is used to perform data preprocessing and topology awareness on the computing task to acquire the computing graph of the computing task; the subgraph partitioning model 320 is used to partition the computing graph into subgraphs to obtain computing subgraphs and package the computing subgraphs into schedulable units; the computing module 330 is used to obtain the computing efficiency of schedulable units by determining the latency, power consumption and heterogeneity coefficient of allocating schedulable units to computing nodes in different regions; the optimization module 340 is used to construct a task scheduling model that meets the service level target based on the minimax algorithm and computing efficiency, wherein the task scheduling model is used to optimize the allocation of schedulable units on computing nodes by calculating the optimal computing efficiency, and the execution time of schedulable units conforms to a preset time window; the parallel scheduling module 350 is used to determine the optimal allocation of schedulable units on computing nodes through the task scheduling model, and schedule the schedulable units to computing nodes in parallel according to the optimal allocation.

[0107] In some embodiments of the present disclosure, the obtaining module 310 is specifically configured to: measure each operator of the computing task respectively, and obtain the computing parameters of each operator, the computing parameters including at least one of computing time, communication volume, required computing power resource, and rated power consumption; number all the operators, add a first entry and a second entry in each operator based on the calling link between the operators, the first entry being a superior operator communicating with the operator, and the second entry being a subordinate operator of the operator; construct a topology structure graph according to the first entries and the second entries of all the operators, wherein the vertices of the topology structure graph represent the operators, the edges of the topology structure graph represent the calling relationship between the operators, and the weight of the edge represents the data transmission volume between the operators; take the computing parameters of each operator as the feature data of each vertex in the topology structure graph, to obtain a topology structure graph with attribute features, and determine the topology structure graph with attribute features as the computation graph of the computing task.

[0108] In some embodiments of the present disclosure, the subgraph division model 320 is specifically configured to: determine a critical path in the computation graph according to a critical path algorithm; predict at least one of the required power consumption, computing power and network delay of the operators included in each subgraph in the computation graph according to historical data, to obtain a prediction result; divide the computation graph into computing subgraphs based on the critical path and the prediction result; and pack the computing subgraphs into schedulable units by quantifying the communication volume and resource utilization between the operators.

[0109] In some embodiments of the present disclosure, the subgraph division model 320 is further configured to: perform unsupervised clustering based on the prediction result and the schedulable units, to obtain the sensitivity of the schedulable units; and assign a resource sensitivity coefficient to the schedulable units according to the sensitivity, wherein the resource sensitivity coefficient is used to assist in calculating the delay, power consumption and heterogeneity coefficient of executing the schedulable units on different regional computing nodes.

[0110] In some embodiments of the present disclosure, the computing module 330 is specifically configured to: merge the schedulable units according to a calling graph, and merge functions with data transmission volume greater than a preset value in the execution process of the schedulable units into a new subgraph; determine the transmission delay of executing the subgraph on a computing node according to the network delay, the execution time and a first product, and determine the delay computing benefit of the schedulable unit based on the transmission delay, wherein the first product is the product of the cold start delay and the cold start times; determine the total cost of executing the subgraph on the computing node according to the product of the execution cost difference per unit time between the central processing unit and the graphics processing unit of the computing node and the execution time, and confirm the power consumption computing benefit of the schedulable unit based on the total cost; determine the coefficients of variation of the central processing unit and the graphics processing unit according to the performance indicators of the central processing unit and the graphics processing unit, and determine the heterogeneous computing benefit of the schedulable unit based on the coefficients of variation; and confirm the computing benefit of the schedulable unit based on the delay computing benefit, the power consumption computing benefit and the heterogeneous computing benefit.

[0111] In some embodiments of the present disclosure, determining the coefficient of variation of the central processor and the graphics processor according to the performance indicators of the central processor and the graphics processor comprises: collecting the performance indicators of the central processor and the graphics processor of each computing node; determining the computing power of the central processor and the graphics processor of each computing node according to the performance indicators; determining the mean and the standard deviation of the computing power of the central processor and the graphics processor according to the computing power of the central processor and the graphics processor and the number of computing nodes; and determining the coefficient of variation of the central processor and the graphics processor according to the ratio of the mean to the standard deviation of the computing power.

[0112] To sum up, the computing power scheduling device provided by the present disclosure uses the link between the computing units to construct a topology graph structure by quantifying the parameters such as the computing time, the communication volume and the computing power resources, the expected power consumption and the like of the perception operator level, comprehensively delays, power consumption and heterogeneous scheduling strategies to ensure parallel scheduling of tasks, which can be applicable to the heterogeneous case of cross-domain hardware resources, meet the SLA requirements, and solve the problems existing in the related art cross-region task scheduling.

[0113] The computing power scheduling device provided by the above embodiments and the computing power scheduling method embodiment provided by the embodiments of the present disclosure belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be described here.

[0114] Figure 5 The hardware composition structure diagram of the communication device provided by the embodiments of the present disclosure is shown in FIG. 4, which comprises at least one processor 402, and a memory 401 in communication connection with the at least one processor 402, wherein the memory 401 stores instructions executable by the at least one processor 402, and the instructions are executed by the at least one processor 402 to implement the steps of the computing power scheduling method provided by the embodiments of the present disclosure, or the instructions are executed by the at least one processor 402 to implement the steps of the computing power scheduling method provided by the embodiments of the present disclosure. Figure 5 Optionally, the communication device can be a control device of the embodiments of the present application, and the communication device can implement the corresponding processes in the various methods of the embodiments of the present application implemented by the control device. For the sake of brevity, they will not be described here.

[0115] It can be understood that the communication device further comprises a communication interface 403. The various components in the communication device are coupled together through a bus system 404. It can be understood that the bus system 404 is used to realize the connection communication between the components. The bus system 404 includes not only a data bus, but also a power bus, a control bus and a status signal bus. However, for the sake of clear illustration, only the data bus is shown in the figure.

[0116] Figure 5 ​The various buses are all bus systems 404.

[0117] It can be understood that the memory 401 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a ferromagnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM can be used, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus random access memory (DRRAM).The memory 401 described in the embodiments of the present application is intended to include, but is not limited to, these and any other suitable type of memory.

[0118] The method disclosed in the embodiments of the present application can be applied to the processor 402 or implemented by the processor 402. The processor 402 can be an integrated circuit chip having a processing capability of signals. In the implementation process, each step of the above method can be completed by the integrated logic circuit of hardware in the processor 402 or the instruction in the form of software. The processor 402 described above can be a general processor, a DSP, or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. The processor 402 can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application. The general processor can be a microprocessor or any conventional processor, etc. In combination with the steps of the method disclosed in the embodiments of the present application, the hardware decoding processor can be directly embodied to execute the above method, or the combination of hardware and software modules in the decoding processor can be executed. The software module can be located in the storage medium, which is located in the memory 401, and the processor 402 reads the information in the memory 401 to complete the above method in combination with the hardware thereof.

[0119] In the exemplary embodiments, the communication device can be implemented by one or more application specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), FPGAs, general-purpose processors, controllers, MCUs, microprocessors (Microprocessors), or other electronic elements, for executing the above method.

[0120] The embodiments of the present application also provide a non-transitory computer readable storage medium storing computer instructions, which are used to make the computer execute the steps of the computing power scheduling method disclosed in the embodiments of the present application; or the computer instructions are used to make the computer execute the steps of the computing power scheduling method disclosed in the embodiments of the present application.

[0121] Optionally, the computer readable storage medium can be applied to the control device in the embodiments of the present application, and the computer instructions make the computer execute the corresponding processes implemented by the control device in each method of the embodiments of the present application. For brevity, details are not described here.

[0122] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other manners. The described device embodiments are merely illustrative, for example, the division of the units is only a logical function division, and there can be another division manner in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling, or direct coupling or communication connection between the components can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0123] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, they can be located in one place or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0124] In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be realized in the form of hardware or in the form of hardware plus software functional unit.

[0125] Those of ordinary skill in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by a program instructing related hardware, and the foregoing program can be stored in a computer readable storage medium, and the program executes the steps of the above-mentioned method embodiments when executed; and the foregoing storage medium includes mobile storage devices, ROM, RAM, magnetic discs or optical discs, and various media that can store program codes.

[0126] Alternatively, the integrated unit of the present application, if implemented in the form of a software function module and sold or used as an independent product, can also be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present application. The foregoing storage medium includes mobile storage devices, ROM, RAM, magnetic discs or optical discs, and various media that can store program codes.

[0127] The above merely illustrates the specific embodiments of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A computing power scheduling method, characterized in that, The method includes: Perform data preprocessing and topology awareness on the computing task to obtain the computing graph of the computing task; The computation graph is divided into subgraphs to obtain computation subgraphs, and the computation subgraphs are packaged into schedulable units. The computational efficiency of the schedulable unit is obtained by determining the latency, power consumption, and heterogeneity coefficient of the computing nodes in different regions to which the schedulable unit is assigned. Based on the minimax algorithm and the computational efficiency, a task scheduling model that meets the service level objective is constructed. The task scheduling model is used to optimize the allocation of the schedulable units on the computing nodes by calculating the optimal computational efficiency, and the execution time of the schedulable units conforms to a preset time window. The optimal allocation of the schedulable units on the computing node is determined by the task scheduling model, and the schedulable units are scheduled to the computing node in parallel according to the optimal allocation.

2. The method according to claim 1, characterized in that, The step of performing data preprocessing and topology awareness on the computing task to obtain the computing graph of the computing task includes: Each operator of the computation task is measured to obtain the computation parameters of each operator. The computation parameters include at least one of the following: computation time, communication volume, required computing resources, and rated power consumption. Number all the operators, and add a first entry and a second entry to each operator based on the call chain between the operators. The first entry is the parent operator that communicates with the operator, and the second entry is the child operator that communicates with the operator. Based on the first and second entries of all the operators, the topology graph is constructed, wherein the vertices of the topology graph represent the operators, the edges of the topology graph represent the calling relationships between the operators, and the weight of the edges represents the amount of data transmission between the operators; The computational parameters of each operator are used as feature data for each vertex in the topology graph to obtain a topology graph with attribute features. The topology graph with attribute features is then determined as the computation graph for the computation task.

3. The method according to claim 1, characterized in that, The step of partitioning the computation graph into subgraphs to obtain computation subgraphs and packaging the computation subgraphs into schedulable units includes: The critical path in the computation graph is determined according to the critical path algorithm; Based on historical data, predict at least one of the power consumption, computing power, and network latency required by the operators contained in each subgraph of the computation graph to obtain the prediction result; Based on the critical path and the prediction results, the computation graph is divided into the computation subgraphs; By quantifying the communication volume and resource utilization between operators, the computational subgraph is packaged into the schedulable unit.

4. The method according to claim 3, characterized in that, The method further includes: Unsupervised clustering is performed based on the prediction results and the schedulable units to obtain the sensitivity of the schedulable units; Based on the sensitivity, a resource sensitivity coefficient is assigned to the schedulable unit, wherein the resource sensitivity coefficient is used to assist in calculating the latency, power consumption, and heterogeneity coefficient of allocating the schedulable unit to computing nodes in different regions for execution.

5. The method according to claim 4, characterized in that, The step of determining the latency, power consumption, and heterogeneity coefficient of allocating the schedulable unit to computing nodes in different regions to obtain the computational efficiency of the schedulable unit includes: The call graphs of the schedulable units are merged, and functions whose data transmission volume exceeds a preset value during the execution of the schedulable units are merged into new subgraphs; The transmission delay of the subgraph executed on the computing node is determined based on the network latency, execution time, and a first product, and the latency calculation benefit of the schedulable unit is determined based on the transmission delay, wherein the first product is the product of cold start delay and cold start count; The total cost of executing the subgraph on the computing node is determined by multiplying the difference in execution cost per unit time between the central processing unit and the graphics processing unit of the computing node by the execution time, and the power consumption calculation efficiency of the schedulable unit is confirmed based on the total cost. Based on the performance metrics of the central processing unit and the graphics processing unit, the coefficients of variation of the central processing unit and the graphics processing unit are determined, and the heterogeneous computing benefits of the schedulable unit are determined based on the coefficients of variation. The computational efficiency of the schedulable unit is determined based on the latency computation efficiency, the power consumption computation efficiency, and the heterogeneous computation efficiency.

6. The method according to claim 5, characterized in that, The step of determining the coefficients of variation of the central processing unit and the graphics processing unit based on their performance metrics includes: Collect performance metrics of the central processing unit and the graphics processing unit of each computing node; Based on the performance metrics, determine the computing power of the central processing unit and the graphics processing unit of each computing node; The average value and standard deviation of the computing power of the central processing unit and the graphics processing unit are determined based on the computing power of the central processing unit and the graphics processing unit and the number of computing nodes; The coefficients of variation of the central processing unit and the graphics processing unit are determined based on the ratio of the average value to the standard deviation of the computing power.

7. A computing power scheduling device, characterized in that, The device includes: The acquisition module is used to perform data preprocessing and topology awareness on the computing task to acquire the computing graph of the computing task; A subgraph partitioning model is used to partition the computation graph into subgraphs to obtain computation subgraphs, and then package the computation subgraphs into schedulable units. The computing module is used to obtain the computing efficiency of the schedulable unit by determining the latency, power consumption, and heterogeneity coefficient of the computing nodes that allocate the schedulable unit to different regions for execution. An optimization module is used to construct a task scheduling model that meets the service level objective based on the minimization algorithm and the computational efficiency. The task scheduling model is used to optimize the allocation of the schedulable units on the computing nodes by calculating the optimal computational efficiency, and the execution time of the schedulable units conforms to a preset time window. The parallel scheduling module is used to determine the optimal allocation of the schedulable units on the computing node through the task scheduling model, and to schedule the schedulable units to the computing node in parallel according to the optimal allocation.

8. A communication device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1 to 6.

10. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the method according to any one of claims 1 to 6.

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