Communication chip layout defect automatic identification method based on artificial intelligence

Abstract

The invention discloses a communication chip layout defect automatic identification method based on artificial intelligence. The method comprises the following steps: analyzing a communication chip layout design file; executing design rule check and parameter extraction; an improved NCA model is constructed, state initialization is completed, and a fast-scale update parameter set and a slow-scale update parameter set are generated; executing iterative evolution based on the fast-scale updating parameter set and the slow-scale updating parameter set, and outputting an evolution intermediate representation set; conditional modulation is carried out on an update function of the improved NCA model; constructing a graph neural network topology consistency verification mechanism, and generating a verified defect region set; and performing defect discrimination and labeling, and outputting a defect type set, a defect distribution heat map and a defect coordinate set. According to the method, the communication chip layout defect identification accuracy is improved, and the cross-layer connectivity verification capability is enhanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit physical design, and in particular to a communication chip layout defect automatic identification method based on artificial intelligence. BACKGROUND

[0002] In the physical design process of a communication chip, automatic identification of layout defects is a key link to ensure circuit performance and process manufacturability. In the prior art, layout defect detection mainly relies on design rule checking and image processing methods based on empirical rules. Such methods usually compare line width, spacing, via size and connectivity through a rule library, but when the complexity and number of layers of the layout increase, problems such as low detection efficiency, high false positive rate and insufficient adaptability to new defects are likely to occur.

[0003] In addition, existing defect detection tools rely on static thresholds and single geometric rules for judgment, and lack the ability to model the overall topology relationship across layers. For the multi-layer interconnection and complex process constraints existing in communication chips, traditional methods often cannot accurately capture the coupling relationship between local anomalies and global consistency, making it difficult to identify some defects in a timely manner. At the same time, existing methods lack refined output in defect positioning and labeling, and can only give rough violation prompts, making it difficult to meet the needs of accurate analysis and optimization.

[0004] Therefore, how to provide a communication chip layout defect automatic identification method based on artificial intelligence is a problem that needs to be solved by those skilled in the art. SUMMARY

[0005] One object of the present application is to provide a communication chip layout defect automatic identification method based on artificial intelligence. The present application introduces an improved NCA model, combines a multi-layer image matrix set and a geometric topology constraint set to evolve cell states, uses a conditional variable set to modulate an update function to generate a candidate defect region set, and realizes cross-layer connectivity determination through a graph neural network topology consistency verification mechanism, finally completes defect type labeling and coordinate heat map output. The present application has the advantages of high identification accuracy, strong cross-layer topology consistency and fine defect positioning.

[0006] According to the communication chip layout defect automatic identification method based on artificial intelligence, the following steps are included: The communication chip layout design file is parsed, the layout data is converted into a multi-layer image matrix set, and a geometric boundary set and an interlayer connection relationship graph are extracted; Based on the multi-layer image matrix set, design rule checking and parameter extraction are performed, and a geometric topology constraint set is generated; Construct an improved NCA model and complete state initialization. Encode the multi-layer image matrix set and the geometric topology constraint set into the cell state vector multi-channel input. Initialize the fast scale update parameter set, the slow scale update parameter set, and the conditional variable set; Based on the fast scale update parameter set and the slow scale update parameter set, iteratively evolve the cell state vector to generate an evolution intermediate representation set; Conditionally modulate the update function of the improved NCA model with the conditional variable set, and combine the evolution intermediate representation set to generate a candidate defect region set; Construct a graph neural network topology consistency verification mechanism, taking the interlayer connection relationship graph and the candidate defect region set as input, calculate the connectivity verification result set and output the verified defect region set; According to the verified defect region set and the geometric topology constraint set, perform defect discrimination and labeling to generate a defect type set, a defect distribution heat map, and a defect coordinate set.

[0007] Optionally, the generation of the multi-layer image matrix set, the geometric boundary set, and the interlayer connection relationship graph includes: Receive the communication chip layout design file, parse the layer number, layer type, and geometric shape data; Map the geometric shape data to the corresponding layer according to the layer number, perform coordinate normalization and unit conversion, convert each layer into a two-dimensional image matrix, and collect them into a multi-layer image matrix set, including a metal layer image matrix, a via layer image matrix, and a barrier layer image matrix; Calculate the boundary based on the geometric shape data, extract the line segment boundary, arc segment boundary, and polygon boundary, and merge them into a geometric boundary set; According to the position relationship between the via layer and the metal layer, detect the cross-layer contact area and the connected path, and construct the interlayer connection relationship graph.

[0008] Optionally, the generation of the geometric topology constraint set includes: Based on the multi-layer image matrix set, load the process rule file and generate a rule set, including line width rules, spacing rules, via diameter rules, and interlayer connection rules; Based on the metal layer image matrix, calculate the center line width around the geometric boundary set, and perform verification according to the line width rule to generate a line width parameter; Based on the metal layer image matrix and the barrier layer image matrix, calculate the minimum distance between adjacent geometric boundaries, perform verification according to the spacing rule to generate a spacing parameter; Based on the via layer image matrix, identify the via geometric boundary and calculate the equivalent diameter, perform verification according to the via diameter rule to generate a via diameter parameter; Based on the inter-layer connection relationship diagram, a cross-layer connection path is identified and connectivity verification is performed, and inter-layer connectivity parameters are generated according to an inter-layer connection rule; The bus width parameter, the pitch parameter, the via diameter parameter and the inter-layer connectivity parameter are summarized to construct a geometric topology constraint set.

[0009] Optionally, the construction of the improved NCA model comprises: Based on the multi-layer image matrix set and the geometric topology constraint set, the channel order and length of the cell state vector multi-channel input are determined; The multi-layer image matrix set is encoded into an image channel in the cell state vector multi-channel input, the geometric topology constraint set is encoded into a parameter channel in the cell state vector multi-channel input, and coordinate alignment and scale normalization are performed; An improved NCA model is constructed, and the cell state vector is initialized as an initial value of the cell state vector multi-channel input; An initial fast-scale update parameter set is initialized, and the iteration step number, the neighborhood perception range and the update sparsity probability are configured as parameter elements in the set; An initial slow-scale update parameter set is initialized, and the weight coefficient and the gating threshold are configured as parameter elements in the set; According to the layer number and the geometric topology constraint set, a process layer level identification variable and a geometric topology constraint scalar code are constructed, and a conditional variable set is generated by merging.

[0010] Optionally, the generation of the evolutionary intermediate representation set comprises: Based on the multi-layer image matrix set and the geometric boundary set, neighborhood features are extracted, the fast-scale update parameter set and the slow-scale update parameter set are loaded, and the update process of the cell state vector is configured; The neighborhood features represent the pixel value distribution, the geometric boundary direction information and the local topology relationship within a preset neighborhood range around the current position of the cell state vector; In the fast-scale update stage, the neighborhood features and the geometric boundary set are input, the local neighborhood update of the cell state vector is performed, the local defect response map is output and accumulated, and the cell state vector is updated; Specifically, in the current position of the cell state vector and its neighborhood range, based on the iteration step number, the neighborhood perception range and the update sparsity probability set in the fast-scale update parameter set, the update position of the cell state vector is determined by sampling according to the update sparsity probability before each iteration, the pixel value distribution and the geometric boundary direction information contained in the neighborhood features are extracted, the extracted neighborhood features are input into the local update function of the improved NCA model, the state change amount of each position in the neighborhood is calculated through the convolution kernel weight, and the state change amount is added to the corresponding cell state vector channel to generate the updated cell state vector. In the slow-scale update stage, the inter-layer connection relationship graph is taken as the input to perform global topological consistency update on the cell state vector, output and accumulate the global topological consistency graph, and update the cell state vector at the same time; Specifically, before each slow-scale update, the weight coefficients and the gating threshold in the slow-scale update parameter set are loaded, cross-layer connectivity aggregation is performed on the entire cell state vector under the constraint of the inter-layer connection relationship graph, the global consistency value of each cell position is calculated in combination with the inter-layer connectivity parameters in the geometric topological constraint set, the global consistency value is compared with the gating threshold to screen out low consistency positions, the global consistency correction term is added to the parameter channel of the cell state vector for the positions that pass the screening, and the updated cell state vector is written back, and the global consistency values obtained in each slow-scale update are normalized and mapped to the image coordinates and accumulated in the iteration order to form the global topological consistency graph. After the fast-scale update stage and the slow-scale update stage are completed, in combination with the latest cell state vector, the local defect response graph and the global topological consistency graph, the multi-channel content of the latest cell state vector is taken as the basic representation, the local defect response graph and the global topological consistency graph are aligned and mapped to the corresponding positions according to the spatial coordinates and the layer number, the three inputs are normalized and fused based on the geometric topological constraint set, a three-dimensional tensor structure containing the local defect sensitivity, the global topological consistency index and the cell state evolution trajectory is generated, and the three-dimensional tensor structure is taken as the evolution intermediate representation set.

[0011] Optionally, the generation of the candidate defect region set comprises: The conditional variable set is bound to the update function of the improved NCA model in the parameter relationship, and the conditional variable set is injected into the weight coefficient, the gating vector and the normalization factor of the update function; The spatial coordinates and the layer number of the evolution intermediate representation set, the original local defect response graph and the original global topological consistency graph are aligned, and the pixel distribution of the evolution intermediate representation set, the original local defect response graph and the original global topological consistency graph is spliced into a unified fusion feature tensor; The fusion feature tensor is taken as the input, the update function is called, the defect response intensity is calculated under the modulation of the conditional variable set, and the defect confidence map is output; According to the process level identification variable and the geometric topological constraint scalar code in the conditional variable set, the segmentation threshold parameter is set, the threshold segmentation and connected domain analysis are performed on the defect confidence map, and the candidate defect region set is generated; The morphological refinement and overlap elimination are performed on the candidate defect region set, and finally the candidate defect region set with clear boundary and no redundant overlap is output.

[0012] Optionally, the generation of the verified defect region set comprises: Using the inter-layer connection graph and the set of candidate defect regions as input, a graph neural network topology consistency verification mechanism is constructed, including an input layer, a message passing layer, an aggregation layer, and an output layer. Based on the candidate defect region set, a node feature matrix is ​​generated through geometric feature extraction and attribute encoding. Based on the inter-layer connection graph, an edge feature matrix is ​​generated through topological relationship parsing and edge attribute encoding. The input layer receives the node feature matrix and the edge feature matrix; In the message passing layer and aggregation layer, process-level identifier variables and geometric topology constraint scalar codes of conditional variable sets are introduced to modulate the weight coefficients, gating vectors and aggregation weights of the update function, generating node embedding representations and graph embedding matrices. In the output layer, based on the connectivity threshold parameter, the connectivity of the node embedding representation is determined, and a set of connectivity verification results is generated by combining the graph embedding matrix. The connectivity threshold parameter is obtained by mapping the set of geometric topological constraints to the set of conditional variables; Based on the connectivity verification result set, filter the normally connected regions, output the abnormally connected regions, and form a set of defective regions after verification.

[0013] Optionally, the generation of the defect type set, defect distribution heatmap, and defect coordinate set includes: Using the set of verified defect regions and the set of geometric topological constraints as input, a one-to-one correspondence between regions and parameters is established. The line width parameter, spacing parameter, through-hole diameter parameter and interlayer connectivity parameter values ​​of each region are extracted, and the parameter deviation is calculated and recorded as region records. Based on the parameter deviation in the region record, perform type discrimination, output type labels, and construct a defect type set; The type label is bound to the region boundary, and the layer number is bound to the parameter deviation to generate a defect coordinate set, which includes the region centroid coordinates and the boundary vertex coordinates. The parameter deviation is mapped to the image grid according to spatial coordinates, and the intensity distribution is generated by interpolation mapping and Gaussian smoothing to form a defect distribution heatmap. Summarize the defect type set, defect distribution heatmap, and defect coordinate set.

[0014] The beneficial effects of this invention are: First, this invention constructs an improved NCA model to achieve joint modeling of multi-layer image matrix sets and geometric topological constraint sets. It considers both local features and global topological information during the evolution of cell state vectors, thereby improving the accuracy and completeness of communication chip layout defect identification.

[0015] Secondly, the application introduces a conditional variable set in the update function, adaptively modulates the convolution kernel weight and bias, enables the model to dynamically adjust the update mechanism for different process levels and geometric rules, and effectively reduces the false positive rate and missed detection rate generated by the traditional method in the complex layout scene.

[0016] In addition, the application solves the problem that it is difficult to accurately judge the cross-layer connectivity abnormality in the prior art by constructing a graph neural network topological consistency verification mechanism to jointly determine the candidate defect region set and the interlayer connection relationship graph, thereby guaranteeing the reliability and robustness of the identification result.

[0017] Finally, the application generates a defect type set, a defect distribution heat map and a defect coordinate set in the defect discrimination and labeling stage, realizes the refinement of defect positioning and result output, and provides an efficient and reliable reference for subsequent process optimization and design correction. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings are included to provide a further understanding of the application and constitute a part of the specification, which together with the embodiments of the application, serve to explain the application, and do not constitute a limitation on the application. In the drawings:

[0019] Fig. 1 A whole flow chart of an improved NCA model in the cell state vector multi-channel input and iterative evolution is provided for the application; Fig. 2 A structure schematic diagram of an improved NCA model in the cell state vector multi-channel input and iterative evolution is provided for the application; Fig. 3 A structure schematic diagram of a graph neural network topological consistency verification mechanism in the joint determination of the candidate defect region set and the interlayer connection relationship graph is provided for the application. DETAILED DESCRIPTION

[0020] The application will now be further described in detail with reference to the accompanying drawings. These drawings are all simplified schematic diagrams, and only schematically show the basic structure of the application, and therefore only show the components related to the application.

[0021] Reference Figs. 1-3 A communication chip layout defect automatic identification method based on artificial intelligence, comprising the following steps: The communication chip layout design file is parsed, GDSII layout file parsing technology is adopted, the layout data is converted into a multi-layer image matrix set, and a geometric boundary set and an interlayer connection relationship graph are extracted; Based on the multi-layer image matrix set, design rule checking and parameter extraction are performed, a geometric topological constraint set is generated, and the geometric topological constraint set includes line width parameters, spacing parameters, via diameter parameters and interlayer connectivity parameters; Construct an improved NCA model and complete state initialization. Encode the multi-layer image matrix set and the geometric topology constraint set into a cell state vector multi-channel input. Initialize the fast scale update parameter set, the slow scale update parameter set, and the conditional variable set; Based on the fast scale update parameter set and the slow scale update parameter set, iteratively evolve the cell state vector. The fast scale update calculates a local defect response map based on the neighborhood features and the geometric boundary set. The slow scale update calculates a global topology consistency map based on the inter-layer connection relationship graph. Generate an evolution intermediate representation set; Conditionally modulate the update function of the improved NCA model with the conditional variable set. Combine the evolution intermediate representation set, the local defect response map, and the global topology consistency map to generate a candidate defect region set; Based on the graph neural network topology consistency verification technology, input the inter-layer connection relationship graph and the candidate defect region set. Calculate the connectivity verification result set and output the verified defect region set; Based on the verified defect region set and the geometric topology constraint set, perform defect discrimination and labeling to generate a defect type set, a defect distribution heat map, and a defect coordinate set.

[0022] In this embodiment, the generation of the multi-layer image matrix set, the geometric boundary set, and the inter-layer connection relationship graph includes: Receive a communication chip layout design file and call a GDSII layout file parsing technology to parse layer number, layer type, and geometric shape data; The GDSII layout file parsing technology means decoding the layout data file stored in binary stream form into layer number information, layer type information, and geometric shape information. Recover polygons, rectangles, and paths and other geometric objects according to the coordinate data recorded in the file, and extract the hierarchical relationship between different layers to serve as input data for constructing the multi-layer image matrix set; Map the geometric shape data to the corresponding layer according to the layer number. Perform coordinate normalization and unit conversion to convert each layer into a two-dimensional image matrix and collect them into a multi-layer image matrix set. The multi-layer image matrix set includes a metal layer image matrix, a via layer image matrix, and a barrier layer image matrix; Calculate the boundary based on the geometric shape data. Extract line segment boundaries, arc segment boundaries, and polygon boundaries and merge them into a geometric boundary set; Detect cross-layer contact areas and connected paths based on the position relationship between the via layer and the metal layer to construct an inter-layer connection relationship graph; Perform consistency checking on the multi-layer image matrix set, the geometric boundary set, and the inter-layer connection relationship graph.

[0023] In this embodiment, the generation of the geometric topology constraint set includes: Based on the multi-layer image matrix set, a process rule file is loaded and a rule set is generated, the rule set including line width rules, spacing rules, via diameter rules and interlayer connection rules; The process rule file is specifically a design rule set provided by a semiconductor manufacturing process, containing line width lower limits, spacing lower limits, via diameter ranges and cross-layer connection constraint parameters corresponding to different layer numbers, and defining geometric size limits, interlayer interaction conditions and tolerance ranges in the form of rule tables or scripts, for guiding the execution of line width calculation, spacing calculation, via diameter calculation and interlayer connectivity verification; Based on the metal layer image matrix, the center line width is calculated around the geometric boundary set, and the line width parameter is generated by performing verification according to the line width rules; Based on the metal layer image matrix and the barrier layer image matrix, the minimum distance between adjacent geometric boundaries is calculated, and the spacing parameter is generated by performing verification according to the spacing rules; Based on the via layer image matrix, the via geometric boundary is identified and the equivalent diameter is calculated, and the via diameter parameter is generated by performing verification according to the via diameter rules; Based on the interlayer connection relationship graph, the cross-layer connection path is identified and the connectivity verification is performed, and the interlayer connectivity parameter is generated according to the interlayer connection rules; The line width parameter, the spacing parameter, the via diameter parameter and the interlayer connectivity parameter are summarized to construct a geometric topological constraint set.

[0024] In this embodiment, the construction of the improved NCA model includes: Based on the multi-layer image matrix set and the geometric topological constraint set, the channel order and length of the cell state vector multi-channel input are determined; The cell state vector multi-channel refers to that in the improved NCA model, the state vector corresponding to each cell position is composed of multiple channels, which include image channels from the multi-layer image matrix set and parameter channels from the geometric topological constraint set, for simultaneously representing local geometric features, hierarchical process information and design rule parameters, thereby providing complete input for subsequent iterative evolution; The metal layer image matrix, the via layer image matrix and the barrier layer image matrix in the multi-layer image matrix set are encoded into the image channels in the cell state vector multi-channel input, and the line width parameter, the spacing parameter, the via diameter parameter and the interlayer connectivity parameter in the geometric topological constraint set are encoded into the parameter channels in the cell state vector multi-channel input, and coordinate alignment and scale normalization are performed; The improved NCA model is constructed, and the state initialization is completed, and the cell state vector is initialized as the initial value of the cell state vector multi-channel input; Initialize the fast-scale update parameter set, configure the iteration step number, neighborhood perception range and update sparse probability as parameter elements into the set for the execution of local neighborhood update; Initialize the slow-scale update parameter set, configure the weight coefficient and gating threshold as parameter elements into the set for the execution of global topology consistency calculation; According to the layer number and the geometric topology constraint set, construct the process layer level identification variable and the geometric topology constraint scalar code, merge to generate the conditional variable set, and bind the conditional variable set, the fast-scale update parameter set and the slow-scale update parameter set to the update function of the improved NCA model; The generation of the conditional variable set is specifically that the process layer level identification variable is established based on the analyzed layer number, different layer numbers are mapped into corresponding layer level code vectors; the line width parameter, the spacing parameter, the through hole diameter parameter and the interlayer connectivity parameter in the geometric topology constraint set are normalized calculated and converted into constraint scalar codes; the process layer level identification variable and the geometric topology constraint scalar code are spliced and corrected in the channel dimension to output the conditional variable set, and the conditional variable set includes the process layer level identification variable channel and the geometric topology constraint scalar code channel.

[0025] In the embodiment, the generation of the evolution intermediate representation set includes: Based on the multi-layer image matrix set and the geometric boundary set, extract the neighborhood feature, load the fast-scale update parameter set and the slow-scale update parameter set, and configure the update process of the cell state vector; The neighborhood feature represents the pixel value distribution, the geometric boundary direction information and the local topology relationship within the preset neighborhood range around the current position of the cell state vector, which is used to describe the geometric morphology and structure change in the local area and provide input information for local defect detection; In the fast-scale update stage, the neighborhood feature and the geometric boundary set are input, the local neighborhood update is performed on the cell state vector, the local defect response map is output and accumulated, and the cell state vector is updated for subsequent slow-scale update; Specifically, in the current position and its neighborhood range of the cell state vector, based on the iteration step number, the neighborhood perception range and the update sparse probability set in the fast-scale update parameter set, the update position of the cell state vector is determined according to the update sparse probability before each iteration, the pixel value distribution and the geometric boundary direction information contained in the neighborhood feature are extracted, the extracted neighborhood feature is input into the local update function of the improved NCA model, the state change amount of each position in the neighborhood is calculated through the convolution kernel weight, and the state change amount is superimposed to the corresponding cell state vector channel to generate the updated cell state vector; After each local neighborhood update, according to the process level features recorded in the cell state vector and the geometric topology constraint parameters, the probability value of the area inconsistent with the standard rule is calculated, the probability value is mapped to the pixel intensity distribution in the local defect response map, and the complete local defect response map is output after multiple iterations. In the slow scale update stage, the inter-layer connection relationship graph is input, the global topology consistency update is performed on the cell state vector, and the global topology consistency graph is output and accumulated, and the cell state vector is updated for the next round of fast scale update. Specifically, before each slow scale update, the weight coefficient and the gating threshold in the slow scale update parameter set are loaded, the cross-layer connectivity aggregation is performed on the whole cell state vector under the constraint of the inter-layer connection relationship graph, the global consistency value of each cell position is calculated combined with the inter-layer connectivity parameters in the geometric topology constraint set, the global consistency value is compared with the gating threshold to screen out low consistency positions, the global consistency correction term is added to the parameter channel of the cell state vector for the positions passing the screening, and the updated cell state vector is written back, and the global consistency value obtained in each slow scale update is normalized and mapped to the image coordinates and accumulated in the iteration order to form the global topology consistency graph. After the fast scale update stage and the slow scale update stage are completed, combined with the latest cell state vector, the local defect response graph and the global topology consistency graph, the multi-channel content of the latest cell state vector is taken as the basic representation, the local defect response graph and the global topology consistency graph are aligned and mapped to the corresponding position according to the spatial coordinates and the layer number, the three inputs are normalized and fused based on the geometric topology constraint set, a three-dimensional tensor structure containing local defect sensitivity, global topology consistency index and cell state evolution trajectory is generated, and the three-dimensional tensor structure is taken as the evolution intermediate representation set.

[0026] In the embodiment, the generation of the candidate defect region set includes: The conditional variable set is bound to the update function of the improved NCA model, and the conditional variable set is injected into the weight coefficient, the gating vector and the normalization factor of the update function. The spatial coordinates and the layer number of the evolution intermediate representation set, the original local defect response graph and the original global topology consistency graph are aligned, the cell state vector, the local defect sensitivity and the global topology consistency index of the evolution intermediate representation set are spliced into a unified fusion feature tensor with the pixel distribution of the original local defect response graph and the original global topology consistency graph. The fusion feature tensor is taken as the input, the update function is called, the defect response intensity is calculated under the modulation of the conditional variable set, and the defect confidence map is output. Specifically, in the fusion of the feature tensor input update function, first, the convolution kernel weight and bias of the update function are modulated according to the process level identification variable and the geometric topological constraint scalar code in the conditional variable set, including selecting the corresponding convolution kernel sub-weight matrix based on the process level identification variable, adjusting the channel weight coefficient of the convolution kernel based on the geometric topological constraint scalar code, dynamically correcting the bias value based on the fast scale update parameter set and the slow scale update parameter set, and introducing a gating vector in the calculation process to realize weight sparsification control, so that the update function has adaptability under different process levels and geometric rules; Then, the cell state vector channel, local defect response map and global topological consistency map contained in the fusion feature tensor are input into the update function layer by layer, and the defect response intensity value of each pixel position is calculated; Finally, based on the normalization mapping technology, the defect response intensity value is converted into a probability distribution to generate a pixel-level defect confidence map, which is used to represent the possibility of each position in the communication chip layout belonging to the defect area; According to the process level identification variable and the geometric topological constraint scalar code in the conditional variable set, a segmentation threshold parameter is set to perform threshold segmentation and connected component analysis on the defect confidence map to generate a candidate defect region set; The segmentation threshold parameter distinguishes the defect sensitivity levels of different metal layers, via layers and barrier layers according to the process level identification variable, and sets the upper and lower limits of the threshold value in combination with the line width parameter, the pitch parameter and the via diameter parameter in the geometric topological constraint scalar code. Different levels and rules correspond to different threshold value ranges to ensure that the defect judgment standard is consistent with the process design rule; The threshold segmentation and connected component analysis are specifically: first, compare the pixel intensity in the defect confidence map with the segmentation threshold parameter to generate a binary defect candidate map; Then, based on the pixel connectivity principle, region clustering is performed in the binary defect candidate map to aggregate spatially adjacent high-confidence pixels into connected domains; Further, according to the interlayer connection relationship graph, isolated regions that do not meet the connectivity constraint are filtered out, and finally the candidate defect region set that meets the process rules is output; Perform morphological thinning and overlap elimination on the candidate defect region set to finally output a candidate defect region set with clear boundaries and no redundant overlap; The morphological refinement and overlap elimination includes performing erosion and dilation operations on each defect region boundary in the candidate defect region set to remove isolated noise points and smooth the region boundary, so that the defect region profile is closer to the true geometric morphology; then performing opening and closing operations on the defect region at different scales to eliminate local burrs and small area artifacts while maintaining the overall connectivity of the defect region; on this basis, the candidate defect regions with spatial position overlap or high intersection are subjected to overlap elimination, the process of overlap elimination is to calculate the overlap rate of the intersection region, when the overlap rate is higher than the set threshold, the overlapping regions are merged into a single defect region, when the overlap rate is lower than the set threshold, the independent regions are retained, and finally a candidate defect region set with clear boundary and no redundant overlap is output.

[0027] In the embodiment, the generation of the verified defect region set includes: Taking the inter-layer connection relationship graph and the candidate defect region set as inputs, a graph neural network topology consistency verification mechanism is constructed, which includes an input layer, a message passing layer, an aggregation layer and an output layer. Based on the candidate defect region set, a node feature matrix is generated through geometric feature extraction and attribute encoding, which contains area, perimeter, layer number, barycentric coordinates and local parameters calculated based on the geometric topology constraint set. Based on the inter-layer connection relationship graph, an edge feature matrix is generated through topology relationship analysis and edge attribute encoding, which contains cross-layer connection type, geometric distance and connection direction. The input layer receives the node feature matrix and the edge feature matrix to provide input representation for the connectivity verification calculation of the subsequent message passing layer and aggregation layer; In the message passing layer and the aggregation layer, the process level identification variable and the geometric topology constraint scalar code of the conditional variable set are introduced to modulate the weight coefficient, the gating vector and the aggregation weight of the update function, so that the graph neural network topology consistency verification mechanism can dynamically adjust the message passing process according to different process levels and geometric topology constraints to generate node embedding representation and graph embedding matrix. In the output layer, the connectivity of the node embedding representation is determined according to the connectivity threshold parameter, and the connectivity verification result set is generated combined with the graph embedding matrix, and is indexed and mapped with the candidate defect region set; The connectivity threshold parameter is obtained by mapping the geometric topology constraint set and the conditional variable set; According to the connectivity verification result set, the connected normal region is filtered, the connected abnormal region is output, and the verified defect region set is formed.

[0028] In the embodiment, the generation of the defect type set, the defect distribution heat map and the defect coordinate set includes: With the verified defect region set and the geometric topology constraint set as input, a one-to-one correspondence between the region and the parameter is established, the line width parameter, the spacing parameter, the via diameter parameter and the interlayer connectivity parameter value of each region position are extracted, the parameter deviation is calculated and recorded as a region record; According to the parameter deviation in the region record, type discrimination is performed, the upper and lower limits of the deviation line width are determined as the line width violation type, the lower limit of the deviation spacing is determined as the spacing violation type, the deviation via diameter range is determined as the via diameter violation type, and the violation of the interlayer connectivity parameter is determined as the connectivity abnormality type, a type label is output and a defect type set is constructed; The type label is bound with the region boundary, the layer number and the parameter deviation to generate a defect coordinate set, and the defect coordinate set includes the region center coordinates and the boundary vertex coordinates; The parameter deviation is mapped to the image grid according to the spatial coordinates, the intensity distribution is generated by using interpolation mapping and Gaussian smoothing, and a defect distribution heat map is formed; The defect type set, the defect distribution heat map and the defect coordinate set are summarized and output.

[0029] Example 1 In order to verify the feasibility of the application in implementation, the application is applied to the task of automatic identification of communication chip layout defects. In the actual chip design process, with the continuous reduction of process nodes and the continuous increase of layout layers, the traditional defect detection method relying on rule library and static threshold often has problems of insufficient efficiency, high false positive rate and difficulty in accurately identifying cross-layer defects when facing complex layout data. The application introduces an improved NCA model and a graph neural network topology consistency verification mechanism to realize the automation modeling and iterative calculation of layout data, and realizes the efficiency and reliability of defect identification.

[0030] In the application scenario, the test sample comes from a layout design file of a communication chip, the file contains 11 metal layers, 2 via layers and 1 barrier layer, the layout data volume reaches 8GB, contains more than 1.4 million geometric figures and about 370,000 cross-layer connection relationships. Through the GDSII layout file parsing technology, the layout data is converted into a multi-layer image matrix set, and the geometric boundary information and the interlayer connection relationship are extracted. Combined with the design rule check, the line width parameter, the spacing parameter, the via diameter parameter and the interlayer connectivity parameter are extracted, and a complete geometric topological constraint set is constructed. On the basis of the input, the application constructs an improved NCA model, performs local defect response calculation and global topological consistency modeling on the layout data, and then adaptively modulates the update function through the conditional variable set to generate a candidate defect region set. The candidate defect region is jointly judged with the interlayer connection relationship after entering the graph neural network topological consistency verification mechanism, and finally the verified defect region set is output, and on this basis, the defect type labeling, the defect distribution heat map drawing and the generation of the defect coordinate set are completed.

[0031] In the experiment, in order to verify the improvement effect of the application relative to the traditional method, three dimensional evaluation indexes are selected, including defect recognition accuracy, defect false alarm rate and defect positioning deviation. The experimental comparison method is the traditional rule-based DRC method and the artificial intelligence method proposed in the application. Under the same data set and hardware environment, each method processes 1.4 million geometric figures and 370,000 cross-layer connections, and records the final recognition result and statistical data.

[0032] The experimental results are shown in the following table: Table 1 Comparison results of communication chip layout defect recognition performance

[0033] As can be seen from Table 1, in terms of defect identification accuracy, the present application reaches 91.4%, which is obviously improved compared with 82.3% of the traditional rule base method, indicating that the present application can better capture potential defects in a complex layout environment. In terms of defect false alarm rate, the present application is 2.9%, which is significantly lower than 11.6% of the traditional method, greatly reducing unnecessary manual review work and improving overall detection efficiency. In terms of defect positioning deviation, the average deviation of the present application method is 0.65 microns, which is better than 0.82 microns of the traditional method, indicating that the present application has higher precision in the coordinate output and defect labeling link. In terms of processing time, the present application takes 105 minutes, which is 23 minutes shorter than 128 minutes of the traditional method, reflecting the efficiency advantage under the iterative evolution and parallel processing mechanism. In terms of cross-layer connectivity defect detection rate, the present application reaches 92.1%, which is higher than 81.7% of the traditional method, proving that after introducing the graph neural network topological consistency verification mechanism, the present application can more accurately identify cross-layer connectivity abnormalities, thereby significantly improving the reliability of the detection result.

[0034] Through comparative analysis, it can be concluded that the advantages of the present application method mainly lie in three aspects. Firstly, the improved NCA model can model the layout for multi-channel input, and improve the accuracy and comprehensiveness of identification through the joint evolution mechanism of fast scale and slow scale. Secondly, the introduction of the conditional variable set enables the update function to have self-adaptive modulation capability, which can maintain stable detection effect under different process levels and geometric rules, thereby effectively reducing the false alarm rate. Thirdly, the graph neural network topological consistency verification mechanism ensures that cross-layer connectivity abnormalities can be accurately identified, which fundamentally makes up for the deficiency of the traditional method that is difficult to find complex topological defects.

[0035] The above describes only the preferred specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can make equivalent substitutions or changes to the technical solutions and inventive concepts of the present application within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application.

Claims

1. An automatic identification method for layout defects in communication chips based on artificial intelligence, characterized in that, Includes the following steps: The layout design file of the communication chip is parsed, the layout data is transformed into a multi-layer image matrix set, and the geometric boundary set and inter-layer connection relationship diagram are extracted. Based on a multi-layer image matrix set, design rule checks and parameter extraction are performed to generate a set of geometric topological constraints. An improved NCA model was constructed and the state was initialized. The multi-layer image matrix set and the geometric topological constraint set were encoded into the cell state vector multi-channel input. The fast-scale update parameter set, the slow-scale update parameter set and the conditional variable set were initialized. Based on the fast-scale and slow-scale parameter update sets, the cell state vector is iteratively evolved to generate an intermediate evolutionary representation set; The update function of the improved NCA model is conditionally modulated using a set of conditional variables, and a set of candidate defect regions is generated by combining the set of evolutionary intermediate representations. A graph neural network topology consistency verification mechanism is constructed. Taking the inter-layer connection graph and the candidate defect region set as input, the connectivity verification result set is calculated and the verified defect region set is output. Based on the verified defect region set and geometric topological constraint set, defects are identified and labeled, generating a defect type set, a defect distribution heatmap, and a defect coordinate set.

2. The method for automatic identification of layout defects in communication chips based on artificial intelligence according to claim 1, characterized in that, The generation of the multi-layer image matrix set, geometric boundary set, and inter-layer connection graph includes: Receive the layout design file of the communication chip and parse the layer number, layer type and geometric shape data; The geometric data is mapped to the corresponding layer according to the layer number, coordinate normalization and unit conversion are performed, each layer is converted into a two-dimensional image matrix and collected into a multi-layer image matrix set, including the metal layer image matrix, the via layer image matrix and the barrier layer image matrix. Based on geometric shape data, the boundary is calculated, and line segment boundaries, arc segment boundaries, and polygon boundaries are extracted and merged into a set of geometric boundaries. Based on the positional relationship between the via layer and the metal layer, the cross-layer contact area and connection path are detected, and an interlayer connection relationship diagram is constructed.

3. The method for automatic identification of layout defects in communication chips based on artificial intelligence according to claim 1, characterized in that, The generation of the set of geometric topological constraints includes: Based on a multi-layer image matrix set, a process rule file is loaded and a rule set is generated, which includes line width rules, spacing rules, via diameter rules, and inter-layer connection rules. Based on the metal layer image matrix, the centerline width is calculated around the geometric boundary set, and verification is performed according to the line width rules to generate line width parameters; Based on the metal layer image matrix and the barrier layer image matrix, the minimum distance between adjacent geometric boundaries is calculated, and a verification is performed according to the spacing rules to generate spacing parameters. Based on the through-hole layer image matrix, the geometric boundaries of the through-holes are identified and the equivalent diameter is calculated. Verification is performed according to the through-hole diameter rules to generate through-hole diameter parameters. Based on the inter-layer connection graph, cross-layer connection paths are identified and connectivity checks are performed. Inter-layer connectivity parameters are generated according to the inter-layer connection rules. By summarizing line width parameters, spacing parameters, through-hole diameter parameters, and inter-layer connectivity parameters, a set of geometric topological constraints is constructed.

4. The method for automatic identification of layout defects in communication chips based on artificial intelligence according to claim 1, characterized in that, The construction of the improved NCA model includes: Based on a multi-layer image matrix set and a geometric topological constraint set, the channel order and length of the multi-channel input of the cell state vector are determined. The set of multi-layer image matrices is encoded into the image channels of the cell state vector multi-channel input, the set of geometric topological constraints is encoded into the parameter channels of the cell state vector multi-channel input, and coordinate alignment and scale normalization are performed. An improved NCA model is constructed, in which the cell state vector is initialized with the initial values ​​of the multi-channel input of the cell state vector; Initialize the fast-scale update parameter set, and configure the iteration step number, neighborhood perception range and update sparsity probability as parameter elements into the set; Initialize the slow-scale update parameter set, and configure the weight coefficients and gating thresholds as parameter elements into the set; Based on the layer number and the set of geometric topology constraints, construct the process layer identifier variable and the scalar code of the geometric topology constraint, and merge them to generate a set of conditional variables.

5. The method for automatic identification of layout defects in communication chips based on artificial intelligence according to claim 1, characterized in that, The generation of the evolutionary intermediate representation set includes: Based on a multi-layer image matrix set and a geometric boundary set, neighborhood features are extracted, and a fast-scale update parameter set and a slow-scale update parameter set are loaded to configure the update process of the cell state vector. The neighborhood features represent the pixel value distribution, geometric boundary direction information, and local topological relationships within a preset neighborhood range around the current position of the cell state vector; In the fast-scale update stage, the local neighborhood update is performed on the cell state vector using the neighborhood features and geometric boundary set as input, outputting and accumulating the local defect response map, while updating the cell state vector. Specifically, within the current position of the cell state vector and its neighborhood, based on the iteration step number, neighborhood perception range, and update sparsity probability set by the fast-scale update parameter set, the cell state vector is sampled to determine the update position before each iteration according to the update sparsity probability. The pixel value distribution and geometric boundary direction information contained in the neighborhood features are extracted. The extracted neighborhood features are input into the local update function of the improved NCA model. The state change amount at each position in the neighborhood is calculated through the convolution kernel weights, and the state change amount is superimposed on the corresponding cell state vector channel to generate the updated cell state vector. During the slow-scale update phase, the cell state vector is updated globally with the inter-layer connectivity graph as input, and the global topological consistency graph is output and accumulated, while the cell state vector is updated. Specifically, before each slow-scale update, the weight coefficients and gating thresholds in the slow-scale update parameter set are loaded. Under the constraints of the inter-layer connectivity graph, cross-layer connectivity aggregation is performed on all cell state vectors. The global consistency value of each cell position is calculated by combining the inter-layer connectivity parameters in the geometric topology constraint set. The global consistency value is compared with the gating threshold to filter out low consistency positions. For the positions that pass the filtering, a global consistency correction term is added to the parameter channel of the cell state vector and written back to the updated cell state vector. The global consistency value obtained from each slow-scale update is normalized, mapped to image coordinates, and accumulated in the iterative order to form a global topological consistency graph. After the fast-scale update phase and the slow-scale update phase are completed, the latest cell state vector, the local defect response map, and the global topological consistency map are combined. The multi-channel content of the latest cell state vector is used as the basic representation. The local defect response map and the global topological consistency map are aligned and mapped to the corresponding positions according to the spatial coordinates and layer numbers. The three inputs are normalized and fused based on the geometric topological constraint set to generate a three-dimensional tensor structure containing local defect sensitivity, global topological consistency index and cell state evolution trajectory. This three-dimensional tensor structure is used as the intermediate representation set for evolution.

6. The method for automatic identification of layout defects in communication chips based on artificial intelligence according to claim 1, characterized in that, The generation of the candidate defect region set includes: Establish a parameter binding relationship between the set of conditional variables and the update function of the improved NCA model, and inject the set of conditional variables into the weight coefficients, gate vectors and normalization factors of the update function; The spatial coordinates and layer numbers of the intermediate evolutionary representation set are aligned with the original local defect response map and the original global topology consistency map. The pixel distributions of the intermediate evolutionary representation set, the original local defect response map, and the original global topology consistency map are then stitched together into a unified fusion feature tensor. Using the fused feature tensor as input, the update function is called to calculate the defect response intensity under the modulation of the conditional variable set, and the defect confidence map is output. Based on the process level identifier variable and geometric topology constraint scalar encoding in the conditional variable set, a segmentation threshold parameter is set, and threshold segmentation and connected component analysis are performed on the defect confidence map to generate a candidate defect region set. Morphological refinement and overlap resolution are performed on the candidate defect region set to finally output a candidate defect region set with clear boundaries and no redundant overlap.

7. The method for automatic identification of layout defects in communication chips based on artificial intelligence according to claim 1, characterized in that, The generation of the verified defect region set includes: Using the inter-layer connection graph and the set of candidate defect regions as input, a graph neural network topology consistency verification mechanism is constructed, including an input layer, a message passing layer, an aggregation layer, and an output layer. Based on the candidate defect region set, a node feature matrix is ​​generated through geometric feature extraction and attribute encoding. Based on the inter-layer connection graph, an edge feature matrix is ​​generated through topological relationship parsing and edge attribute encoding. The input layer receives the node feature matrix and the edge feature matrix; In the message passing layer and aggregation layer, process-level identifier variables and geometric topology constraint scalar codes of conditional variable sets are introduced to modulate the weight coefficients, gating vectors and aggregation weights of the update function, generating node embedding representations and graph embedding matrices. In the output layer, based on the connectivity threshold parameter, the connectivity of the node embedding representation is determined, and a set of connectivity verification results is generated by combining the graph embedding matrix. The connectivity threshold parameter is obtained by mapping the set of geometric topological constraints to the set of conditional variables; Based on the connectivity verification result set, filter the normally connected regions, output the abnormally connected regions, and form a set of defective regions after verification.

8. The method for automatic identification of layout defects in communication chips based on artificial intelligence according to claim 1, characterized in that, The generation of the defect type set, defect distribution heatmap, and defect coordinate set includes: Using the set of verified defect regions and the set of geometric topological constraints as input, a one-to-one correspondence between regions and parameters is established. The line width parameter, spacing parameter, through-hole diameter parameter and interlayer connectivity parameter values ​​of each region are extracted, and the parameter deviation is calculated and recorded as region records. Based on the parameter deviation in the region record, perform type discrimination, output type labels, and construct a defect type set; The type label is bound to the region boundary, and the layer number is bound to the parameter deviation to generate a defect coordinate set, which includes the region centroid coordinates and the boundary vertex coordinates. The parameter deviation is mapped to the image grid according to spatial coordinates, and the intensity distribution is generated by interpolation mapping and Gaussian smoothing to form a defect distribution heatmap. Summarize the defect type set, defect distribution heatmap, and defect coordinate set.

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